Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	999715	1			T13	4223		T14	4088		T15	1084
auto[1]	8065013	1			T1	8507		T2	2237		T3	42683
auto[2]	811484	1			T13	3896		T14	2855		T15	804
auto[3]	7798816	1			T1	6097		T2	2349		T3	40044

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10251396	1			T1	12193		T2	4586		T3	68940
auto[1]	1662740	1			T1	1164		T3	6580		T4	1093
auto[2]	1688487	1			T1	1125		T3	6617		T4	1105
auto[3]	4072405	1			T1	122		T3	590		T4	179

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5336280

1

T1

14603

T2

4586

T3

82725

auto[1]

12338748

1

T1

1

T3

2

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	284528	1			T13	1		T14	3390		T15	879
auto[0]	auto[0]	auto[1]	29532	1			T13	29		T14	329		T15	101
auto[0]	auto[0]	auto[2]	29791	1			T13	26		T14	342		T15	88
auto[0]	auto[0]	auto[3]	78057	1			T13	4165		T14	27		T15	16
auto[0]	auto[1]	auto[0]	1558232	1			T1	7093		T2	2237		T3	35545
auto[0]	auto[1]	auto[1]	184270	1			T1	661		T3	3208		T4	809
auto[0]	auto[1]	auto[2]	191589	1			T1	682		T3	3624		T4	305
auto[0]	auto[1]	auto[3]	448791	1			T1	70		T3	306		T4	95
auto[0]	auto[2]	auto[0]	217665	1			T13	1		T14	2254		T15	665
auto[0]	auto[2]	auto[1]	27801	1			T13	248		T14	230		T15	69
auto[0]	auto[2]	auto[2]	21311	1			T13	21		T14	337		T15	59
auto[0]	auto[2]	auto[3]	57774	1			T13	3626		T14	33		T15	11
auto[0]	auto[3]	auto[0]	1427282	1			T1	5099		T2	2349		T3	33393
auto[0]	auto[3]	auto[1]	173982	1			T1	503		T3	3372		T4	284
auto[0]	auto[3]	auto[2]	200852	1			T1	443		T3	2993		T4	800
auto[0]	auto[3]	auto[3]	404823	1			T1	52		T3	284		T4	84
auto[1]	auto[0]	auto[0]	19177	1			T88	501		T126	800		T127	709
auto[1]	auto[0]	auto[1]	86320	1			T88	2175		T126	3551		T127	3053
auto[1]	auto[0]	auto[2]	86138	1			T88	2155		T126	3474		T127	3040
auto[1]	auto[0]	auto[3]	386172	1			T13	2		T88	9648		T126	15766
auto[1]	auto[1]	auto[0]	3368279	1			T1	1		T85	199		T86	1857
auto[1]	auto[1]	auto[1]	576279	1			T85	2544		T86	8478		T87	4418
auto[1]	auto[1]	auto[2]	522683	1			T22	1		T85	847		T86	8483
auto[1]	auto[1]	auto[3]	1214890	1			T19	1		T85	11323		T86	37785
auto[1]	auto[2]	auto[0]	16162	1			T88	268		T126	707		T127	611
auto[1]	auto[2]	auto[1]	73465	1			T88	1303		T126	3278		T127	2713
auto[1]	auto[2]	auto[2]	71895	1			T14	1		T88	2063		T126	2378
auto[1]	auto[2]	auto[3]	325411	1			T88	9161		T126	10810		T127	11261
auto[1]	auto[3]	auto[0]	3360071	1			T3	2		T4	1		T21	1
auto[1]	auto[3]	auto[1]	511091	1			T20	1		T85	763		T86	8555
auto[1]	auto[3]	auto[2]	564228	1			T85	2584		T86	8552		T87	4436
auto[1]	auto[3]	auto[3]	1156487	1			T85	11355		T86	37802		T87	452