Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1060615175	172451	0	0
ctrl_regwen_rd_A	1060615175	6853	0	0
exec_rd_A	1060615175	6606	0	0
exec_regwen_rd_A	1060615175	7084	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060615175	172451	0	0
T5	47789	2604	0	0
T6	75712	1735	0	0
T12	951584	0	0	0
T13	455513	0	0	0
T17	324441	0	0	0
T19	436670	0	0	0
T20	124054	4145	0	0
T21	71508	0	0	0
T22	95202	0	0	0
T23	87291	0	0	0
T44	0	3624	0	0
T45	0	1272	0	0
T46	0	1783	0	0
T47	0	6627	0	0
T48	0	1506	0	0
T49	0	4254	0	0
T50	0	5332	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060615175	6853	0	0
T6	75712	237	0	0
T12	951584	0	0	0
T13	455513	0	0	0
T17	324441	0	0	0
T19	436670	0	0	0
T20	124054	0	0	0
T21	71508	0	0	0
T22	95202	0	0	0
T23	87291	0	0	0
T66	79921	0	0	0
T98	0	621	0	0
T99	0	264	0	0
T100	0	448	0	0
T101	0	280	0	0
T102	0	533	0	0
T103	0	598	0	0
T104	0	1089	0	0
T105	0	246	0	0
T106	0	827	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060615175	6606	0	0
T6	75712	262	0	0
T12	951584	0	0	0
T13	455513	0	0	0
T17	324441	0	0	0
T19	436670	0	0	0
T20	124054	0	0	0
T21	71508	0	0	0
T22	95202	0	0	0
T23	87291	0	0	0
T66	79921	0	0	0
T98	0	487	0	0
T99	0	274	0	0
T100	0	390	0	0
T101	0	333	0	0
T102	0	474	0	0
T103	0	514	0	0
T104	0	902	0	0
T105	0	276	0	0
T106	0	839	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060615175	7084	0	0
T6	75712	249	0	0
T12	951584	0	0	0
T13	455513	0	0	0
T17	324441	0	0	0
T19	436670	0	0	0
T20	124054	0	0	0
T21	71508	0	0	0
T22	95202	0	0	0
T23	87291	0	0	0
T66	79921	0	0	0
T98	0	547	0	0
T99	0	260	0	0
T100	0	471	0	0
T101	0	319	0	0
T102	0	451	0	0
T103	0	619	0	0
T104	0	1173	0	0
T105	0	373	0	0
T106	0	835	0	0