c30684b3ca| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.775m | 15.285ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.760s | 16.737us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.680s | 20.665us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.200s | 174.871us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.700s | 63.892us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 5.260s | 724.848us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.680s | 20.665us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.700s | 63.892us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 6.656m | 298.128ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 2.678m | 4.421ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 204 | 205 | 99.51 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 26.957m | 130.841ms | 48 | 50 | 96.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 6.897m | 6.907ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 46.777m | 718.399ms | 46 | 50 | 92.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 5.735m | 3.586ms | 0 | 50 | 0.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 11.046m | 49.094ms | 39 | 50 | 78.00 |
| V2 | executable | sram_ctrl_executable | 24.769m | 26.298ms | 48 | 50 | 96.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.550m | 2.678ms | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 11.445m | 64.946ms | 47 | 50 | 94.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.409m | 1.593ms | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.697m | 11.178ms | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 26.026m | 16.635ms | 48 | 50 | 96.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 4.510s | 4.186ms | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 2.607h | 2.252s | 38 | 50 | 76.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.710s | 18.570us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.410s | 2.199ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.410s | 2.199ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.760s | 16.737us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.680s | 20.665us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.700s | 63.892us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.810s | 25.856us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.760s | 16.737us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.680s | 20.665us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.700s | 63.892us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.810s | 25.856us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 654 | 740 | 88.38 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 58.600s | 41.377ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.270s | 1.856ms | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.760s | 432.718us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.270s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.760s | 432.718us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 26.026m | 16.635ms | 48 | 50 | 96.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.680s | 20.665us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 24.769m | 26.298ms | 48 | 50 | 96.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 24.769m | 26.298ms | 48 | 50 | 96.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 24.769m | 26.298ms | 48 | 50 | 96.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 11.046m | 49.094ms | 39 | 50 | 78.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 58.600s | 41.377ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.775m | 15.285ms | 49 | 50 | 98.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.775m | 15.285ms | 49 | 50 | 98.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 24.769m | 26.298ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.270s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 11.046m | 49.094ms | 39 | 50 | 78.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.270s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.270s | 1.856ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.775m | 15.285ms | 49 | 50 | 98.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.270s | 1.856ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 9.944m | 3.126ms | 49 | 50 | 98.00 |
| V3 | TOTAL | 49 | 50 | 98.00 | |||
| TOTAL | 952 | 1040 | 91.54 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 16 | 8 | 50.00 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.43 | 100.00 | 98.04 | 100.00 | 100.00 | 99.72 | 99.70 | 98.52 |
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 50 failures:
0.sram_ctrl_access_during_key_req.65993888229727460306820235234339528489496783058881525225887985746018085449078
Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
UVM_ERROR @ 701890166 ps: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x47) != exp (0x66)
UVM_INFO @ 701890166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_access_during_key_req.50162597343908183346479262336099223701978684842102201256024190858125133771555
Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
UVM_ERROR @ 1638549660 ps: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x78) != exp (0x41)
UVM_INFO @ 1638549660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:413) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 16 failures:
Test sram_ctrl_smoke has 1 failures.
4.sram_ctrl_smoke.53936520323990496076839166375881004451758910116218007590354802453875570492757
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest/run.log
UVM_ERROR @ 2635687493 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 2635687493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_multiple_keys has 2 failures.
6.sram_ctrl_multiple_keys.64275890799123459747846630437365011794254419370267378207053983117839537325738
Line 312, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest/run.log
UVM_ERROR @ 54218081268 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 54218081268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.sram_ctrl_multiple_keys.32095244658058261764150942895568556109475279010991873637393897184873064553777
Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest/run.log
UVM_ERROR @ 50300362133 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 50300362133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_regwen has 2 failures.
13.sram_ctrl_regwen.39493905076321545803038753383360609873781085594858959272773094701037436099754
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest/run.log
UVM_ERROR @ 673236540 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 673236540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.sram_ctrl_regwen.20458062847715200315385489669115855974551618122534613201277953361571599705060
Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest/run.log
UVM_ERROR @ 19337824897 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 19337824897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_partial_access_b2b has 3 failures.
15.sram_ctrl_partial_access_b2b.61101823638049119943290288479148722418857087747454023896940701802942678955747
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest/run.log
UVM_ERROR @ 1932426881 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 1932426881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.sram_ctrl_partial_access_b2b.15423071234102231912211752306261550750640399063770461268950308952138490872432
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest/run.log
UVM_ERROR @ 2348312263 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 2348312263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test sram_ctrl_executable has 2 failures.
15.sram_ctrl_executable.25433340776661536149681201398526527247488985096183584394838855229663399589191
Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 1419699815 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 1419699815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.sram_ctrl_executable.60166231587879840941779019866711461274989068875820809126622818370302765872072
Line 300, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 24937086707 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 24937086707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more tests.
UVM_ERROR (sram_ctrl_scoreboard.sv:397) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 12 failures:
1.sram_ctrl_stress_all.97936560768580702152110959953047467961330811119819173525928539940923049980545
Line 394, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 32181042603 ps: (sram_ctrl_scoreboard.sv:397) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 32181042603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.sram_ctrl_stress_all.4706760332986652365763136035865102815242834889136569415917983104494795311810
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 78930919994 ps: (sram_ctrl_scoreboard.sv:397) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 78930919994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
4.sram_ctrl_lc_escalation.79177164905200763643465193786730452584549652296515963312288116360205946332285
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 3627006467 ps: (sram_ctrl_scoreboard.sv:397) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 3627006467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.sram_ctrl_lc_escalation.956528867092316590529893349598817859880268304294401257777955236202667941234
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 13125369246 ps: (sram_ctrl_scoreboard.sv:397) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 13125369246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (sram_ctrl_base_vseq.sv:102) [sram_ctrl_bijection_vseq] Timed out waiting for key request done has 6 failures:
18.sram_ctrl_stress_all.87709501153467916125169419418045608679143342047491499279876903459588435730502
Line 401, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 512467496793 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 512467496793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.sram_ctrl_stress_all.106098578044020009607568072442507727263141757336531141824482827119297518725860
Line 454, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 128449570139 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 128449570139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
24.sram_ctrl_bijection.33164982601108213507105004282003705189631283718333922199772944873625158566095
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 542214352466 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 542214352466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.sram_ctrl_bijection.108643103503907923949231477050568377767149643324923139407109235488078991109002
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 222929363415 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 222929363415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout sram_ctrl_regs_reg_block.status.scr_key_valid (addr=*) == * has 1 failures:
0.sram_ctrl_lc_escalation.60168897420864569767856672769760770099606786928423806343828763301337781522473
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest/run.log
UVM_FATAL @ 23586055012 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout sram_ctrl_regs_reg_block.status.scr_key_valid (addr=0xbbc40284) == 0x1
UVM_INFO @ 23586055012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 1 failures:
4.sram_ctrl_stress_all.6122493873953798307062147101870317638351876526275224406859587310333019819444
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 898555286 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 898555286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:827) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
29.sram_ctrl_stress_all_with_rand_reset.111279683416084158284887286419742701451051576184626163608980150617098999024213
Line 352, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3746606581 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3746606581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
45.sram_ctrl_bijection.46701753481807175886650764536922946624214438785783005815028268547191568927330
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---