| T546 |
/workspace/coverage/default/44.sram_ctrl_executable.1690707925 |
|
|
Mar 07 01:15:29 PM PST 24 |
Mar 07 01:38:10 PM PST 24 |
25476275434 ps |
| T547 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.2527260401 |
|
|
Mar 07 01:13:25 PM PST 24 |
Mar 07 01:13:28 PM PST 24 |
363777367 ps |
| T548 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2433625752 |
|
|
Mar 07 01:15:16 PM PST 24 |
Mar 07 01:16:02 PM PST 24 |
965699880 ps |
| T549 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.4022324856 |
|
|
Mar 07 01:12:45 PM PST 24 |
Mar 07 01:13:39 PM PST 24 |
3111841274 ps |
| T550 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1706268635 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:24:09 PM PST 24 |
58636785611 ps |
| T551 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3487939859 |
|
|
Mar 07 01:14:22 PM PST 24 |
Mar 07 01:16:48 PM PST 24 |
2180100572 ps |
| T552 |
/workspace/coverage/default/0.sram_ctrl_regwen.4191401213 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:27:47 PM PST 24 |
3250605317 ps |
| T553 |
/workspace/coverage/default/10.sram_ctrl_smoke.2441854664 |
|
|
Mar 07 01:12:07 PM PST 24 |
Mar 07 01:12:19 PM PST 24 |
384097598 ps |
| T554 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1583551307 |
|
|
Mar 07 01:14:07 PM PST 24 |
Mar 07 01:15:24 PM PST 24 |
10039626794 ps |
| T22 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3732523415 |
|
|
Mar 07 01:11:40 PM PST 24 |
Mar 07 01:11:44 PM PST 24 |
580050866 ps |
| T555 |
/workspace/coverage/default/47.sram_ctrl_alert_test.27414541 |
|
|
Mar 07 01:16:16 PM PST 24 |
Mar 07 01:16:17 PM PST 24 |
48612315 ps |
| T556 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1451720624 |
|
|
Mar 07 01:12:42 PM PST 24 |
Mar 07 01:17:05 PM PST 24 |
4336392779 ps |
| T557 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.4093670042 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:13:14 PM PST 24 |
2370567137 ps |
| T558 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2871769338 |
|
|
Mar 07 01:11:29 PM PST 24 |
Mar 07 01:11:30 PM PST 24 |
13273363 ps |
| T559 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.3631851942 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:11:42 PM PST 24 |
364946695 ps |
| T560 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.4114897441 |
|
|
Mar 07 01:12:06 PM PST 24 |
Mar 07 01:12:11 PM PST 24 |
1346629679 ps |
| T561 |
/workspace/coverage/default/32.sram_ctrl_alert_test.444636642 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 01:13:57 PM PST 24 |
57092172 ps |
| T562 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.1804260622 |
|
|
Mar 07 01:13:41 PM PST 24 |
Mar 07 01:17:51 PM PST 24 |
3945604365 ps |
| T563 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1503052664 |
|
|
Mar 07 01:11:56 PM PST 24 |
Mar 07 01:22:48 PM PST 24 |
33336103889 ps |
| T564 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.785969523 |
|
|
Mar 07 01:12:10 PM PST 24 |
Mar 07 01:12:42 PM PST 24 |
719239670 ps |
| T565 |
/workspace/coverage/default/12.sram_ctrl_bijection.4221597889 |
|
|
Mar 07 01:12:09 PM PST 24 |
Mar 07 01:37:13 PM PST 24 |
460438117431 ps |
| T566 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2981924444 |
|
|
Mar 07 01:13:43 PM PST 24 |
Mar 07 01:13:47 PM PST 24 |
1471267733 ps |
| T567 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1412786595 |
|
|
Mar 07 01:12:14 PM PST 24 |
Mar 07 01:12:37 PM PST 24 |
705858382 ps |
| T568 |
/workspace/coverage/default/44.sram_ctrl_smoke.2044960012 |
|
|
Mar 07 01:15:29 PM PST 24 |
Mar 07 01:15:45 PM PST 24 |
3460484654 ps |
| T569 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1590491661 |
|
|
Mar 07 01:13:24 PM PST 24 |
Mar 07 01:31:44 PM PST 24 |
18737197848 ps |
| T570 |
/workspace/coverage/default/17.sram_ctrl_executable.566246527 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:19:11 PM PST 24 |
14076289106 ps |
| T571 |
/workspace/coverage/default/4.sram_ctrl_partial_access.150245943 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:13:35 PM PST 24 |
873331798 ps |
| T572 |
/workspace/coverage/default/25.sram_ctrl_alert_test.4285212614 |
|
|
Mar 07 01:13:04 PM PST 24 |
Mar 07 01:13:05 PM PST 24 |
14132148 ps |
| T573 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2795890255 |
|
|
Mar 07 01:14:42 PM PST 24 |
Mar 07 02:19:18 PM PST 24 |
424328079828 ps |
| T23 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.4113548473 |
|
|
Mar 07 01:11:40 PM PST 24 |
Mar 07 01:11:44 PM PST 24 |
647288047 ps |
| T574 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2792389139 |
|
|
Mar 07 01:12:14 PM PST 24 |
Mar 07 01:16:23 PM PST 24 |
4109409229 ps |
| T575 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1573268423 |
|
|
Mar 07 01:13:03 PM PST 24 |
Mar 07 01:14:59 PM PST 24 |
1526497717 ps |
| T576 |
/workspace/coverage/default/40.sram_ctrl_smoke.1560896146 |
|
|
Mar 07 01:14:43 PM PST 24 |
Mar 07 01:15:08 PM PST 24 |
2960191744 ps |
| T577 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2296624063 |
|
|
Mar 07 01:11:47 PM PST 24 |
Mar 07 01:16:49 PM PST 24 |
11055300672 ps |
| T578 |
/workspace/coverage/default/10.sram_ctrl_stress_all.938152638 |
|
|
Mar 07 01:11:57 PM PST 24 |
Mar 07 02:44:41 PM PST 24 |
236132093247 ps |
| T579 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.3539221073 |
|
|
Mar 07 01:12:47 PM PST 24 |
Mar 07 01:22:51 PM PST 24 |
52751292094 ps |
| T580 |
/workspace/coverage/default/1.sram_ctrl_bijection.408330792 |
|
|
Mar 07 01:11:28 PM PST 24 |
Mar 07 01:24:06 PM PST 24 |
397842372919 ps |
| T581 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3434048974 |
|
|
Mar 07 01:15:15 PM PST 24 |
Mar 07 01:15:53 PM PST 24 |
2589867602 ps |
| T582 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.506467079 |
|
|
Mar 07 01:14:22 PM PST 24 |
Mar 07 01:16:45 PM PST 24 |
11749728799 ps |
| T583 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3394476079 |
|
|
Mar 07 01:16:00 PM PST 24 |
Mar 07 01:22:16 PM PST 24 |
5072412886 ps |
| T584 |
/workspace/coverage/default/16.sram_ctrl_executable.3361624628 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:24:11 PM PST 24 |
28348491328 ps |
| T585 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2868821940 |
|
|
Mar 07 01:12:04 PM PST 24 |
Mar 07 01:14:08 PM PST 24 |
13150026586 ps |
| T105 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2003188231 |
|
|
Mar 07 01:13:23 PM PST 24 |
Mar 07 01:13:57 PM PST 24 |
6676581779 ps |
| T586 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.21276375 |
|
|
Mar 07 01:13:44 PM PST 24 |
Mar 07 01:14:52 PM PST 24 |
4908777109 ps |
| T587 |
/workspace/coverage/default/26.sram_ctrl_executable.1727978479 |
|
|
Mar 07 01:13:03 PM PST 24 |
Mar 07 01:23:51 PM PST 24 |
9184015559 ps |
| T588 |
/workspace/coverage/default/42.sram_ctrl_partial_access.3950714783 |
|
|
Mar 07 01:15:06 PM PST 24 |
Mar 07 01:15:36 PM PST 24 |
658079631 ps |
| T589 |
/workspace/coverage/default/26.sram_ctrl_smoke.4280189664 |
|
|
Mar 07 01:13:11 PM PST 24 |
Mar 07 01:13:22 PM PST 24 |
6961961262 ps |
| T590 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.995674478 |
|
|
Mar 07 01:16:19 PM PST 24 |
Mar 07 01:16:22 PM PST 24 |
1408038073 ps |
| T591 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3010694217 |
|
|
Mar 07 01:14:48 PM PST 24 |
Mar 07 01:19:20 PM PST 24 |
4345872359 ps |
| T592 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.15090097 |
|
|
Mar 07 01:15:40 PM PST 24 |
Mar 07 01:29:06 PM PST 24 |
37042969974 ps |
| T593 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1266661559 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:37:22 PM PST 24 |
82231487969 ps |
| T594 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1967055123 |
|
|
Mar 07 01:13:39 PM PST 24 |
Mar 07 01:17:06 PM PST 24 |
4190980867 ps |
| T595 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.309923031 |
|
|
Mar 07 01:12:10 PM PST 24 |
Mar 07 01:16:07 PM PST 24 |
4024593848 ps |
| T596 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1401833310 |
|
|
Mar 07 01:12:28 PM PST 24 |
Mar 07 01:16:10 PM PST 24 |
3562056890 ps |
| T597 |
/workspace/coverage/default/15.sram_ctrl_alert_test.792330153 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:12:26 PM PST 24 |
50919131 ps |
| T598 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1802359397 |
|
|
Mar 07 01:11:57 PM PST 24 |
Mar 07 01:15:08 PM PST 24 |
6058848382 ps |
| T599 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.968906152 |
|
|
Mar 07 01:15:31 PM PST 24 |
Mar 07 01:15:35 PM PST 24 |
3343969691 ps |
| T600 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.3410732922 |
|
|
Mar 07 01:14:36 PM PST 24 |
Mar 07 01:15:18 PM PST 24 |
777414056 ps |
| T601 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3712467366 |
|
|
Mar 07 01:16:23 PM PST 24 |
Mar 07 01:16:27 PM PST 24 |
6709825454 ps |
| T602 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.140914097 |
|
|
Mar 07 01:13:29 PM PST 24 |
Mar 07 01:15:34 PM PST 24 |
5372638508 ps |
| T603 |
/workspace/coverage/default/22.sram_ctrl_partial_access.316261624 |
|
|
Mar 07 01:12:42 PM PST 24 |
Mar 07 01:12:55 PM PST 24 |
1635501289 ps |
| T604 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2477710861 |
|
|
Mar 07 01:12:38 PM PST 24 |
Mar 07 01:13:17 PM PST 24 |
714159425 ps |
| T605 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.1658731338 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 01:14:00 PM PST 24 |
700746409 ps |
| T606 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2480692238 |
|
|
Mar 07 01:14:21 PM PST 24 |
Mar 07 01:15:36 PM PST 24 |
2646036779 ps |
| T607 |
/workspace/coverage/default/46.sram_ctrl_smoke.374719085 |
|
|
Mar 07 01:15:48 PM PST 24 |
Mar 07 01:18:03 PM PST 24 |
1688600668 ps |
| T608 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3869804481 |
|
|
Mar 07 01:15:08 PM PST 24 |
Mar 07 01:15:09 PM PST 24 |
18681782 ps |
| T609 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.3588358458 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 01:15:26 PM PST 24 |
4395296140 ps |
| T610 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1746925143 |
|
|
Mar 07 01:11:52 PM PST 24 |
Mar 07 01:15:28 PM PST 24 |
3241447899 ps |
| T611 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1181046794 |
|
|
Mar 07 01:15:18 PM PST 24 |
Mar 07 01:15:22 PM PST 24 |
3748252476 ps |
| T612 |
/workspace/coverage/default/49.sram_ctrl_regwen.206214525 |
|
|
Mar 07 01:16:22 PM PST 24 |
Mar 07 01:18:36 PM PST 24 |
5629024128 ps |
| T613 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2240265677 |
|
|
Mar 07 01:15:06 PM PST 24 |
Mar 07 01:17:07 PM PST 24 |
1620798552 ps |
| T614 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1220645140 |
|
|
Mar 07 01:14:46 PM PST 24 |
Mar 07 01:19:39 PM PST 24 |
16735203480 ps |
| T106 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2882428051 |
|
|
Mar 07 01:12:09 PM PST 24 |
Mar 07 01:14:30 PM PST 24 |
1452945869 ps |
| T615 |
/workspace/coverage/default/21.sram_ctrl_regwen.2974088341 |
|
|
Mar 07 01:12:43 PM PST 24 |
Mar 07 01:24:00 PM PST 24 |
22041271465 ps |
| T616 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3199709404 |
|
|
Mar 07 01:11:35 PM PST 24 |
Mar 07 01:13:17 PM PST 24 |
818386760 ps |
| T617 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2959019613 |
|
|
Mar 07 01:11:37 PM PST 24 |
Mar 07 01:13:20 PM PST 24 |
2012346480 ps |
| T618 |
/workspace/coverage/default/38.sram_ctrl_alert_test.972256665 |
|
|
Mar 07 01:14:43 PM PST 24 |
Mar 07 01:14:44 PM PST 24 |
15389319 ps |
| T619 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.4169457667 |
|
|
Mar 07 01:15:48 PM PST 24 |
Mar 07 01:17:32 PM PST 24 |
3044611285 ps |
| T620 |
/workspace/coverage/default/33.sram_ctrl_smoke.1879130525 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 01:14:26 PM PST 24 |
2246414942 ps |
| T621 |
/workspace/coverage/default/30.sram_ctrl_stress_all.3695892484 |
|
|
Mar 07 01:13:37 PM PST 24 |
Mar 07 02:39:48 PM PST 24 |
276501759818 ps |
| T622 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.4028129286 |
|
|
Mar 07 01:12:39 PM PST 24 |
Mar 07 01:31:42 PM PST 24 |
14878699220 ps |
| T623 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.2415941402 |
|
|
Mar 07 01:14:06 PM PST 24 |
Mar 07 01:18:32 PM PST 24 |
23756060454 ps |
| T624 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2112410479 |
|
|
Mar 07 01:15:30 PM PST 24 |
Mar 07 01:15:37 PM PST 24 |
684819784 ps |
| T625 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.1882693625 |
|
|
Mar 07 01:15:31 PM PST 24 |
Mar 07 01:16:26 PM PST 24 |
769178493 ps |
| T626 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1152622704 |
|
|
Mar 07 01:13:40 PM PST 24 |
Mar 07 01:13:59 PM PST 24 |
611917459 ps |
| T627 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.359396062 |
|
|
Mar 07 01:11:47 PM PST 24 |
Mar 07 01:29:20 PM PST 24 |
111823533218 ps |
| T628 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1637068445 |
|
|
Mar 07 01:11:43 PM PST 24 |
Mar 07 01:15:56 PM PST 24 |
5784312884 ps |
| T629 |
/workspace/coverage/default/11.sram_ctrl_regwen.201489746 |
|
|
Mar 07 01:12:10 PM PST 24 |
Mar 07 01:29:11 PM PST 24 |
97802555613 ps |
| T630 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.614214587 |
|
|
Mar 07 01:14:48 PM PST 24 |
Mar 07 01:20:15 PM PST 24 |
64115196897 ps |
| T631 |
/workspace/coverage/default/11.sram_ctrl_bijection.2313348608 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:54:47 PM PST 24 |
529213220609 ps |
| T632 |
/workspace/coverage/default/27.sram_ctrl_executable.1136088877 |
|
|
Mar 07 01:13:23 PM PST 24 |
Mar 07 01:19:32 PM PST 24 |
8207761137 ps |
| T633 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2341790071 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:13:02 PM PST 24 |
5492351010 ps |
| T634 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3684745177 |
|
|
Mar 07 01:12:29 PM PST 24 |
Mar 07 01:14:02 PM PST 24 |
1475826287 ps |
| T635 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.535882407 |
|
|
Mar 07 01:11:59 PM PST 24 |
Mar 07 01:24:13 PM PST 24 |
21707330490 ps |
| T636 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1719488373 |
|
|
Mar 07 01:15:21 PM PST 24 |
Mar 07 01:15:28 PM PST 24 |
714299304 ps |
| T637 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3069216913 |
|
|
Mar 07 01:12:24 PM PST 24 |
Mar 07 01:12:31 PM PST 24 |
845227751 ps |
| T638 |
/workspace/coverage/default/21.sram_ctrl_smoke.1147716722 |
|
|
Mar 07 01:12:37 PM PST 24 |
Mar 07 01:12:51 PM PST 24 |
2085546532 ps |
| T639 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2442194420 |
|
|
Mar 07 01:15:59 PM PST 24 |
Mar 07 01:18:43 PM PST 24 |
3320561275 ps |
| T640 |
/workspace/coverage/default/42.sram_ctrl_executable.3125802600 |
|
|
Mar 07 01:15:16 PM PST 24 |
Mar 07 01:25:16 PM PST 24 |
11948942756 ps |
| T641 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.111989999 |
|
|
Mar 07 01:12:06 PM PST 24 |
Mar 07 01:18:37 PM PST 24 |
13592202381 ps |
| T642 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3280956375 |
|
|
Mar 07 01:12:01 PM PST 24 |
Mar 07 01:12:26 PM PST 24 |
2888116202 ps |
| T643 |
/workspace/coverage/default/49.sram_ctrl_partial_access.4203707750 |
|
|
Mar 07 01:16:26 PM PST 24 |
Mar 07 01:16:35 PM PST 24 |
839600880 ps |
| T644 |
/workspace/coverage/default/19.sram_ctrl_bijection.1775616297 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:38:14 PM PST 24 |
199459544510 ps |
| T645 |
/workspace/coverage/default/2.sram_ctrl_executable.3086377914 |
|
|
Mar 07 01:11:42 PM PST 24 |
Mar 07 01:18:54 PM PST 24 |
14014979224 ps |
| T646 |
/workspace/coverage/default/10.sram_ctrl_alert_test.669950765 |
|
|
Mar 07 01:12:10 PM PST 24 |
Mar 07 01:12:10 PM PST 24 |
29080318 ps |
| T647 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2123498398 |
|
|
Mar 07 01:13:22 PM PST 24 |
Mar 07 01:29:05 PM PST 24 |
32184042718 ps |
| T648 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.3502749212 |
|
|
Mar 07 01:14:27 PM PST 24 |
Mar 07 01:19:04 PM PST 24 |
14348886884 ps |
| T649 |
/workspace/coverage/default/46.sram_ctrl_regwen.3922521215 |
|
|
Mar 07 01:16:01 PM PST 24 |
Mar 07 01:30:41 PM PST 24 |
9784592474 ps |
| T650 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2288618027 |
|
|
Mar 07 01:16:23 PM PST 24 |
Mar 07 01:29:33 PM PST 24 |
13085275929 ps |
| T651 |
/workspace/coverage/default/8.sram_ctrl_alert_test.3403589303 |
|
|
Mar 07 01:12:05 PM PST 24 |
Mar 07 01:12:06 PM PST 24 |
11216177 ps |
| T652 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1156175085 |
|
|
Mar 07 01:14:48 PM PST 24 |
Mar 07 01:18:13 PM PST 24 |
13593603548 ps |
| T33 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.3098859067 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:11:44 PM PST 24 |
209979993 ps |
| T653 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3598231168 |
|
|
Mar 07 01:12:52 PM PST 24 |
Mar 07 01:13:58 PM PST 24 |
5004641595 ps |
| T654 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.1816818596 |
|
|
Mar 07 01:12:48 PM PST 24 |
Mar 07 01:12:51 PM PST 24 |
710470444 ps |
| T655 |
/workspace/coverage/default/5.sram_ctrl_smoke.1122175930 |
|
|
Mar 07 01:11:44 PM PST 24 |
Mar 07 01:12:04 PM PST 24 |
3215490693 ps |
| T656 |
/workspace/coverage/default/34.sram_ctrl_bijection.2012097314 |
|
|
Mar 07 01:14:07 PM PST 24 |
Mar 07 01:35:15 PM PST 24 |
89443217254 ps |
| T657 |
/workspace/coverage/default/44.sram_ctrl_regwen.3853882421 |
|
|
Mar 07 01:15:38 PM PST 24 |
Mar 07 01:23:01 PM PST 24 |
2110035721 ps |
| T658 |
/workspace/coverage/default/43.sram_ctrl_regwen.269637190 |
|
|
Mar 07 01:15:33 PM PST 24 |
Mar 07 01:21:46 PM PST 24 |
4671712777 ps |
| T659 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1205958467 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 01:16:01 PM PST 24 |
1623535117 ps |
| T660 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.177646625 |
|
|
Mar 07 01:12:37 PM PST 24 |
Mar 07 01:26:57 PM PST 24 |
18347281404 ps |
| T661 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2331541780 |
|
|
Mar 07 01:12:23 PM PST 24 |
Mar 07 01:12:27 PM PST 24 |
4764969734 ps |
| T662 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1013217662 |
|
|
Mar 07 01:15:31 PM PST 24 |
Mar 07 01:16:21 PM PST 24 |
4589385172 ps |
| T663 |
/workspace/coverage/default/36.sram_ctrl_executable.632685819 |
|
|
Mar 07 01:14:24 PM PST 24 |
Mar 07 01:31:24 PM PST 24 |
7687179530 ps |
| T664 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.494253596 |
|
|
Mar 07 01:15:31 PM PST 24 |
Mar 07 01:21:53 PM PST 24 |
17318106443 ps |
| T665 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.822823647 |
|
|
Mar 07 01:13:05 PM PST 24 |
Mar 07 01:24:31 PM PST 24 |
91402219508 ps |
| T666 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3340010762 |
|
|
Mar 07 01:11:50 PM PST 24 |
Mar 07 01:12:17 PM PST 24 |
1963645593 ps |
| T667 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.336437085 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:13:48 PM PST 24 |
1856943314 ps |
| T668 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1403762284 |
|
|
Mar 07 01:14:34 PM PST 24 |
Mar 07 01:33:56 PM PST 24 |
11026873307 ps |
| T669 |
/workspace/coverage/default/39.sram_ctrl_stress_all.1399040974 |
|
|
Mar 07 01:14:42 PM PST 24 |
Mar 07 01:48:56 PM PST 24 |
118699597283 ps |
| T670 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.3014624629 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 01:17:42 PM PST 24 |
6872100598 ps |
| T671 |
/workspace/coverage/default/2.sram_ctrl_regwen.4292228425 |
|
|
Mar 07 01:11:36 PM PST 24 |
Mar 07 01:24:46 PM PST 24 |
21974524028 ps |
| T672 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1849220845 |
|
|
Mar 07 01:11:44 PM PST 24 |
Mar 07 01:12:49 PM PST 24 |
4302524124 ps |
| T673 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3559147057 |
|
|
Mar 07 01:12:47 PM PST 24 |
Mar 07 01:15:06 PM PST 24 |
20231499012 ps |
| T674 |
/workspace/coverage/default/1.sram_ctrl_regwen.19261464 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:25:24 PM PST 24 |
8309622383 ps |
| T675 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3981200349 |
|
|
Mar 07 01:12:47 PM PST 24 |
Mar 07 01:15:23 PM PST 24 |
20655030085 ps |
| T676 |
/workspace/coverage/default/2.sram_ctrl_stress_all.1254954788 |
|
|
Mar 07 01:11:38 PM PST 24 |
Mar 07 02:22:54 PM PST 24 |
204122550346 ps |
| T677 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1256191175 |
|
|
Mar 07 01:11:59 PM PST 24 |
Mar 07 01:19:06 PM PST 24 |
19371668370 ps |
| T678 |
/workspace/coverage/default/39.sram_ctrl_bijection.3072970548 |
|
|
Mar 07 01:14:42 PM PST 24 |
Mar 07 01:45:47 PM PST 24 |
380792242438 ps |
| T679 |
/workspace/coverage/default/31.sram_ctrl_smoke.1674770652 |
|
|
Mar 07 01:13:42 PM PST 24 |
Mar 07 01:15:46 PM PST 24 |
3698100356 ps |
| T680 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3647442722 |
|
|
Mar 07 01:13:04 PM PST 24 |
Mar 07 01:15:32 PM PST 24 |
9217918960 ps |
| T681 |
/workspace/coverage/default/18.sram_ctrl_bijection.2023559454 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:28:57 PM PST 24 |
166586189482 ps |
| T682 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.272199564 |
|
|
Mar 07 01:13:22 PM PST 24 |
Mar 07 01:16:08 PM PST 24 |
3181398532 ps |
| T683 |
/workspace/coverage/default/19.sram_ctrl_alert_test.1182750864 |
|
|
Mar 07 01:12:39 PM PST 24 |
Mar 07 01:12:40 PM PST 24 |
22925262 ps |
| T684 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3296020488 |
|
|
Mar 07 01:14:42 PM PST 24 |
Mar 07 01:28:12 PM PST 24 |
22397181726 ps |
| T685 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2468385002 |
|
|
Mar 07 01:12:36 PM PST 24 |
Mar 07 01:18:55 PM PST 24 |
24764431883 ps |
| T686 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1331471827 |
|
|
Mar 07 01:12:10 PM PST 24 |
Mar 07 01:13:17 PM PST 24 |
7828208298 ps |
| T687 |
/workspace/coverage/default/18.sram_ctrl_regwen.1035420146 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:23:11 PM PST 24 |
159225525207 ps |
| T688 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3827752810 |
|
|
Mar 07 01:13:43 PM PST 24 |
Mar 07 01:14:09 PM PST 24 |
2097782049 ps |
| T689 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3192505164 |
|
|
Mar 07 01:12:29 PM PST 24 |
Mar 07 01:12:46 PM PST 24 |
2549262530 ps |
| T690 |
/workspace/coverage/default/6.sram_ctrl_partial_access.2897476446 |
|
|
Mar 07 01:11:48 PM PST 24 |
Mar 07 01:12:17 PM PST 24 |
2614347210 ps |
| T691 |
/workspace/coverage/default/24.sram_ctrl_bijection.1305607602 |
|
|
Mar 07 01:12:49 PM PST 24 |
Mar 07 01:23:39 PM PST 24 |
9916953048 ps |
| T692 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2741524234 |
|
|
Mar 07 01:14:06 PM PST 24 |
Mar 07 01:24:45 PM PST 24 |
149112101202 ps |
| T693 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3276936232 |
|
|
Mar 07 01:14:32 PM PST 24 |
Mar 07 01:14:39 PM PST 24 |
2695176663 ps |
| T694 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.768171383 |
|
|
Mar 07 01:14:42 PM PST 24 |
Mar 07 01:15:43 PM PST 24 |
997185686 ps |
| T695 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2639230708 |
|
|
Mar 07 01:12:01 PM PST 24 |
Mar 07 01:12:09 PM PST 24 |
1417244377 ps |
| T696 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1870800007 |
|
|
Mar 07 01:14:56 PM PST 24 |
Mar 07 01:14:59 PM PST 24 |
1355176697 ps |
| T697 |
/workspace/coverage/default/4.sram_ctrl_executable.1406493524 |
|
|
Mar 07 01:11:40 PM PST 24 |
Mar 07 01:28:50 PM PST 24 |
58506546915 ps |
| T698 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.1230786279 |
|
|
Mar 07 01:14:21 PM PST 24 |
Mar 07 01:14:35 PM PST 24 |
725718780 ps |
| T699 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2319144968 |
|
|
Mar 07 01:13:05 PM PST 24 |
Mar 07 01:27:02 PM PST 24 |
19459780002 ps |
| T700 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2697864095 |
|
|
Mar 07 01:11:57 PM PST 24 |
Mar 07 01:11:57 PM PST 24 |
38960804 ps |
| T701 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.253035646 |
|
|
Mar 07 01:14:06 PM PST 24 |
Mar 07 01:15:45 PM PST 24 |
780341925 ps |
| T702 |
/workspace/coverage/default/9.sram_ctrl_regwen.3426335497 |
|
|
Mar 07 01:11:59 PM PST 24 |
Mar 07 01:25:38 PM PST 24 |
11218644153 ps |
| T703 |
/workspace/coverage/default/37.sram_ctrl_smoke.3103201953 |
|
|
Mar 07 01:14:32 PM PST 24 |
Mar 07 01:14:39 PM PST 24 |
782712308 ps |
| T704 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.769088814 |
|
|
Mar 07 01:13:04 PM PST 24 |
Mar 07 01:13:08 PM PST 24 |
6683570168 ps |
| T705 |
/workspace/coverage/default/15.sram_ctrl_stress_all.1833690630 |
|
|
Mar 07 01:12:26 PM PST 24 |
Mar 07 02:51:43 PM PST 24 |
847223812741 ps |
| T706 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3322211276 |
|
|
Mar 07 01:14:08 PM PST 24 |
Mar 07 01:15:19 PM PST 24 |
956554328 ps |
| T707 |
/workspace/coverage/default/38.sram_ctrl_executable.856962470 |
|
|
Mar 07 01:14:35 PM PST 24 |
Mar 07 01:34:11 PM PST 24 |
23405013525 ps |
| T708 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3325296796 |
|
|
Mar 07 01:14:09 PM PST 24 |
Mar 07 01:14:10 PM PST 24 |
42395398 ps |
| T709 |
/workspace/coverage/default/28.sram_ctrl_stress_all.1090887959 |
|
|
Mar 07 01:13:43 PM PST 24 |
Mar 07 02:02:03 PM PST 24 |
207675465337 ps |
| T710 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.158451194 |
|
|
Mar 07 01:11:46 PM PST 24 |
Mar 07 01:32:40 PM PST 24 |
7967169095 ps |
| T711 |
/workspace/coverage/default/13.sram_ctrl_smoke.3276565810 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:14:08 PM PST 24 |
1555331928 ps |
| T712 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.727973140 |
|
|
Mar 07 01:13:06 PM PST 24 |
Mar 07 01:13:10 PM PST 24 |
1983719792 ps |
| T713 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3410166804 |
|
|
Mar 07 01:11:54 PM PST 24 |
Mar 07 01:11:55 PM PST 24 |
23166434 ps |
| T714 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2377693945 |
|
|
Mar 07 01:12:04 PM PST 24 |
Mar 07 01:13:11 PM PST 24 |
793749970 ps |
| T715 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.565441873 |
|
|
Mar 07 01:16:12 PM PST 24 |
Mar 07 01:16:24 PM PST 24 |
1431775934 ps |
| T716 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2784468515 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:24:41 PM PST 24 |
31975072425 ps |
| T717 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.4179529714 |
|
|
Mar 07 01:14:05 PM PST 24 |
Mar 07 01:38:54 PM PST 24 |
76464911282 ps |
| T718 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.853175954 |
|
|
Mar 07 01:11:56 PM PST 24 |
Mar 07 01:12:54 PM PST 24 |
3105081471 ps |
| T719 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2774700111 |
|
|
Mar 07 01:13:26 PM PST 24 |
Mar 07 01:22:16 PM PST 24 |
118806054824 ps |
| T720 |
/workspace/coverage/default/37.sram_ctrl_alert_test.2789049911 |
|
|
Mar 07 01:14:33 PM PST 24 |
Mar 07 01:14:33 PM PST 24 |
30215727 ps |
| T721 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.3934156444 |
|
|
Mar 07 01:15:17 PM PST 24 |
Mar 07 01:17:21 PM PST 24 |
8225568953 ps |
| T722 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1269065802 |
|
|
Mar 07 01:14:36 PM PST 24 |
Mar 07 01:14:40 PM PST 24 |
1779997385 ps |
| T723 |
/workspace/coverage/default/6.sram_ctrl_executable.3873230590 |
|
|
Mar 07 01:11:49 PM PST 24 |
Mar 07 01:20:54 PM PST 24 |
6119874108 ps |
| T724 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1970870344 |
|
|
Mar 07 01:16:12 PM PST 24 |
Mar 07 01:20:15 PM PST 24 |
16283117207 ps |
| T725 |
/workspace/coverage/default/46.sram_ctrl_bijection.4104056602 |
|
|
Mar 07 01:15:51 PM PST 24 |
Mar 07 01:47:34 PM PST 24 |
63230212831 ps |
| T726 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.4003871985 |
|
|
Mar 07 01:12:23 PM PST 24 |
Mar 07 01:17:40 PM PST 24 |
37627690274 ps |
| T727 |
/workspace/coverage/default/0.sram_ctrl_smoke.2812791106 |
|
|
Mar 07 01:11:32 PM PST 24 |
Mar 07 01:12:40 PM PST 24 |
958142987 ps |
| T728 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3027114987 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:16:08 PM PST 24 |
15550156902 ps |
| T729 |
/workspace/coverage/default/4.sram_ctrl_bijection.4143613492 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:23:57 PM PST 24 |
11288304317 ps |
| T730 |
/workspace/coverage/default/34.sram_ctrl_regwen.1347548477 |
|
|
Mar 07 01:14:06 PM PST 24 |
Mar 07 01:29:59 PM PST 24 |
11177666417 ps |
| T731 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1405553315 |
|
|
Mar 07 01:12:30 PM PST 24 |
Mar 07 01:14:52 PM PST 24 |
4375131702 ps |
| T732 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1616782611 |
|
|
Mar 07 01:15:38 PM PST 24 |
Mar 07 01:18:15 PM PST 24 |
27486953335 ps |
| T733 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2140490658 |
|
|
Mar 07 01:12:38 PM PST 24 |
Mar 07 01:19:01 PM PST 24 |
15402231730 ps |
| T734 |
/workspace/coverage/default/48.sram_ctrl_bijection.430529089 |
|
|
Mar 07 01:16:11 PM PST 24 |
Mar 07 01:42:45 PM PST 24 |
25371656207 ps |
| T735 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1533458255 |
|
|
Mar 07 01:12:05 PM PST 24 |
Mar 07 01:31:26 PM PST 24 |
26442141219 ps |
| T736 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3174883901 |
|
|
Mar 07 01:12:36 PM PST 24 |
Mar 07 01:14:41 PM PST 24 |
1973489223 ps |
| T737 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3522408529 |
|
|
Mar 07 01:12:26 PM PST 24 |
Mar 07 01:12:43 PM PST 24 |
4708733788 ps |
| T738 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2300650876 |
|
|
Mar 07 01:16:22 PM PST 24 |
Mar 07 03:02:37 PM PST 24 |
54300971051 ps |
| T739 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3341128884 |
|
|
Mar 07 01:16:21 PM PST 24 |
Mar 07 01:20:49 PM PST 24 |
31514676820 ps |
| T740 |
/workspace/coverage/default/19.sram_ctrl_regwen.3627728524 |
|
|
Mar 07 01:12:28 PM PST 24 |
Mar 07 01:19:20 PM PST 24 |
33268950219 ps |
| T741 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.1904652040 |
|
|
Mar 07 01:13:37 PM PST 24 |
Mar 07 01:25:42 PM PST 24 |
90998876840 ps |
| T742 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2421717221 |
|
|
Mar 07 01:13:39 PM PST 24 |
Mar 07 01:15:54 PM PST 24 |
1758827623 ps |
| T743 |
/workspace/coverage/default/45.sram_ctrl_regwen.867087252 |
|
|
Mar 07 01:15:42 PM PST 24 |
Mar 07 01:26:41 PM PST 24 |
2936368374 ps |
| T744 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1931497473 |
|
|
Mar 07 01:13:39 PM PST 24 |
Mar 07 01:13:43 PM PST 24 |
513627013 ps |
| T745 |
/workspace/coverage/default/45.sram_ctrl_bijection.2037320590 |
|
|
Mar 07 01:15:41 PM PST 24 |
Mar 07 02:02:40 PM PST 24 |
220842811231 ps |
| T746 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.218930488 |
|
|
Mar 07 01:13:39 PM PST 24 |
Mar 07 01:13:49 PM PST 24 |
261043825 ps |
| T747 |
/workspace/coverage/default/7.sram_ctrl_bijection.2221827935 |
|
|
Mar 07 01:12:05 PM PST 24 |
Mar 07 01:38:11 PM PST 24 |
335558993529 ps |
| T748 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3871173904 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 01:16:08 PM PST 24 |
1554272221 ps |
| T749 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1463297245 |
|
|
Mar 07 01:11:31 PM PST 24 |
Mar 07 01:11:35 PM PST 24 |
1342184583 ps |
| T750 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2092015350 |
|
|
Mar 07 01:13:39 PM PST 24 |
Mar 07 01:28:52 PM PST 24 |
16096856836 ps |
| T751 |
/workspace/coverage/default/17.sram_ctrl_regwen.1047200601 |
|
|
Mar 07 01:12:23 PM PST 24 |
Mar 07 01:24:38 PM PST 24 |
16119862436 ps |
| T752 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3080248260 |
|
|
Mar 07 01:11:49 PM PST 24 |
Mar 07 01:16:26 PM PST 24 |
18700626048 ps |
| T753 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.4023443164 |
|
|
Mar 07 01:12:23 PM PST 24 |
Mar 07 01:12:52 PM PST 24 |
3394162074 ps |
| T754 |
/workspace/coverage/default/40.sram_ctrl_executable.61468300 |
|
|
Mar 07 01:14:56 PM PST 24 |
Mar 07 01:35:19 PM PST 24 |
8411920207 ps |
| T755 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.447307017 |
|
|
Mar 07 01:13:05 PM PST 24 |
Mar 07 01:20:25 PM PST 24 |
38396325670 ps |
| T756 |
/workspace/coverage/default/49.sram_ctrl_smoke.1782123602 |
|
|
Mar 07 01:16:21 PM PST 24 |
Mar 07 01:16:30 PM PST 24 |
7519689326 ps |
| T757 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.484890466 |
|
|
Mar 07 01:14:08 PM PST 24 |
Mar 07 01:16:58 PM PST 24 |
43014310581 ps |
| T758 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2098996015 |
|
|
Mar 07 01:13:05 PM PST 24 |
Mar 07 01:15:23 PM PST 24 |
5671816874 ps |
| T759 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.911470074 |
|
|
Mar 07 01:12:05 PM PST 24 |
Mar 07 01:14:35 PM PST 24 |
14381095533 ps |
| T760 |
/workspace/coverage/default/3.sram_ctrl_bijection.417541224 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:28:21 PM PST 24 |
55730902730 ps |
| T761 |
/workspace/coverage/default/17.sram_ctrl_stress_all.2301762199 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 03:10:11 PM PST 24 |
855931511849 ps |
| T762 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.935776162 |
|
|
Mar 07 01:15:42 PM PST 24 |
Mar 07 01:16:02 PM PST 24 |
702458865 ps |
| T763 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2899363657 |
|
|
Mar 07 01:12:47 PM PST 24 |
Mar 07 01:12:53 PM PST 24 |
738116480 ps |
| T764 |
/workspace/coverage/default/25.sram_ctrl_partial_access.2407243610 |
|
|
Mar 07 01:13:04 PM PST 24 |
Mar 07 01:13:23 PM PST 24 |
5348160388 ps |
| T765 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3422653513 |
|
|
Mar 07 01:12:51 PM PST 24 |
Mar 07 01:13:09 PM PST 24 |
1645740323 ps |
| T766 |
/workspace/coverage/default/5.sram_ctrl_bijection.2272501187 |
|
|
Mar 07 01:11:43 PM PST 24 |
Mar 07 01:27:52 PM PST 24 |
56016750718 ps |
| T767 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3299353119 |
|
|
Mar 07 01:11:36 PM PST 24 |
Mar 07 01:16:05 PM PST 24 |
19633966564 ps |
| T768 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3878959844 |
|
|
Mar 07 01:12:06 PM PST 24 |
Mar 07 01:17:38 PM PST 24 |
5650489138 ps |
| T769 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1212808455 |
|
|
Mar 07 01:15:48 PM PST 24 |
Mar 07 01:17:02 PM PST 24 |
2471875426 ps |
| T770 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2762053076 |
|
|
Mar 07 01:12:23 PM PST 24 |
Mar 07 01:32:40 PM PST 24 |
37789498899 ps |
| T34 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.675130103 |
|
|
Mar 07 01:11:28 PM PST 24 |
Mar 07 01:11:32 PM PST 24 |
285384520 ps |
| T771 |
/workspace/coverage/default/8.sram_ctrl_smoke.2329543637 |
|
|
Mar 07 01:11:47 PM PST 24 |
Mar 07 01:11:54 PM PST 24 |
2349302065 ps |
| T772 |
/workspace/coverage/default/37.sram_ctrl_executable.700224926 |
|
|
Mar 07 01:14:32 PM PST 24 |
Mar 07 01:30:15 PM PST 24 |
16427943140 ps |
| T773 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.573081667 |
|
|
Mar 07 01:11:30 PM PST 24 |
Mar 07 01:14:43 PM PST 24 |
15547813397 ps |
| T774 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3398654999 |
|
|
Mar 07 01:12:00 PM PST 24 |
Mar 07 01:12:37 PM PST 24 |
769469217 ps |
| T775 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3890893011 |
|
|
Mar 07 01:12:14 PM PST 24 |
Mar 07 01:12:17 PM PST 24 |
364976088 ps |
| T776 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3108048769 |
|
|
Mar 07 01:14:42 PM PST 24 |
Mar 07 01:23:19 PM PST 24 |
22077018144 ps |
| T777 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2663913224 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:12:48 PM PST 24 |
807119135 ps |
| T778 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.4071236748 |
|
|
Mar 07 01:14:35 PM PST 24 |
Mar 07 01:17:48 PM PST 24 |
12174320670 ps |
| T779 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2668498784 |
|
|
Mar 07 01:12:13 PM PST 24 |
Mar 07 01:12:20 PM PST 24 |
1300261851 ps |
| T780 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.178223096 |
|
|
Mar 07 01:12:55 PM PST 24 |
Mar 07 01:15:06 PM PST 24 |
1532207781 ps |
| T781 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1387585907 |
|
|
Mar 07 01:13:55 PM PST 24 |
Mar 07 01:18:22 PM PST 24 |
48447295794 ps |
| T782 |
/workspace/coverage/default/25.sram_ctrl_stress_all.1551767388 |
|
|
Mar 07 01:13:03 PM PST 24 |
Mar 07 03:32:13 PM PST 24 |
4012005946220 ps |
| T783 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2067218325 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:12:33 PM PST 24 |
1118695324 ps |
| T784 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3432392308 |
|
|
Mar 07 01:14:31 PM PST 24 |
Mar 07 01:15:09 PM PST 24 |
718376196 ps |
| T785 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2544459795 |
|
|
Mar 07 01:12:54 PM PST 24 |
Mar 07 02:04:36 PM PST 24 |
219476216176 ps |
| T786 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2339657177 |
|
|
Mar 07 01:13:22 PM PST 24 |
Mar 07 01:13:43 PM PST 24 |
2569081789 ps |
| T787 |
/workspace/coverage/default/9.sram_ctrl_alert_test.3649432578 |
|
|
Mar 07 01:12:09 PM PST 24 |
Mar 07 01:12:10 PM PST 24 |
30624925 ps |
| T788 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.3409436437 |
|
|
Mar 07 01:15:06 PM PST 24 |
Mar 07 01:19:33 PM PST 24 |
47784055496 ps |
| T789 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2486671496 |
|
|
Mar 07 01:11:53 PM PST 24 |
Mar 07 01:11:54 PM PST 24 |
35182111 ps |