| T790 |
/workspace/coverage/default/33.sram_ctrl_bijection.773789176 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 01:36:04 PM PST 24 |
133498555445 ps |
| T791 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1285002895 |
|
|
Mar 07 01:12:02 PM PST 24 |
Mar 07 01:13:07 PM PST 24 |
3957664966 ps |
| T792 |
/workspace/coverage/default/10.sram_ctrl_bijection.2516765999 |
|
|
Mar 07 01:12:00 PM PST 24 |
Mar 07 01:43:54 PM PST 24 |
111453776973 ps |
| T793 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.220579087 |
|
|
Mar 07 01:12:45 PM PST 24 |
Mar 07 01:13:04 PM PST 24 |
2924885771 ps |
| T794 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1157805425 |
|
|
Mar 07 01:14:05 PM PST 24 |
Mar 07 01:18:34 PM PST 24 |
63801388390 ps |
| T795 |
/workspace/coverage/default/19.sram_ctrl_executable.3193252758 |
|
|
Mar 07 01:12:30 PM PST 24 |
Mar 07 01:34:08 PM PST 24 |
70514833180 ps |
| T796 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.117446334 |
|
|
Mar 07 01:14:58 PM PST 24 |
Mar 07 01:15:55 PM PST 24 |
4156832148 ps |
| T797 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.323550763 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:16:56 PM PST 24 |
45948264929 ps |
| T798 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2985105300 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:12:05 PM PST 24 |
726650229 ps |
| T799 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.844674722 |
|
|
Mar 07 01:16:21 PM PST 24 |
Mar 07 01:21:02 PM PST 24 |
12811857285 ps |
| T800 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.3987146643 |
|
|
Mar 07 01:13:24 PM PST 24 |
Mar 07 01:18:13 PM PST 24 |
10089399894 ps |
| T801 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2820590230 |
|
|
Mar 07 01:12:48 PM PST 24 |
Mar 07 01:15:19 PM PST 24 |
9738592338 ps |
| T802 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2087972716 |
|
|
Mar 07 01:13:22 PM PST 24 |
Mar 07 01:14:40 PM PST 24 |
2479604041 ps |
| T803 |
/workspace/coverage/default/41.sram_ctrl_smoke.2313705401 |
|
|
Mar 07 01:14:56 PM PST 24 |
Mar 07 01:16:02 PM PST 24 |
768303711 ps |
| T804 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3702153233 |
|
|
Mar 07 01:11:59 PM PST 24 |
Mar 07 01:13:52 PM PST 24 |
5352640958 ps |
| T805 |
/workspace/coverage/default/21.sram_ctrl_executable.3905313410 |
|
|
Mar 07 01:12:40 PM PST 24 |
Mar 07 01:21:10 PM PST 24 |
110129162667 ps |
| T806 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1893036147 |
|
|
Mar 07 01:12:13 PM PST 24 |
Mar 07 01:17:18 PM PST 24 |
20634657858 ps |
| T807 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1913182090 |
|
|
Mar 07 01:11:52 PM PST 24 |
Mar 07 01:17:36 PM PST 24 |
24186950437 ps |
| T808 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1927483587 |
|
|
Mar 07 01:12:10 PM PST 24 |
Mar 07 01:13:08 PM PST 24 |
1576550596 ps |
| T809 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.913034521 |
|
|
Mar 07 01:16:12 PM PST 24 |
Mar 07 01:17:17 PM PST 24 |
8353937497 ps |
| T810 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.4068557970 |
|
|
Mar 07 01:13:24 PM PST 24 |
Mar 07 01:50:10 PM PST 24 |
117501371986 ps |
| T811 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3532573331 |
|
|
Mar 07 01:15:29 PM PST 24 |
Mar 07 01:17:32 PM PST 24 |
4028043634 ps |
| T812 |
/workspace/coverage/default/33.sram_ctrl_partial_access.3081828643 |
|
|
Mar 07 01:13:55 PM PST 24 |
Mar 07 01:14:12 PM PST 24 |
573132789 ps |
| T813 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4619223 |
|
|
Mar 07 01:14:41 PM PST 24 |
Mar 07 01:17:24 PM PST 24 |
1137476472 ps |
| T814 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2292434516 |
|
|
Mar 07 01:15:15 PM PST 24 |
Mar 07 01:23:40 PM PST 24 |
45801618371 ps |
| T815 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1567320031 |
|
|
Mar 07 01:12:09 PM PST 24 |
Mar 07 01:12:13 PM PST 24 |
1875335040 ps |
| T816 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.951471250 |
|
|
Mar 07 01:13:05 PM PST 24 |
Mar 07 01:13:53 PM PST 24 |
10772448176 ps |
| T817 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2581817182 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:17:44 PM PST 24 |
217913379080 ps |
| T818 |
/workspace/coverage/default/25.sram_ctrl_regwen.3675431007 |
|
|
Mar 07 01:13:05 PM PST 24 |
Mar 07 01:16:40 PM PST 24 |
2138796816 ps |
| T819 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1288010997 |
|
|
Mar 07 01:11:56 PM PST 24 |
Mar 07 01:12:24 PM PST 24 |
3202315184 ps |
| T820 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3723651493 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:12:26 PM PST 24 |
39350263 ps |
| T821 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.167063868 |
|
|
Mar 07 01:13:55 PM PST 24 |
Mar 07 01:14:43 PM PST 24 |
3241029303 ps |
| T822 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3860636049 |
|
|
Mar 07 01:13:42 PM PST 24 |
Mar 07 01:16:04 PM PST 24 |
949658701 ps |
| T823 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1287341138 |
|
|
Mar 07 01:12:50 PM PST 24 |
Mar 07 01:12:51 PM PST 24 |
42467779 ps |
| T824 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1493554279 |
|
|
Mar 07 01:15:32 PM PST 24 |
Mar 07 01:18:11 PM PST 24 |
19815222786 ps |
| T825 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2028141344 |
|
|
Mar 07 01:13:44 PM PST 24 |
Mar 07 01:27:09 PM PST 24 |
6978823762 ps |
| T826 |
/workspace/coverage/default/29.sram_ctrl_regwen.3838386952 |
|
|
Mar 07 01:13:42 PM PST 24 |
Mar 07 01:34:48 PM PST 24 |
106669964366 ps |
| T827 |
/workspace/coverage/default/40.sram_ctrl_alert_test.1865789164 |
|
|
Mar 07 01:14:58 PM PST 24 |
Mar 07 01:14:58 PM PST 24 |
13921290 ps |
| T828 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2584091319 |
|
|
Mar 07 01:16:24 PM PST 24 |
Mar 07 01:16:25 PM PST 24 |
53809332 ps |
| T829 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3636372222 |
|
|
Mar 07 01:11:48 PM PST 24 |
Mar 07 01:12:13 PM PST 24 |
893619555 ps |
| T830 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.1355545220 |
|
|
Mar 07 01:13:23 PM PST 24 |
Mar 07 01:15:57 PM PST 24 |
9324763093 ps |
| T831 |
/workspace/coverage/default/36.sram_ctrl_partial_access.4218658015 |
|
|
Mar 07 01:14:25 PM PST 24 |
Mar 07 01:14:30 PM PST 24 |
578176489 ps |
| T832 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.2583465433 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:16:33 PM PST 24 |
17135245069 ps |
| T833 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2672816141 |
|
|
Mar 07 01:12:44 PM PST 24 |
Mar 07 01:13:18 PM PST 24 |
3974522001 ps |
| T834 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2644310870 |
|
|
Mar 07 01:11:33 PM PST 24 |
Mar 07 01:14:31 PM PST 24 |
13148870257 ps |
| T835 |
/workspace/coverage/default/21.sram_ctrl_stress_all.1334493861 |
|
|
Mar 07 01:12:41 PM PST 24 |
Mar 07 02:23:47 PM PST 24 |
293275635964 ps |
| T836 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2586035819 |
|
|
Mar 07 01:12:48 PM PST 24 |
Mar 07 01:12:49 PM PST 24 |
37966807 ps |
| T837 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2307250342 |
|
|
Mar 07 01:12:16 PM PST 24 |
Mar 07 01:12:51 PM PST 24 |
769218662 ps |
| T838 |
/workspace/coverage/default/13.sram_ctrl_regwen.2155736098 |
|
|
Mar 07 01:12:10 PM PST 24 |
Mar 07 01:29:04 PM PST 24 |
18146833169 ps |
| T839 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1059705348 |
|
|
Mar 07 01:13:24 PM PST 24 |
Mar 07 01:16:11 PM PST 24 |
3183096588 ps |
| T840 |
/workspace/coverage/default/38.sram_ctrl_regwen.2894660089 |
|
|
Mar 07 01:14:48 PM PST 24 |
Mar 07 01:22:48 PM PST 24 |
28247642707 ps |
| T841 |
/workspace/coverage/default/18.sram_ctrl_executable.486913868 |
|
|
Mar 07 01:12:28 PM PST 24 |
Mar 07 01:22:47 PM PST 24 |
14464936005 ps |
| T842 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.748496048 |
|
|
Mar 07 01:13:04 PM PST 24 |
Mar 07 01:13:31 PM PST 24 |
962167717 ps |
| T843 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3726577997 |
|
|
Mar 07 01:14:32 PM PST 24 |
Mar 07 01:36:05 PM PST 24 |
114099334647 ps |
| T844 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.45501649 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:15:11 PM PST 24 |
819318332 ps |
| T845 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.421613725 |
|
|
Mar 07 01:13:05 PM PST 24 |
Mar 07 01:33:13 PM PST 24 |
45033794026 ps |
| T846 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2140319998 |
|
|
Mar 07 01:16:12 PM PST 24 |
Mar 07 01:20:49 PM PST 24 |
14061422001 ps |
| T847 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3380903753 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:12:46 PM PST 24 |
2117798075 ps |
| T848 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1929715905 |
|
|
Mar 07 01:12:57 PM PST 24 |
Mar 07 01:15:56 PM PST 24 |
7416496837 ps |
| T849 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.3961008139 |
|
|
Mar 07 01:11:42 PM PST 24 |
Mar 07 01:16:44 PM PST 24 |
73283260820 ps |
| T850 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2598954000 |
|
|
Mar 07 01:15:07 PM PST 24 |
Mar 07 01:15:55 PM PST 24 |
1504438499 ps |
| T851 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2030362867 |
|
|
Mar 07 01:12:28 PM PST 24 |
Mar 07 01:12:32 PM PST 24 |
1341436431 ps |
| T852 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2680888294 |
|
|
Mar 07 01:12:51 PM PST 24 |
Mar 07 01:13:01 PM PST 24 |
1852421487 ps |
| T853 |
/workspace/coverage/default/44.sram_ctrl_bijection.2698956981 |
|
|
Mar 07 01:15:32 PM PST 24 |
Mar 07 01:32:46 PM PST 24 |
63554369722 ps |
| T854 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.4260848263 |
|
|
Mar 07 01:15:15 PM PST 24 |
Mar 07 01:30:39 PM PST 24 |
50338043382 ps |
| T855 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.244458071 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:17:56 PM PST 24 |
4606662801 ps |
| T856 |
/workspace/coverage/default/47.sram_ctrl_smoke.1832445709 |
|
|
Mar 07 01:16:06 PM PST 24 |
Mar 07 01:18:12 PM PST 24 |
2656987989 ps |
| T857 |
/workspace/coverage/default/32.sram_ctrl_regwen.3324871931 |
|
|
Mar 07 01:13:58 PM PST 24 |
Mar 07 01:29:11 PM PST 24 |
35349824672 ps |
| T858 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.2006894069 |
|
|
Mar 07 01:15:05 PM PST 24 |
Mar 07 01:37:21 PM PST 24 |
61907884141 ps |
| T859 |
/workspace/coverage/default/28.sram_ctrl_regwen.1721351846 |
|
|
Mar 07 01:13:38 PM PST 24 |
Mar 07 01:23:41 PM PST 24 |
38918393093 ps |
| T860 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.719494162 |
|
|
Mar 07 01:15:39 PM PST 24 |
Mar 07 01:18:15 PM PST 24 |
9409697261 ps |
| T861 |
/workspace/coverage/default/19.sram_ctrl_smoke.1046835576 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:12:57 PM PST 24 |
1617283649 ps |
| T862 |
/workspace/coverage/default/29.sram_ctrl_alert_test.962080004 |
|
|
Mar 07 01:13:40 PM PST 24 |
Mar 07 01:13:41 PM PST 24 |
22801858 ps |
| T863 |
/workspace/coverage/default/23.sram_ctrl_smoke.1259368581 |
|
|
Mar 07 01:12:51 PM PST 24 |
Mar 07 01:15:37 PM PST 24 |
1564491937 ps |
| T864 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3647510334 |
|
|
Mar 07 01:13:38 PM PST 24 |
Mar 07 01:21:06 PM PST 24 |
19726491099 ps |
| T865 |
/workspace/coverage/default/31.sram_ctrl_executable.2918404657 |
|
|
Mar 07 01:13:43 PM PST 24 |
Mar 07 01:15:26 PM PST 24 |
5637238226 ps |
| T866 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.801753704 |
|
|
Mar 07 01:16:01 PM PST 24 |
Mar 07 01:22:38 PM PST 24 |
19679030525 ps |
| T867 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.461647035 |
|
|
Mar 07 01:12:24 PM PST 24 |
Mar 07 01:16:16 PM PST 24 |
8378336496 ps |
| T868 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3408816976 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:12:14 PM PST 24 |
1400489387 ps |
| T869 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3790282578 |
|
|
Mar 07 01:12:39 PM PST 24 |
Mar 07 01:14:56 PM PST 24 |
3527038914 ps |
| T870 |
/workspace/coverage/default/32.sram_ctrl_smoke.3449469064 |
|
|
Mar 07 01:13:55 PM PST 24 |
Mar 07 01:14:05 PM PST 24 |
4160596524 ps |
| T871 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2741533170 |
|
|
Mar 07 01:11:37 PM PST 24 |
Mar 07 01:23:33 PM PST 24 |
11744709720 ps |
| T872 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3520151219 |
|
|
Mar 07 01:14:21 PM PST 24 |
Mar 07 01:30:18 PM PST 24 |
137293527592 ps |
| T873 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.712667629 |
|
|
Mar 07 01:14:48 PM PST 24 |
Mar 07 01:44:54 PM PST 24 |
31974096582 ps |
| T874 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3618370032 |
|
|
Mar 07 01:13:40 PM PST 24 |
Mar 07 01:18:53 PM PST 24 |
4653379244 ps |
| T875 |
/workspace/coverage/default/29.sram_ctrl_smoke.1426856417 |
|
|
Mar 07 01:13:43 PM PST 24 |
Mar 07 01:14:01 PM PST 24 |
1034663650 ps |
| T876 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.4219014444 |
|
|
Mar 07 01:13:58 PM PST 24 |
Mar 07 01:17:39 PM PST 24 |
20230824844 ps |
| T877 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.736963956 |
|
|
Mar 07 01:11:40 PM PST 24 |
Mar 07 01:19:15 PM PST 24 |
35114815705 ps |
| T878 |
/workspace/coverage/default/12.sram_ctrl_smoke.1657401621 |
|
|
Mar 07 01:12:08 PM PST 24 |
Mar 07 01:12:14 PM PST 24 |
713066306 ps |
| T879 |
/workspace/coverage/default/16.sram_ctrl_regwen.197431510 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:26:34 PM PST 24 |
10823723630 ps |
| T880 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1893786222 |
|
|
Mar 07 01:15:40 PM PST 24 |
Mar 07 01:16:46 PM PST 24 |
3782519362 ps |
| T881 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.27868985 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:42:25 PM PST 24 |
87718760402 ps |
| T882 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.310982447 |
|
|
Mar 07 01:16:01 PM PST 24 |
Mar 07 01:21:48 PM PST 24 |
187844820977 ps |
| T883 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.2407889079 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:15:40 PM PST 24 |
3942487934 ps |
| T884 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3472910470 |
|
|
Mar 07 01:13:39 PM PST 24 |
Mar 07 01:16:23 PM PST 24 |
9991930960 ps |
| T885 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.4011230176 |
|
|
Mar 07 01:14:43 PM PST 24 |
Mar 07 01:28:38 PM PST 24 |
54270262474 ps |
| T886 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.4256784096 |
|
|
Mar 07 01:12:13 PM PST 24 |
Mar 07 01:13:32 PM PST 24 |
7558122593 ps |
| T887 |
/workspace/coverage/default/13.sram_ctrl_partial_access.400712935 |
|
|
Mar 07 01:12:17 PM PST 24 |
Mar 07 01:12:30 PM PST 24 |
896411330 ps |
| T888 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3902628894 |
|
|
Mar 07 01:13:06 PM PST 24 |
Mar 07 01:17:11 PM PST 24 |
8210153090 ps |
| T889 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.395739413 |
|
|
Mar 07 01:11:28 PM PST 24 |
Mar 07 01:16:34 PM PST 24 |
63182281826 ps |
| T890 |
/workspace/coverage/default/26.sram_ctrl_alert_test.1726831400 |
|
|
Mar 07 01:13:26 PM PST 24 |
Mar 07 01:13:27 PM PST 24 |
13670556 ps |
| T891 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.777777843 |
|
|
Mar 07 01:11:57 PM PST 24 |
Mar 07 01:20:24 PM PST 24 |
86783070812 ps |
| T892 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3026981814 |
|
|
Mar 07 01:11:42 PM PST 24 |
Mar 07 01:13:55 PM PST 24 |
2155829611 ps |
| T893 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3171989890 |
|
|
Mar 07 01:12:00 PM PST 24 |
Mar 07 01:12:32 PM PST 24 |
3463377903 ps |
| T894 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3437004693 |
|
|
Mar 07 01:12:05 PM PST 24 |
Mar 07 01:13:20 PM PST 24 |
9427966618 ps |
| T895 |
/workspace/coverage/default/35.sram_ctrl_regwen.3859893964 |
|
|
Mar 07 01:14:21 PM PST 24 |
Mar 07 01:30:15 PM PST 24 |
13954339398 ps |
| T896 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.900926297 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:12:30 PM PST 24 |
357549961 ps |
| T897 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3644473142 |
|
|
Mar 07 01:12:12 PM PST 24 |
Mar 07 01:12:16 PM PST 24 |
345404126 ps |
| T898 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1916615444 |
|
|
Mar 07 01:11:49 PM PST 24 |
Mar 07 01:12:49 PM PST 24 |
754348552 ps |
| T899 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.498354492 |
|
|
Mar 07 01:12:51 PM PST 24 |
Mar 07 01:13:40 PM PST 24 |
2937114726 ps |
| T900 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.2517300030 |
|
|
Mar 07 01:11:44 PM PST 24 |
Mar 07 01:13:52 PM PST 24 |
7592410708 ps |
| T901 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2282023689 |
|
|
Mar 07 01:14:23 PM PST 24 |
Mar 07 01:32:18 PM PST 24 |
84544158002 ps |
| T902 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.879480297 |
|
|
Mar 07 01:11:50 PM PST 24 |
Mar 07 01:11:53 PM PST 24 |
347221538 ps |
| T903 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.963005348 |
|
|
Mar 07 01:16:01 PM PST 24 |
Mar 07 01:32:25 PM PST 24 |
34876079428 ps |
| T904 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1548594626 |
|
|
Mar 07 01:12:24 PM PST 24 |
Mar 07 01:13:43 PM PST 24 |
8320661242 ps |
| T905 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2246920728 |
|
|
Mar 07 01:14:09 PM PST 24 |
Mar 07 01:15:45 PM PST 24 |
743530317 ps |
| T906 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.164948286 |
|
|
Mar 07 01:13:40 PM PST 24 |
Mar 07 01:19:37 PM PST 24 |
117083386790 ps |
| T907 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4075394972 |
|
|
Mar 07 01:11:56 PM PST 24 |
Mar 07 01:17:16 PM PST 24 |
29023664498 ps |
| T908 |
/workspace/coverage/default/21.sram_ctrl_bijection.949990221 |
|
|
Mar 07 01:12:41 PM PST 24 |
Mar 07 01:50:12 PM PST 24 |
33124675627 ps |
| T909 |
/workspace/coverage/default/49.sram_ctrl_bijection.4242247480 |
|
|
Mar 07 01:16:23 PM PST 24 |
Mar 07 01:29:59 PM PST 24 |
13052514715 ps |
| T910 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.881002188 |
|
|
Mar 07 01:12:24 PM PST 24 |
Mar 07 01:14:44 PM PST 24 |
18151517713 ps |
| T911 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4168993663 |
|
|
Mar 07 01:15:49 PM PST 24 |
Mar 07 01:43:00 PM PST 24 |
26775481449 ps |
| T912 |
/workspace/coverage/default/41.sram_ctrl_partial_access.2258728139 |
|
|
Mar 07 01:14:57 PM PST 24 |
Mar 07 01:15:23 PM PST 24 |
10039086101 ps |
| T913 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.4066482789 |
|
|
Mar 07 01:12:51 PM PST 24 |
Mar 07 01:20:10 PM PST 24 |
18555375211 ps |
| T914 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1063473263 |
|
|
Mar 07 01:11:48 PM PST 24 |
Mar 07 01:14:07 PM PST 24 |
8701407127 ps |
| T915 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1594660071 |
|
|
Mar 07 01:11:57 PM PST 24 |
Mar 07 01:12:01 PM PST 24 |
5612318179 ps |
| T916 |
/workspace/coverage/default/27.sram_ctrl_smoke.2599698138 |
|
|
Mar 07 01:13:23 PM PST 24 |
Mar 07 01:14:42 PM PST 24 |
3291414875 ps |
| T917 |
/workspace/coverage/default/41.sram_ctrl_bijection.1573262336 |
|
|
Mar 07 01:15:02 PM PST 24 |
Mar 07 01:23:00 PM PST 24 |
137814647157 ps |
| T918 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.563649706 |
|
|
Mar 07 01:14:24 PM PST 24 |
Mar 07 01:17:04 PM PST 24 |
3060359094 ps |
| T919 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2133997505 |
|
|
Mar 07 01:11:59 PM PST 24 |
Mar 07 01:14:03 PM PST 24 |
11412827534 ps |
| T920 |
/workspace/coverage/default/25.sram_ctrl_executable.1858870017 |
|
|
Mar 07 01:13:04 PM PST 24 |
Mar 07 01:35:19 PM PST 24 |
18679982443 ps |
| T921 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.779173100 |
|
|
Mar 07 01:16:11 PM PST 24 |
Mar 07 01:17:15 PM PST 24 |
3816056452 ps |
| T922 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1133836792 |
|
|
Mar 07 01:16:10 PM PST 24 |
Mar 07 01:38:32 PM PST 24 |
23888773271 ps |
| T923 |
/workspace/coverage/default/40.sram_ctrl_regwen.2647888841 |
|
|
Mar 07 01:14:55 PM PST 24 |
Mar 07 01:19:55 PM PST 24 |
17955945175 ps |
| T924 |
/workspace/coverage/default/9.sram_ctrl_partial_access.4149532695 |
|
|
Mar 07 01:11:58 PM PST 24 |
Mar 07 01:12:32 PM PST 24 |
1048114229 ps |
| T89 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3196355668 |
|
|
Mar 07 12:53:37 PM PST 24 |
Mar 07 12:53:38 PM PST 24 |
21533097 ps |
| T60 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3787408315 |
|
|
Mar 07 12:53:12 PM PST 24 |
Mar 07 12:53:59 PM PST 24 |
14770203655 ps |
| T925 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2259775372 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:53:27 PM PST 24 |
466848992 ps |
| T61 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4061207676 |
|
|
Mar 07 12:53:44 PM PST 24 |
Mar 07 12:53:45 PM PST 24 |
32595365 ps |
| T62 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1621055822 |
|
|
Mar 07 12:53:37 PM PST 24 |
Mar 07 12:53:38 PM PST 24 |
20365241 ps |
| T63 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1253686764 |
|
|
Mar 07 12:53:36 PM PST 24 |
Mar 07 12:54:07 PM PST 24 |
14767202698 ps |
| T64 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.785375703 |
|
|
Mar 07 12:53:37 PM PST 24 |
Mar 07 12:53:38 PM PST 24 |
30678573 ps |
| T98 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3688185520 |
|
|
Mar 07 12:53:32 PM PST 24 |
Mar 07 12:53:34 PM PST 24 |
137232611 ps |
| T926 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2749200657 |
|
|
Mar 07 12:53:08 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
33599412 ps |
| T65 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2727243116 |
|
|
Mar 07 12:53:47 PM PST 24 |
Mar 07 12:54:18 PM PST 24 |
16812446929 ps |
| T927 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3693849713 |
|
|
Mar 07 12:53:39 PM PST 24 |
Mar 07 12:53:44 PM PST 24 |
1510030825 ps |
| T928 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1012152840 |
|
|
Mar 07 12:53:17 PM PST 24 |
Mar 07 12:53:22 PM PST 24 |
574026219 ps |
| T929 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2826699857 |
|
|
Mar 07 12:53:18 PM PST 24 |
Mar 07 12:53:20 PM PST 24 |
345941131 ps |
| T930 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2914944198 |
|
|
Mar 07 12:53:38 PM PST 24 |
Mar 07 12:53:44 PM PST 24 |
140599222 ps |
| T931 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.392646826 |
|
|
Mar 07 12:53:17 PM PST 24 |
Mar 07 12:53:25 PM PST 24 |
361867942 ps |
| T932 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2815375356 |
|
|
Mar 07 12:53:44 PM PST 24 |
Mar 07 12:53:47 PM PST 24 |
341712631 ps |
| T99 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4047757727 |
|
|
Mar 07 12:53:38 PM PST 24 |
Mar 07 12:53:41 PM PST 24 |
752476554 ps |
| T100 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1897431635 |
|
|
Mar 07 12:53:30 PM PST 24 |
Mar 07 12:53:33 PM PST 24 |
304341389 ps |
| T933 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.724739999 |
|
|
Mar 07 12:53:16 PM PST 24 |
Mar 07 12:53:23 PM PST 24 |
125869605 ps |
| T97 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3372006096 |
|
|
Mar 07 12:53:42 PM PST 24 |
Mar 07 12:53:43 PM PST 24 |
74343109 ps |
| T90 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3894522050 |
|
|
Mar 07 12:53:09 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
11895246 ps |
| T91 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1813677967 |
|
|
Mar 07 12:53:45 PM PST 24 |
Mar 07 12:53:46 PM PST 24 |
12350647 ps |
| T934 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.344243806 |
|
|
Mar 07 12:53:22 PM PST 24 |
Mar 07 12:53:24 PM PST 24 |
24664834 ps |
| T935 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2962192796 |
|
|
Mar 07 12:53:38 PM PST 24 |
Mar 07 12:53:43 PM PST 24 |
481338899 ps |
| T119 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.810598952 |
|
|
Mar 07 12:53:06 PM PST 24 |
Mar 07 12:53:09 PM PST 24 |
661507641 ps |
| T936 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3630594431 |
|
|
Mar 07 12:53:43 PM PST 24 |
Mar 07 12:53:47 PM PST 24 |
352726287 ps |
| T937 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3775922984 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:53:28 PM PST 24 |
545766813 ps |
| T66 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3428790498 |
|
|
Mar 07 12:53:36 PM PST 24 |
Mar 07 12:54:03 PM PST 24 |
3848885287 ps |
| T938 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.375256334 |
|
|
Mar 07 12:53:43 PM PST 24 |
Mar 07 12:53:43 PM PST 24 |
45829280 ps |
| T939 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2224198650 |
|
|
Mar 07 12:53:34 PM PST 24 |
Mar 07 12:53:38 PM PST 24 |
697425190 ps |
| T940 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.662048430 |
|
|
Mar 07 12:53:39 PM PST 24 |
Mar 07 12:53:41 PM PST 24 |
130295001 ps |
| T941 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.669714082 |
|
|
Mar 07 12:53:31 PM PST 24 |
Mar 07 12:53:37 PM PST 24 |
713074203 ps |
| T942 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3062606595 |
|
|
Mar 07 12:53:08 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
550162286 ps |
| T943 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1076043252 |
|
|
Mar 07 12:53:18 PM PST 24 |
Mar 07 12:53:22 PM PST 24 |
145162585 ps |
| T113 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2749375506 |
|
|
Mar 07 12:53:28 PM PST 24 |
Mar 07 12:53:31 PM PST 24 |
258547361 ps |
| T67 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1750730752 |
|
|
Mar 07 12:53:33 PM PST 24 |
Mar 07 12:53:34 PM PST 24 |
10941800 ps |
| T68 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3623899850 |
|
|
Mar 07 12:53:11 PM PST 24 |
Mar 07 12:53:12 PM PST 24 |
31679988 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3438670985 |
|
|
Mar 07 12:53:27 PM PST 24 |
Mar 07 12:53:53 PM PST 24 |
9555837785 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1303390083 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:53:50 PM PST 24 |
3768764926 ps |
| T114 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.581320231 |
|
|
Mar 07 12:53:42 PM PST 24 |
Mar 07 12:53:44 PM PST 24 |
601651471 ps |
| T79 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.564582800 |
|
|
Mar 07 12:53:40 PM PST 24 |
Mar 07 12:53:41 PM PST 24 |
19517241 ps |
| T945 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.420881133 |
|
|
Mar 07 12:53:22 PM PST 24 |
Mar 07 12:53:25 PM PST 24 |
48063202 ps |
| T70 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2196972733 |
|
|
Mar 07 12:53:21 PM PST 24 |
Mar 07 12:53:22 PM PST 24 |
26727966 ps |
| T946 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1151305846 |
|
|
Mar 07 12:53:51 PM PST 24 |
Mar 07 12:54:20 PM PST 24 |
4926489384 ps |
| T71 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2915897715 |
|
|
Mar 07 12:53:40 PM PST 24 |
Mar 07 12:53:41 PM PST 24 |
12482620 ps |
| T947 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.433540815 |
|
|
Mar 07 12:53:34 PM PST 24 |
Mar 07 12:53:34 PM PST 24 |
26729216 ps |
| T948 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2508903949 |
|
|
Mar 07 12:53:30 PM PST 24 |
Mar 07 12:53:33 PM PST 24 |
703473318 ps |
| T949 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3100830949 |
|
|
Mar 07 12:53:33 PM PST 24 |
Mar 07 12:53:34 PM PST 24 |
41204776 ps |
| T950 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2996859434 |
|
|
Mar 07 12:53:39 PM PST 24 |
Mar 07 12:53:42 PM PST 24 |
266904961 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2314420391 |
|
|
Mar 07 12:53:07 PM PST 24 |
Mar 07 12:53:09 PM PST 24 |
87897332 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2375312970 |
|
|
Mar 07 12:53:14 PM PST 24 |
Mar 07 12:53:14 PM PST 24 |
36316782 ps |
| T121 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.788200379 |
|
|
Mar 07 12:53:42 PM PST 24 |
Mar 07 12:53:45 PM PST 24 |
481762082 ps |
| T953 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2323105418 |
|
|
Mar 07 12:53:35 PM PST 24 |
Mar 07 12:53:36 PM PST 24 |
16042172 ps |
| T954 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2456469117 |
|
|
Mar 07 12:53:40 PM PST 24 |
Mar 07 12:53:41 PM PST 24 |
28823762 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.236037245 |
|
|
Mar 07 12:53:38 PM PST 24 |
Mar 07 12:53:42 PM PST 24 |
460183046 ps |
| T72 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.708012661 |
|
|
Mar 07 12:53:39 PM PST 24 |
Mar 07 12:54:07 PM PST 24 |
7375866086 ps |
| T956 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.808236714 |
|
|
Mar 07 12:53:28 PM PST 24 |
Mar 07 12:53:29 PM PST 24 |
34959935 ps |
| T957 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.717359525 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:53:26 PM PST 24 |
150952229 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2849833597 |
|
|
Mar 07 12:53:20 PM PST 24 |
Mar 07 12:53:21 PM PST 24 |
24491516 ps |
| T959 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.76097942 |
|
|
Mar 07 12:53:42 PM PST 24 |
Mar 07 12:53:46 PM PST 24 |
355391235 ps |
| T960 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3514600522 |
|
|
Mar 07 12:53:38 PM PST 24 |
Mar 07 12:53:43 PM PST 24 |
708980185 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.868098199 |
|
|
Mar 07 12:53:35 PM PST 24 |
Mar 07 12:53:38 PM PST 24 |
153131384 ps |
| T962 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3019574661 |
|
|
Mar 07 12:53:51 PM PST 24 |
Mar 07 12:54:43 PM PST 24 |
14698066913 ps |
| T963 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.132141598 |
|
|
Mar 07 12:53:11 PM PST 24 |
Mar 07 12:53:12 PM PST 24 |
35408072 ps |
| T964 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3722448806 |
|
|
Mar 07 12:53:44 PM PST 24 |
Mar 07 12:53:45 PM PST 24 |
25913002 ps |
| T120 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.912044633 |
|
|
Mar 07 12:53:40 PM PST 24 |
Mar 07 12:53:41 PM PST 24 |
346329882 ps |
| T965 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1776852922 |
|
|
Mar 07 12:53:32 PM PST 24 |
Mar 07 12:53:38 PM PST 24 |
1238078528 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.901931248 |
|
|
Mar 07 12:53:45 PM PST 24 |
Mar 07 12:53:49 PM PST 24 |
143097358 ps |
| T967 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3693307418 |
|
|
Mar 07 12:53:42 PM PST 24 |
Mar 07 12:53:43 PM PST 24 |
78130872 ps |
| T115 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1971030972 |
|
|
Mar 07 12:53:55 PM PST 24 |
Mar 07 12:53:56 PM PST 24 |
353326276 ps |
| T968 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1485109005 |
|
|
Mar 07 12:53:34 PM PST 24 |
Mar 07 12:53:35 PM PST 24 |
14699658 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2122493635 |
|
|
Mar 07 12:53:09 PM PST 24 |
Mar 07 12:53:10 PM PST 24 |
30844270 ps |
| T970 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3611361429 |
|
|
Mar 07 12:53:13 PM PST 24 |
Mar 07 12:53:16 PM PST 24 |
856788743 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2992524140 |
|
|
Mar 07 12:53:42 PM PST 24 |
Mar 07 12:54:09 PM PST 24 |
4951698162 ps |
| T972 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3141575783 |
|
|
Mar 07 12:53:27 PM PST 24 |
Mar 07 12:53:32 PM PST 24 |
1471667762 ps |
| T973 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1695024910 |
|
|
Mar 07 12:53:48 PM PST 24 |
Mar 07 12:53:49 PM PST 24 |
27834489 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3262790085 |
|
|
Mar 07 12:53:27 PM PST 24 |
Mar 07 12:53:28 PM PST 24 |
63611156 ps |
| T80 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.958551069 |
|
|
Mar 07 12:53:38 PM PST 24 |
Mar 07 12:54:05 PM PST 24 |
7713688820 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.670145585 |
|
|
Mar 07 12:53:33 PM PST 24 |
Mar 07 12:53:36 PM PST 24 |
658962521 ps |
| T975 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2792042708 |
|
|
Mar 07 12:53:45 PM PST 24 |
Mar 07 12:53:46 PM PST 24 |
22829330 ps |
| T81 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.576888116 |
|
|
Mar 07 12:53:33 PM PST 24 |
Mar 07 12:53:34 PM PST 24 |
19172404 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2926115577 |
|
|
Mar 07 12:53:31 PM PST 24 |
Mar 07 12:53:34 PM PST 24 |
78024299 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2517678041 |
|
|
Mar 07 12:53:40 PM PST 24 |
Mar 07 12:53:42 PM PST 24 |
368472173 ps |
| T978 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2875445915 |
|
|
Mar 07 12:53:42 PM PST 24 |
Mar 07 12:53:44 PM PST 24 |
249064318 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3389088386 |
|
|
Mar 07 12:53:38 PM PST 24 |
Mar 07 12:53:40 PM PST 24 |
183308915 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3671446732 |
|
|
Mar 07 12:53:16 PM PST 24 |
Mar 07 12:53:17 PM PST 24 |
29220976 ps |
| T981 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2280405254 |
|
|
Mar 07 12:53:48 PM PST 24 |
Mar 07 12:53:52 PM PST 24 |
355240017 ps |
| T982 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2515243223 |
|
|
Mar 07 12:53:40 PM PST 24 |
Mar 07 12:53:43 PM PST 24 |
1360865954 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2199588010 |
|
|
Mar 07 12:53:34 PM PST 24 |
Mar 07 12:53:35 PM PST 24 |
20867814 ps |
| T87 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.474979233 |
|
|
Mar 07 12:53:30 PM PST 24 |
Mar 07 12:53:58 PM PST 24 |
7516465887 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4144622834 |
|
|
Mar 07 12:53:32 PM PST 24 |
Mar 07 12:53:33 PM PST 24 |
49199953 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3056690308 |
|
|
Mar 07 12:53:17 PM PST 24 |
Mar 07 12:53:18 PM PST 24 |
131691993 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1282283047 |
|
|
Mar 07 12:53:29 PM PST 24 |
Mar 07 12:53:33 PM PST 24 |
2136313513 ps |
| T987 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4189194573 |
|
|
Mar 07 12:53:30 PM PST 24 |
Mar 07 12:53:36 PM PST 24 |
6900027667 ps |
| T988 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2087856673 |
|
|
Mar 07 12:53:48 PM PST 24 |
Mar 07 12:53:51 PM PST 24 |
310852782 ps |
| T989 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.490620929 |
|
|
Mar 07 12:53:47 PM PST 24 |
Mar 07 12:53:51 PM PST 24 |
131216100 ps |
| T82 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4158971936 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:54:14 PM PST 24 |
14410879797 ps |
| T83 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4040559206 |
|
|
Mar 07 12:53:32 PM PST 24 |
Mar 07 12:54:24 PM PST 24 |
100535593719 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.442804283 |
|
|
Mar 07 12:53:28 PM PST 24 |
Mar 07 12:53:29 PM PST 24 |
14854433 ps |
| T84 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.888879545 |
|
|
Mar 07 12:53:41 PM PST 24 |
Mar 07 12:54:12 PM PST 24 |
14804996221 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.289225715 |
|
|
Mar 07 12:53:42 PM PST 24 |
Mar 07 12:53:43 PM PST 24 |
36539499 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4024468422 |
|
|
Mar 07 12:53:42 PM PST 24 |
Mar 07 12:53:43 PM PST 24 |
77204311 ps |
| T993 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1688211361 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:53:49 PM PST 24 |
3872016123 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1496611296 |
|
|
Mar 07 12:53:32 PM PST 24 |
Mar 07 12:53:35 PM PST 24 |
31173678 ps |
| T995 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3170443321 |
|
|
Mar 07 12:53:31 PM PST 24 |
Mar 07 12:53:35 PM PST 24 |
360821313 ps |
| T85 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1386494420 |
|
|
Mar 07 12:53:05 PM PST 24 |
Mar 07 12:54:02 PM PST 24 |
44020557271 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3996916581 |
|
|
Mar 07 12:53:22 PM PST 24 |
Mar 07 12:53:26 PM PST 24 |
378048098 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3507775463 |
|
|
Mar 07 12:53:12 PM PST 24 |
Mar 07 12:53:14 PM PST 24 |
338894884 ps |
| T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3234292445 |
|
|
Mar 07 12:53:44 PM PST 24 |
Mar 07 12:53:48 PM PST 24 |
719317406 ps |
| T116 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.975307254 |
|
|
Mar 07 12:53:27 PM PST 24 |
Mar 07 12:53:30 PM PST 24 |
223098042 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3266338767 |
|
|
Mar 07 12:53:10 PM PST 24 |
Mar 07 12:53:11 PM PST 24 |
20930124 ps |
| T1000 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4062969207 |
|
|
Mar 07 12:53:29 PM PST 24 |
Mar 07 12:53:30 PM PST 24 |
23906004 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1972583593 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:53:24 PM PST 24 |
83089279 ps |
| T1002 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.444641824 |
|
|
Mar 07 12:53:23 PM PST 24 |
Mar 07 12:53:28 PM PST 24 |
1449560560 ps |
| T1003 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3672956208 |
|
|
Mar 07 12:53:38 PM PST 24 |
Mar 07 12:53:43 PM PST 24 |
111274561 ps |