| T790 |
/workspace/coverage/default/43.sram_ctrl_partial_access.4027704579 |
|
|
Mar 21 01:28:11 PM PDT 24 |
Mar 21 01:30:45 PM PDT 24 |
5798808281 ps |
| T791 |
/workspace/coverage/default/48.sram_ctrl_partial_access.1170699965 |
|
|
Mar 21 01:28:48 PM PDT 24 |
Mar 21 01:29:12 PM PDT 24 |
6535471194 ps |
| T792 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2651878470 |
|
|
Mar 21 01:28:13 PM PDT 24 |
Mar 21 01:28:13 PM PDT 24 |
13711243 ps |
| T793 |
/workspace/coverage/default/30.sram_ctrl_bijection.2815304331 |
|
|
Mar 21 01:26:33 PM PDT 24 |
Mar 21 01:54:23 PM PDT 24 |
103514457003 ps |
| T794 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2683694146 |
|
|
Mar 21 01:28:48 PM PDT 24 |
Mar 21 01:49:55 PM PDT 24 |
17613996310 ps |
| T795 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1194688223 |
|
|
Mar 21 01:28:12 PM PDT 24 |
Mar 21 01:33:34 PM PDT 24 |
71540948051 ps |
| T796 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1395313014 |
|
|
Mar 21 01:26:10 PM PDT 24 |
Mar 21 01:27:51 PM PDT 24 |
798318679 ps |
| T797 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.3334214170 |
|
|
Mar 21 01:26:59 PM PDT 24 |
Mar 21 01:29:35 PM PDT 24 |
36812725847 ps |
| T798 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3215963068 |
|
|
Mar 21 01:26:17 PM PDT 24 |
Mar 21 01:32:04 PM PDT 24 |
11210442767 ps |
| T799 |
/workspace/coverage/default/48.sram_ctrl_stress_all.4023730171 |
|
|
Mar 21 01:28:57 PM PDT 24 |
Mar 21 02:09:23 PM PDT 24 |
536915207090 ps |
| T800 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.354225924 |
|
|
Mar 21 01:25:24 PM PDT 24 |
Mar 21 01:25:40 PM PDT 24 |
9255415451 ps |
| T801 |
/workspace/coverage/default/23.sram_ctrl_regwen.529684679 |
|
|
Mar 21 01:26:18 PM PDT 24 |
Mar 21 01:47:21 PM PDT 24 |
32831932134 ps |
| T802 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3644842329 |
|
|
Mar 21 01:25:37 PM PDT 24 |
Mar 21 01:26:54 PM PDT 24 |
2613248944 ps |
| T803 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.134119007 |
|
|
Mar 21 01:25:51 PM PDT 24 |
Mar 21 01:27:13 PM PDT 24 |
37327551336 ps |
| T804 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.1317873289 |
|
|
Mar 21 01:25:24 PM PDT 24 |
Mar 21 01:38:17 PM PDT 24 |
15513238518 ps |
| T805 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.501154416 |
|
|
Mar 21 01:25:25 PM PDT 24 |
Mar 21 01:26:12 PM PDT 24 |
1777481495 ps |
| T806 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3010798987 |
|
|
Mar 21 01:25:34 PM PDT 24 |
Mar 21 01:26:10 PM PDT 24 |
13041549426 ps |
| T807 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1254843133 |
|
|
Mar 21 01:26:19 PM PDT 24 |
Mar 21 01:26:42 PM PDT 24 |
1237652263 ps |
| T808 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3161459842 |
|
|
Mar 21 01:25:28 PM PDT 24 |
Mar 21 01:30:48 PM PDT 24 |
21535384373 ps |
| T809 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1043859944 |
|
|
Mar 21 01:26:10 PM PDT 24 |
Mar 21 01:26:15 PM PDT 24 |
395589926 ps |
| T810 |
/workspace/coverage/default/25.sram_ctrl_executable.61260271 |
|
|
Mar 21 01:26:19 PM PDT 24 |
Mar 21 01:42:55 PM PDT 24 |
72971421589 ps |
| T811 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.2592461286 |
|
|
Mar 21 01:26:31 PM PDT 24 |
Mar 21 01:27:26 PM PDT 24 |
9667639137 ps |
| T812 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.2492049416 |
|
|
Mar 21 01:25:36 PM PDT 24 |
Mar 21 01:25:46 PM PDT 24 |
694195088 ps |
| T813 |
/workspace/coverage/default/18.sram_ctrl_bijection.3425621705 |
|
|
Mar 21 01:26:10 PM PDT 24 |
Mar 21 02:02:45 PM PDT 24 |
63600991686 ps |
| T814 |
/workspace/coverage/default/9.sram_ctrl_regwen.1437208778 |
|
|
Mar 21 01:25:31 PM PDT 24 |
Mar 21 01:38:03 PM PDT 24 |
9076175994 ps |
| T815 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1216485457 |
|
|
Mar 21 01:28:11 PM PDT 24 |
Mar 21 01:30:02 PM PDT 24 |
3120002585 ps |
| T816 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2385931973 |
|
|
Mar 21 01:26:11 PM PDT 24 |
Mar 21 01:29:31 PM PDT 24 |
2712313904 ps |
| T817 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1774259061 |
|
|
Mar 21 01:26:20 PM PDT 24 |
Mar 21 01:26:29 PM PDT 24 |
2700725386 ps |
| T818 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2273727745 |
|
|
Mar 21 01:26:02 PM PDT 24 |
Mar 21 01:28:49 PM PDT 24 |
17356399115 ps |
| T819 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.1869684918 |
|
|
Mar 21 01:27:47 PM PDT 24 |
Mar 21 01:32:42 PM PDT 24 |
5318944287 ps |
| T820 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.927402091 |
|
|
Mar 21 01:28:21 PM PDT 24 |
Mar 21 01:30:42 PM PDT 24 |
7616877768 ps |
| T821 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1407280089 |
|
|
Mar 21 01:25:47 PM PDT 24 |
Mar 21 01:30:10 PM PDT 24 |
19287000556 ps |
| T822 |
/workspace/coverage/default/8.sram_ctrl_partial_access.2363876241 |
|
|
Mar 21 01:25:25 PM PDT 24 |
Mar 21 01:25:40 PM PDT 24 |
2794620371 ps |
| T823 |
/workspace/coverage/default/36.sram_ctrl_partial_access.526073947 |
|
|
Mar 21 01:27:29 PM PDT 24 |
Mar 21 01:27:46 PM PDT 24 |
7905040255 ps |
| T824 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.2242001166 |
|
|
Mar 21 01:25:57 PM PDT 24 |
Mar 21 01:30:10 PM PDT 24 |
4107177962 ps |
| T825 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2988267063 |
|
|
Mar 21 01:26:11 PM PDT 24 |
Mar 21 01:27:17 PM PDT 24 |
4762410562 ps |
| T826 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4027396785 |
|
|
Mar 21 01:25:25 PM PDT 24 |
Mar 21 01:26:51 PM PDT 24 |
2815411131 ps |
| T827 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2521343832 |
|
|
Mar 21 01:27:29 PM PDT 24 |
Mar 21 01:27:43 PM PDT 24 |
2973562930 ps |
| T828 |
/workspace/coverage/default/2.sram_ctrl_stress_all.3942611267 |
|
|
Mar 21 01:25:26 PM PDT 24 |
Mar 21 02:31:25 PM PDT 24 |
73637214361 ps |
| T829 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1526461971 |
|
|
Mar 21 01:28:13 PM PDT 24 |
Mar 21 02:31:03 PM PDT 24 |
73820192954 ps |
| T830 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1464807156 |
|
|
Mar 21 01:28:38 PM PDT 24 |
Mar 21 01:29:22 PM PDT 24 |
734883197 ps |
| T831 |
/workspace/coverage/default/20.sram_ctrl_regwen.3374978164 |
|
|
Mar 21 01:26:01 PM PDT 24 |
Mar 21 01:28:54 PM PDT 24 |
5202307777 ps |
| T832 |
/workspace/coverage/default/24.sram_ctrl_bijection.3159937248 |
|
|
Mar 21 01:26:14 PM PDT 24 |
Mar 21 01:36:12 PM PDT 24 |
204420800229 ps |
| T833 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.3511101712 |
|
|
Mar 21 01:26:48 PM PDT 24 |
Mar 21 01:28:33 PM PDT 24 |
125204440568 ps |
| T834 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.1516619250 |
|
|
Mar 21 01:27:24 PM PDT 24 |
Mar 21 01:28:26 PM PDT 24 |
5061914571 ps |
| T835 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3967107763 |
|
|
Mar 21 01:25:36 PM PDT 24 |
Mar 21 01:27:17 PM PDT 24 |
58869824404 ps |
| T836 |
/workspace/coverage/default/46.sram_ctrl_partial_access.1013254861 |
|
|
Mar 21 01:28:30 PM PDT 24 |
Mar 21 01:28:37 PM PDT 24 |
2212563219 ps |
| T837 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.877514078 |
|
|
Mar 21 01:28:40 PM PDT 24 |
Mar 21 01:28:50 PM PDT 24 |
713770354 ps |
| T838 |
/workspace/coverage/default/35.sram_ctrl_executable.1622619230 |
|
|
Mar 21 01:27:27 PM PDT 24 |
Mar 21 01:41:56 PM PDT 24 |
32931992416 ps |
| T839 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1490994872 |
|
|
Mar 21 01:28:56 PM PDT 24 |
Mar 21 01:30:04 PM PDT 24 |
1508445460 ps |
| T840 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3843812205 |
|
|
Mar 21 01:28:13 PM PDT 24 |
Mar 21 01:28:24 PM PDT 24 |
633326067 ps |
| T841 |
/workspace/coverage/default/38.sram_ctrl_executable.3546687342 |
|
|
Mar 21 01:27:35 PM PDT 24 |
Mar 21 01:32:17 PM PDT 24 |
4878817095 ps |
| T842 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2697413997 |
|
|
Mar 21 01:26:57 PM PDT 24 |
Mar 21 01:27:01 PM PDT 24 |
3064682829 ps |
| T843 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3301720337 |
|
|
Mar 21 01:25:24 PM PDT 24 |
Mar 21 01:25:28 PM PDT 24 |
350219249 ps |
| T844 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1364538167 |
|
|
Mar 21 01:26:20 PM PDT 24 |
Mar 21 01:54:24 PM PDT 24 |
48488739663 ps |
| T845 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2570398481 |
|
|
Mar 21 01:26:35 PM PDT 24 |
Mar 21 01:29:07 PM PDT 24 |
18647914041 ps |
| T846 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2515222823 |
|
|
Mar 21 01:26:49 PM PDT 24 |
Mar 21 01:31:37 PM PDT 24 |
13781073993 ps |
| T847 |
/workspace/coverage/default/0.sram_ctrl_regwen.3114488413 |
|
|
Mar 21 01:25:14 PM PDT 24 |
Mar 21 01:28:09 PM PDT 24 |
539658819 ps |
| T848 |
/workspace/coverage/default/12.sram_ctrl_smoke.1710725755 |
|
|
Mar 21 01:26:04 PM PDT 24 |
Mar 21 01:26:17 PM PDT 24 |
3991742070 ps |
| T849 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3149690585 |
|
|
Mar 21 01:28:56 PM PDT 24 |
Mar 21 01:30:05 PM PDT 24 |
2436814475 ps |
| T850 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.3935010152 |
|
|
Mar 21 01:26:01 PM PDT 24 |
Mar 21 01:38:38 PM PDT 24 |
19329058262 ps |
| T851 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.604422539 |
|
|
Mar 21 01:26:58 PM PDT 24 |
Mar 21 01:29:26 PM PDT 24 |
1626901544 ps |
| T852 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1456038207 |
|
|
Mar 21 01:27:39 PM PDT 24 |
Mar 21 01:28:38 PM PDT 24 |
9232495144 ps |
| T853 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1829855353 |
|
|
Mar 21 01:25:40 PM PDT 24 |
Mar 21 01:25:49 PM PDT 24 |
462936649 ps |
| T854 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.4153288985 |
|
|
Mar 21 01:27:30 PM PDT 24 |
Mar 21 01:28:06 PM PDT 24 |
28307868406 ps |
| T855 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.4070350010 |
|
|
Mar 21 01:25:44 PM PDT 24 |
Mar 21 01:28:17 PM PDT 24 |
49272600544 ps |
| T856 |
/workspace/coverage/default/9.sram_ctrl_executable.4232989911 |
|
|
Mar 21 01:25:56 PM PDT 24 |
Mar 21 01:49:27 PM PDT 24 |
28070914694 ps |
| T857 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.916325333 |
|
|
Mar 21 01:26:11 PM PDT 24 |
Mar 21 01:29:56 PM PDT 24 |
18007051778 ps |
| T858 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1272183945 |
|
|
Mar 21 01:29:04 PM PDT 24 |
Mar 21 01:30:02 PM PDT 24 |
7771442259 ps |
| T859 |
/workspace/coverage/default/12.sram_ctrl_executable.1436645052 |
|
|
Mar 21 01:25:54 PM PDT 24 |
Mar 21 01:32:38 PM PDT 24 |
5335278835 ps |
| T860 |
/workspace/coverage/default/19.sram_ctrl_executable.1344537395 |
|
|
Mar 21 01:26:02 PM PDT 24 |
Mar 21 01:37:13 PM PDT 24 |
45210201858 ps |
| T861 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1606236224 |
|
|
Mar 21 01:28:04 PM PDT 24 |
Mar 21 01:30:12 PM PDT 24 |
8968275201 ps |
| T862 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.308393696 |
|
|
Mar 21 01:26:16 PM PDT 24 |
Mar 21 01:29:51 PM PDT 24 |
6371368172 ps |
| T863 |
/workspace/coverage/default/30.sram_ctrl_partial_access.4289486060 |
|
|
Mar 21 01:26:30 PM PDT 24 |
Mar 21 01:26:38 PM PDT 24 |
2065411660 ps |
| T864 |
/workspace/coverage/default/17.sram_ctrl_regwen.4184976159 |
|
|
Mar 21 01:26:08 PM PDT 24 |
Mar 21 01:44:59 PM PDT 24 |
12235137842 ps |
| T865 |
/workspace/coverage/default/2.sram_ctrl_smoke.1095799670 |
|
|
Mar 21 01:25:24 PM PDT 24 |
Mar 21 01:25:30 PM PDT 24 |
1697149701 ps |
| T866 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2781891992 |
|
|
Mar 21 01:26:04 PM PDT 24 |
Mar 21 01:27:04 PM PDT 24 |
782799473 ps |
| T867 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.3386699528 |
|
|
Mar 21 01:26:10 PM PDT 24 |
Mar 21 01:26:52 PM PDT 24 |
3093448432 ps |
| T868 |
/workspace/coverage/default/36.sram_ctrl_stress_all.2075972324 |
|
|
Mar 21 01:27:29 PM PDT 24 |
Mar 21 02:42:01 PM PDT 24 |
173699534116 ps |
| T869 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.4171801294 |
|
|
Mar 21 01:26:59 PM PDT 24 |
Mar 21 01:29:09 PM PDT 24 |
17249480922 ps |
| T870 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.657958985 |
|
|
Mar 21 01:26:57 PM PDT 24 |
Mar 21 01:46:59 PM PDT 24 |
49078410505 ps |
| T871 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.995579719 |
|
|
Mar 21 01:27:38 PM PDT 24 |
Mar 21 01:30:16 PM PDT 24 |
5151541444 ps |
| T872 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2616452146 |
|
|
Mar 21 01:27:33 PM PDT 24 |
Mar 21 01:28:22 PM PDT 24 |
3103460159 ps |
| T873 |
/workspace/coverage/default/10.sram_ctrl_stress_all.3408384451 |
|
|
Mar 21 01:25:46 PM PDT 24 |
Mar 21 02:47:21 PM PDT 24 |
727968571982 ps |
| T874 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2133785587 |
|
|
Mar 21 01:25:37 PM PDT 24 |
Mar 21 01:26:37 PM PDT 24 |
10163395359 ps |
| T875 |
/workspace/coverage/default/2.sram_ctrl_regwen.332205149 |
|
|
Mar 21 01:25:29 PM PDT 24 |
Mar 21 01:49:39 PM PDT 24 |
52651432285 ps |
| T876 |
/workspace/coverage/default/49.sram_ctrl_partial_access.191210493 |
|
|
Mar 21 01:28:56 PM PDT 24 |
Mar 21 01:32:17 PM PDT 24 |
1802700522 ps |
| T877 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.1740010625 |
|
|
Mar 21 01:26:19 PM PDT 24 |
Mar 21 01:28:46 PM PDT 24 |
7175769118 ps |
| T878 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.889914772 |
|
|
Mar 21 01:26:09 PM PDT 24 |
Mar 21 01:27:24 PM PDT 24 |
13583203049 ps |
| T879 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.3837499653 |
|
|
Mar 21 01:27:25 PM PDT 24 |
Mar 21 01:27:28 PM PDT 24 |
370754596 ps |
| T880 |
/workspace/coverage/default/25.sram_ctrl_alert_test.793688969 |
|
|
Mar 21 01:26:20 PM PDT 24 |
Mar 21 01:26:21 PM PDT 24 |
13091051 ps |
| T881 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.1521269384 |
|
|
Mar 21 01:26:04 PM PDT 24 |
Mar 21 01:57:30 PM PDT 24 |
66380143322 ps |
| T882 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.2917901616 |
|
|
Mar 21 01:27:37 PM PDT 24 |
Mar 21 01:28:20 PM PDT 24 |
6296815570 ps |
| T883 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.137031177 |
|
|
Mar 21 01:26:10 PM PDT 24 |
Mar 21 01:27:51 PM PDT 24 |
60844413764 ps |
| T884 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3154656153 |
|
|
Mar 21 01:26:47 PM PDT 24 |
Mar 21 01:29:18 PM PDT 24 |
6912864566 ps |
| T885 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.2795728766 |
|
|
Mar 21 01:26:09 PM PDT 24 |
Mar 21 01:26:13 PM PDT 24 |
357450579 ps |
| T886 |
/workspace/coverage/default/18.sram_ctrl_executable.4262497470 |
|
|
Mar 21 01:26:12 PM PDT 24 |
Mar 21 01:48:52 PM PDT 24 |
100245220509 ps |
| T887 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.4142945465 |
|
|
Mar 21 01:25:44 PM PDT 24 |
Mar 21 01:30:09 PM PDT 24 |
2435507096 ps |
| T888 |
/workspace/coverage/default/44.sram_ctrl_regwen.3212550867 |
|
|
Mar 21 01:28:22 PM PDT 24 |
Mar 21 01:36:21 PM PDT 24 |
7305591297 ps |
| T889 |
/workspace/coverage/default/3.sram_ctrl_bijection.1968843488 |
|
|
Mar 21 01:25:28 PM PDT 24 |
Mar 21 01:59:06 PM PDT 24 |
121591038440 ps |
| T890 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2492159814 |
|
|
Mar 21 01:26:48 PM PDT 24 |
Mar 21 01:27:01 PM PDT 24 |
1336616761 ps |
| T891 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.940549169 |
|
|
Mar 21 01:25:54 PM PDT 24 |
Mar 21 01:38:47 PM PDT 24 |
54634415331 ps |
| T892 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.89372299 |
|
|
Mar 21 01:25:37 PM PDT 24 |
Mar 21 01:25:51 PM PDT 24 |
1025945898 ps |
| T893 |
/workspace/coverage/default/13.sram_ctrl_regwen.1159510779 |
|
|
Mar 21 01:25:58 PM PDT 24 |
Mar 21 01:37:30 PM PDT 24 |
55168125833 ps |
| T894 |
/workspace/coverage/default/39.sram_ctrl_partial_access.116666160 |
|
|
Mar 21 01:27:43 PM PDT 24 |
Mar 21 01:27:48 PM PDT 24 |
397623893 ps |
| T895 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.3711497074 |
|
|
Mar 21 01:27:35 PM PDT 24 |
Mar 21 01:41:45 PM PDT 24 |
33262980003 ps |
| T896 |
/workspace/coverage/default/5.sram_ctrl_bijection.454413966 |
|
|
Mar 21 01:25:30 PM PDT 24 |
Mar 21 01:59:47 PM PDT 24 |
121576553003 ps |
| T897 |
/workspace/coverage/default/15.sram_ctrl_executable.2820858063 |
|
|
Mar 21 01:25:54 PM PDT 24 |
Mar 21 01:36:26 PM PDT 24 |
8809207205 ps |
| T898 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.338408840 |
|
|
Mar 21 01:25:30 PM PDT 24 |
Mar 21 01:29:48 PM PDT 24 |
5553379453 ps |
| T899 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.349816877 |
|
|
Mar 21 01:25:51 PM PDT 24 |
Mar 21 01:27:12 PM PDT 24 |
762383720 ps |
| T900 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4165841861 |
|
|
Mar 21 01:28:21 PM PDT 24 |
Mar 21 01:37:59 PM PDT 24 |
14189264282 ps |
| T901 |
/workspace/coverage/default/27.sram_ctrl_executable.341039465 |
|
|
Mar 21 01:26:21 PM PDT 24 |
Mar 21 01:50:39 PM PDT 24 |
11565192136 ps |
| T902 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.320378929 |
|
|
Mar 21 01:27:32 PM PDT 24 |
Mar 21 01:28:14 PM PDT 24 |
4020509443 ps |
| T903 |
/workspace/coverage/default/45.sram_ctrl_regwen.2919871583 |
|
|
Mar 21 01:28:30 PM PDT 24 |
Mar 21 01:37:11 PM PDT 24 |
28610660784 ps |
| T904 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3384684704 |
|
|
Mar 21 01:25:26 PM PDT 24 |
Mar 21 01:26:42 PM PDT 24 |
4957658419 ps |
| T905 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.589748215 |
|
|
Mar 21 01:26:12 PM PDT 24 |
Mar 21 01:30:08 PM PDT 24 |
4107861134 ps |
| T906 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.3325933214 |
|
|
Mar 21 01:26:03 PM PDT 24 |
Mar 21 01:27:13 PM PDT 24 |
750691924 ps |
| T907 |
/workspace/coverage/default/41.sram_ctrl_partial_access.2856962297 |
|
|
Mar 21 01:27:56 PM PDT 24 |
Mar 21 01:28:07 PM PDT 24 |
1392213557 ps |
| T908 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.3792669404 |
|
|
Mar 21 01:27:53 PM PDT 24 |
Mar 21 01:30:02 PM PDT 24 |
814707018 ps |
| T909 |
/workspace/coverage/default/16.sram_ctrl_alert_test.2609628346 |
|
|
Mar 21 01:26:03 PM PDT 24 |
Mar 21 01:26:04 PM PDT 24 |
17584902 ps |
| T910 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2199088672 |
|
|
Mar 21 01:27:35 PM PDT 24 |
Mar 21 01:33:17 PM PDT 24 |
19928305825 ps |
| T911 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.164944250 |
|
|
Mar 21 01:26:10 PM PDT 24 |
Mar 21 01:26:49 PM PDT 24 |
5614787075 ps |
| T912 |
/workspace/coverage/default/34.sram_ctrl_smoke.1590441751 |
|
|
Mar 21 01:27:01 PM PDT 24 |
Mar 21 01:27:08 PM PDT 24 |
1971884803 ps |
| T913 |
/workspace/coverage/default/48.sram_ctrl_alert_test.335878968 |
|
|
Mar 21 01:28:56 PM PDT 24 |
Mar 21 01:28:57 PM PDT 24 |
14890800 ps |
| T914 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2624558270 |
|
|
Mar 21 01:28:43 PM PDT 24 |
Mar 21 01:28:44 PM PDT 24 |
13538187 ps |
| T915 |
/workspace/coverage/default/23.sram_ctrl_executable.3749037072 |
|
|
Mar 21 01:26:17 PM PDT 24 |
Mar 21 01:49:12 PM PDT 24 |
8537213730 ps |
| T916 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3516631767 |
|
|
Mar 21 01:25:27 PM PDT 24 |
Mar 21 01:31:02 PM PDT 24 |
6115450526 ps |
| T917 |
/workspace/coverage/default/26.sram_ctrl_alert_test.4245324549 |
|
|
Mar 21 01:26:22 PM PDT 24 |
Mar 21 01:26:23 PM PDT 24 |
17543166 ps |
| T918 |
/workspace/coverage/default/25.sram_ctrl_partial_access.1788502949 |
|
|
Mar 21 01:26:16 PM PDT 24 |
Mar 21 01:27:48 PM PDT 24 |
3349142418 ps |
| T919 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3557647709 |
|
|
Mar 21 01:25:33 PM PDT 24 |
Mar 21 01:35:24 PM PDT 24 |
48238989163 ps |
| T920 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4256280115 |
|
|
Mar 21 01:25:24 PM PDT 24 |
Mar 21 01:31:22 PM PDT 24 |
68346999523 ps |
| T921 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.2349964008 |
|
|
Mar 21 01:27:54 PM PDT 24 |
Mar 21 01:28:27 PM PDT 24 |
6702942727 ps |
| T922 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.2444924789 |
|
|
Mar 21 01:27:10 PM PDT 24 |
Mar 21 01:27:13 PM PDT 24 |
1342310691 ps |
| T923 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1076641303 |
|
|
Mar 21 01:28:39 PM PDT 24 |
Mar 21 01:29:46 PM PDT 24 |
4091012662 ps |
| T924 |
/workspace/coverage/default/4.sram_ctrl_executable.791727649 |
|
|
Mar 21 01:25:33 PM PDT 24 |
Mar 21 01:35:57 PM PDT 24 |
37979099950 ps |
| T925 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3230499370 |
|
|
Mar 21 01:26:13 PM PDT 24 |
Mar 21 01:26:16 PM PDT 24 |
345476815 ps |
| T926 |
/workspace/coverage/default/13.sram_ctrl_bijection.1193379644 |
|
|
Mar 21 01:25:55 PM PDT 24 |
Mar 21 01:37:37 PM PDT 24 |
166629389481 ps |
| T927 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3787807985 |
|
|
Mar 21 01:28:41 PM PDT 24 |
Mar 21 01:29:20 PM PDT 24 |
6185746184 ps |
| T928 |
/workspace/coverage/default/47.sram_ctrl_executable.1161587797 |
|
|
Mar 21 01:28:39 PM PDT 24 |
Mar 21 01:47:43 PM PDT 24 |
18374737903 ps |
| T929 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1154596764 |
|
|
Mar 21 01:26:11 PM PDT 24 |
Mar 21 01:28:44 PM PDT 24 |
19734756737 ps |
| T930 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.1838262447 |
|
|
Mar 21 01:28:30 PM PDT 24 |
Mar 21 01:29:50 PM PDT 24 |
2963344309 ps |
| T931 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1689373778 |
|
|
Mar 21 01:26:18 PM PDT 24 |
Mar 21 01:26:40 PM PDT 24 |
1416008357 ps |
| T932 |
/workspace/coverage/default/38.sram_ctrl_alert_test.2174891690 |
|
|
Mar 21 01:27:36 PM PDT 24 |
Mar 21 01:27:37 PM PDT 24 |
21119158 ps |
| T933 |
/workspace/coverage/default/34.sram_ctrl_alert_test.656639530 |
|
|
Mar 21 01:27:25 PM PDT 24 |
Mar 21 01:27:27 PM PDT 24 |
12342564 ps |
| T934 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.407179457 |
|
|
Mar 21 01:27:31 PM PDT 24 |
Mar 21 01:30:52 PM PDT 24 |
46303626393 ps |
| T935 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1609754762 |
|
|
Mar 21 01:27:31 PM PDT 24 |
Mar 21 01:32:39 PM PDT 24 |
4896452063 ps |
| T936 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.147690939 |
|
|
Mar 21 01:27:01 PM PDT 24 |
Mar 21 01:28:29 PM PDT 24 |
14843288257 ps |
| T937 |
/workspace/coverage/default/16.sram_ctrl_bijection.2282744625 |
|
|
Mar 21 01:26:01 PM PDT 24 |
Mar 21 01:36:46 PM PDT 24 |
19591658457 ps |
| T938 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1334722114 |
|
|
Mar 21 01:25:35 PM PDT 24 |
Mar 21 03:38:16 PM PDT 24 |
541999486207 ps |
| T939 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.179919173 |
|
|
Mar 21 01:26:07 PM PDT 24 |
Mar 21 01:26:42 PM PDT 24 |
1304962792 ps |
| T940 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2468040773 |
|
|
Mar 21 01:26:58 PM PDT 24 |
Mar 21 01:44:39 PM PDT 24 |
19028620178 ps |
| T84 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1613316393 |
|
|
Mar 21 01:17:11 PM PDT 24 |
Mar 21 01:17:13 PM PDT 24 |
27186317 ps |
| T941 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.603962822 |
|
|
Mar 21 01:16:59 PM PDT 24 |
Mar 21 01:17:02 PM PDT 24 |
343565397 ps |
| T95 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3159691988 |
|
|
Mar 21 01:17:12 PM PDT 24 |
Mar 21 01:17:14 PM PDT 24 |
152305421 ps |
| T54 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4061139137 |
|
|
Mar 21 01:16:59 PM PDT 24 |
Mar 21 01:17:45 PM PDT 24 |
7295494131 ps |
| T942 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2925089999 |
|
|
Mar 21 01:17:22 PM PDT 24 |
Mar 21 01:17:27 PM PDT 24 |
105628702 ps |
| T55 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2379640784 |
|
|
Mar 21 01:17:16 PM PDT 24 |
Mar 21 01:17:18 PM PDT 24 |
18397294 ps |
| T943 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4088117519 |
|
|
Mar 21 01:17:23 PM PDT 24 |
Mar 21 01:17:27 PM PDT 24 |
608716081 ps |
| T56 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.544551881 |
|
|
Mar 21 01:17:14 PM PDT 24 |
Mar 21 01:17:14 PM PDT 24 |
13182994 ps |
| T96 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4273127437 |
|
|
Mar 21 01:17:14 PM PDT 24 |
Mar 21 01:17:18 PM PDT 24 |
287326267 ps |
| T944 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3523012194 |
|
|
Mar 21 01:17:14 PM PDT 24 |
Mar 21 01:17:16 PM PDT 24 |
507365933 ps |
| T945 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1583935516 |
|
|
Mar 21 01:17:12 PM PDT 24 |
Mar 21 01:17:16 PM PDT 24 |
691222045 ps |
| T57 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3278809947 |
|
|
Mar 21 01:17:10 PM PDT 24 |
Mar 21 01:17:36 PM PDT 24 |
7408820951 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1818740732 |
|
|
Mar 21 01:17:12 PM PDT 24 |
Mar 21 01:17:17 PM PDT 24 |
1435869913 ps |
| T85 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.585115630 |
|
|
Mar 21 01:17:09 PM PDT 24 |
Mar 21 01:17:10 PM PDT 24 |
20348804 ps |
| T86 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3871405646 |
|
|
Mar 21 01:17:13 PM PDT 24 |
Mar 21 01:17:14 PM PDT 24 |
37736294 ps |
| T58 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2294381943 |
|
|
Mar 21 01:17:22 PM PDT 24 |
Mar 21 01:17:24 PM PDT 24 |
13640532 ps |
| T947 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2891723189 |
|
|
Mar 21 01:17:17 PM PDT 24 |
Mar 21 01:17:23 PM PDT 24 |
367375959 ps |
| T94 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3543385172 |
|
|
Mar 21 01:17:00 PM PDT 24 |
Mar 21 01:17:01 PM PDT 24 |
39633291 ps |
| T87 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1244302944 |
|
|
Mar 21 01:17:11 PM PDT 24 |
Mar 21 01:17:13 PM PDT 24 |
16487106 ps |
| T97 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4138662494 |
|
|
Mar 21 01:17:17 PM PDT 24 |
Mar 21 01:17:19 PM PDT 24 |
875445609 ps |
| T106 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3078927480 |
|
|
Mar 21 01:17:22 PM PDT 24 |
Mar 21 01:17:26 PM PDT 24 |
709910588 ps |
| T108 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.750198604 |
|
|
Mar 21 01:17:09 PM PDT 24 |
Mar 21 01:17:11 PM PDT 24 |
1122107438 ps |
| T948 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.480691697 |
|
|
Mar 21 01:17:12 PM PDT 24 |
Mar 21 01:17:15 PM PDT 24 |
70607877 ps |
| T949 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.652324596 |
|
|
Mar 21 01:17:14 PM PDT 24 |
Mar 21 01:17:17 PM PDT 24 |
48235253 ps |
| T88 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1985093317 |
|
|
Mar 21 01:17:20 PM PDT 24 |
Mar 21 01:17:22 PM PDT 24 |
52310217 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.513370894 |
|
|
Mar 21 01:17:21 PM PDT 24 |
Mar 21 01:17:24 PM PDT 24 |
27321689 ps |
| T110 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4033708342 |
|
|
Mar 21 01:17:21 PM PDT 24 |
Mar 21 01:17:25 PM PDT 24 |
569125153 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.580874225 |
|
|
Mar 21 01:16:58 PM PDT 24 |
Mar 21 01:17:02 PM PDT 24 |
3452129065 ps |
| T89 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.503342989 |
|
|
Mar 21 01:17:16 PM PDT 24 |
Mar 21 01:17:17 PM PDT 24 |
39865637 ps |
| T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1538934744 |
|
|
Mar 21 01:17:13 PM PDT 24 |
Mar 21 01:17:14 PM PDT 24 |
19405423 ps |
| T59 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1430858563 |
|
|
Mar 21 01:17:24 PM PDT 24 |
Mar 21 01:18:12 PM PDT 24 |
7262736134 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1446152537 |
|
|
Mar 21 01:16:58 PM PDT 24 |
Mar 21 01:17:41 PM PDT 24 |
7843716807 ps |
| T953 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1834662383 |
|
|
Mar 21 01:17:21 PM PDT 24 |
Mar 21 01:17:26 PM PDT 24 |
379778284 ps |
| T954 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3861271129 |
|
|
Mar 21 01:17:18 PM PDT 24 |
Mar 21 01:17:24 PM PDT 24 |
1412679598 ps |
| T955 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3296261668 |
|
|
Mar 21 01:17:02 PM PDT 24 |
Mar 21 01:17:02 PM PDT 24 |
36376330 ps |
| T956 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3841860744 |
|
|
Mar 21 01:16:56 PM PDT 24 |
Mar 21 01:16:57 PM PDT 24 |
25072410 ps |
| T957 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1757317877 |
|
|
Mar 21 01:17:20 PM PDT 24 |
Mar 21 01:17:23 PM PDT 24 |
57471701 ps |
| T116 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3114314724 |
|
|
Mar 21 01:17:14 PM PDT 24 |
Mar 21 01:17:16 PM PDT 24 |
723383418 ps |
| T958 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4219349028 |
|
|
Mar 21 01:17:09 PM PDT 24 |
Mar 21 01:17:12 PM PDT 24 |
1355367865 ps |
| T113 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1530935587 |
|
|
Mar 21 01:17:29 PM PDT 24 |
Mar 21 01:17:31 PM PDT 24 |
73758447 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1433903076 |
|
|
Mar 21 01:17:23 PM PDT 24 |
Mar 21 01:17:28 PM PDT 24 |
115311742 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2948817470 |
|
|
Mar 21 01:16:57 PM PDT 24 |
Mar 21 01:17:01 PM PDT 24 |
1984616600 ps |
| T61 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2743022751 |
|
|
Mar 21 01:16:59 PM PDT 24 |
Mar 21 01:17:00 PM PDT 24 |
18260085 ps |
| T62 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3507587039 |
|
|
Mar 21 01:17:12 PM PDT 24 |
Mar 21 01:17:46 PM PDT 24 |
26295421087 ps |
| T63 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3733504827 |
|
|
Mar 21 01:17:24 PM PDT 24 |
Mar 21 01:18:12 PM PDT 24 |
7862659329 ps |
| T961 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.867470290 |
|
|
Mar 21 01:17:18 PM PDT 24 |
Mar 21 01:17:19 PM PDT 24 |
24131532 ps |
| T962 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2330649385 |
|
|
Mar 21 01:17:16 PM PDT 24 |
Mar 21 01:17:20 PM PDT 24 |
362343853 ps |
| T963 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3059500822 |
|
|
Mar 21 01:17:19 PM PDT 24 |
Mar 21 01:17:21 PM PDT 24 |
38991042 ps |
| T107 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2765876046 |
|
|
Mar 21 01:16:59 PM PDT 24 |
Mar 21 01:17:01 PM PDT 24 |
537519620 ps |
| T964 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2272203091 |
|
|
Mar 21 01:17:11 PM PDT 24 |
Mar 21 01:17:16 PM PDT 24 |
360878981 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3017651650 |
|
|
Mar 21 01:17:10 PM PDT 24 |
Mar 21 01:17:11 PM PDT 24 |
22851385 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1508120877 |
|
|
Mar 21 01:17:11 PM PDT 24 |
Mar 21 01:17:17 PM PDT 24 |
729190113 ps |
| T967 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3284785821 |
|
|
Mar 21 01:17:19 PM PDT 24 |
Mar 21 01:17:25 PM PDT 24 |
1190731612 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3914259841 |
|
|
Mar 21 01:17:05 PM PDT 24 |
Mar 21 01:17:07 PM PDT 24 |
188657354 ps |
| T969 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3127062389 |
|
|
Mar 21 01:17:11 PM PDT 24 |
Mar 21 01:17:42 PM PDT 24 |
15437511511 ps |
| T970 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2734356914 |
|
|
Mar 21 01:17:20 PM PDT 24 |
Mar 21 01:17:22 PM PDT 24 |
46058948 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.920559217 |
|
|
Mar 21 01:17:00 PM PDT 24 |
Mar 21 01:17:01 PM PDT 24 |
63245905 ps |
| T972 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.916393143 |
|
|
Mar 21 01:17:14 PM PDT 24 |
Mar 21 01:17:17 PM PDT 24 |
60782195 ps |
| T973 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2749299424 |
|
|
Mar 21 01:17:15 PM PDT 24 |
Mar 21 01:17:17 PM PDT 24 |
51818737 ps |
| T974 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.546138384 |
|
|
Mar 21 01:17:13 PM PDT 24 |
Mar 21 01:17:17 PM PDT 24 |
119538671 ps |
| T975 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1141096682 |
|
|
Mar 21 01:17:02 PM PDT 24 |
Mar 21 01:17:03 PM PDT 24 |
303181441 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.153947608 |
|
|
Mar 21 01:16:59 PM PDT 24 |
Mar 21 01:17:56 PM PDT 24 |
28120503372 ps |
| T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1068657512 |
|
|
Mar 21 01:17:11 PM PDT 24 |
Mar 21 01:17:13 PM PDT 24 |
50505253 ps |
| T67 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2410241221 |
|
|
Mar 21 01:17:22 PM PDT 24 |
Mar 21 01:17:49 PM PDT 24 |
3815987101 ps |
| T72 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2269031127 |
|
|
Mar 21 01:17:16 PM PDT 24 |
Mar 21 01:18:06 PM PDT 24 |
7764534837 ps |
| T977 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1553222043 |
|
|
Mar 21 01:17:10 PM PDT 24 |
Mar 21 01:17:11 PM PDT 24 |
65170412 ps |
| T978 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1967897059 |
|
|
Mar 21 01:17:09 PM PDT 24 |
Mar 21 01:17:35 PM PDT 24 |
7729713849 ps |
| T979 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1773693699 |
|
|
Mar 21 01:17:22 PM PDT 24 |
Mar 21 01:17:25 PM PDT 24 |
81376500 ps |
| T109 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2945285589 |
|
|
Mar 21 01:17:11 PM PDT 24 |
Mar 21 01:17:14 PM PDT 24 |
762963096 ps |
| T112 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4172944244 |
|
|
Mar 21 01:17:00 PM PDT 24 |
Mar 21 01:17:02 PM PDT 24 |
559908906 ps |
| T980 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2675194714 |
|
|
Mar 21 01:17:14 PM PDT 24 |
Mar 21 01:17:18 PM PDT 24 |
715268805 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3219036492 |
|
|
Mar 21 01:17:15 PM PDT 24 |
Mar 21 01:17:43 PM PDT 24 |
14818915470 ps |
| T982 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.423726898 |
|
|
Mar 21 01:17:17 PM PDT 24 |
Mar 21 01:17:44 PM PDT 24 |
3813586313 ps |
| T114 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2818160905 |
|
|
Mar 21 01:17:17 PM PDT 24 |
Mar 21 01:17:19 PM PDT 24 |
343668073 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3695636945 |
|
|
Mar 21 01:16:58 PM PDT 24 |
Mar 21 01:16:59 PM PDT 24 |
52426598 ps |
| T73 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4073008506 |
|
|
Mar 21 01:17:12 PM PDT 24 |
Mar 21 01:18:02 PM PDT 24 |
7554680456 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1669387917 |
|
|
Mar 21 01:17:08 PM PDT 24 |
Mar 21 01:17:09 PM PDT 24 |
19841039 ps |
| T985 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4194802016 |
|
|
Mar 21 01:17:22 PM PDT 24 |
Mar 21 01:17:24 PM PDT 24 |
18838458 ps |
| T111 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.113783642 |
|
|
Mar 21 01:17:10 PM PDT 24 |
Mar 21 01:17:13 PM PDT 24 |
317285224 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3987779389 |
|
|
Mar 21 01:17:16 PM PDT 24 |
Mar 21 01:17:17 PM PDT 24 |
14735954 ps |
| T987 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.714900704 |
|
|
Mar 21 01:17:09 PM PDT 24 |
Mar 21 01:17:14 PM PDT 24 |
552636727 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3045975557 |
|
|
Mar 21 01:17:09 PM PDT 24 |
Mar 21 01:17:13 PM PDT 24 |
1388118384 ps |
| T989 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.612681321 |
|
|
Mar 21 01:17:09 PM PDT 24 |
Mar 21 01:17:12 PM PDT 24 |
119371421 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.71806646 |
|
|
Mar 21 01:17:04 PM PDT 24 |
Mar 21 01:17:07 PM PDT 24 |
38137148 ps |
| T76 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.731598083 |
|
|
Mar 21 01:17:15 PM PDT 24 |
Mar 21 01:17:17 PM PDT 24 |
36158743 ps |
| T991 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.866850348 |
|
|
Mar 21 01:17:02 PM PDT 24 |
Mar 21 01:17:04 PM PDT 24 |
23610065 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.961287144 |
|
|
Mar 21 01:17:04 PM PDT 24 |
Mar 21 01:17:05 PM PDT 24 |
15981417 ps |
| T993 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.909389332 |
|
|
Mar 21 01:17:16 PM PDT 24 |
Mar 21 01:17:18 PM PDT 24 |
51486975 ps |
| T994 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2922291395 |
|
|
Mar 21 01:17:10 PM PDT 24 |
Mar 21 01:17:13 PM PDT 24 |
115277217 ps |
| T995 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1031648300 |
|
|
Mar 21 01:17:17 PM PDT 24 |
Mar 21 01:17:23 PM PDT 24 |
1332905319 ps |
| T996 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3306296153 |
|
|
Mar 21 01:17:22 PM PDT 24 |
Mar 21 01:17:24 PM PDT 24 |
33084616 ps |
| T997 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4117316505 |
|
|
Mar 21 01:17:21 PM PDT 24 |
Mar 21 01:17:23 PM PDT 24 |
19396585 ps |
| T74 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4262931305 |
|
|
Mar 21 01:17:19 PM PDT 24 |
Mar 21 01:18:12 PM PDT 24 |
14403589933 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.955942124 |
|
|
Mar 21 01:16:59 PM PDT 24 |
Mar 21 01:17:00 PM PDT 24 |
12018050 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1952003517 |
|
|
Mar 21 01:17:01 PM PDT 24 |
Mar 21 01:17:02 PM PDT 24 |
19487938 ps |
| T1000 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.83380415 |
|
|
Mar 21 01:17:12 PM PDT 24 |
Mar 21 01:17:15 PM PDT 24 |
435599949 ps |
| T1001 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3984157782 |
|
|
Mar 21 01:17:12 PM PDT 24 |
Mar 21 01:17:14 PM PDT 24 |
626069785 ps |
| T1002 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2398285678 |
|
|
Mar 21 01:17:10 PM PDT 24 |
Mar 21 01:17:15 PM PDT 24 |
224353234 ps |
| T1003 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3252379262 |
|
|
Mar 21 01:17:19 PM PDT 24 |
Mar 21 01:17:21 PM PDT 24 |
234375505 ps |