Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.41 100.00 97.91 100.00 100.00 99.72 99.70 98.52


Total test records in report: 1036
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T1004 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4026109007 Mar 21 01:17:21 PM PDT 24 Mar 21 01:17:26 PM PDT 24 153903574 ps
T1005 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.124961614 Mar 21 01:17:10 PM PDT 24 Mar 21 01:17:12 PM PDT 24 179432944 ps
T1006 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3622887981 Mar 21 01:17:21 PM PDT 24 Mar 21 01:17:23 PM PDT 24 86357893 ps
T75 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3934776065 Mar 21 01:17:16 PM PDT 24 Mar 21 01:18:04 PM PDT 24 7375059517 ps
T1007 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3006490651 Mar 21 01:17:13 PM PDT 24 Mar 21 01:17:15 PM PDT 24 26123351 ps
T1008 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1932543481 Mar 21 01:17:22 PM PDT 24 Mar 21 01:17:24 PM PDT 24 16019494 ps
T1009 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1948070975 Mar 21 01:16:59 PM PDT 24 Mar 21 01:17:31 PM PDT 24 14812976192 ps
T1010 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3916833761 Mar 21 01:17:10 PM PDT 24 Mar 21 01:17:38 PM PDT 24 19644706407 ps
T1011 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3367788022 Mar 21 01:16:59 PM PDT 24 Mar 21 01:17:00 PM PDT 24 20371157 ps
T1012 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3806438660 Mar 21 01:17:10 PM PDT 24 Mar 21 01:17:11 PM PDT 24 24144494 ps
T1013 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.526700157 Mar 21 01:17:14 PM PDT 24 Mar 21 01:17:19 PM PDT 24 1414956546 ps
T77 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2333371714 Mar 21 01:17:12 PM PDT 24 Mar 21 01:17:13 PM PDT 24 32574132 ps
T1014 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.683369953 Mar 21 01:17:18 PM PDT 24 Mar 21 01:17:21 PM PDT 24 22031231 ps
T1015 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3613441277 Mar 21 01:17:01 PM PDT 24 Mar 21 01:17:02 PM PDT 24 27473728 ps
T115 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3842367528 Mar 21 01:17:01 PM PDT 24 Mar 21 01:17:04 PM PDT 24 329393610 ps
T1016 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2206475107 Mar 21 01:17:14 PM PDT 24 Mar 21 01:17:15 PM PDT 24 11880109 ps
T1017 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.91870461 Mar 21 01:17:17 PM PDT 24 Mar 21 01:17:21 PM PDT 24 1850109214 ps
T1018 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3186305819 Mar 21 01:17:11 PM PDT 24 Mar 21 01:17:13 PM PDT 24 18550747 ps
T1019 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1759657694 Mar 21 01:17:09 PM PDT 24 Mar 21 01:17:10 PM PDT 24 14499882 ps
T1020 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3403172122 Mar 21 01:17:13 PM PDT 24 Mar 21 01:17:37 PM PDT 24 7630282600 ps
T1021 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1603919945 Mar 21 01:16:59 PM PDT 24 Mar 21 01:17:03 PM PDT 24 34788003 ps
T1022 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.788851767 Mar 21 01:17:20 PM PDT 24 Mar 21 01:17:26 PM PDT 24 683936576 ps
T1023 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3610480137 Mar 21 01:17:09 PM PDT 24 Mar 21 01:17:09 PM PDT 24 16992401 ps
T1024 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.168379560 Mar 21 01:17:13 PM PDT 24 Mar 21 01:17:17 PM PDT 24 367549338 ps
T1025 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4006392860 Mar 21 01:17:10 PM PDT 24 Mar 21 01:17:12 PM PDT 24 38115673 ps
T1026 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3111326635 Mar 21 01:17:11 PM PDT 24 Mar 21 01:17:14 PM PDT 24 120461450 ps
T1027 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.174913561 Mar 21 01:16:58 PM PDT 24 Mar 21 01:16:59 PM PDT 24 16164885 ps
T1028 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2441066278 Mar 21 01:17:07 PM PDT 24 Mar 21 01:18:01 PM PDT 24 33574048861 ps
T1029 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2771227306 Mar 21 01:17:02 PM PDT 24 Mar 21 01:17:03 PM PDT 24 259027427 ps
T1030 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3939611280 Mar 21 01:17:12 PM PDT 24 Mar 21 01:17:13 PM PDT 24 32707510 ps
T1031 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1265009608 Mar 21 01:17:18 PM PDT 24 Mar 21 01:17:19 PM PDT 24 37347280 ps
T1032 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2981830855 Mar 21 01:17:16 PM PDT 24 Mar 21 01:17:19 PM PDT 24 115596496 ps
T1033 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4076499754 Mar 21 01:17:21 PM PDT 24 Mar 21 01:17:24 PM PDT 24 28802227 ps
T1034 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.156898150 Mar 21 01:16:56 PM PDT 24 Mar 21 01:17:01 PM PDT 24 148673691 ps
T1035 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1294672487 Mar 21 01:17:19 PM PDT 24 Mar 21 01:17:20 PM PDT 24 44687401 ps
T1036 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1286702319 Mar 21 01:17:08 PM PDT 24 Mar 21 01:17:09 PM PDT 24 61713089 ps

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3301041043
Short name T12
Test name
Test status
Simulation time 1433556763 ps
CPU time 51.12 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:28:18 PM PDT 24
Peak memory 258964 kb
Host smart-ae3110be-f04b-4907-b869-109c501b75b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3301041043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3301041043
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.2526917881
Short name T7
Test name
Test status
Simulation time 94595048980 ps
CPU time 3895.13 seconds
Started Mar 21 01:27:23 PM PDT 24
Finished Mar 21 02:32:19 PM PDT 24
Peak memory 384460 kb
Host smart-685af317-bae8-4db0-8056-37d3d38a2801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526917881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.2526917881
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.1414600679
Short name T4
Test name
Test status
Simulation time 1319145725 ps
CPU time 128.15 seconds
Started Mar 21 01:26:49 PM PDT 24
Finished Mar 21 01:28:57 PM PDT 24
Peak memory 350504 kb
Host smart-8a6b87ed-60fb-43f7-b7ff-e383cc187539
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414600679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.1414600679
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.2668951508
Short name T21
Test name
Test status
Simulation time 973425801 ps
CPU time 3.35 seconds
Started Mar 21 01:25:22 PM PDT 24
Finished Mar 21 01:25:26 PM PDT 24
Peak memory 221588 kb
Host smart-9cad7d6c-6a28-4c4c-91ff-cc0ec8d04bea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668951508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.2668951508
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4033708342
Short name T110
Test name
Test status
Simulation time 569125153 ps
CPU time 2.23 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:25 PM PDT 24
Peak memory 202972 kb
Host smart-addfea83-72d8-495a-9772-6887b985459b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033708342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.4033708342
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.478316242
Short name T92
Test name
Test status
Simulation time 24466146617 ps
CPU time 241.85 seconds
Started Mar 21 01:26:58 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 202420 kb
Host smart-4a06933d-a659-4443-83d5-fa932129ab2c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478316242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.sram_ctrl_partial_access_b2b.478316242
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4061139137
Short name T54
Test name
Test status
Simulation time 7295494131 ps
CPU time 45.9 seconds
Started Mar 21 01:16:59 PM PDT 24
Finished Mar 21 01:17:45 PM PDT 24
Peak memory 203224 kb
Host smart-38fa5454-7cf8-46af-865b-e73de87f53d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061139137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.4061139137
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2198827502
Short name T3
Test name
Test status
Simulation time 10964378276 ps
CPU time 579.05 seconds
Started Mar 21 01:28:38 PM PDT 24
Finished Mar 21 01:38:17 PM PDT 24
Peak memory 379204 kb
Host smart-72b89937-8a5a-4f93-b8ae-a856641a71df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198827502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.2198827502
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.3265873618
Short name T19
Test name
Test status
Simulation time 14540405 ps
CPU time 0.72 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:25:27 PM PDT 24
Peak memory 202084 kb
Host smart-d21c5d97-b810-4822-ab1d-274f44655a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265873618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.3265873618
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3839362419
Short name T47
Test name
Test status
Simulation time 2581632558 ps
CPU time 59.87 seconds
Started Mar 21 01:27:36 PM PDT 24
Finished Mar 21 01:28:36 PM PDT 24
Peak memory 283964 kb
Host smart-1d394165-9734-4449-a0d4-52a7ee4cf76d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3839362419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3839362419
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.3530301062
Short name T241
Test name
Test status
Simulation time 705521366 ps
CPU time 3.22 seconds
Started Mar 21 01:25:55 PM PDT 24
Finished Mar 21 01:25:58 PM PDT 24
Peak memory 202420 kb
Host smart-cf98be08-8483-471d-8a7a-4de37cacd12f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530301062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3530301062
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2765876046
Short name T107
Test name
Test status
Simulation time 537519620 ps
CPU time 2.69 seconds
Started Mar 21 01:16:59 PM PDT 24
Finished Mar 21 01:17:01 PM PDT 24
Peak memory 202252 kb
Host smart-4aca4a29-fc1a-4a5e-b4e9-4c125ea517f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765876046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2765876046
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.3418286321
Short name T25
Test name
Test status
Simulation time 104383895950 ps
CPU time 6800.18 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 03:18:45 PM PDT 24
Peak memory 379208 kb
Host smart-6d722cfa-553e-40a3-b969-e39b0a173b5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418286321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.3418286321
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.113783642
Short name T111
Test name
Test status
Simulation time 317285224 ps
CPU time 2.54 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:13 PM PDT 24
Peak memory 202968 kb
Host smart-fa517eaf-6216-4e3e-b6c6-be607d7ab000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113783642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.sram_ctrl_tl_intg_err.113783642
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3377617613
Short name T46
Test name
Test status
Simulation time 4002217903 ps
CPU time 187.27 seconds
Started Mar 21 01:25:48 PM PDT 24
Finished Mar 21 01:28:55 PM PDT 24
Peak memory 375216 kb
Host smart-4f7db61e-bc6d-4c27-8366-660702ffe778
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3377617613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3377617613
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1530935587
Short name T113
Test name
Test status
Simulation time 73758447 ps
CPU time 1.43 seconds
Started Mar 21 01:17:29 PM PDT 24
Finished Mar 21 01:17:31 PM PDT 24
Peak memory 203016 kb
Host smart-100a5b46-181b-49ae-b7a6-0c41b6f05fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530935587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.1530935587
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2743022751
Short name T61
Test name
Test status
Simulation time 18260085 ps
CPU time 0.7 seconds
Started Mar 21 01:16:59 PM PDT 24
Finished Mar 21 01:17:00 PM PDT 24
Peak memory 202580 kb
Host smart-dac681e5-5fca-40bd-9d55-3f81b98df499
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743022751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.2743022751
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2771227306
Short name T1029
Test name
Test status
Simulation time 259027427 ps
CPU time 1.38 seconds
Started Mar 21 01:17:02 PM PDT 24
Finished Mar 21 01:17:03 PM PDT 24
Peak memory 202836 kb
Host smart-fa021457-29e8-4e0e-b486-685439fe6f67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771227306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.2771227306
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.955942124
Short name T998
Test name
Test status
Simulation time 12018050 ps
CPU time 0.67 seconds
Started Mar 21 01:16:59 PM PDT 24
Finished Mar 21 01:17:00 PM PDT 24
Peak memory 202664 kb
Host smart-db96f83f-7eab-4fac-aacc-37e4eaea2240
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955942124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_hw_reset.955942124
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.580874225
Short name T951
Test name
Test status
Simulation time 3452129065 ps
CPU time 4.28 seconds
Started Mar 21 01:16:58 PM PDT 24
Finished Mar 21 01:17:02 PM PDT 24
Peak memory 212756 kb
Host smart-32e25f5c-6947-44da-bc25-7d7a4e7aff0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580874225 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.580874225
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.961287144
Short name T992
Test name
Test status
Simulation time 15981417 ps
CPU time 0.67 seconds
Started Mar 21 01:17:04 PM PDT 24
Finished Mar 21 01:17:05 PM PDT 24
Peak memory 202688 kb
Host smart-de926adc-c8f9-40a8-afd1-27d516bf0ff2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961287144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.sram_ctrl_csr_rw.961287144
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.153947608
Short name T66
Test name
Test status
Simulation time 28120503372 ps
CPU time 56.66 seconds
Started Mar 21 01:16:59 PM PDT 24
Finished Mar 21 01:17:56 PM PDT 24
Peak memory 203288 kb
Host smart-fb400c4d-ee56-4150-8697-d7c12d0b8fb4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153947608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.153947608
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.174913561
Short name T1027
Test name
Test status
Simulation time 16164885 ps
CPU time 0.74 seconds
Started Mar 21 01:16:58 PM PDT 24
Finished Mar 21 01:16:59 PM PDT 24
Peak memory 202704 kb
Host smart-3387fd6f-fdc9-4bed-8a40-e38d4e7a57cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174913561 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.174913561
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.71806646
Short name T990
Test name
Test status
Simulation time 38137148 ps
CPU time 3.29 seconds
Started Mar 21 01:17:04 PM PDT 24
Finished Mar 21 01:17:07 PM PDT 24
Peak memory 203108 kb
Host smart-21154074-253f-42f1-b80b-7742d068deb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71806646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_tl_errors.71806646
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4172944244
Short name T112
Test name
Test status
Simulation time 559908906 ps
CPU time 1.73 seconds
Started Mar 21 01:17:00 PM PDT 24
Finished Mar 21 01:17:02 PM PDT 24
Peak memory 202952 kb
Host smart-ded100da-06cf-4436-a18f-8ce0b7e5f5d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172944244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.4172944244
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.920559217
Short name T971
Test name
Test status
Simulation time 63245905 ps
CPU time 0.73 seconds
Started Mar 21 01:17:00 PM PDT 24
Finished Mar 21 01:17:01 PM PDT 24
Peak memory 202672 kb
Host smart-5f508e92-10c2-41e3-8b27-9c5d6f79d78b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920559217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_aliasing.920559217
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3914259841
Short name T968
Test name
Test status
Simulation time 188657354 ps
CPU time 2.29 seconds
Started Mar 21 01:17:05 PM PDT 24
Finished Mar 21 01:17:07 PM PDT 24
Peak memory 202872 kb
Host smart-ad1ce4dd-0e1c-4391-aaee-319fa2a3f88f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914259841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.3914259841
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3841860744
Short name T956
Test name
Test status
Simulation time 25072410 ps
CPU time 0.73 seconds
Started Mar 21 01:16:56 PM PDT 24
Finished Mar 21 01:16:57 PM PDT 24
Peak memory 202136 kb
Host smart-83b9357f-b275-476c-ae33-6f22aa111772
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841860744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.3841860744
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.603962822
Short name T941
Test name
Test status
Simulation time 343565397 ps
CPU time 3.61 seconds
Started Mar 21 01:16:59 PM PDT 24
Finished Mar 21 01:17:02 PM PDT 24
Peak memory 210268 kb
Host smart-8c10b729-60e6-4ad3-a29d-06bad7dfbea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603962822 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.603962822
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3543385172
Short name T94
Test name
Test status
Simulation time 39633291 ps
CPU time 0.65 seconds
Started Mar 21 01:17:00 PM PDT 24
Finished Mar 21 01:17:01 PM PDT 24
Peak memory 202372 kb
Host smart-d9e402c7-d90e-4e96-9289-cab332d78139
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543385172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.3543385172
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3695636945
Short name T983
Test name
Test status
Simulation time 52426598 ps
CPU time 0.68 seconds
Started Mar 21 01:16:58 PM PDT 24
Finished Mar 21 01:16:59 PM PDT 24
Peak memory 202584 kb
Host smart-9b93833d-dc9e-4c45-a859-b06737398b8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695636945 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3695636945
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.156898150
Short name T1034
Test name
Test status
Simulation time 148673691 ps
CPU time 3.92 seconds
Started Mar 21 01:16:56 PM PDT 24
Finished Mar 21 01:17:01 PM PDT 24
Peak memory 203128 kb
Host smart-a1f51b7c-c95a-45d1-999b-6316b8cd921c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156898150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_tl_errors.156898150
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3842367528
Short name T115
Test name
Test status
Simulation time 329393610 ps
CPU time 2.6 seconds
Started Mar 21 01:17:01 PM PDT 24
Finished Mar 21 01:17:04 PM PDT 24
Peak memory 202848 kb
Host smart-ec324985-06da-408a-8578-accab710d6f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842367528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.3842367528
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.526700157
Short name T1013
Test name
Test status
Simulation time 1414956546 ps
CPU time 3.39 seconds
Started Mar 21 01:17:14 PM PDT 24
Finished Mar 21 01:17:19 PM PDT 24
Peak memory 213772 kb
Host smart-ff971796-fa33-4576-b77d-8a822122372c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526700157 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.526700157
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4006392860
Short name T1025
Test name
Test status
Simulation time 38115673 ps
CPU time 0.68 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:12 PM PDT 24
Peak memory 202748 kb
Host smart-6a546a64-79a0-4731-a170-46107929d8b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006392860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.4006392860
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1967897059
Short name T978
Test name
Test status
Simulation time 7729713849 ps
CPU time 25.49 seconds
Started Mar 21 01:17:09 PM PDT 24
Finished Mar 21 01:17:35 PM PDT 24
Peak memory 202964 kb
Host smart-5e8f8a9e-33cd-4dec-a01a-f6caba076f23
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967897059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.1967897059
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1068657512
Short name T976
Test name
Test status
Simulation time 50505253 ps
CPU time 0.8 seconds
Started Mar 21 01:17:11 PM PDT 24
Finished Mar 21 01:17:13 PM PDT 24
Peak memory 202752 kb
Host smart-c60afe96-32b0-4b54-80e8-e555c558daa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068657512 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.1068657512
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2922291395
Short name T994
Test name
Test status
Simulation time 115277217 ps
CPU time 2.97 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:13 PM PDT 24
Peak memory 203000 kb
Host smart-1af91799-d02b-49ff-ab6d-68e9aa824f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922291395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.2922291395
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.124961614
Short name T1005
Test name
Test status
Simulation time 179432944 ps
CPU time 1.46 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:12 PM PDT 24
Peak memory 203048 kb
Host smart-73382563-68d8-46c9-9487-212c1327b31e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124961614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.sram_ctrl_tl_intg_err.124961614
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1583935516
Short name T945
Test name
Test status
Simulation time 691222045 ps
CPU time 3.87 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:17:16 PM PDT 24
Peak memory 211160 kb
Host smart-8d691803-adf6-40bd-b19b-2beb4a0b3a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583935516 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1583935516
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3939611280
Short name T1030
Test name
Test status
Simulation time 32707510 ps
CPU time 0.69 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:17:13 PM PDT 24
Peak memory 202216 kb
Host smart-ff006e0d-97f5-4bdc-bcc7-979c22eedbaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939611280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.3939611280
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3916833761
Short name T1010
Test name
Test status
Simulation time 19644706407 ps
CPU time 27.9 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:38 PM PDT 24
Peak memory 203004 kb
Host smart-3d480d5a-818e-4f82-a133-e61c20a3f723
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916833761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.3916833761
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1613316393
Short name T84
Test name
Test status
Simulation time 27186317 ps
CPU time 0.83 seconds
Started Mar 21 01:17:11 PM PDT 24
Finished Mar 21 01:17:13 PM PDT 24
Peak memory 202784 kb
Host smart-d06a4960-47b4-49ed-bc0a-41cea286feff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613316393 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1613316393
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2398285678
Short name T1002
Test name
Test status
Simulation time 224353234 ps
CPU time 4.4 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:15 PM PDT 24
Peak memory 202996 kb
Host smart-a8fb808d-a447-4270-a32d-0c102117117b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398285678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.2398285678
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3159691988
Short name T95
Test name
Test status
Simulation time 152305421 ps
CPU time 1.68 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:17:14 PM PDT 24
Peak memory 202976 kb
Host smart-1ce1240f-8043-4ccd-9822-ba6782bd389b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159691988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.3159691988
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3861271129
Short name T954
Test name
Test status
Simulation time 1412679598 ps
CPU time 5.29 seconds
Started Mar 21 01:17:18 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 211280 kb
Host smart-489a8505-3b4e-4731-9396-7374d546e2f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861271129 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3861271129
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2333371714
Short name T77
Test name
Test status
Simulation time 32574132 ps
CPU time 0.66 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:17:13 PM PDT 24
Peak memory 202680 kb
Host smart-cf2ee4b6-ccbe-4e26-a8ea-d1cfebdd1a49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333371714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.2333371714
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4262931305
Short name T74
Test name
Test status
Simulation time 14403589933 ps
CPU time 51.86 seconds
Started Mar 21 01:17:19 PM PDT 24
Finished Mar 21 01:18:12 PM PDT 24
Peak memory 203136 kb
Host smart-d8418828-7eae-44fa-81ec-7b8a5f39edfe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262931305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.4262931305
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2379640784
Short name T55
Test name
Test status
Simulation time 18397294 ps
CPU time 0.79 seconds
Started Mar 21 01:17:16 PM PDT 24
Finished Mar 21 01:17:18 PM PDT 24
Peak memory 202688 kb
Host smart-f86dca65-5676-4b7b-a169-49d99c053f03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379640784 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2379640784
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.652324596
Short name T949
Test name
Test status
Simulation time 48235253 ps
CPU time 2.28 seconds
Started Mar 21 01:17:14 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 203032 kb
Host smart-c17cecc6-89b1-4d87-ab95-09e315541a43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652324596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_tl_errors.652324596
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3984157782
Short name T1001
Test name
Test status
Simulation time 626069785 ps
CPU time 1.49 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:17:14 PM PDT 24
Peak memory 203024 kb
Host smart-ef53428a-3ff5-4776-9984-ee55e7b9014e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984157782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.3984157782
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2330649385
Short name T962
Test name
Test status
Simulation time 362343853 ps
CPU time 3.21 seconds
Started Mar 21 01:17:16 PM PDT 24
Finished Mar 21 01:17:20 PM PDT 24
Peak memory 211068 kb
Host smart-1840ee82-c09d-4bb2-834f-325c2be744f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330649385 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2330649385
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4194802016
Short name T985
Test name
Test status
Simulation time 18838458 ps
CPU time 0.65 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 202680 kb
Host smart-9d2337ec-3cfe-4699-89af-0cce21250925
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194802016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.4194802016
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.423726898
Short name T982
Test name
Test status
Simulation time 3813586313 ps
CPU time 26.35 seconds
Started Mar 21 01:17:17 PM PDT 24
Finished Mar 21 01:17:44 PM PDT 24
Peak memory 203000 kb
Host smart-744bbe82-7d6a-4b60-858f-2bddecd74a4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423726898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.423726898
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1985093317
Short name T88
Test name
Test status
Simulation time 52310217 ps
CPU time 0.69 seconds
Started Mar 21 01:17:20 PM PDT 24
Finished Mar 21 01:17:22 PM PDT 24
Peak memory 202744 kb
Host smart-ad91b267-5088-4769-b34c-cde36be76ca7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985093317 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.1985093317
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1031648300
Short name T995
Test name
Test status
Simulation time 1332905319 ps
CPU time 4.69 seconds
Started Mar 21 01:17:17 PM PDT 24
Finished Mar 21 01:17:23 PM PDT 24
Peak memory 203088 kb
Host smart-b1c36d80-8a6b-48f6-a0bb-5fcbe7a3e312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031648300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.1031648300
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2818160905
Short name T114
Test name
Test status
Simulation time 343668073 ps
CPU time 1.6 seconds
Started Mar 21 01:17:17 PM PDT 24
Finished Mar 21 01:17:19 PM PDT 24
Peak memory 202976 kb
Host smart-70d93a5f-eabd-4e8b-a90d-d0b060e3347b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818160905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.2818160905
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1834662383
Short name T953
Test name
Test status
Simulation time 379778284 ps
CPU time 4.35 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:26 PM PDT 24
Peak memory 212384 kb
Host smart-c22c060c-0795-4373-b12e-f0aee6959aac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834662383 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1834662383
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.731598083
Short name T76
Test name
Test status
Simulation time 36158743 ps
CPU time 0.66 seconds
Started Mar 21 01:17:15 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 202700 kb
Host smart-f5b63539-b0d8-4753-ab97-eb150e02ce01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731598083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 14.sram_ctrl_csr_rw.731598083
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3934776065
Short name T75
Test name
Test status
Simulation time 7375059517 ps
CPU time 46.55 seconds
Started Mar 21 01:17:16 PM PDT 24
Finished Mar 21 01:18:04 PM PDT 24
Peak memory 203188 kb
Host smart-57e50809-2b4f-4c6c-83f6-39702ff529bc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934776065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3934776065
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3622887981
Short name T1006
Test name
Test status
Simulation time 86357893 ps
CPU time 0.81 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:23 PM PDT 24
Peak memory 202636 kb
Host smart-9e301df9-406f-44b0-9b47-409dae2e47a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622887981 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.3622887981
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4026109007
Short name T1004
Test name
Test status
Simulation time 153903574 ps
CPU time 4.2 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:26 PM PDT 24
Peak memory 211176 kb
Host smart-aba25129-d0d6-44f6-96a4-d3dd191a3501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026109007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.4026109007
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3114314724
Short name T116
Test name
Test status
Simulation time 723383418 ps
CPU time 1.76 seconds
Started Mar 21 01:17:14 PM PDT 24
Finished Mar 21 01:17:16 PM PDT 24
Peak memory 203064 kb
Host smart-af6a6924-90db-4d20-8544-138110bea87a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114314724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.3114314724
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3284785821
Short name T967
Test name
Test status
Simulation time 1190731612 ps
CPU time 4.99 seconds
Started Mar 21 01:17:19 PM PDT 24
Finished Mar 21 01:17:25 PM PDT 24
Peak memory 211140 kb
Host smart-09e31cb3-04aa-4f27-9a86-85a90ad16751
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284785821 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3284785821
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3059500822
Short name T963
Test name
Test status
Simulation time 38991042 ps
CPU time 0.67 seconds
Started Mar 21 01:17:19 PM PDT 24
Finished Mar 21 01:17:21 PM PDT 24
Peak memory 202744 kb
Host smart-e45b23a8-8b75-4ec9-9346-0d4c4e09205d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059500822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3059500822
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3219036492
Short name T981
Test name
Test status
Simulation time 14818915470 ps
CPU time 26.87 seconds
Started Mar 21 01:17:15 PM PDT 24
Finished Mar 21 01:17:43 PM PDT 24
Peak memory 202964 kb
Host smart-5e032bd9-0e41-4e6f-9e86-0cb17d3adca3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219036492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3219036492
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2734356914
Short name T970
Test name
Test status
Simulation time 46058948 ps
CPU time 0.76 seconds
Started Mar 21 01:17:20 PM PDT 24
Finished Mar 21 01:17:22 PM PDT 24
Peak memory 202704 kb
Host smart-9a1bb098-7d8d-4939-a47e-83ef761978b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734356914 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2734356914
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.916393143
Short name T972
Test name
Test status
Simulation time 60782195 ps
CPU time 2.16 seconds
Started Mar 21 01:17:14 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 203100 kb
Host smart-932d2fa2-efe8-4a52-9ccc-457a989e541f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916393143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_tl_errors.916393143
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4273127437
Short name T96
Test name
Test status
Simulation time 287326267 ps
CPU time 1.49 seconds
Started Mar 21 01:17:14 PM PDT 24
Finished Mar 21 01:17:18 PM PDT 24
Peak memory 202916 kb
Host smart-bad7f48d-2eef-480d-a282-c850498f7c62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273127437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.4273127437
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4088117519
Short name T943
Test name
Test status
Simulation time 608716081 ps
CPU time 3.73 seconds
Started Mar 21 01:17:23 PM PDT 24
Finished Mar 21 01:17:27 PM PDT 24
Peak memory 211036 kb
Host smart-609ac51a-755a-4d27-b2cf-d639a82f7127
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088117519 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.4088117519
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3306296153
Short name T996
Test name
Test status
Simulation time 33084616 ps
CPU time 0.62 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 202652 kb
Host smart-8b230131-0747-4b1e-861c-d93a12c40bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306296153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.3306296153
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2269031127
Short name T72
Test name
Test status
Simulation time 7764534837 ps
CPU time 49.93 seconds
Started Mar 21 01:17:16 PM PDT 24
Finished Mar 21 01:18:06 PM PDT 24
Peak memory 203212 kb
Host smart-0a75c196-a156-4fb7-a5c1-a5a12e8ceb68
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269031127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2269031127
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2294381943
Short name T58
Test name
Test status
Simulation time 13640532 ps
CPU time 0.74 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 202844 kb
Host smart-f00837b1-4661-4c7e-8ffc-1706ee975f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294381943 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2294381943
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.513370894
Short name T950
Test name
Test status
Simulation time 27321689 ps
CPU time 1.76 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 202984 kb
Host smart-c37e1563-6a0c-48dd-a830-92672e166222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513370894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.513370894
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3078927480
Short name T106
Test name
Test status
Simulation time 709910588 ps
CPU time 2.46 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:26 PM PDT 24
Peak memory 203008 kb
Host smart-66ca0724-aa88-40c1-8454-39d96c50e599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078927480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.3078927480
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.91870461
Short name T1017
Test name
Test status
Simulation time 1850109214 ps
CPU time 3.88 seconds
Started Mar 21 01:17:17 PM PDT 24
Finished Mar 21 01:17:21 PM PDT 24
Peak memory 211204 kb
Host smart-1e502256-b0b0-4e2e-ae8b-3c8dee2a5742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91870461 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.91870461
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4117316505
Short name T997
Test name
Test status
Simulation time 19396585 ps
CPU time 0.71 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:23 PM PDT 24
Peak memory 202696 kb
Host smart-ef946914-8cb5-451d-ae92-73e6ee7e9d0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117316505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.4117316505
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1430858563
Short name T59
Test name
Test status
Simulation time 7262736134 ps
CPU time 48.51 seconds
Started Mar 21 01:17:24 PM PDT 24
Finished Mar 21 01:18:12 PM PDT 24
Peak memory 203284 kb
Host smart-7ef89247-6cf2-4511-8347-2e9e28fedd50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430858563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.1430858563
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.867470290
Short name T961
Test name
Test status
Simulation time 24131532 ps
CPU time 0.71 seconds
Started Mar 21 01:17:18 PM PDT 24
Finished Mar 21 01:17:19 PM PDT 24
Peak memory 202720 kb
Host smart-a1b8e690-04d7-44a0-9862-02ec8a23a243
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867470290 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.867470290
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1757317877
Short name T957
Test name
Test status
Simulation time 57471701 ps
CPU time 2.19 seconds
Started Mar 21 01:17:20 PM PDT 24
Finished Mar 21 01:17:23 PM PDT 24
Peak memory 202996 kb
Host smart-d53dc1f1-f8b8-4638-b394-0ed726ea9546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757317877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1757317877
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.788851767
Short name T1022
Test name
Test status
Simulation time 683936576 ps
CPU time 4.77 seconds
Started Mar 21 01:17:20 PM PDT 24
Finished Mar 21 01:17:26 PM PDT 24
Peak memory 211132 kb
Host smart-fb491cce-6801-441d-ad36-1c7000a46c24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788851767 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.788851767
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1265009608
Short name T1031
Test name
Test status
Simulation time 37347280 ps
CPU time 0.68 seconds
Started Mar 21 01:17:18 PM PDT 24
Finished Mar 21 01:17:19 PM PDT 24
Peak memory 202636 kb
Host smart-9e8fd1f1-6c17-4282-8de3-911107f9192d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265009608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.1265009608
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3733504827
Short name T63
Test name
Test status
Simulation time 7862659329 ps
CPU time 47.89 seconds
Started Mar 21 01:17:24 PM PDT 24
Finished Mar 21 01:18:12 PM PDT 24
Peak memory 203208 kb
Host smart-b970185a-b1e4-4d59-a161-79998b5e630a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733504827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3733504827
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4076499754
Short name T1033
Test name
Test status
Simulation time 28802227 ps
CPU time 0.76 seconds
Started Mar 21 01:17:21 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 202704 kb
Host smart-cc5dccc6-f975-4de2-90d7-6d4ba340df22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076499754 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.4076499754
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1433903076
Short name T959
Test name
Test status
Simulation time 115311742 ps
CPU time 4.15 seconds
Started Mar 21 01:17:23 PM PDT 24
Finished Mar 21 01:17:28 PM PDT 24
Peak memory 203100 kb
Host smart-6e00f44d-fc24-47f4-99fa-7298762493b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433903076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.1433903076
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4138662494
Short name T97
Test name
Test status
Simulation time 875445609 ps
CPU time 1.58 seconds
Started Mar 21 01:17:17 PM PDT 24
Finished Mar 21 01:17:19 PM PDT 24
Peak memory 202964 kb
Host smart-cd4f40b3-2a58-48aa-8d2e-4f933f8e8e00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138662494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.4138662494
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2891723189
Short name T947
Test name
Test status
Simulation time 367375959 ps
CPU time 4.54 seconds
Started Mar 21 01:17:17 PM PDT 24
Finished Mar 21 01:17:23 PM PDT 24
Peak memory 211164 kb
Host smart-817de6d6-8fd9-4d12-8398-951dcf6861bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891723189 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.2891723189
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1294672487
Short name T1035
Test name
Test status
Simulation time 44687401 ps
CPU time 0.69 seconds
Started Mar 21 01:17:19 PM PDT 24
Finished Mar 21 01:17:20 PM PDT 24
Peak memory 202740 kb
Host smart-b2fc1f02-1488-48a6-a249-803306627a82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294672487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.1294672487
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2410241221
Short name T67
Test name
Test status
Simulation time 3815987101 ps
CPU time 25.92 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:49 PM PDT 24
Peak memory 203028 kb
Host smart-bd55ff5c-c4ea-4bd7-8f6d-46432717098c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410241221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2410241221
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1932543481
Short name T1008
Test name
Test status
Simulation time 16019494 ps
CPU time 0.7 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:24 PM PDT 24
Peak memory 202668 kb
Host smart-4fb30779-9fa6-4d5d-9f8c-84dfc2cd7703
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932543481 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1932543481
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2925089999
Short name T942
Test name
Test status
Simulation time 105628702 ps
CPU time 3.76 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:27 PM PDT 24
Peak memory 202988 kb
Host smart-8811b1cc-6071-4c0e-9d89-c95e7653ab89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925089999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.2925089999
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3252379262
Short name T1003
Test name
Test status
Simulation time 234375505 ps
CPU time 2.36 seconds
Started Mar 21 01:17:19 PM PDT 24
Finished Mar 21 01:17:21 PM PDT 24
Peak memory 202956 kb
Host smart-f0e6a407-d3ba-4bf1-aac3-6c8850989456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252379262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.3252379262
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3367788022
Short name T1011
Test name
Test status
Simulation time 20371157 ps
CPU time 0.73 seconds
Started Mar 21 01:16:59 PM PDT 24
Finished Mar 21 01:17:00 PM PDT 24
Peak memory 202576 kb
Host smart-d50c11c0-c25a-492f-91d2-a7457b4173d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367788022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.3367788022
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1141096682
Short name T975
Test name
Test status
Simulation time 303181441 ps
CPU time 1.4 seconds
Started Mar 21 01:17:02 PM PDT 24
Finished Mar 21 01:17:03 PM PDT 24
Peak memory 202792 kb
Host smart-f75ff564-e2ba-42c1-9049-b43c8809e8e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141096682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.1141096682
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3613441277
Short name T1015
Test name
Test status
Simulation time 27473728 ps
CPU time 0.71 seconds
Started Mar 21 01:17:01 PM PDT 24
Finished Mar 21 01:17:02 PM PDT 24
Peak memory 202680 kb
Host smart-ce326559-0c28-4660-8b61-7e25bd450bfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613441277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.3613441277
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2948817470
Short name T960
Test name
Test status
Simulation time 1984616600 ps
CPU time 3.43 seconds
Started Mar 21 01:16:57 PM PDT 24
Finished Mar 21 01:17:01 PM PDT 24
Peak memory 202840 kb
Host smart-831d3e39-43cc-41ca-a2d5-a6c101a9fc2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948817470 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2948817470
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3296261668
Short name T955
Test name
Test status
Simulation time 36376330 ps
CPU time 0.67 seconds
Started Mar 21 01:17:02 PM PDT 24
Finished Mar 21 01:17:02 PM PDT 24
Peak memory 202632 kb
Host smart-e3302ca7-7276-4d76-8570-e701abe888be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296261668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.3296261668
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1446152537
Short name T60
Test name
Test status
Simulation time 7843716807 ps
CPU time 43.4 seconds
Started Mar 21 01:16:58 PM PDT 24
Finished Mar 21 01:17:41 PM PDT 24
Peak memory 203228 kb
Host smart-d76f35b8-5c0d-4463-b78f-c5e6849613be
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446152537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1446152537
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1952003517
Short name T999
Test name
Test status
Simulation time 19487938 ps
CPU time 0.75 seconds
Started Mar 21 01:17:01 PM PDT 24
Finished Mar 21 01:17:02 PM PDT 24
Peak memory 202720 kb
Host smart-f86dd23a-0ffc-4f01-971b-833657bcd70b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952003517 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1952003517
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1603919945
Short name T1021
Test name
Test status
Simulation time 34788003 ps
CPU time 3.44 seconds
Started Mar 21 01:16:59 PM PDT 24
Finished Mar 21 01:17:03 PM PDT 24
Peak memory 202976 kb
Host smart-4bd78d4c-8cb3-4c32-93b6-4581c52b59a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603919945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.1603919945
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1538934744
Short name T952
Test name
Test status
Simulation time 19405423 ps
CPU time 0.72 seconds
Started Mar 21 01:17:13 PM PDT 24
Finished Mar 21 01:17:14 PM PDT 24
Peak memory 202608 kb
Host smart-ee155f7d-2b65-4666-a28d-fc389c823682
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538934744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.1538934744
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1773693699
Short name T979
Test name
Test status
Simulation time 81376500 ps
CPU time 1.87 seconds
Started Mar 21 01:17:22 PM PDT 24
Finished Mar 21 01:17:25 PM PDT 24
Peak memory 202840 kb
Host smart-1db8829d-de3d-43dc-ad7e-bfb988be3194
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773693699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1773693699
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3017651650
Short name T965
Test name
Test status
Simulation time 22851385 ps
CPU time 0.72 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:11 PM PDT 24
Peak memory 202644 kb
Host smart-25cd4228-8376-4b61-9b89-43df222676e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017651650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.3017651650
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1818740732
Short name T946
Test name
Test status
Simulation time 1435869913 ps
CPU time 3.97 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 211204 kb
Host smart-b9045ab5-cbf1-4bb6-9353-e509d257b239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818740732 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.1818740732
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.503342989
Short name T89
Test name
Test status
Simulation time 39865637 ps
CPU time 0.64 seconds
Started Mar 21 01:17:16 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 202612 kb
Host smart-b207332a-b6b1-438b-9821-0bde190fd1df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503342989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_csr_rw.503342989
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1948070975
Short name T1009
Test name
Test status
Simulation time 14812976192 ps
CPU time 31.17 seconds
Started Mar 21 01:16:59 PM PDT 24
Finished Mar 21 01:17:31 PM PDT 24
Peak memory 202940 kb
Host smart-0f148156-191f-40b3-94b3-14f0bd46a1f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948070975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1948070975
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1286702319
Short name T1036
Test name
Test status
Simulation time 61713089 ps
CPU time 0.76 seconds
Started Mar 21 01:17:08 PM PDT 24
Finished Mar 21 01:17:09 PM PDT 24
Peak memory 202796 kb
Host smart-4eb3bea7-f64f-4d7e-b95d-08486430940b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286702319 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1286702319
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.866850348
Short name T991
Test name
Test status
Simulation time 23610065 ps
CPU time 2.25 seconds
Started Mar 21 01:17:02 PM PDT 24
Finished Mar 21 01:17:04 PM PDT 24
Peak memory 211128 kb
Host smart-91a8e28c-d58b-427f-b466-bc09c3bc2d79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866850348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_tl_errors.866850348
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.750198604
Short name T108
Test name
Test status
Simulation time 1122107438 ps
CPU time 1.55 seconds
Started Mar 21 01:17:09 PM PDT 24
Finished Mar 21 01:17:11 PM PDT 24
Peak memory 203008 kb
Host smart-3e0f04d1-4bc8-4699-9958-8b649bf9376b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750198604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.sram_ctrl_tl_intg_err.750198604
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1669387917
Short name T984
Test name
Test status
Simulation time 19841039 ps
CPU time 0.75 seconds
Started Mar 21 01:17:08 PM PDT 24
Finished Mar 21 01:17:09 PM PDT 24
Peak memory 202672 kb
Host smart-6461e7d9-274e-4a99-8f81-d9ef74ed45f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669387917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.1669387917
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3523012194
Short name T944
Test name
Test status
Simulation time 507365933 ps
CPU time 1.39 seconds
Started Mar 21 01:17:14 PM PDT 24
Finished Mar 21 01:17:16 PM PDT 24
Peak memory 202976 kb
Host smart-0b9e6f8b-1230-4163-8880-57d377116783
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523012194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3523012194
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2206475107
Short name T1016
Test name
Test status
Simulation time 11880109 ps
CPU time 0.65 seconds
Started Mar 21 01:17:14 PM PDT 24
Finished Mar 21 01:17:15 PM PDT 24
Peak memory 202140 kb
Host smart-928e291c-7187-4086-a8b8-38ce50e2623e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206475107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.2206475107
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1508120877
Short name T966
Test name
Test status
Simulation time 729190113 ps
CPU time 5.08 seconds
Started Mar 21 01:17:11 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 211224 kb
Host smart-98eeb692-d9dd-42e1-8f80-68ba112960af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508120877 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1508120877
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3806438660
Short name T1012
Test name
Test status
Simulation time 24144494 ps
CPU time 0.68 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:11 PM PDT 24
Peak memory 202596 kb
Host smart-7d233a08-41a4-4866-8d1a-8f747f0f35db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806438660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3806438660
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3278809947
Short name T57
Test name
Test status
Simulation time 7408820951 ps
CPU time 26.17 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:36 PM PDT 24
Peak memory 203044 kb
Host smart-49ef0542-c58e-405f-abfc-56cbbbb0c383
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278809947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3278809947
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3610480137
Short name T1023
Test name
Test status
Simulation time 16992401 ps
CPU time 0.7 seconds
Started Mar 21 01:17:09 PM PDT 24
Finished Mar 21 01:17:09 PM PDT 24
Peak memory 202804 kb
Host smart-43665bf1-2520-464c-ae21-e573059737fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610480137 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3610480137
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3006490651
Short name T1007
Test name
Test status
Simulation time 26123351 ps
CPU time 2.24 seconds
Started Mar 21 01:17:13 PM PDT 24
Finished Mar 21 01:17:15 PM PDT 24
Peak memory 203108 kb
Host smart-8e62ec78-9797-4cb9-aa9e-2872cb7ce14f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006490651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.3006490651
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2675194714
Short name T980
Test name
Test status
Simulation time 715268805 ps
CPU time 3.55 seconds
Started Mar 21 01:17:14 PM PDT 24
Finished Mar 21 01:17:18 PM PDT 24
Peak memory 211004 kb
Host smart-1b9e237e-3170-464b-a3ea-cceec3429a97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675194714 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2675194714
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1759657694
Short name T1019
Test name
Test status
Simulation time 14499882 ps
CPU time 0.64 seconds
Started Mar 21 01:17:09 PM PDT 24
Finished Mar 21 01:17:10 PM PDT 24
Peak memory 202240 kb
Host smart-4aa76589-8b94-431f-8e5d-e824f35c0e66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759657694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.1759657694
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4073008506
Short name T73
Test name
Test status
Simulation time 7554680456 ps
CPU time 49.54 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:18:02 PM PDT 24
Peak memory 203232 kb
Host smart-914d5343-eac3-40c7-9559-70859e68fb1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073008506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.4073008506
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3987779389
Short name T986
Test name
Test status
Simulation time 14735954 ps
CPU time 0.74 seconds
Started Mar 21 01:17:16 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 202768 kb
Host smart-ec74e846-9d1e-49fd-86c0-f86cf0b87d01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987779389 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3987779389
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.480691697
Short name T948
Test name
Test status
Simulation time 70607877 ps
CPU time 2.33 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:17:15 PM PDT 24
Peak memory 203028 kb
Host smart-0bf00aef-21d5-4b42-840a-f2ca354953f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480691697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_tl_errors.480691697
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.83380415
Short name T1000
Test name
Test status
Simulation time 435599949 ps
CPU time 2.14 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:17:15 PM PDT 24
Peak memory 203000 kb
Host smart-3bb4bb1b-fba9-4344-a71e-105fb6f4358a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83380415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te
st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.sram_ctrl_tl_intg_err.83380415
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2272203091
Short name T964
Test name
Test status
Simulation time 360878981 ps
CPU time 3.78 seconds
Started Mar 21 01:17:11 PM PDT 24
Finished Mar 21 01:17:16 PM PDT 24
Peak memory 211252 kb
Host smart-d18647ff-a8f4-4e8e-9f14-31aadcfa4370
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272203091 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2272203091
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.544551881
Short name T56
Test name
Test status
Simulation time 13182994 ps
CPU time 0.68 seconds
Started Mar 21 01:17:14 PM PDT 24
Finished Mar 21 01:17:14 PM PDT 24
Peak memory 202636 kb
Host smart-343aa3e0-6cab-43cf-a847-a2609900008a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544551881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_csr_rw.544551881
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3127062389
Short name T969
Test name
Test status
Simulation time 15437511511 ps
CPU time 30.35 seconds
Started Mar 21 01:17:11 PM PDT 24
Finished Mar 21 01:17:42 PM PDT 24
Peak memory 202936 kb
Host smart-cb046674-0b6c-49ec-89eb-f8ca9d1affaf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127062389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3127062389
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1553222043
Short name T977
Test name
Test status
Simulation time 65170412 ps
CPU time 0.7 seconds
Started Mar 21 01:17:10 PM PDT 24
Finished Mar 21 01:17:11 PM PDT 24
Peak memory 202852 kb
Host smart-605ccb32-3a06-40fd-92fb-ab8e11c7f255
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553222043 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1553222043
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.714900704
Short name T987
Test name
Test status
Simulation time 552636727 ps
CPU time 4.77 seconds
Started Mar 21 01:17:09 PM PDT 24
Finished Mar 21 01:17:14 PM PDT 24
Peak memory 202936 kb
Host smart-f6e6d718-50a6-4f7b-acb7-34c7916b87f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714900704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_tl_errors.714900704
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2981830855
Short name T1032
Test name
Test status
Simulation time 115596496 ps
CPU time 1.59 seconds
Started Mar 21 01:17:16 PM PDT 24
Finished Mar 21 01:17:19 PM PDT 24
Peak memory 202988 kb
Host smart-96f24397-0bc5-4176-bfc9-8b85d93337f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981830855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.2981830855
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3045975557
Short name T988
Test name
Test status
Simulation time 1388118384 ps
CPU time 3.76 seconds
Started Mar 21 01:17:09 PM PDT 24
Finished Mar 21 01:17:13 PM PDT 24
Peak memory 211056 kb
Host smart-664d10e5-97cf-47c7-8b4b-de088c431d7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045975557 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3045975557
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3186305819
Short name T1018
Test name
Test status
Simulation time 18550747 ps
CPU time 0.68 seconds
Started Mar 21 01:17:11 PM PDT 24
Finished Mar 21 01:17:13 PM PDT 24
Peak memory 202668 kb
Host smart-b767a59f-e99b-401b-a72e-5803406d806d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186305819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.3186305819
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2441066278
Short name T1028
Test name
Test status
Simulation time 33574048861 ps
CPU time 53.41 seconds
Started Mar 21 01:17:07 PM PDT 24
Finished Mar 21 01:18:01 PM PDT 24
Peak memory 203140 kb
Host smart-e40ed5ac-6fdf-4553-9bb7-a44f39df5ebb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441066278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2441066278
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.585115630
Short name T85
Test name
Test status
Simulation time 20348804 ps
CPU time 0.73 seconds
Started Mar 21 01:17:09 PM PDT 24
Finished Mar 21 01:17:10 PM PDT 24
Peak memory 202804 kb
Host smart-735dd46a-5a7e-428a-96d7-0453d2b6e504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585115630 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.585115630
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.546138384
Short name T974
Test name
Test status
Simulation time 119538671 ps
CPU time 3.02 seconds
Started Mar 21 01:17:13 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 203160 kb
Host smart-4fa733de-b099-4eac-978d-84fb6051de33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546138384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_tl_errors.546138384
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3111326635
Short name T1026
Test name
Test status
Simulation time 120461450 ps
CPU time 1.56 seconds
Started Mar 21 01:17:11 PM PDT 24
Finished Mar 21 01:17:14 PM PDT 24
Peak memory 203020 kb
Host smart-60f9f221-75e4-4e78-afac-35d1b9656697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111326635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.3111326635
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.168379560
Short name T1024
Test name
Test status
Simulation time 367549338 ps
CPU time 3.4 seconds
Started Mar 21 01:17:13 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 211000 kb
Host smart-f9e1ab20-8c86-4f28-800f-c384180b9a33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168379560 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.168379560
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2749299424
Short name T973
Test name
Test status
Simulation time 51818737 ps
CPU time 0.64 seconds
Started Mar 21 01:17:15 PM PDT 24
Finished Mar 21 01:17:17 PM PDT 24
Peak memory 202480 kb
Host smart-34bcbabf-6b40-467b-b4b3-69d6f3338552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749299424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.2749299424
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3507587039
Short name T62
Test name
Test status
Simulation time 26295421087 ps
CPU time 32.88 seconds
Started Mar 21 01:17:12 PM PDT 24
Finished Mar 21 01:17:46 PM PDT 24
Peak memory 202940 kb
Host smart-237eb11f-d9be-4190-824f-17262b21a389
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507587039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3507587039
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3871405646
Short name T86
Test name
Test status
Simulation time 37736294 ps
CPU time 0.77 seconds
Started Mar 21 01:17:13 PM PDT 24
Finished Mar 21 01:17:14 PM PDT 24
Peak memory 202692 kb
Host smart-d28e8599-5943-4903-bb33-20c9093c3d2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871405646 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3871405646
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.612681321
Short name T989
Test name
Test status
Simulation time 119371421 ps
CPU time 2.42 seconds
Started Mar 21 01:17:09 PM PDT 24
Finished Mar 21 01:17:12 PM PDT 24
Peak memory 202984 kb
Host smart-48e0a8e9-f3c5-4770-abe7-559628939eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612681321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_tl_errors.612681321
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4219349028
Short name T958
Test name
Test status
Simulation time 1355367865 ps
CPU time 3.49 seconds
Started Mar 21 01:17:09 PM PDT 24
Finished Mar 21 01:17:12 PM PDT 24
Peak memory 202732 kb
Host smart-2e445413-0b46-4e80-be9b-4e7f22efe288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219349028 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.4219349028
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1244302944
Short name T87
Test name
Test status
Simulation time 16487106 ps
CPU time 0.66 seconds
Started Mar 21 01:17:11 PM PDT 24
Finished Mar 21 01:17:13 PM PDT 24
Peak memory 202608 kb
Host smart-c24f8a07-77b5-4a91-a97c-5b12c5f6d035
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244302944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.1244302944
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3403172122
Short name T1020
Test name
Test status
Simulation time 7630282600 ps
CPU time 24.31 seconds
Started Mar 21 01:17:13 PM PDT 24
Finished Mar 21 01:17:37 PM PDT 24
Peak memory 202984 kb
Host smart-b390e95a-9922-4785-ab2f-9f270a52ac43
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403172122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3403172122
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.909389332
Short name T993
Test name
Test status
Simulation time 51486975 ps
CPU time 0.77 seconds
Started Mar 21 01:17:16 PM PDT 24
Finished Mar 21 01:17:18 PM PDT 24
Peak memory 202692 kb
Host smart-d34864fc-b00d-41a4-856f-f783db697281
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909389332 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.909389332
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.683369953
Short name T1014
Test name
Test status
Simulation time 22031231 ps
CPU time 2.15 seconds
Started Mar 21 01:17:18 PM PDT 24
Finished Mar 21 01:17:21 PM PDT 24
Peak memory 203016 kb
Host smart-4f430741-eba7-480d-a8be-1c805cbe347e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683369953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_tl_errors.683369953
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2945285589
Short name T109
Test name
Test status
Simulation time 762963096 ps
CPU time 2.37 seconds
Started Mar 21 01:17:11 PM PDT 24
Finished Mar 21 01:17:14 PM PDT 24
Peak memory 202972 kb
Host smart-9b5aebf2-eb42-4242-b07e-f58904b84508
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945285589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.2945285589
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3800319441
Short name T693
Test name
Test status
Simulation time 2838884277 ps
CPU time 188.51 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:28:31 PM PDT 24
Peak memory 330216 kb
Host smart-635b69e1-e168-4c04-904a-8c2647a78a58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800319441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.3800319441
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.3818214243
Short name T775
Test name
Test status
Simulation time 23895686 ps
CPU time 0.67 seconds
Started Mar 21 01:25:20 PM PDT 24
Finished Mar 21 01:25:21 PM PDT 24
Peak memory 202156 kb
Host smart-d1eda91f-905b-4b33-ac9d-7377b07069c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818214243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.3818214243
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.2701833813
Short name T285
Test name
Test status
Simulation time 27977693708 ps
CPU time 654.89 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:36:16 PM PDT 24
Peak memory 202724 kb
Host smart-4551d9cb-aaaf-447d-a8b6-076343471276
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701833813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
2701833813
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.4267651293
Short name T272
Test name
Test status
Simulation time 10031762127 ps
CPU time 724.61 seconds
Started Mar 21 01:25:14 PM PDT 24
Finished Mar 21 01:37:18 PM PDT 24
Peak memory 375992 kb
Host smart-997fe79a-62fc-4007-9803-581c0f48b34e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267651293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.4267651293
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.2693026246
Short name T490
Test name
Test status
Simulation time 26653941523 ps
CPU time 78.39 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:26:33 PM PDT 24
Peak memory 202480 kb
Host smart-fe685f53-90bd-4678-8aed-c16a6b7eb6cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693026246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.2693026246
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.1876354580
Short name T385
Test name
Test status
Simulation time 809895742 ps
CPU time 101.02 seconds
Started Mar 21 01:25:19 PM PDT 24
Finished Mar 21 01:27:00 PM PDT 24
Peak memory 370020 kb
Host smart-2e9da79e-1d4e-496d-b00c-283ab3433104
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876354580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.1876354580
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2441298976
Short name T624
Test name
Test status
Simulation time 3145918432 ps
CPU time 72.72 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:26:38 PM PDT 24
Peak memory 210612 kb
Host smart-64cff6a6-ff29-4829-93f1-e171a106c5e6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441298976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.2441298976
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.1647710453
Short name T151
Test name
Test status
Simulation time 14357906099 ps
CPU time 142.11 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:27:46 PM PDT 24
Peak memory 202416 kb
Host smart-c2c55442-4ba0-41f5-b874-1bb3d5fb001f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647710453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.1647710453
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.773383176
Short name T574
Test name
Test status
Simulation time 7573305766 ps
CPU time 604.6 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:35:20 PM PDT 24
Peak memory 374268 kb
Host smart-a4ee1426-c4ba-4da7-94ba-27e77474b03d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773383176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multipl
e_keys.773383176
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.713015901
Short name T37
Test name
Test status
Simulation time 3817651604 ps
CPU time 25.09 seconds
Started Mar 21 01:25:11 PM PDT 24
Finished Mar 21 01:25:37 PM PDT 24
Peak memory 202412 kb
Host smart-14250730-7f2c-4c68-abe5-6f03e40752f3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713015901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr
am_ctrl_partial_access.713015901
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1380974304
Short name T547
Test name
Test status
Simulation time 4671361566 ps
CPU time 256.52 seconds
Started Mar 21 01:25:13 PM PDT 24
Finished Mar 21 01:29:30 PM PDT 24
Peak memory 202428 kb
Host smart-51c4ff85-1f5f-4eb4-9809-8d4c26a4362b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380974304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1380974304
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.1103981516
Short name T776
Test name
Test status
Simulation time 1347822247 ps
CPU time 3.72 seconds
Started Mar 21 01:25:08 PM PDT 24
Finished Mar 21 01:25:12 PM PDT 24
Peak memory 202532 kb
Host smart-82281d95-acdc-4fdd-8a10-a7f02501ff82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103981516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1103981516
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.3114488413
Short name T847
Test name
Test status
Simulation time 539658819 ps
CPU time 175.26 seconds
Started Mar 21 01:25:14 PM PDT 24
Finished Mar 21 01:28:09 PM PDT 24
Peak memory 362656 kb
Host smart-41a5b19b-310f-4373-8726-3ed7d2a198d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114488413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3114488413
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.1926974385
Short name T20
Test name
Test status
Simulation time 1220547831 ps
CPU time 5.04 seconds
Started Mar 21 01:25:18 PM PDT 24
Finished Mar 21 01:25:24 PM PDT 24
Peak memory 221648 kb
Host smart-92025ca5-6282-4d9d-a5b2-ac209a371cd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926974385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.1926974385
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.2952634463
Short name T665
Test name
Test status
Simulation time 3648832074 ps
CPU time 20.82 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:25:42 PM PDT 24
Peak memory 202344 kb
Host smart-82a3e3bf-adb6-4da8-abe8-8d875bbeda02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952634463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2952634463
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.2269419467
Short name T562
Test name
Test status
Simulation time 365148809827 ps
CPU time 6752.06 seconds
Started Mar 21 01:25:19 PM PDT 24
Finished Mar 21 03:17:52 PM PDT 24
Peak memory 397820 kb
Host smart-594a9eba-17cd-46e8-b24e-08a81434912c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269419467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.2269419467
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4075797970
Short name T600
Test name
Test status
Simulation time 459838102 ps
CPU time 17.43 seconds
Started Mar 21 01:25:19 PM PDT 24
Finished Mar 21 01:25:42 PM PDT 24
Peak memory 210552 kb
Host smart-0a9ab5d9-0563-48c9-a1ea-f038abd4688e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4075797970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.4075797970
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1674334846
Short name T613
Test name
Test status
Simulation time 4618377148 ps
CPU time 209.32 seconds
Started Mar 21 01:25:18 PM PDT 24
Finished Mar 21 01:28:47 PM PDT 24
Peak memory 202420 kb
Host smart-f6e2e703-62de-42f6-8006-e3fb73b0510b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674334846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.1674334846
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4010173062
Short name T340
Test name
Test status
Simulation time 3066039978 ps
CPU time 34.11 seconds
Started Mar 21 01:25:10 PM PDT 24
Finished Mar 21 01:25:45 PM PDT 24
Peak memory 300576 kb
Host smart-63e07306-d864-4842-b358-8ad992379287
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010173062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.4010173062
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.129647424
Short name T330
Test name
Test status
Simulation time 6899434191 ps
CPU time 320.92 seconds
Started Mar 21 01:25:30 PM PDT 24
Finished Mar 21 01:30:51 PM PDT 24
Peak memory 356116 kb
Host smart-8dac7ce3-913e-461e-a322-99b3aecb8e99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129647424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_access_during_key_req.129647424
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.1048559941
Short name T572
Test name
Test status
Simulation time 20393254 ps
CPU time 0.65 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:25:27 PM PDT 24
Peak memory 201920 kb
Host smart-64773056-c45c-422a-98f7-369d84f8b099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048559941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.1048559941
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.1573148208
Short name T718
Test name
Test status
Simulation time 225105194147 ps
CPU time 2444.11 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 02:06:17 PM PDT 24
Peak memory 202384 kb
Host smart-60c9587b-c1e1-40fe-8b29-b6f695e7a8fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573148208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
1573148208
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.2114250240
Short name T513
Test name
Test status
Simulation time 16706280174 ps
CPU time 948.53 seconds
Started Mar 21 01:25:19 PM PDT 24
Finished Mar 21 01:41:07 PM PDT 24
Peak memory 375136 kb
Host smart-283ac7df-628e-4c9c-8479-e576ea9b2e8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114250240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.2114250240
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.3967107763
Short name T835
Test name
Test status
Simulation time 58869824404 ps
CPU time 101.11 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:27:17 PM PDT 24
Peak memory 202480 kb
Host smart-47c4adb1-0656-480a-ad9f-545c634b943f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967107763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.3967107763
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.654797303
Short name T529
Test name
Test status
Simulation time 948872565 ps
CPU time 11.49 seconds
Started Mar 21 01:25:22 PM PDT 24
Finished Mar 21 01:25:38 PM PDT 24
Peak memory 235136 kb
Host smart-33f97db7-2500-4ef3-8114-2c156e1da12e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654797303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.sram_ctrl_max_throughput.654797303
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1142999836
Short name T520
Test name
Test status
Simulation time 2672577633 ps
CPU time 76.83 seconds
Started Mar 21 01:25:16 PM PDT 24
Finished Mar 21 01:26:33 PM PDT 24
Peak memory 210520 kb
Host smart-bbdadee8-7c30-4b9c-ae1a-fc3cd5e2b3df
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142999836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.1142999836
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.3659204014
Short name T398
Test name
Test status
Simulation time 47200738225 ps
CPU time 175.71 seconds
Started Mar 21 01:25:22 PM PDT 24
Finished Mar 21 01:28:17 PM PDT 24
Peak memory 202344 kb
Host smart-650ce629-0715-4d0f-a93b-ce869323c839
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659204014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.3659204014
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.3979505697
Short name T586
Test name
Test status
Simulation time 17917768895 ps
CPU time 378.65 seconds
Started Mar 21 01:25:31 PM PDT 24
Finished Mar 21 01:31:50 PM PDT 24
Peak memory 372204 kb
Host smart-1a68bb3e-5b82-4fac-869d-2eedee06c59e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979505697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.3979505697
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.293159252
Short name T672
Test name
Test status
Simulation time 2404837846 ps
CPU time 72.56 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:26:38 PM PDT 24
Peak memory 321808 kb
Host smart-1a1ec305-12ba-4e21-8635-730491944c54
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293159252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sr
am_ctrl_partial_access.293159252
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1354869528
Short name T429
Test name
Test status
Simulation time 15464517398 ps
CPU time 365.96 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 202328 kb
Host smart-0832f85a-289e-4aa7-87a8-8fcbc4c0d6e7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354869528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.1354869528
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.3878603955
Short name T707
Test name
Test status
Simulation time 360084198 ps
CPU time 3.26 seconds
Started Mar 21 01:25:11 PM PDT 24
Finished Mar 21 01:25:15 PM PDT 24
Peak memory 202412 kb
Host smart-0e98d371-684b-409f-98cd-2d2e0d08c8f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878603955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3878603955
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.750120635
Short name T52
Test name
Test status
Simulation time 3684170363 ps
CPU time 155.64 seconds
Started Mar 21 01:25:22 PM PDT 24
Finished Mar 21 01:27:58 PM PDT 24
Peak memory 313064 kb
Host smart-a7b403f2-14ec-4704-a42f-7fd748f0f385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750120635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.750120635
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.4216528039
Short name T755
Test name
Test status
Simulation time 9314039726 ps
CPU time 14.16 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:25:35 PM PDT 24
Peak memory 202360 kb
Host smart-62cb306c-362d-4e8a-a4dc-11b4a65bfb8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216528039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.4216528039
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.1823027904
Short name T338
Test name
Test status
Simulation time 39457252115 ps
CPU time 1735.98 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:54:30 PM PDT 24
Peak memory 355976 kb
Host smart-f17a9515-534d-4dc6-9bbc-7b0cf53890ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823027904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.1823027904
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.219099653
Short name T451
Test name
Test status
Simulation time 5274227656 ps
CPU time 44.2 seconds
Started Mar 21 01:25:29 PM PDT 24
Finished Mar 21 01:26:13 PM PDT 24
Peak memory 210760 kb
Host smart-c7a99438-4031-4125-8eb6-90e4294a24c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=219099653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.219099653
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1578801583
Short name T240
Test name
Test status
Simulation time 9157811646 ps
CPU time 297.09 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:30:21 PM PDT 24
Peak memory 202556 kb
Host smart-c617d69f-2eab-4b19-be31-02d4c5e7d1b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578801583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.1578801583
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.914092624
Short name T548
Test name
Test status
Simulation time 834991344 ps
CPU time 103.68 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:27:05 PM PDT 24
Peak memory 336172 kb
Host smart-0c29bcd6-0a0b-43f6-85d6-9355e9b8d514
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914092624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.914092624
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3018117094
Short name T788
Test name
Test status
Simulation time 21068601117 ps
CPU time 618.58 seconds
Started Mar 21 01:25:46 PM PDT 24
Finished Mar 21 01:36:06 PM PDT 24
Peak memory 340384 kb
Host smart-4da5a5c2-5ce0-47c0-9ab3-88212007600d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018117094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.3018117094
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.1423199751
Short name T405
Test name
Test status
Simulation time 16123316 ps
CPU time 0.65 seconds
Started Mar 21 01:25:53 PM PDT 24
Finished Mar 21 01:25:54 PM PDT 24
Peak memory 201928 kb
Host smart-f371bd8a-60d1-4b9e-af70-0899975a0132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423199751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.1423199751
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.870843813
Short name T722
Test name
Test status
Simulation time 75695757637 ps
CPU time 1208.83 seconds
Started Mar 21 01:25:37 PM PDT 24
Finished Mar 21 01:45:46 PM PDT 24
Peak memory 202336 kb
Host smart-d8ae0bfe-e2d5-4611-9fea-8122fc3697b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870843813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.
870843813
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.3919205125
Short name T146
Test name
Test status
Simulation time 19192689436 ps
CPU time 326.02 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:31:23 PM PDT 24
Peak memory 371120 kb
Host smart-9ce46426-49c6-4fa6-b293-8f936fc89e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919205125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.3919205125
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.1485416129
Short name T483
Test name
Test status
Simulation time 48020354500 ps
CPU time 80.99 seconds
Started Mar 21 01:25:38 PM PDT 24
Finished Mar 21 01:27:00 PM PDT 24
Peak memory 202360 kb
Host smart-7215d3e1-7a5a-4aba-8d0e-f71e5ae09323
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485416129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.1485416129
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.3209626834
Short name T553
Test name
Test status
Simulation time 736907394 ps
CPU time 31.54 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:26:06 PM PDT 24
Peak memory 288156 kb
Host smart-e33c817a-111e-4048-b3d1-5703652e67ef
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209626834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.3209626834
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.134119007
Short name T803
Test name
Test status
Simulation time 37327551336 ps
CPU time 80.94 seconds
Started Mar 21 01:25:51 PM PDT 24
Finished Mar 21 01:27:13 PM PDT 24
Peak memory 210620 kb
Host smart-b6a4929b-1bfd-4078-9985-490deb2e174a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134119007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.sram_ctrl_mem_partial_access.134119007
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.2242001166
Short name T824
Test name
Test status
Simulation time 4107177962 ps
CPU time 252.5 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:30:10 PM PDT 24
Peak memory 202472 kb
Host smart-256c66a1-be93-4531-a64d-005720dfb1ad
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242001166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.2242001166
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.4126648399
Short name T200
Test name
Test status
Simulation time 5016738219 ps
CPU time 36.93 seconds
Started Mar 21 01:25:38 PM PDT 24
Finished Mar 21 01:26:16 PM PDT 24
Peak memory 293116 kb
Host smart-a3b5195f-fd2f-4fb4-acb8-29d189c2e7ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126648399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.4126648399
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.1503434835
Short name T786
Test name
Test status
Simulation time 2215829398 ps
CPU time 119.73 seconds
Started Mar 21 01:25:41 PM PDT 24
Finished Mar 21 01:27:41 PM PDT 24
Peak memory 347396 kb
Host smart-62675e32-436e-4a8a-a3d8-9d655db010aa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503434835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.1503434835
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3516631767
Short name T916
Test name
Test status
Simulation time 6115450526 ps
CPU time 334.86 seconds
Started Mar 21 01:25:27 PM PDT 24
Finished Mar 21 01:31:02 PM PDT 24
Peak memory 202420 kb
Host smart-1cf3e6dc-89d9-4108-a5bd-da045bd8546c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516631767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.3516631767
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.3888094714
Short name T503
Test name
Test status
Simulation time 346823672 ps
CPU time 3.2 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:26:00 PM PDT 24
Peak memory 202500 kb
Host smart-398a9d74-3944-4afa-8453-93a4fbbd1108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888094714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3888094714
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1629085224
Short name T232
Test name
Test status
Simulation time 10309701844 ps
CPU time 285.75 seconds
Started Mar 21 01:25:28 PM PDT 24
Finished Mar 21 01:30:14 PM PDT 24
Peak memory 367248 kb
Host smart-e0bf49c7-9104-4799-bdce-8e0132463dcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629085224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1629085224
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.345412203
Short name T346
Test name
Test status
Simulation time 781761601 ps
CPU time 48.38 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:26:20 PM PDT 24
Peak memory 302824 kb
Host smart-c00b0f0a-bd71-44cb-adde-f2bdf21e86fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345412203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.345412203
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.3408384451
Short name T873
Test name
Test status
Simulation time 727968571982 ps
CPU time 4894.86 seconds
Started Mar 21 01:25:46 PM PDT 24
Finished Mar 21 02:47:21 PM PDT 24
Peak memory 380284 kb
Host smart-7726069e-1f1e-48a5-9bb2-f17737860326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408384451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.3408384451
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1874732061
Short name T734
Test name
Test status
Simulation time 3177638610 ps
CPU time 142.7 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:27:59 PM PDT 24
Peak memory 202328 kb
Host smart-6d82d845-5c25-46c4-8e32-576ae39f9930
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874732061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.1874732061
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.349816877
Short name T899
Test name
Test status
Simulation time 762383720 ps
CPU time 80.85 seconds
Started Mar 21 01:25:51 PM PDT 24
Finished Mar 21 01:27:12 PM PDT 24
Peak memory 315584 kb
Host smart-2a5de5ae-f7b9-4612-aa18-e561cca06c5d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349816877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.349816877
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1900714611
Short name T730
Test name
Test status
Simulation time 1857211461 ps
CPU time 47.35 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:26:20 PM PDT 24
Peak memory 203228 kb
Host smart-07f37261-c774-466e-aecc-eb09ee5e30f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900714611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.1900714611
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.4234143622
Short name T303
Test name
Test status
Simulation time 118859719 ps
CPU time 0.62 seconds
Started Mar 21 01:25:56 PM PDT 24
Finished Mar 21 01:25:57 PM PDT 24
Peak memory 202064 kb
Host smart-5fb9a786-2491-45f8-a438-39a4571ac366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234143622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.4234143622
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.484818383
Short name T254
Test name
Test status
Simulation time 85017746504 ps
CPU time 914.1 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:40:50 PM PDT 24
Peak memory 202864 kb
Host smart-20ce3a23-1367-49fe-92e3-f729933a5b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484818383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.
484818383
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.1882803789
Short name T459
Test name
Test status
Simulation time 15504220103 ps
CPU time 470.6 seconds
Started Mar 21 01:25:38 PM PDT 24
Finished Mar 21 01:33:30 PM PDT 24
Peak memory 372108 kb
Host smart-f8adc5ec-c729-4ae0-bc17-1b64c60bf620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882803789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.1882803789
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.1430374860
Short name T148
Test name
Test status
Simulation time 10230697570 ps
CPU time 64.88 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:26:38 PM PDT 24
Peak memory 202348 kb
Host smart-022908de-ddc9-40ab-bfd0-b8532452fd8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430374860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.1430374860
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.2062148333
Short name T246
Test name
Test status
Simulation time 679781190 ps
CPU time 6.34 seconds
Started Mar 21 01:25:45 PM PDT 24
Finished Mar 21 01:25:52 PM PDT 24
Peak memory 210488 kb
Host smart-15011f55-ab3d-4a20-8bd8-73fb4a7b634d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062148333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.2062148333
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3162876273
Short name T119
Test name
Test status
Simulation time 5098685396 ps
CPU time 148.77 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 01:28:04 PM PDT 24
Peak memory 210588 kb
Host smart-4b0f24c2-864d-4182-a592-e68e9419df71
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162876273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.3162876273
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.4070350010
Short name T855
Test name
Test status
Simulation time 49272600544 ps
CPU time 152.11 seconds
Started Mar 21 01:25:44 PM PDT 24
Finished Mar 21 01:28:17 PM PDT 24
Peak memory 202392 kb
Host smart-36aed811-5abc-4675-a88f-52c0cfcc33f8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070350010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.4070350010
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.3557647709
Short name T919
Test name
Test status
Simulation time 48238989163 ps
CPU time 590.31 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:35:24 PM PDT 24
Peak memory 376172 kb
Host smart-97ce015e-2f2f-4e56-8375-62508e89afc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557647709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.3557647709
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.2213493896
Short name T9
Test name
Test status
Simulation time 818383962 ps
CPU time 16.99 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 01:25:52 PM PDT 24
Peak memory 262664 kb
Host smart-49140889-1bb5-493b-8c17-e47f5144cded
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213493896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.2213493896
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2823884652
Short name T225
Test name
Test status
Simulation time 88482462792 ps
CPU time 478.16 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:33:32 PM PDT 24
Peak memory 202404 kb
Host smart-c220bcf9-ec76-4349-af3e-80882ec96535
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823884652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.2823884652
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.4255812328
Short name T243
Test name
Test status
Simulation time 5063409756 ps
CPU time 241.1 seconds
Started Mar 21 01:25:29 PM PDT 24
Finished Mar 21 01:29:30 PM PDT 24
Peak memory 352056 kb
Host smart-3d1ea60f-99f1-47b3-acc9-f72a69b26d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255812328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.4255812328
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.1452819202
Short name T216
Test name
Test status
Simulation time 1196366051 ps
CPU time 143.14 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:28:00 PM PDT 24
Peak memory 365832 kb
Host smart-6ec05e07-5e05-4c63-9c6e-2535f7734624
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452819202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1452819202
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.2460799639
Short name T446
Test name
Test status
Simulation time 149937217376 ps
CPU time 3562.83 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 02:24:48 PM PDT 24
Peak memory 378980 kb
Host smart-2d577306-8a80-4ae8-ae12-3242a0723437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460799639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.2460799639
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.729809161
Short name T384
Test name
Test status
Simulation time 6979759288 ps
CPU time 47.72 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:26:14 PM PDT 24
Peak memory 210656 kb
Host smart-7951e84e-aaf6-4e3a-ad3e-619891ed9612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=729809161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.729809161
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2658044505
Short name T198
Test name
Test status
Simulation time 2236181869 ps
CPU time 130.46 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:28:08 PM PDT 24
Peak memory 202376 kb
Host smart-066bafab-7fcd-4379-a714-9dacd1ab4b0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658044505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.2658044505
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.62685088
Short name T318
Test name
Test status
Simulation time 1453775383 ps
CPU time 15.84 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:25:49 PM PDT 24
Peak memory 253540 kb
Host smart-5c725165-399a-435e-9210-186b8ce56617
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62685088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.sram_ctrl_throughput_w_partial_write.62685088
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.4142945465
Short name T887
Test name
Test status
Simulation time 2435507096 ps
CPU time 264.47 seconds
Started Mar 21 01:25:44 PM PDT 24
Finished Mar 21 01:30:09 PM PDT 24
Peak memory 372040 kb
Host smart-9ec211dd-b508-47eb-98b7-19b50a5cb2b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142945465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.4142945465
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.873785899
Short name T430
Test name
Test status
Simulation time 14280744 ps
CPU time 0.67 seconds
Started Mar 21 01:25:55 PM PDT 24
Finished Mar 21 01:25:56 PM PDT 24
Peak memory 202136 kb
Host smart-65c1d8e2-7a1d-48b4-ab17-54db4fd1676a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873785899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.873785899
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.2086473995
Short name T247
Test name
Test status
Simulation time 230798049203 ps
CPU time 1300.82 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:47:49 PM PDT 24
Peak memory 202732 kb
Host smart-f317fe96-c84c-41bf-9e4c-afcfbbb4f769
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086473995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.2086473995
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.1436645052
Short name T859
Test name
Test status
Simulation time 5335278835 ps
CPU time 403.94 seconds
Started Mar 21 01:25:54 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 368684 kb
Host smart-9e5e1692-90fc-40e6-9f3a-dbfe1d2e5ae5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436645052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.1436645052
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.3125096388
Short name T465
Test name
Test status
Simulation time 3350822393 ps
CPU time 12.09 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:24 PM PDT 24
Peak memory 214280 kb
Host smart-01d8c46a-9135-4314-b29d-65772d012e33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125096388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.3125096388
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.415208370
Short name T360
Test name
Test status
Simulation time 756479337 ps
CPU time 36.43 seconds
Started Mar 21 01:25:46 PM PDT 24
Finished Mar 21 01:26:24 PM PDT 24
Peak memory 293192 kb
Host smart-3f5494e9-ee08-483f-80a1-6216e99cf6dd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415208370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.sram_ctrl_max_throughput.415208370
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.174357570
Short name T196
Test name
Test status
Simulation time 2485008861 ps
CPU time 76.83 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:27:18 PM PDT 24
Peak memory 210672 kb
Host smart-f17c7f97-3e3b-4913-bb7d-f9c84df312ff
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174357570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.sram_ctrl_mem_partial_access.174357570
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.2063536653
Short name T464
Test name
Test status
Simulation time 20641201547 ps
CPU time 328.78 seconds
Started Mar 21 01:25:44 PM PDT 24
Finished Mar 21 01:31:14 PM PDT 24
Peak memory 202840 kb
Host smart-c3c7fab5-c151-4528-b2a8-0012867dfe3b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063536653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.2063536653
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.3248285653
Short name T175
Test name
Test status
Simulation time 15209715842 ps
CPU time 697.93 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:37:41 PM PDT 24
Peak memory 357756 kb
Host smart-219ff848-8728-434d-a474-b42cae09325d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248285653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.3248285653
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.1920137119
Short name T270
Test name
Test status
Simulation time 1267522359 ps
CPU time 16.72 seconds
Started Mar 21 01:26:05 PM PDT 24
Finished Mar 21 01:26:21 PM PDT 24
Peak memory 202392 kb
Host smart-b244e768-5626-404d-8bb9-2db00f7f09c6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920137119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.1920137119
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1407280089
Short name T821
Test name
Test status
Simulation time 19287000556 ps
CPU time 261.86 seconds
Started Mar 21 01:25:47 PM PDT 24
Finished Mar 21 01:30:10 PM PDT 24
Peak memory 202460 kb
Host smart-5411e333-51a1-4910-bd5b-2cbada42ddd9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407280089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.1407280089
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.3820267462
Short name T506
Test name
Test status
Simulation time 2805046762 ps
CPU time 3.63 seconds
Started Mar 21 01:25:44 PM PDT 24
Finished Mar 21 01:25:48 PM PDT 24
Peak memory 202496 kb
Host smart-248d5957-aae3-4aed-9cff-50e9169b3e0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820267462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3820267462
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.870350623
Short name T159
Test name
Test status
Simulation time 52556403178 ps
CPU time 619.19 seconds
Started Mar 21 01:25:42 PM PDT 24
Finished Mar 21 01:36:01 PM PDT 24
Peak memory 372236 kb
Host smart-f7496e60-d61a-42bd-a051-b3fc6331fd7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870350623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.870350623
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.1710725755
Short name T848
Test name
Test status
Simulation time 3991742070 ps
CPU time 13.16 seconds
Started Mar 21 01:26:04 PM PDT 24
Finished Mar 21 01:26:17 PM PDT 24
Peak memory 202472 kb
Host smart-03607de0-2c1e-43b5-bbf5-fca5d0cac335
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710725755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1710725755
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.370166268
Short name T597
Test name
Test status
Simulation time 39864007155 ps
CPU time 2540.65 seconds
Started Mar 21 01:25:58 PM PDT 24
Finished Mar 21 02:08:19 PM PDT 24
Peak memory 379252 kb
Host smart-e0a093cd-f5fc-4920-a40c-9b5320e3e283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370166268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_stress_all.370166268
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1829855353
Short name T853
Test name
Test status
Simulation time 462936649 ps
CPU time 8.57 seconds
Started Mar 21 01:25:40 PM PDT 24
Finished Mar 21 01:25:49 PM PDT 24
Peak memory 210592 kb
Host smart-79d17631-95e9-43c8-9c1b-66f36dbefafe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1829855353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1829855353
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2376005367
Short name T525
Test name
Test status
Simulation time 18698306322 ps
CPU time 324.52 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:31:22 PM PDT 24
Peak memory 202396 kb
Host smart-5ffdb40e-0c29-4c63-a087-f8715e8c3a2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376005367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.2376005367
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2781891992
Short name T866
Test name
Test status
Simulation time 782799473 ps
CPU time 59.61 seconds
Started Mar 21 01:26:04 PM PDT 24
Finished Mar 21 01:27:04 PM PDT 24
Peak memory 302496 kb
Host smart-9446a8cc-815e-4a0f-acc1-571b9f8c0aca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781891992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.2781891992
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2923670515
Short name T735
Test name
Test status
Simulation time 26774978678 ps
CPU time 997.39 seconds
Started Mar 21 01:25:40 PM PDT 24
Finished Mar 21 01:42:17 PM PDT 24
Peak memory 376144 kb
Host smart-f6cd885d-b568-4381-9370-abf86eb2a505
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923670515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.2923670515
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.1525085483
Short name T724
Test name
Test status
Simulation time 39062110 ps
CPU time 0.66 seconds
Started Mar 21 01:25:58 PM PDT 24
Finished Mar 21 01:25:59 PM PDT 24
Peak memory 201856 kb
Host smart-39f1108c-858c-4ef0-a934-0e912121bf1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525085483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.1525085483
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.1193379644
Short name T926
Test name
Test status
Simulation time 166629389481 ps
CPU time 701.74 seconds
Started Mar 21 01:25:55 PM PDT 24
Finished Mar 21 01:37:37 PM PDT 24
Peak memory 202764 kb
Host smart-3d07fc8f-7a1f-44de-a504-0df480bf8267
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193379644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.1193379644
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.1427098353
Short name T640
Test name
Test status
Simulation time 16451208757 ps
CPU time 860.97 seconds
Started Mar 21 01:25:53 PM PDT 24
Finished Mar 21 01:40:14 PM PDT 24
Peak memory 362972 kb
Host smart-bad17ca7-b095-46e0-8a7f-61abbd4fb7f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427098353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.1427098353
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.1779329871
Short name T206
Test name
Test status
Simulation time 6147857764 ps
CPU time 19.85 seconds
Started Mar 21 01:25:59 PM PDT 24
Finished Mar 21 01:26:19 PM PDT 24
Peak memory 210592 kb
Host smart-9e36f12c-1443-430d-a7f9-4fb88a19306c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779329871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.1779329871
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.579204908
Short name T238
Test name
Test status
Simulation time 3178518709 ps
CPU time 116.13 seconds
Started Mar 21 01:25:59 PM PDT 24
Finished Mar 21 01:27:55 PM PDT 24
Peak memory 368136 kb
Host smart-2b35fd70-7976-408c-818e-e58eacf204fb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579204908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.sram_ctrl_max_throughput.579204908
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3265573123
Short name T455
Test name
Test status
Simulation time 9851387283 ps
CPU time 79.79 seconds
Started Mar 21 01:25:47 PM PDT 24
Finished Mar 21 01:27:07 PM PDT 24
Peak memory 210620 kb
Host smart-7da62fdb-26fd-4c49-8636-b3c7b89cf5a8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265573123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.3265573123
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.1283091388
Short name T745
Test name
Test status
Simulation time 32769181353 ps
CPU time 291.12 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 202504 kb
Host smart-6a3c573c-fe05-469b-8d3d-a8dcdf57199f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283091388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.1283091388
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.2825374211
Short name T780
Test name
Test status
Simulation time 23865154359 ps
CPU time 1440.93 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:49:42 PM PDT 24
Peak memory 379288 kb
Host smart-15f06af6-ec26-434f-8533-109476057a3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825374211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.2825374211
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.2068165690
Short name T633
Test name
Test status
Simulation time 6553533549 ps
CPU time 17.85 seconds
Started Mar 21 01:25:45 PM PDT 24
Finished Mar 21 01:26:04 PM PDT 24
Peak memory 202280 kb
Host smart-d82ef92e-fb76-4ebf-a60f-501003e82164
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068165690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.2068165690
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3051839097
Short name T595
Test name
Test status
Simulation time 6618189037 ps
CPU time 335.16 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:31:12 PM PDT 24
Peak memory 202344 kb
Host smart-d6ae79f4-ae2b-4902-b57d-c703282ce87f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051839097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.3051839097
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.2054755650
Short name T168
Test name
Test status
Simulation time 344594651 ps
CPU time 3.46 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 01:26:03 PM PDT 24
Peak memory 202408 kb
Host smart-5b971a51-ce8b-4760-a869-56f3326d81c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054755650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2054755650
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.1159510779
Short name T893
Test name
Test status
Simulation time 55168125833 ps
CPU time 691.6 seconds
Started Mar 21 01:25:58 PM PDT 24
Finished Mar 21 01:37:30 PM PDT 24
Peak memory 362024 kb
Host smart-07c65fc0-33d5-4fea-87a1-9fd3fd49c715
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159510779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.1159510779
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.3224252288
Short name T717
Test name
Test status
Simulation time 2329346014 ps
CPU time 25.01 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:26:35 PM PDT 24
Peak memory 202424 kb
Host smart-a85194d6-5dd3-4e56-8193-1609290a5595
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224252288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3224252288
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.2903742413
Short name T401
Test name
Test status
Simulation time 518276970656 ps
CPU time 3387.79 seconds
Started Mar 21 01:25:39 PM PDT 24
Finished Mar 21 02:22:07 PM PDT 24
Peak memory 380420 kb
Host smart-ccb30df4-4dbd-47b3-a296-d46b56fc8621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903742413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.2903742413
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1753370066
Short name T771
Test name
Test status
Simulation time 502868184 ps
CPU time 9.76 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:26:08 PM PDT 24
Peak memory 211868 kb
Host smart-67da7d14-7d0f-4f6a-aec7-0c0927c164f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1753370066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1753370066
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1723248761
Short name T419
Test name
Test status
Simulation time 18769506889 ps
CPU time 266.6 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 01:30:02 PM PDT 24
Peak memory 202352 kb
Host smart-3237a927-32e7-4be0-b151-e1d1b1072fb5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723248761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.1723248761
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2998894739
Short name T484
Test name
Test status
Simulation time 3716756728 ps
CPU time 5.73 seconds
Started Mar 21 01:25:59 PM PDT 24
Finished Mar 21 01:26:06 PM PDT 24
Peak memory 210420 kb
Host smart-1480a997-f7a7-49d9-b723-c10af178baba
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998894739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2998894739
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3171237661
Short name T616
Test name
Test status
Simulation time 18166498120 ps
CPU time 1198.17 seconds
Started Mar 21 01:25:56 PM PDT 24
Finished Mar 21 01:45:54 PM PDT 24
Peak memory 378500 kb
Host smart-6eebe505-0d76-43ac-8435-600895b2967c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171237661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.3171237661
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.4010553755
Short name T563
Test name
Test status
Simulation time 24571031 ps
CPU time 0.66 seconds
Started Mar 21 01:25:51 PM PDT 24
Finished Mar 21 01:25:52 PM PDT 24
Peak memory 202148 kb
Host smart-21c94ab2-24e1-428d-acb6-5444118fcfe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010553755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.4010553755
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.1296926827
Short name T424
Test name
Test status
Simulation time 242012725405 ps
CPU time 2340.31 seconds
Started Mar 21 01:25:53 PM PDT 24
Finished Mar 21 02:04:54 PM PDT 24
Peak memory 202368 kb
Host smart-7f94d2ff-35a7-403b-9652-eb079658b779
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296926827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.1296926827
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.3119864727
Short name T421
Test name
Test status
Simulation time 173798671072 ps
CPU time 1965.73 seconds
Started Mar 21 01:26:05 PM PDT 24
Finished Mar 21 01:58:51 PM PDT 24
Peak memory 379428 kb
Host smart-0f66b719-0fff-4c18-a05c-6d86f50c32bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119864727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.3119864727
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.2133785587
Short name T874
Test name
Test status
Simulation time 10163395359 ps
CPU time 59.87 seconds
Started Mar 21 01:25:37 PM PDT 24
Finished Mar 21 01:26:37 PM PDT 24
Peak memory 202432 kb
Host smart-febcd453-a4b3-4f7f-8432-ff90ccc4f890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133785587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.2133785587
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.2905831714
Short name T161
Test name
Test status
Simulation time 5228796879 ps
CPU time 67.27 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 01:27:15 PM PDT 24
Peak memory 316840 kb
Host smart-b1ecc714-6f77-4c74-80fa-b01d18639916
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905831714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.2905831714
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2273727745
Short name T818
Test name
Test status
Simulation time 17356399115 ps
CPU time 166.67 seconds
Started Mar 21 01:26:02 PM PDT 24
Finished Mar 21 01:28:49 PM PDT 24
Peak memory 210572 kb
Host smart-e5cd44da-cab3-490a-918f-85c7a3399ca0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273727745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.2273727745
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.2890394116
Short name T167
Test name
Test status
Simulation time 41241843171 ps
CPU time 301.3 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:31:03 PM PDT 24
Peak memory 203212 kb
Host smart-0ba6ac99-ef1d-4823-a135-c33803ada8ee
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890394116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.2890394116
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.1667290896
Short name T182
Test name
Test status
Simulation time 6859890784 ps
CPU time 534.69 seconds
Started Mar 21 01:25:54 PM PDT 24
Finished Mar 21 01:34:49 PM PDT 24
Peak memory 373124 kb
Host smart-2bcace58-7a27-4598-b4e5-88602f35fa43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667290896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.1667290896
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.3735309102
Short name T38
Test name
Test status
Simulation time 3746365036 ps
CPU time 11.09 seconds
Started Mar 21 01:25:55 PM PDT 24
Finished Mar 21 01:26:06 PM PDT 24
Peak memory 202316 kb
Host smart-ab889278-e41e-465e-bc30-56871cc9f0d4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735309102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.3735309102
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2159614874
Short name T218
Test name
Test status
Simulation time 14885609645 ps
CPU time 434.46 seconds
Started Mar 21 01:25:54 PM PDT 24
Finished Mar 21 01:33:09 PM PDT 24
Peak memory 202420 kb
Host smart-0a7fdbc5-0728-477a-8135-34ecc104750c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159614874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.2159614874
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.2586315783
Short name T741
Test name
Test status
Simulation time 352971404 ps
CPU time 3.29 seconds
Started Mar 21 01:25:50 PM PDT 24
Finished Mar 21 01:25:53 PM PDT 24
Peak memory 202504 kb
Host smart-dc06faad-c1f4-455f-a776-1bf83fdc8b99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586315783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2586315783
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.347103306
Short name T393
Test name
Test status
Simulation time 32049207315 ps
CPU time 787.88 seconds
Started Mar 21 01:26:05 PM PDT 24
Finished Mar 21 01:39:13 PM PDT 24
Peak memory 376296 kb
Host smart-771c4167-3475-4a64-aecf-d1ad9934e8cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347103306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.347103306
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.3161475317
Short name T700
Test name
Test status
Simulation time 3516926218 ps
CPU time 14.23 seconds
Started Mar 21 01:25:51 PM PDT 24
Finished Mar 21 01:26:05 PM PDT 24
Peak memory 202512 kb
Host smart-f216d75f-4345-41e1-8ad4-a34ee8fd49bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161475317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3161475317
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.2233336849
Short name T287
Test name
Test status
Simulation time 195052204803 ps
CPU time 3455.31 seconds
Started Mar 21 01:25:56 PM PDT 24
Finished Mar 21 02:23:32 PM PDT 24
Peak memory 382536 kb
Host smart-1e791805-b8e6-401f-80dc-9fa0068736b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233336849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.2233336849
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2589227496
Short name T309
Test name
Test status
Simulation time 724123950 ps
CPU time 23.28 seconds
Started Mar 21 01:26:04 PM PDT 24
Finished Mar 21 01:26:27 PM PDT 24
Peak memory 211996 kb
Host smart-60f413af-ecba-4385-9740-3d8fdeb09532
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2589227496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.2589227496
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1550536525
Short name T389
Test name
Test status
Simulation time 18454635631 ps
CPU time 273.54 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:30:37 PM PDT 24
Peak memory 202456 kb
Host smart-7ab54532-cd4d-4e4b-8491-a0061797f937
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550536525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.1550536525
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3420415751
Short name T334
Test name
Test status
Simulation time 740977919 ps
CPU time 50.5 seconds
Started Mar 21 01:26:02 PM PDT 24
Finished Mar 21 01:26:53 PM PDT 24
Peak memory 295168 kb
Host smart-86424901-0e48-47c6-b417-e344515ec86a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420415751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3420415751
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1666971750
Short name T511
Test name
Test status
Simulation time 48572204040 ps
CPU time 1217.36 seconds
Started Mar 21 01:25:55 PM PDT 24
Finished Mar 21 01:46:12 PM PDT 24
Peak memory 375164 kb
Host smart-79859a49-006e-46d8-8f2b-9f97bed4e36e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666971750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.1666971750
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.2573614926
Short name T487
Test name
Test status
Simulation time 58552590 ps
CPU time 0.67 seconds
Started Mar 21 01:25:50 PM PDT 24
Finished Mar 21 01:25:51 PM PDT 24
Peak memory 201880 kb
Host smart-e6a50b64-4881-439c-886f-96917dc105d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573614926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.2573614926
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.3185801180
Short name T295
Test name
Test status
Simulation time 105564327576 ps
CPU time 2289.49 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 02:04:11 PM PDT 24
Peak memory 202492 kb
Host smart-d678c327-b21d-443f-ac68-15ef9a45cb9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185801180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.3185801180
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.2820858063
Short name T897
Test name
Test status
Simulation time 8809207205 ps
CPU time 632.06 seconds
Started Mar 21 01:25:54 PM PDT 24
Finished Mar 21 01:36:26 PM PDT 24
Peak memory 362704 kb
Host smart-16899241-385e-4256-b2a8-d7221d4f0a8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820858063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.2820858063
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.246016117
Short name T652
Test name
Test status
Simulation time 9511753785 ps
CPU time 58.55 seconds
Started Mar 21 01:26:06 PM PDT 24
Finished Mar 21 01:27:05 PM PDT 24
Peak memory 202100 kb
Host smart-1ff7c133-eb62-4481-98ae-7ab51d876ddd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246016117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_esc
alation.246016117
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.4166183554
Short name T651
Test name
Test status
Simulation time 2793900092 ps
CPU time 49.7 seconds
Started Mar 21 01:25:56 PM PDT 24
Finished Mar 21 01:26:45 PM PDT 24
Peak memory 300620 kb
Host smart-39eb7c80-09e6-48fd-b294-f6f1b9f2c19d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166183554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.4166183554
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3644842329
Short name T802
Test name
Test status
Simulation time 2613248944 ps
CPU time 76.73 seconds
Started Mar 21 01:25:37 PM PDT 24
Finished Mar 21 01:26:54 PM PDT 24
Peak memory 210508 kb
Host smart-c603edd0-9d68-4f77-99ae-b04b28d0a642
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644842329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.3644842329
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.1809033716
Short name T244
Test name
Test status
Simulation time 8600012050 ps
CPU time 131.2 seconds
Started Mar 21 01:25:55 PM PDT 24
Finished Mar 21 01:28:06 PM PDT 24
Peak memory 202800 kb
Host smart-cafcbfdb-77df-4a3c-abae-595ea0d635cf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809033716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.1809033716
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.3677482738
Short name T231
Test name
Test status
Simulation time 31572874192 ps
CPU time 826.44 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 01:39:47 PM PDT 24
Peak memory 373100 kb
Host smart-eb9eeba5-8153-466c-849f-05a992b5936b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677482738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.3677482738
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.2090535638
Short name T738
Test name
Test status
Simulation time 4693271946 ps
CPU time 53.72 seconds
Started Mar 21 01:25:56 PM PDT 24
Finished Mar 21 01:26:51 PM PDT 24
Peak memory 291224 kb
Host smart-09efe823-1e7d-40d1-888d-e36d864f52a6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090535638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.2090535638
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1467799693
Short name T740
Test name
Test status
Simulation time 12325180196 ps
CPU time 162.36 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 01:28:18 PM PDT 24
Peak memory 202344 kb
Host smart-a7a5760c-6384-4572-b698-d9fda6059ee2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467799693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.1467799693
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.4107197689
Short name T533
Test name
Test status
Simulation time 1679129622 ps
CPU time 3.77 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:26:14 PM PDT 24
Peak memory 202424 kb
Host smart-1cee8b78-6ec9-4592-949e-5316d4033aa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107197689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.4107197689
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.3617730257
Short name T392
Test name
Test status
Simulation time 3992124839 ps
CPU time 1231.57 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:46:29 PM PDT 24
Peak memory 376396 kb
Host smart-f7859c43-0d4f-46a7-bea6-1666e733d8a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617730257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3617730257
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.1235230999
Short name T133
Test name
Test status
Simulation time 433270255 ps
CPU time 9.89 seconds
Started Mar 21 01:25:44 PM PDT 24
Finished Mar 21 01:25:54 PM PDT 24
Peak memory 202328 kb
Host smart-c873e733-a540-441b-8e6b-a62afc1051d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235230999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1235230999
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.887801292
Short name T24
Test name
Test status
Simulation time 520122175798 ps
CPU time 3499.97 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 02:24:23 PM PDT 24
Peak memory 379300 kb
Host smart-00ac3c51-986c-4b02-bdeb-f799fba82551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887801292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_stress_all.887801292
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1418316857
Short name T99
Test name
Test status
Simulation time 7861510867 ps
CPU time 245.81 seconds
Started Mar 21 01:25:56 PM PDT 24
Finished Mar 21 01:30:02 PM PDT 24
Peak memory 374196 kb
Host smart-c3d78e2d-82d2-4764-a53c-cfdf2b804e83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1418316857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.1418316857
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.586954946
Short name T636
Test name
Test status
Simulation time 3576949247 ps
CPU time 195.11 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:28:52 PM PDT 24
Peak memory 202380 kb
Host smart-b6abd437-3d4b-444b-97d0-3b7ce05c8002
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586954946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_stress_pipeline.586954946
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3760503761
Short name T510
Test name
Test status
Simulation time 2657356039 ps
CPU time 5.93 seconds
Started Mar 21 01:25:52 PM PDT 24
Finished Mar 21 01:25:58 PM PDT 24
Peak memory 202236 kb
Host smart-dad52282-f54d-4ab0-8bc4-dd84d8b42675
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760503761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.3760503761
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.646210369
Short name T388
Test name
Test status
Simulation time 7781566989 ps
CPU time 995.24 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:42:33 PM PDT 24
Peak memory 378252 kb
Host smart-c1fcccf2-ed31-4de4-97a9-9648056135f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646210369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_access_during_key_req.646210369
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.2609628346
Short name T909
Test name
Test status
Simulation time 17584902 ps
CPU time 0.66 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:26:04 PM PDT 24
Peak memory 202084 kb
Host smart-d99fa229-5127-49b5-b8b7-55c485cb9261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609628346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.2609628346
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.2282744625
Short name T937
Test name
Test status
Simulation time 19591658457 ps
CPU time 644.01 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:36:46 PM PDT 24
Peak memory 202520 kb
Host smart-ce2e24ce-5298-4d5c-bc01-7e9b01efbf7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282744625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.2282744625
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.500595462
Short name T335
Test name
Test status
Simulation time 24816449676 ps
CPU time 1139.57 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:45:01 PM PDT 24
Peak memory 373264 kb
Host smart-c37e6257-10a9-4d18-be70-caa2a0c881a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500595462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executabl
e.500595462
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.3121208983
Short name T592
Test name
Test status
Simulation time 8265940139 ps
CPU time 50.1 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:26:58 PM PDT 24
Peak memory 210644 kb
Host smart-c37c38d7-b1be-4c97-b68f-ffd9f284cc35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121208983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.3121208983
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.3887502243
Short name T400
Test name
Test status
Simulation time 1410080680 ps
CPU time 6.88 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:18 PM PDT 24
Peak memory 215924 kb
Host smart-93a2fbc5-d6b0-4c8a-acd0-8d21e69531a3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887502243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.3887502243
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.4209383663
Short name T183
Test name
Test status
Simulation time 994205868 ps
CPU time 61.13 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:27:09 PM PDT 24
Peak memory 210528 kb
Host smart-76562a2b-0466-4cf1-9261-3a7b7a0c6ea1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209383663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.4209383663
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.3032761169
Short name T193
Test name
Test status
Simulation time 9616651386 ps
CPU time 258.49 seconds
Started Mar 21 01:25:56 PM PDT 24
Finished Mar 21 01:30:15 PM PDT 24
Peak memory 202828 kb
Host smart-8a42b1dd-4ee0-4bd2-bea7-f3b0775889a7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032761169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.3032761169
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.271595865
Short name T463
Test name
Test status
Simulation time 8558142815 ps
CPU time 351.4 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:31:28 PM PDT 24
Peak memory 335204 kb
Host smart-f2410280-b735-4e4c-a86d-12f98e6fefe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271595865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multip
le_keys.271595865
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.2880622428
Short name T603
Test name
Test status
Simulation time 1639217707 ps
CPU time 9.2 seconds
Started Mar 21 01:25:38 PM PDT 24
Finished Mar 21 01:25:48 PM PDT 24
Peak memory 202356 kb
Host smart-0c1281d3-0222-452c-90a3-99f16f6a85f0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880622428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.2880622428
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.4177571799
Short name T489
Test name
Test status
Simulation time 13473334577 ps
CPU time 313.67 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:31:17 PM PDT 24
Peak memory 202376 kb
Host smart-5fc603e9-9e80-4bc8-a452-e24a6b601337
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177571799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.4177571799
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.2892014140
Short name T157
Test name
Test status
Simulation time 352353493 ps
CPU time 3.18 seconds
Started Mar 21 01:26:06 PM PDT 24
Finished Mar 21 01:26:09 PM PDT 24
Peak memory 202404 kb
Host smart-67de158e-36bc-4813-81dd-6d29ce7f98d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892014140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2892014140
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.2917145703
Short name T521
Test name
Test status
Simulation time 11921170001 ps
CPU time 936.06 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 01:41:37 PM PDT 24
Peak memory 370032 kb
Host smart-93a4b582-3dea-47f2-ac7b-54c2555e6bdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917145703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2917145703
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.2949390982
Short name T674
Test name
Test status
Simulation time 921857703 ps
CPU time 106.65 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:28:01 PM PDT 24
Peak memory 334192 kb
Host smart-0a748ee2-c7ac-4282-92e7-20950f5a5c0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949390982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2949390982
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.2347631999
Short name T404
Test name
Test status
Simulation time 1739200635282 ps
CPU time 7888.02 seconds
Started Mar 21 01:26:02 PM PDT 24
Finished Mar 21 03:37:31 PM PDT 24
Peak memory 385376 kb
Host smart-6019fc0e-69df-45b7-ae14-29484576d92c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347631999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.2347631999
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.235691178
Short name T100
Test name
Test status
Simulation time 1201777317 ps
CPU time 28.74 seconds
Started Mar 21 01:26:05 PM PDT 24
Finished Mar 21 01:26:34 PM PDT 24
Peak memory 211724 kb
Host smart-5f6ebf95-45ff-4817-bfe7-3f79fada96ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=235691178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.235691178
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.417509656
Short name T588
Test name
Test status
Simulation time 17734534317 ps
CPU time 300.91 seconds
Started Mar 21 01:25:49 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 202364 kb
Host smart-563f3256-360e-4e58-a640-87380d669651
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417509656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.sram_ctrl_stress_pipeline.417509656
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3574436214
Short name T217
Test name
Test status
Simulation time 1476143629 ps
CPU time 25.45 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 01:26:33 PM PDT 24
Peak memory 280968 kb
Host smart-0283c656-f9ba-48f6-bd5b-6697a7f4fc07
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574436214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.3574436214
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1521269384
Short name T881
Test name
Test status
Simulation time 66380143322 ps
CPU time 1885.22 seconds
Started Mar 21 01:26:04 PM PDT 24
Finished Mar 21 01:57:30 PM PDT 24
Peak memory 378296 kb
Host smart-d5ce17d9-63b0-4c50-a36a-7594b535b1ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521269384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.1521269384
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.4163011900
Short name T397
Test name
Test status
Simulation time 18632783 ps
CPU time 0.66 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:26:04 PM PDT 24
Peak memory 202088 kb
Host smart-2c1ea198-e2bf-4132-a434-4a21a12df836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163011900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.4163011900
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.1853156812
Short name T602
Test name
Test status
Simulation time 142446103020 ps
CPU time 896.09 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 01:40:57 PM PDT 24
Peak memory 202752 kb
Host smart-f82ecaeb-bb17-42bc-8dd5-4e51eb944573
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853156812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.1853156812
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.514997252
Short name T621
Test name
Test status
Simulation time 88916155686 ps
CPU time 601.34 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 01:36:02 PM PDT 24
Peak memory 350628 kb
Host smart-7a760297-1ad7-4b10-a0cd-81c3a508ee66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514997252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl
e.514997252
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.1209036272
Short name T27
Test name
Test status
Simulation time 14249882719 ps
CPU time 79.38 seconds
Started Mar 21 01:25:54 PM PDT 24
Finished Mar 21 01:27:13 PM PDT 24
Peak memory 202384 kb
Host smart-dc9d2ef7-64dd-4295-a9f2-a18ccade829e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209036272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.1209036272
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.3325933214
Short name T906
Test name
Test status
Simulation time 750691924 ps
CPU time 69.37 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:27:13 PM PDT 24
Peak memory 326032 kb
Host smart-e22dcfa9-ae3a-46c4-b7e0-94f56efff41d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325933214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.3325933214
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3394016566
Short name T426
Test name
Test status
Simulation time 3637032708 ps
CPU time 66.45 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:27:18 PM PDT 24
Peak memory 210532 kb
Host smart-3b48008e-8bdd-44e4-8ce4-c51e122bd217
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394016566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.3394016566
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.3796712185
Short name T538
Test name
Test status
Simulation time 6159488152 ps
CPU time 256.06 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 01:30:24 PM PDT 24
Peak memory 202868 kb
Host smart-f60bf314-5048-41da-9b1b-17d00bf48d8e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796712185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.3796712185
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.3476847668
Short name T380
Test name
Test status
Simulation time 15491431166 ps
CPU time 886.64 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:40:59 PM PDT 24
Peak memory 374212 kb
Host smart-d9684d61-9a50-4251-8940-2f6a49413b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476847668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.3476847668
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.3028314736
Short name T1
Test name
Test status
Simulation time 672161401 ps
CPU time 30.39 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:26:31 PM PDT 24
Peak memory 276816 kb
Host smart-d9dcc68b-2d3d-4402-bfc6-1e2e3e926b79
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028314736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.3028314736
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1798603751
Short name T753
Test name
Test status
Simulation time 26127156122 ps
CPU time 286.27 seconds
Started Mar 21 01:26:02 PM PDT 24
Finished Mar 21 01:30:49 PM PDT 24
Peak memory 202436 kb
Host smart-9416723f-d71c-48e4-bbaf-746ef69f6b95
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798603751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.1798603751
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.677041030
Short name T2
Test name
Test status
Simulation time 1408034066 ps
CPU time 3.01 seconds
Started Mar 21 01:26:05 PM PDT 24
Finished Mar 21 01:26:08 PM PDT 24
Peak memory 202500 kb
Host smart-9f2f094a-6140-4cd6-b788-54da9ca5716d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677041030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.677041030
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.4184976159
Short name T864
Test name
Test status
Simulation time 12235137842 ps
CPU time 1128.99 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:44:59 PM PDT 24
Peak memory 378276 kb
Host smart-173a384c-d361-4117-ac90-acf2b0099069
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184976159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.4184976159
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.1936621856
Short name T781
Test name
Test status
Simulation time 933786298 ps
CPU time 19.49 seconds
Started Mar 21 01:25:55 PM PDT 24
Finished Mar 21 01:26:15 PM PDT 24
Peak memory 202296 kb
Host smart-c986ab6c-b9bb-4ed4-bcc3-0582e2abd1a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936621856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1936621856
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.2913179932
Short name T308
Test name
Test status
Simulation time 75870866129 ps
CPU time 3312.6 seconds
Started Mar 21 01:26:06 PM PDT 24
Finished Mar 21 02:21:20 PM PDT 24
Peak memory 385192 kb
Host smart-a85213fa-6390-458c-9fde-37b5c85fbc0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913179932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.sram_ctrl_stress_all.2913179932
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3833013441
Short name T101
Test name
Test status
Simulation time 1488714419 ps
CPU time 13.2 seconds
Started Mar 21 01:26:04 PM PDT 24
Finished Mar 21 01:26:17 PM PDT 24
Peak memory 210740 kb
Host smart-357c3ed8-9815-47f8-9d41-2fc99915544c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3833013441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.3833013441
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.916325333
Short name T857
Test name
Test status
Simulation time 18007051778 ps
CPU time 224.31 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:29:56 PM PDT 24
Peak memory 202408 kb
Host smart-aaae4580-0e3a-4132-929e-174c2d90c851
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916325333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_stress_pipeline.916325333
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1116395878
Short name T784
Test name
Test status
Simulation time 3065901502 ps
CPU time 115.5 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 01:28:10 PM PDT 24
Peak memory 347516 kb
Host smart-491d6004-9718-4b8c-9a4a-da81a248dc5e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116395878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1116395878
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3935010152
Short name T850
Test name
Test status
Simulation time 19329058262 ps
CPU time 756.02 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:38:38 PM PDT 24
Peak memory 371052 kb
Host smart-7996a1e1-03f5-40d0-9b9e-11b22e2e7540
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935010152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.3935010152
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.35922507
Short name T569
Test name
Test status
Simulation time 70364200 ps
CPU time 0.63 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:26:13 PM PDT 24
Peak memory 202040 kb
Host smart-de908f36-6428-44bb-919b-dd6ae931dc48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35922507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_alert_test.35922507
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.3425621705
Short name T813
Test name
Test status
Simulation time 63600991686 ps
CPU time 2193.51 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 202344 kb
Host smart-93d69bf3-dcd3-4e3a-baf7-7c5701ca56bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425621705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.3425621705
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.4262497470
Short name T886
Test name
Test status
Simulation time 100245220509 ps
CPU time 1359.6 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:48:52 PM PDT 24
Peak memory 378424 kb
Host smart-d26f3150-6ae5-4391-a782-c4e0083f2272
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262497470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.4262497470
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.3632370157
Short name T351
Test name
Test status
Simulation time 118308053206 ps
CPU time 59.96 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:27:12 PM PDT 24
Peak memory 202340 kb
Host smart-f0acb090-203a-49d3-be78-25787ef06659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632370157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.3632370157
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.1835470681
Short name T234
Test name
Test status
Simulation time 680963472 ps
CPU time 5.6 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:26:03 PM PDT 24
Peak memory 210376 kb
Host smart-32fa2ef2-5845-4e19-aaf8-0abd9077a25a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835470681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.1835470681
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1946208930
Short name T327
Test name
Test status
Simulation time 8768172578 ps
CPU time 151.2 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:28:41 PM PDT 24
Peak memory 210480 kb
Host smart-8f7d2ab8-5c9b-4f81-8f71-a42bb11e4678
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946208930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.1946208930
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.2261954806
Short name T609
Test name
Test status
Simulation time 2039147422 ps
CPU time 124.36 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:28:16 PM PDT 24
Peak memory 202520 kb
Host smart-6c296709-6219-4b24-9967-74afcadf3ff3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261954806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.2261954806
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.124513372
Short name T370
Test name
Test status
Simulation time 40674121057 ps
CPU time 788.89 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:39:19 PM PDT 24
Peak memory 351656 kb
Host smart-dfbbda3e-c719-4517-b67c-56f9d4928387
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124513372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip
le_keys.124513372
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.4230041881
Short name T661
Test name
Test status
Simulation time 3427979433 ps
CPU time 10.82 seconds
Started Mar 21 01:26:05 PM PDT 24
Finished Mar 21 01:26:16 PM PDT 24
Peak memory 202340 kb
Host smart-b3dba680-833c-4f7d-b1a6-b5bf2bb118e8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230041881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.4230041881
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1197324153
Short name T434
Test name
Test status
Simulation time 20284805654 ps
CPU time 474.79 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:33:58 PM PDT 24
Peak memory 202412 kb
Host smart-e2f294ca-be5a-42b6-921d-abdd9822aa33
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197324153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.1197324153
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.1048304108
Short name T288
Test name
Test status
Simulation time 356458356 ps
CPU time 3.21 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 01:26:10 PM PDT 24
Peak memory 202496 kb
Host smart-4e42456f-02b2-4e6e-90ae-ede9abc42fbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048304108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.1048304108
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.190498204
Short name T332
Test name
Test status
Simulation time 3743160655 ps
CPU time 1620.29 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 01:53:07 PM PDT 24
Peak memory 377300 kb
Host smart-e481d8c1-0b3b-44bb-925f-0efe14b77be7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190498204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.190498204
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.4212812561
Short name T639
Test name
Test status
Simulation time 386562498 ps
CPU time 4.09 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:26:05 PM PDT 24
Peak memory 202316 kb
Host smart-3c866ac2-85f3-45ac-be74-1947f2e03899
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212812561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.4212812561
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.3716582848
Short name T481
Test name
Test status
Simulation time 47216802808 ps
CPU time 2726.21 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 02:11:35 PM PDT 24
Peak memory 382304 kb
Host smart-554ad281-1f18-4717-982f-a9ac580650fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716582848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.3716582848
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.537660376
Short name T518
Test name
Test status
Simulation time 1516618280 ps
CPU time 8.93 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 01:26:09 PM PDT 24
Peak memory 210560 kb
Host smart-17394196-b20f-4cd0-bee3-bec2c231f0d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=537660376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.537660376
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.268934403
Short name T450
Test name
Test status
Simulation time 24728755850 ps
CPU time 396.63 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 202296 kb
Host smart-ae389b72-eef5-4499-baad-61db85acab52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268934403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.sram_ctrl_stress_pipeline.268934403
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1501880817
Short name T271
Test name
Test status
Simulation time 771278646 ps
CPU time 44.69 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 01:26:52 PM PDT 24
Peak memory 300432 kb
Host smart-d85c0d88-6d51-4036-afb6-25e016f6bc8f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501880817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1501880817
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3105522029
Short name T585
Test name
Test status
Simulation time 6246604099 ps
CPU time 873.76 seconds
Started Mar 21 01:26:02 PM PDT 24
Finished Mar 21 01:40:37 PM PDT 24
Peak memory 378888 kb
Host smart-e9884d64-cca3-4fb7-9f0a-c4ad25ddd41b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105522029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3105522029
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2890384366
Short name T578
Test name
Test status
Simulation time 23195823 ps
CPU time 0.66 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:26:13 PM PDT 24
Peak memory 202120 kb
Host smart-dedd6b16-6c26-4982-bc1d-a22178483bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890384366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2890384366
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.1501832471
Short name T299
Test name
Test status
Simulation time 55407059989 ps
CPU time 1230.38 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:46:43 PM PDT 24
Peak memory 202660 kb
Host smart-a520c030-09cb-4e64-b1ca-ee3c37547644
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501832471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.1501832471
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.1344537395
Short name T860
Test name
Test status
Simulation time 45210201858 ps
CPU time 671.05 seconds
Started Mar 21 01:26:02 PM PDT 24
Finished Mar 21 01:37:13 PM PDT 24
Peak memory 375264 kb
Host smart-d6427818-b838-4cb0-9957-b1d60fa615c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344537395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.1344537395
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.4161618027
Short name T403
Test name
Test status
Simulation time 9089601894 ps
CPU time 51.28 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:27:01 PM PDT 24
Peak memory 210536 kb
Host smart-5870fb13-5ac7-43a8-8f52-5c5b007927a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161618027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.4161618027
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.4093099442
Short name T396
Test name
Test status
Simulation time 3016819157 ps
CPU time 112.56 seconds
Started Mar 21 01:26:06 PM PDT 24
Finished Mar 21 01:27:59 PM PDT 24
Peak memory 356836 kb
Host smart-43fa1011-de0d-42e7-83cf-83ecfa52c5dc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093099442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.4093099442
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2488443153
Short name T496
Test name
Test status
Simulation time 2353640757 ps
CPU time 74.52 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:27:27 PM PDT 24
Peak memory 210632 kb
Host smart-610409cd-be22-48a4-abe3-d40042a7bce7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488443153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.2488443153
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2183607003
Short name T363
Test name
Test status
Simulation time 41304577982 ps
CPU time 156.49 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:28:48 PM PDT 24
Peak memory 202356 kb
Host smart-c0004375-0440-4c01-91e2-08ade5994d33
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183607003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2183607003
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.1738468785
Short name T736
Test name
Test status
Simulation time 19043957216 ps
CPU time 1144.14 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:45:08 PM PDT 24
Peak memory 377288 kb
Host smart-816a9cdb-d60b-4f38-9aea-998c9c5ecca3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738468785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.1738468785
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.271495560
Short name T779
Test name
Test status
Simulation time 1456655836 ps
CPU time 48.47 seconds
Started Mar 21 01:26:05 PM PDT 24
Finished Mar 21 01:26:53 PM PDT 24
Peak memory 300488 kb
Host smart-3c1cb44d-76c2-4ea3-b03b-8802f4b952d9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271495560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s
ram_ctrl_partial_access.271495560
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1812263060
Short name T348
Test name
Test status
Simulation time 14012264443 ps
CPU time 317.72 seconds
Started Mar 21 01:26:04 PM PDT 24
Finished Mar 21 01:31:22 PM PDT 24
Peak memory 202332 kb
Host smart-0aeebde1-a3ee-4c1b-b749-5df3d089880b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812263060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.1812263060
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.435345999
Short name T8
Test name
Test status
Simulation time 3742198134 ps
CPU time 4.17 seconds
Started Mar 21 01:26:17 PM PDT 24
Finished Mar 21 01:26:21 PM PDT 24
Peak memory 202480 kb
Host smart-574e4d6e-2531-424b-98e2-43f76723618e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435345999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.435345999
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.4065404507
Short name T539
Test name
Test status
Simulation time 39989571869 ps
CPU time 958.21 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:42:11 PM PDT 24
Peak memory 379420 kb
Host smart-92e3b648-b74f-4450-ba91-895963bcadfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065404507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4065404507
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.585070434
Short name T381
Test name
Test status
Simulation time 3056206716 ps
CPU time 10.21 seconds
Started Mar 21 01:25:58 PM PDT 24
Finished Mar 21 01:26:09 PM PDT 24
Peak memory 202368 kb
Host smart-c3f8f433-e371-4d39-848f-2281051a140a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585070434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.585070434
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.798800050
Short name T620
Test name
Test status
Simulation time 59806980651 ps
CPU time 3460.14 seconds
Started Mar 21 01:26:06 PM PDT 24
Finished Mar 21 02:23:47 PM PDT 24
Peak memory 387504 kb
Host smart-885ace4b-adef-4293-a272-7ff9e44d80a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798800050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_stress_all.798800050
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.841447573
Short name T570
Test name
Test status
Simulation time 428817097 ps
CPU time 11.73 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:26:22 PM PDT 24
Peak memory 210620 kb
Host smart-81f7929d-3dbe-4250-90b1-f06f8252a4b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=841447573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.841447573
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1781737996
Short name T445
Test name
Test status
Simulation time 22820652999 ps
CPU time 435.97 seconds
Started Mar 21 01:26:05 PM PDT 24
Finished Mar 21 01:33:21 PM PDT 24
Peak memory 202440 kb
Host smart-1782fab3-d825-4c2a-be62-395494a60dd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781737996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.1781737996
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.303255926
Short name T591
Test name
Test status
Simulation time 764172362 ps
CPU time 36.83 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:48 PM PDT 24
Peak memory 289640 kb
Host smart-4f688c24-2780-4752-b232-4ab9181adf75
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303255926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.303255926
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.590084603
Short name T402
Test name
Test status
Simulation time 22003901207 ps
CPU time 620.06 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:35:44 PM PDT 24
Peak memory 378288 kb
Host smart-b27e2070-a067-4af3-8bdc-4986fc17f60d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590084603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.sram_ctrl_access_during_key_req.590084603
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.4292735410
Short name T143
Test name
Test status
Simulation time 20558464 ps
CPU time 0.67 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:25:22 PM PDT 24
Peak memory 202092 kb
Host smart-5d74355c-a236-4392-b762-9ccefcf5a2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292735410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.4292735410
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.4061877536
Short name T354
Test name
Test status
Simulation time 78690541167 ps
CPU time 1532.99 seconds
Started Mar 21 01:25:16 PM PDT 24
Finished Mar 21 01:50:49 PM PDT 24
Peak memory 202576 kb
Host smart-2743c9df-9640-4383-a7a1-2734cd5978c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061877536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
4061877536
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.2875898409
Short name T659
Test name
Test status
Simulation time 46153639052 ps
CPU time 670.09 seconds
Started Mar 21 01:25:29 PM PDT 24
Finished Mar 21 01:36:39 PM PDT 24
Peak memory 374160 kb
Host smart-2e0d2cb2-8ab2-4959-93c1-cd0eb6d34feb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875898409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.2875898409
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.2730531258
Short name T708
Test name
Test status
Simulation time 13760201087 ps
CPU time 25.79 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:26:00 PM PDT 24
Peak memory 215120 kb
Host smart-64295691-28bd-46a4-9712-13055459aff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730531258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.2730531258
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.851005053
Short name T673
Test name
Test status
Simulation time 2896798047 ps
CPU time 40.23 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:26:05 PM PDT 24
Peak memory 294444 kb
Host smart-cb4fef73-6411-42d1-9e24-af26d231f8f4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851005053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.sram_ctrl_max_throughput.851005053
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1936675967
Short name T79
Test name
Test status
Simulation time 10487927143 ps
CPU time 149.8 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:27:53 PM PDT 24
Peak memory 210592 kb
Host smart-305f54b1-fa4c-422b-8311-98c3199fbaf9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936675967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.1936675967
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.3889015413
Short name T322
Test name
Test status
Simulation time 15160256120 ps
CPU time 260.61 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:29:46 PM PDT 24
Peak memory 202320 kb
Host smart-387f6563-2c8b-4112-b774-637ddd80372a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889015413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.3889015413
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.1317873289
Short name T804
Test name
Test status
Simulation time 15513238518 ps
CPU time 773.5 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:38:17 PM PDT 24
Peak memory 373104 kb
Host smart-38ffdc2c-12cc-499c-a338-d5fd3e090e4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317873289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.1317873289
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.1907107020
Short name T678
Test name
Test status
Simulation time 6032027159 ps
CPU time 14.55 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:25:40 PM PDT 24
Peak memory 202420 kb
Host smart-92bf8885-2e30-4592-be6d-9f3d631eef4b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907107020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.1907107020
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1175080810
Short name T759
Test name
Test status
Simulation time 84007846506 ps
CPU time 511.6 seconds
Started Mar 21 01:25:31 PM PDT 24
Finished Mar 21 01:34:02 PM PDT 24
Peak memory 202412 kb
Host smart-3174f9ef-15ea-4890-81bd-261000e6ef63
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175080810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.1175080810
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.942973615
Short name T277
Test name
Test status
Simulation time 2249138046 ps
CPU time 3.69 seconds
Started Mar 21 01:25:20 PM PDT 24
Finished Mar 21 01:25:24 PM PDT 24
Peak memory 202436 kb
Host smart-fb73ccc5-5a6d-4811-b70a-08db79fc5db4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942973615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.942973615
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.332205149
Short name T875
Test name
Test status
Simulation time 52651432285 ps
CPU time 1450.05 seconds
Started Mar 21 01:25:29 PM PDT 24
Finished Mar 21 01:49:39 PM PDT 24
Peak memory 378260 kb
Host smart-5c5dfaec-0c37-4fb2-8fed-6cac7ca5196b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332205149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.332205149
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.734648202
Short name T22
Test name
Test status
Simulation time 230164667 ps
CPU time 2.2 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:25:36 PM PDT 24
Peak memory 221592 kb
Host smart-bacc2687-102b-43ee-99f7-d07e40079ec1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734648202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_sec_cm.734648202
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.1095799670
Short name T865
Test name
Test status
Simulation time 1697149701 ps
CPU time 6.33 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:25:30 PM PDT 24
Peak memory 212924 kb
Host smart-66049615-679e-4ae0-ad3e-c83cab0b93b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095799670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1095799670
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.3942611267
Short name T828
Test name
Test status
Simulation time 73637214361 ps
CPU time 3958.93 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 02:31:25 PM PDT 24
Peak memory 204616 kb
Host smart-3d0a9d83-3b4b-41a9-9b2a-78d4ea4f78e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942611267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.3942611267
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.469793860
Short name T28
Test name
Test status
Simulation time 792444937 ps
CPU time 18.02 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:25:41 PM PDT 24
Peak memory 210840 kb
Host smart-90dc361f-f515-40ce-99ce-3423397f874a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=469793860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.469793860
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.746402118
Short name T444
Test name
Test status
Simulation time 14755826721 ps
CPU time 216.67 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:29:13 PM PDT 24
Peak memory 202328 kb
Host smart-8df06730-9c38-4387-8989-c9475059f138
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746402118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_stress_pipeline.746402118
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.647678087
Short name T144
Test name
Test status
Simulation time 758642689 ps
CPU time 33.18 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:26:00 PM PDT 24
Peak memory 284072 kb
Host smart-4f443905-b979-4ad2-a299-c82463a2fe00
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647678087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.647678087
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1194767850
Short name T761
Test name
Test status
Simulation time 3336243781 ps
CPU time 378.74 seconds
Started Mar 21 01:25:56 PM PDT 24
Finished Mar 21 01:32:15 PM PDT 24
Peak memory 367932 kb
Host smart-cf40cf0c-947f-4246-8d9e-709e2e92c4a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194767850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.1194767850
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.1920568705
Short name T683
Test name
Test status
Simulation time 13617857 ps
CPU time 0.66 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:12 PM PDT 24
Peak memory 201912 kb
Host smart-236836ba-0058-4f4a-a4b4-3b4ffc451d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920568705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.1920568705
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.2765687942
Short name T352
Test name
Test status
Simulation time 6897472055 ps
CPU time 463.75 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:33:52 PM PDT 24
Peak memory 202752 kb
Host smart-851d03a1-5c1c-469c-8681-73d82459921a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765687942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.2765687942
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.3681303358
Short name T150
Test name
Test status
Simulation time 3953410889 ps
CPU time 527.42 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:34:45 PM PDT 24
Peak memory 375232 kb
Host smart-696f323d-d433-4576-aa13-d6c515ce7038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681303358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.3681303358
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.2642190313
Short name T53
Test name
Test status
Simulation time 8447829444 ps
CPU time 46.43 seconds
Started Mar 21 01:26:14 PM PDT 24
Finished Mar 21 01:27:01 PM PDT 24
Peak memory 202376 kb
Host smart-1630ea5e-0f87-463d-8e28-b9c236e131c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642190313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.2642190313
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.1395313014
Short name T796
Test name
Test status
Simulation time 798318679 ps
CPU time 99.44 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:27:51 PM PDT 24
Peak memory 360796 kb
Host smart-50a21d08-a7f7-4277-a9bd-22d8ce051255
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395313014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.1395313014
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1751178369
Short name T78
Test name
Test status
Simulation time 3950233912 ps
CPU time 62.01 seconds
Started Mar 21 01:26:06 PM PDT 24
Finished Mar 21 01:27:08 PM PDT 24
Peak memory 210484 kb
Host smart-59d20638-5033-43cd-8748-68dd4adf7b6a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751178369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.1751178369
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.380893297
Short name T654
Test name
Test status
Simulation time 7881601286 ps
CPU time 247.42 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:30:11 PM PDT 24
Peak memory 203236 kb
Host smart-f6eb3773-83d4-48a8-ae8e-5b3702bea891
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380893297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl
_mem_walk.380893297
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.4147405685
Short name T733
Test name
Test status
Simulation time 7940525940 ps
CPU time 801.11 seconds
Started Mar 21 01:26:03 PM PDT 24
Finished Mar 21 01:39:24 PM PDT 24
Peak memory 377204 kb
Host smart-19bf8c5b-fabd-45a4-accb-e81a11bbe757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147405685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.4147405685
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.1848722472
Short name T297
Test name
Test status
Simulation time 2447829010 ps
CPU time 8.59 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 01:26:09 PM PDT 24
Peak memory 213576 kb
Host smart-dd08971d-c17e-4eaa-9979-a44ae17d56fd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848722472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.1848722472
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2112007473
Short name T379
Test name
Test status
Simulation time 31959907723 ps
CPU time 429.81 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:33:18 PM PDT 24
Peak memory 202444 kb
Host smart-6869a78f-c280-482b-bd5a-515538e38716
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112007473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.2112007473
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.2795728766
Short name T885
Test name
Test status
Simulation time 357450579 ps
CPU time 3.33 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:26:13 PM PDT 24
Peak memory 202512 kb
Host smart-deeff384-82db-490a-9567-28f5f000b3c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795728766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.2795728766
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.3374978164
Short name T831
Test name
Test status
Simulation time 5202307777 ps
CPU time 173.07 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:28:54 PM PDT 24
Peak memory 374080 kb
Host smart-5baf09a3-83c3-4635-943c-5de6152a149e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374978164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3374978164
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.1768008916
Short name T647
Test name
Test status
Simulation time 3408090033 ps
CPU time 17.53 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:26:26 PM PDT 24
Peak memory 202380 kb
Host smart-892fcd46-ba68-4577-b78e-40c8f8e5b7eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768008916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1768008916
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.2528284528
Short name T256
Test name
Test status
Simulation time 942885263104 ps
CPU time 5761.69 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 03:02:23 PM PDT 24
Peak memory 382436 kb
Host smart-cc741bfb-c046-40b7-8806-4cc053ff800a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528284528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.2528284528
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2368827974
Short name T237
Test name
Test status
Simulation time 1726462984 ps
CPU time 23.31 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:26:33 PM PDT 24
Peak memory 210592 kb
Host smart-bd5ac62f-9ba3-439a-86d0-8eb5c34a62fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2368827974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.2368827974
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1391500593
Short name T505
Test name
Test status
Simulation time 13250334838 ps
CPU time 159.64 seconds
Started Mar 21 01:25:57 PM PDT 24
Finished Mar 21 01:28:37 PM PDT 24
Peak memory 202328 kb
Host smart-ac8d0b19-cdd6-4e51-ba56-f989d69b4d78
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391500593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1391500593
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3819449195
Short name T423
Test name
Test status
Simulation time 749760285 ps
CPU time 54.97 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:26:57 PM PDT 24
Peak memory 312648 kb
Host smart-022323e8-8e87-4c6d-8979-108180deb4f3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819449195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3819449195
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3585356945
Short name T15
Test name
Test status
Simulation time 15324387770 ps
CPU time 902.28 seconds
Started Mar 21 01:26:06 PM PDT 24
Finished Mar 21 01:41:09 PM PDT 24
Peak memory 366944 kb
Host smart-222064fa-bbe5-43bd-a764-e38a3e6efe35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585356945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.3585356945
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.4266823397
Short name T260
Test name
Test status
Simulation time 168110604 ps
CPU time 0.69 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:26:12 PM PDT 24
Peak memory 202128 kb
Host smart-46d0a5d7-a8a4-453b-9624-d9d63c97cade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266823397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.4266823397
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.2621534332
Short name T493
Test name
Test status
Simulation time 16567118748 ps
CPU time 1077.35 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 01:44:05 PM PDT 24
Peak memory 202680 kb
Host smart-d23520ca-74f2-4c79-aadf-033ebd482f7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621534332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.2621534332
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.3938196075
Short name T532
Test name
Test status
Simulation time 157135410759 ps
CPU time 1478.77 seconds
Started Mar 21 01:26:04 PM PDT 24
Finished Mar 21 01:50:43 PM PDT 24
Peak memory 378144 kb
Host smart-63d724b9-6657-4ab1-9025-7b83bc8f6fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938196075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.3938196075
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.3621629919
Short name T26
Test name
Test status
Simulation time 35679039662 ps
CPU time 58.14 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:27:06 PM PDT 24
Peak memory 202352 kb
Host smart-8f681383-90d6-45f4-97fa-0aa3ae7ece8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621629919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.3621629919
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.3252511750
Short name T542
Test name
Test status
Simulation time 706849021 ps
CPU time 5.29 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:26:15 PM PDT 24
Peak memory 202316 kb
Host smart-3fcbb629-5733-4df3-a669-60fd1cf23ac8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252511750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.3252511750
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1159706453
Short name T723
Test name
Test status
Simulation time 2370938053 ps
CPU time 78.67 seconds
Started Mar 21 01:26:16 PM PDT 24
Finished Mar 21 01:27:36 PM PDT 24
Peak memory 210596 kb
Host smart-c7765817-27f8-4f1a-af96-87079de5c0b1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159706453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.1159706453
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.1600868438
Short name T643
Test name
Test status
Simulation time 15186975218 ps
CPU time 131.7 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:28:20 PM PDT 24
Peak memory 202948 kb
Host smart-31e86eba-695c-4615-acc3-c528fe7510fe
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600868438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.1600868438
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.2402310040
Short name T417
Test name
Test status
Simulation time 30464890360 ps
CPU time 719.72 seconds
Started Mar 21 01:26:13 PM PDT 24
Finished Mar 21 01:38:13 PM PDT 24
Peak memory 371156 kb
Host smart-6d4487d9-f2bf-4a40-bc3b-1d3aec0e9af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402310040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.2402310040
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.4177099743
Short name T263
Test name
Test status
Simulation time 946588759 ps
CPU time 111.88 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:27:54 PM PDT 24
Peak memory 352648 kb
Host smart-3423c6bf-f0cc-4b47-b9df-bdfffc0aa8b0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177099743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.4177099743
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2047285929
Short name T709
Test name
Test status
Simulation time 49032436449 ps
CPU time 357.5 seconds
Started Mar 21 01:26:13 PM PDT 24
Finished Mar 21 01:32:11 PM PDT 24
Peak memory 202384 kb
Host smart-2f237352-ad43-4f4d-8a68-2583d4610cd3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047285929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.2047285929
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.92020157
Short name T356
Test name
Test status
Simulation time 362051818 ps
CPU time 3.16 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 01:26:19 PM PDT 24
Peak memory 202388 kb
Host smart-448bda32-f3ca-4311-b670-434c419c4e5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92020157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.92020157
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.3301194972
Short name T319
Test name
Test status
Simulation time 54310586887 ps
CPU time 828.18 seconds
Started Mar 21 01:26:14 PM PDT 24
Finished Mar 21 01:40:02 PM PDT 24
Peak memory 374224 kb
Host smart-b140e5cb-9e58-494a-a671-47af965ea020
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301194972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3301194972
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.2291005498
Short name T304
Test name
Test status
Simulation time 4834119450 ps
CPU time 17.79 seconds
Started Mar 21 01:26:13 PM PDT 24
Finished Mar 21 01:26:31 PM PDT 24
Peak memory 202448 kb
Host smart-1d41dba3-f6c8-487d-9124-f8dc1f0ca564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291005498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2291005498
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.1785487721
Short name T41
Test name
Test status
Simulation time 130295455486 ps
CPU time 3062.26 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 02:17:10 PM PDT 24
Peak memory 380260 kb
Host smart-27259ba5-c2dd-4ebc-a889-0f8e769b0ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785487721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.sram_ctrl_stress_all.1785487721
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.179919173
Short name T939
Test name
Test status
Simulation time 1304962792 ps
CPU time 34.67 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 01:26:42 PM PDT 24
Peak memory 210552 kb
Host smart-ced6f2d1-5138-449c-baec-89b8aa4b8427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=179919173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.179919173
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3059485790
Short name T394
Test name
Test status
Simulation time 13006935802 ps
CPU time 182.27 seconds
Started Mar 21 01:26:07 PM PDT 24
Finished Mar 21 01:29:09 PM PDT 24
Peak memory 202328 kb
Host smart-ac63e4ca-aff6-4520-acaf-d833c6606279
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059485790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.3059485790
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2621162638
Short name T191
Test name
Test status
Simulation time 2869053140 ps
CPU time 53.22 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:27:05 PM PDT 24
Peak memory 309804 kb
Host smart-e5564457-5dc4-4de6-9417-d8fb0aaba688
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621162638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2621162638
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1475532805
Short name T687
Test name
Test status
Simulation time 49107883631 ps
CPU time 953.13 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:42:13 PM PDT 24
Peak memory 356584 kb
Host smart-9af08201-a4d9-4171-8b8b-623297407137
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475532805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.1475532805
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.3550141481
Short name T306
Test name
Test status
Simulation time 47401636 ps
CPU time 0.65 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:26:13 PM PDT 24
Peak memory 202040 kb
Host smart-5329ad1f-254d-42ed-9cba-5513f0b292b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550141481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.3550141481
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.2688456624
Short name T214
Test name
Test status
Simulation time 12475274974 ps
CPU time 420.11 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 01:33:17 PM PDT 24
Peak memory 366968 kb
Host smart-d6ccbadd-641d-4d21-9061-09ad345942bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688456624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab
le.2688456624
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.2208645274
Short name T184
Test name
Test status
Simulation time 4837604927 ps
CPU time 30.39 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:26:39 PM PDT 24
Peak memory 202336 kb
Host smart-9b68dc2a-d4f9-4f51-bcfa-31e38e1e42f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208645274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.2208645274
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.1700593638
Short name T361
Test name
Test status
Simulation time 738008522 ps
CPU time 27.4 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 01:26:44 PM PDT 24
Peak memory 267652 kb
Host smart-48bac3b4-0a6c-4d56-b242-4c49b447ece9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700593638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.1700593638
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.552223238
Short name T387
Test name
Test status
Simulation time 27160975598 ps
CPU time 157.39 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:28:48 PM PDT 24
Peak memory 210500 kb
Host smart-4f7df129-2aae-4220-952b-768ccc210f1f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552223238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_mem_partial_access.552223238
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.4157277222
Short name T376
Test name
Test status
Simulation time 4107438955 ps
CPU time 242.87 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:30:15 PM PDT 24
Peak memory 202576 kb
Host smart-d432bbf3-0976-4a70-924a-e8dbf048f7b3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157277222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.4157277222
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.1757982044
Short name T739
Test name
Test status
Simulation time 11568561927 ps
CPU time 149.52 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:28:42 PM PDT 24
Peak memory 371212 kb
Host smart-073beec2-d56f-445f-97c4-863be7a7b898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757982044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.1757982044
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.1852701410
Short name T127
Test name
Test status
Simulation time 1373129107 ps
CPU time 17.47 seconds
Started Mar 21 01:26:19 PM PDT 24
Finished Mar 21 01:26:37 PM PDT 24
Peak memory 202272 kb
Host smart-935732e9-d698-4a4d-a00a-690bb72f25f1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852701410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.1852701410
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.4273102007
Short name T629
Test name
Test status
Simulation time 21921156888 ps
CPU time 378.58 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:32:30 PM PDT 24
Peak memory 202400 kb
Host smart-f8c708c0-a8c8-426d-848b-623795a5db26
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273102007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.4273102007
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.2130638223
Short name T290
Test name
Test status
Simulation time 375220529 ps
CPU time 2.95 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:14 PM PDT 24
Peak memory 202544 kb
Host smart-00ba1a67-7b72-41c1-9e00-4e17ee3c3ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130638223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2130638223
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.2206696740
Short name T439
Test name
Test status
Simulation time 31682581745 ps
CPU time 1188.42 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:46:09 PM PDT 24
Peak memory 380308 kb
Host smart-0cfd5a9d-c967-48c4-9ca5-bdf6c23e10c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206696740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2206696740
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.1379286279
Short name T610
Test name
Test status
Simulation time 733955333 ps
CPU time 11.33 seconds
Started Mar 21 01:26:17 PM PDT 24
Finished Mar 21 01:26:29 PM PDT 24
Peak memory 202392 kb
Host smart-6b955f8b-e65a-4015-bcb3-27ad4e39e343
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379286279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1379286279
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.3909278696
Short name T768
Test name
Test status
Simulation time 110241195773 ps
CPU time 1774.9 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:55:45 PM PDT 24
Peak memory 380780 kb
Host smart-10a0d503-373a-4bb2-b894-b63249fbbb17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909278696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.3909278696
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1689373778
Short name T931
Test name
Test status
Simulation time 1416008357 ps
CPU time 21.17 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:26:40 PM PDT 24
Peak memory 211660 kb
Host smart-ea9da533-e394-452c-895e-ac5445358a29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1689373778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1689373778
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.308393696
Short name T862
Test name
Test status
Simulation time 6371368172 ps
CPU time 213.97 seconds
Started Mar 21 01:26:16 PM PDT 24
Finished Mar 21 01:29:51 PM PDT 24
Peak memory 202428 kb
Host smart-3eba0b90-d08e-405a-a7f8-5257adab26e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308393696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_stress_pipeline.308393696
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3357703329
Short name T362
Test name
Test status
Simulation time 3578856924 ps
CPU time 112.17 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:28:02 PM PDT 24
Peak memory 370260 kb
Host smart-e522037c-a351-4f2b-9cd1-ad64b1f86a09
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357703329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3357703329
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1132527545
Short name T716
Test name
Test status
Simulation time 27688489180 ps
CPU time 893.9 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 01:41:11 PM PDT 24
Peak memory 369076 kb
Host smart-db9e7a20-93a3-4642-b3f4-c1bdea8e6059
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132527545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.1132527545
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.928947103
Short name T662
Test name
Test status
Simulation time 16825554 ps
CPU time 0.62 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:26:11 PM PDT 24
Peak memory 202072 kb
Host smart-87e978ec-5dc1-42d7-881f-0f492498196e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928947103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.928947103
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.1321221821
Short name T301
Test name
Test status
Simulation time 63661628730 ps
CPU time 927.09 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:41:39 PM PDT 24
Peak memory 202356 kb
Host smart-f994ec6a-0d04-4967-9ff3-7607b3e4f433
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321221821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.1321221821
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.3749037072
Short name T915
Test name
Test status
Simulation time 8537213730 ps
CPU time 1374.04 seconds
Started Mar 21 01:26:17 PM PDT 24
Finished Mar 21 01:49:12 PM PDT 24
Peak memory 378288 kb
Host smart-7566c67a-d829-4bc1-a9b3-cbc6ab1887b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749037072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.3749037072
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.889914772
Short name T878
Test name
Test status
Simulation time 13583203049 ps
CPU time 74.26 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:27:24 PM PDT 24
Peak memory 202412 kb
Host smart-b8d72648-3b92-4cbb-9f53-aaec02c0a1b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889914772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_esc
alation.889914772
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.3386699528
Short name T867
Test name
Test status
Simulation time 3093448432 ps
CPU time 42.13 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:52 PM PDT 24
Peak memory 302636 kb
Host smart-da7f9f45-c76b-44ec-af4d-dea18db4c94a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386699528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.3386699528
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3672946273
Short name T470
Test name
Test status
Simulation time 17354922739 ps
CPU time 152.04 seconds
Started Mar 21 01:26:13 PM PDT 24
Finished Mar 21 01:28:46 PM PDT 24
Peak memory 210624 kb
Host smart-a7b470cf-f2f3-4b6e-9e11-53e19d375d2a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672946273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.3672946273
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.2736822403
Short name T203
Test name
Test status
Simulation time 41351481354 ps
CPU time 328.29 seconds
Started Mar 21 01:26:26 PM PDT 24
Finished Mar 21 01:31:54 PM PDT 24
Peak memory 203116 kb
Host smart-92f8caf9-d629-48ad-9976-30547d4e75e2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736822403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.2736822403
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.3696762685
Short name T663
Test name
Test status
Simulation time 6311567930 ps
CPU time 713.95 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:38:03 PM PDT 24
Peak memory 370888 kb
Host smart-c7c6aa4c-7f16-4a1e-890a-bbbc48a7787d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696762685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.3696762685
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.2243500815
Short name T142
Test name
Test status
Simulation time 831528015 ps
CPU time 112.94 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:28:11 PM PDT 24
Peak memory 352460 kb
Host smart-ef8973e6-e2b1-412b-b774-7c115d39e1de
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243500815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.2243500815
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2909240391
Short name T123
Test name
Test status
Simulation time 361894208693 ps
CPU time 619.57 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:36:40 PM PDT 24
Peak memory 202416 kb
Host smart-bbf65d3f-94d4-4b77-a570-1520645e8710
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909240391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.2909240391
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2172892477
Short name T413
Test name
Test status
Simulation time 356023490 ps
CPU time 3.17 seconds
Started Mar 21 01:26:17 PM PDT 24
Finished Mar 21 01:26:21 PM PDT 24
Peak memory 202500 kb
Host smart-d920d1fd-3079-4ba8-a192-e46a8aba3292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172892477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2172892477
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.529684679
Short name T801
Test name
Test status
Simulation time 32831932134 ps
CPU time 1262.91 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:47:21 PM PDT 24
Peak memory 377780 kb
Host smart-d0c1ba28-a7fb-4d87-999f-5a049094864c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529684679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.529684679
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.403065340
Short name T534
Test name
Test status
Simulation time 1641248453 ps
CPU time 11.5 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:26:30 PM PDT 24
Peak memory 227892 kb
Host smart-b02b159c-47db-4a61-8b67-785d83dedfb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403065340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.403065340
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.207605540
Short name T357
Test name
Test status
Simulation time 170453986156 ps
CPU time 3743.05 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 02:28:35 PM PDT 24
Peak memory 381388 kb
Host smart-6cd12e90-bd05-44c7-afe4-6ff8b2c84a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207605540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_stress_all.207605540
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2239299803
Short name T45
Test name
Test status
Simulation time 931936680 ps
CPU time 25.81 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:37 PM PDT 24
Peak memory 210752 kb
Host smart-61014918-a32d-49b3-95ea-8728211ad953
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2239299803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2239299803
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2710682907
Short name T758
Test name
Test status
Simulation time 3901234906 ps
CPU time 246.39 seconds
Started Mar 21 01:26:19 PM PDT 24
Finished Mar 21 01:30:26 PM PDT 24
Peak memory 202468 kb
Host smart-ca5479a4-0c59-44ad-b994-d72c2b88c501
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710682907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.2710682907
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2904814814
Short name T452
Test name
Test status
Simulation time 765218524 ps
CPU time 14.36 seconds
Started Mar 21 01:26:13 PM PDT 24
Finished Mar 21 01:26:28 PM PDT 24
Peak memory 250776 kb
Host smart-2e7ea00b-bb16-4679-bf9b-1a72011e08ac
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904814814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2904814814
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.4221868310
Short name T294
Test name
Test status
Simulation time 64182406866 ps
CPU time 1233.27 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:46:52 PM PDT 24
Peak memory 378140 kb
Host smart-63e22331-463a-4167-b695-d14b36995082
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221868310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.4221868310
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.1376675113
Short name T257
Test name
Test status
Simulation time 31890168 ps
CPU time 0.64 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:26:13 PM PDT 24
Peak memory 202116 kb
Host smart-12f876a1-fbb5-4273-8e53-c0a544effa6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376675113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.1376675113
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.3159937248
Short name T832
Test name
Test status
Simulation time 204420800229 ps
CPU time 597.5 seconds
Started Mar 21 01:26:14 PM PDT 24
Finished Mar 21 01:36:12 PM PDT 24
Peak memory 202376 kb
Host smart-bb470552-9ba1-4511-a9c6-720288002623
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159937248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.3159937248
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.640021303
Short name T312
Test name
Test status
Simulation time 12444416697 ps
CPU time 316.32 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:31:28 PM PDT 24
Peak memory 345304 kb
Host smart-66e9027d-5683-4a63-adf2-156633486a75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640021303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executabl
e.640021303
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.36529991
Short name T566
Test name
Test status
Simulation time 5743970961 ps
CPU time 37.97 seconds
Started Mar 21 01:26:25 PM PDT 24
Finished Mar 21 01:27:03 PM PDT 24
Peak memory 202468 kb
Host smart-67aa4fe6-687f-471a-8026-856c5fc97e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36529991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esca
lation.36529991
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.4101029577
Short name T754
Test name
Test status
Simulation time 1456008181 ps
CPU time 57.33 seconds
Started Mar 21 01:26:16 PM PDT 24
Finished Mar 21 01:27:14 PM PDT 24
Peak memory 300412 kb
Host smart-6a4be914-3c7c-4908-9d50-a51e525a3119
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101029577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.4101029577
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2988267063
Short name T825
Test name
Test status
Simulation time 4762410562 ps
CPU time 65.9 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:27:17 PM PDT 24
Peak memory 210496 kb
Host smart-2af87320-cb22-42ad-92d9-cd70d28c0414
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988267063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.2988267063
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.589748215
Short name T905
Test name
Test status
Simulation time 4107861134 ps
CPU time 234.95 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:30:08 PM PDT 24
Peak memory 202436 kb
Host smart-124cdc28-d8d4-46ac-9dc5-48b3b1e58ef2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589748215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_mem_walk.589748215
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.1364538167
Short name T844
Test name
Test status
Simulation time 48488739663 ps
CPU time 1683.73 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:54:24 PM PDT 24
Peak memory 376252 kb
Host smart-cc6826ba-b5e9-4eb9-be55-b60d5b4fa822
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364538167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.1364538167
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.1043859944
Short name T809
Test name
Test status
Simulation time 395589926 ps
CPU time 4.64 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:15 PM PDT 24
Peak memory 207000 kb
Host smart-8d816760-5e8c-43f6-8581-2351962211d9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043859944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.1043859944
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.698416471
Short name T523
Test name
Test status
Simulation time 28997880353 ps
CPU time 365.16 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:32:16 PM PDT 24
Peak memory 202320 kb
Host smart-a6be4e17-7e23-45c3-8117-66d32575d7c6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698416471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.sram_ctrl_partial_access_b2b.698416471
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.126468535
Short name T468
Test name
Test status
Simulation time 2799506713 ps
CPU time 3.5 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:26:16 PM PDT 24
Peak memory 202544 kb
Host smart-21d6a3fe-cf3d-4b8f-85ab-a7a3333e7ad9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126468535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.126468535
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.2190076560
Short name T375
Test name
Test status
Simulation time 2247339505 ps
CPU time 41.99 seconds
Started Mar 21 01:26:08 PM PDT 24
Finished Mar 21 01:26:50 PM PDT 24
Peak memory 284240 kb
Host smart-c825c68b-62c7-493a-aae8-02b05f6d20f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190076560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2190076560
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.172600632
Short name T139
Test name
Test status
Simulation time 1298325531 ps
CPU time 149.87 seconds
Started Mar 21 01:26:09 PM PDT 24
Finished Mar 21 01:28:39 PM PDT 24
Peak memory 367912 kb
Host smart-fd4888e1-8183-4d47-8b93-4c056c7c643d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172600632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.172600632
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.2912906570
Short name T494
Test name
Test status
Simulation time 371165289745 ps
CPU time 5370.85 seconds
Started Mar 21 01:26:23 PM PDT 24
Finished Mar 21 02:55:55 PM PDT 24
Peak memory 383416 kb
Host smart-4dcdebb8-aa64-4e32-b566-9f0f498cfb45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912906570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.2912906570
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.604882810
Short name T205
Test name
Test status
Simulation time 1929816030 ps
CPU time 64.87 seconds
Started Mar 21 01:26:16 PM PDT 24
Finished Mar 21 01:27:22 PM PDT 24
Peak memory 210612 kb
Host smart-ada22428-6b95-482e-81e5-81f27f75d134
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=604882810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.604882810
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3260249712
Short name T461
Test name
Test status
Simulation time 6993643217 ps
CPU time 224.8 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 01:30:02 PM PDT 24
Peak memory 202324 kb
Host smart-85d1754b-b8d4-48b9-9a0e-8fb91241a7db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260249712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.3260249712
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3328014910
Short name T436
Test name
Test status
Simulation time 7463732177 ps
CPU time 58.06 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:27:16 PM PDT 24
Peak memory 316888 kb
Host smart-b161f5a0-11a2-47fd-9ad5-0a70f1f3d9c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328014910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3328014910
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3517975236
Short name T134
Test name
Test status
Simulation time 12536953789 ps
CPU time 255.64 seconds
Started Mar 21 01:26:14 PM PDT 24
Finished Mar 21 01:30:31 PM PDT 24
Peak memory 375200 kb
Host smart-ac94eae6-3b52-4962-9e49-03539827f029
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517975236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.3517975236
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.793688969
Short name T880
Test name
Test status
Simulation time 13091051 ps
CPU time 0.65 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:26:21 PM PDT 24
Peak memory 202172 kb
Host smart-7d4bfea7-bbe7-453e-b6a0-efed83343432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793688969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.793688969
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.2052128064
Short name T479
Test name
Test status
Simulation time 66286423774 ps
CPU time 2098.58 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 02:01:17 PM PDT 24
Peak memory 202360 kb
Host smart-dad3877a-537c-4fca-8a5e-a05fd764cf7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052128064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.2052128064
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.61260271
Short name T810
Test name
Test status
Simulation time 72971421589 ps
CPU time 995.98 seconds
Started Mar 21 01:26:19 PM PDT 24
Finished Mar 21 01:42:55 PM PDT 24
Peak memory 370064 kb
Host smart-f0c2d27d-a95e-48c8-b891-b861be316daa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61260271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable
.61260271
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.137031177
Short name T883
Test name
Test status
Simulation time 60844413764 ps
CPU time 99.57 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:27:51 PM PDT 24
Peak memory 202472 kb
Host smart-ed031d42-1383-4f12-a203-73f470f811ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137031177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esc
alation.137031177
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.4242289213
Short name T731
Test name
Test status
Simulation time 731557396 ps
CPU time 25.88 seconds
Started Mar 21 01:26:21 PM PDT 24
Finished Mar 21 01:26:48 PM PDT 24
Peak memory 274208 kb
Host smart-5f4c6810-e7e2-49a7-a298-a725ebfb2993
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242289213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.4242289213
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.4237181281
Short name T746
Test name
Test status
Simulation time 3260021908 ps
CPU time 124.25 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 01:28:19 PM PDT 24
Peak memory 210528 kb
Host smart-fcb9c9fc-a74c-4375-9770-55ff5a54541e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237181281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.4237181281
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.1740010625
Short name T877
Test name
Test status
Simulation time 7175769118 ps
CPU time 146.86 seconds
Started Mar 21 01:26:19 PM PDT 24
Finished Mar 21 01:28:46 PM PDT 24
Peak memory 202764 kb
Host smart-a01a13c3-99e4-4dc6-bccb-c94dfa05b770
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740010625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.1740010625
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.1875680697
Short name T432
Test name
Test status
Simulation time 6944860291 ps
CPU time 366.45 seconds
Started Mar 21 01:26:16 PM PDT 24
Finished Mar 21 01:32:23 PM PDT 24
Peak memory 366956 kb
Host smart-195f28f3-0596-415c-af2a-e2c1c594c37d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875680697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.1875680697
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.1788502949
Short name T918
Test name
Test status
Simulation time 3349142418 ps
CPU time 90.76 seconds
Started Mar 21 01:26:16 PM PDT 24
Finished Mar 21 01:27:48 PM PDT 24
Peak memory 323304 kb
Host smart-f7fc626b-ae66-4ba7-a161-58ff14c82a5a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788502949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.1788502949
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3215963068
Short name T798
Test name
Test status
Simulation time 11210442767 ps
CPU time 346.86 seconds
Started Mar 21 01:26:17 PM PDT 24
Finished Mar 21 01:32:04 PM PDT 24
Peak memory 202428 kb
Host smart-5ae93f9b-bceb-429b-bb1c-ea4f772a611c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215963068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3215963068
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.3230499370
Short name T925
Test name
Test status
Simulation time 345476815 ps
CPU time 3.12 seconds
Started Mar 21 01:26:13 PM PDT 24
Finished Mar 21 01:26:16 PM PDT 24
Peak memory 202432 kb
Host smart-c92d68b1-40e6-4bce-8581-9fa2b7203f2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230499370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3230499370
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.3684382140
Short name T567
Test name
Test status
Simulation time 4855026362 ps
CPU time 657.62 seconds
Started Mar 21 01:26:25 PM PDT 24
Finished Mar 21 01:37:22 PM PDT 24
Peak memory 372116 kb
Host smart-0ee893f1-2d84-47b8-91d8-9f300d6388be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684382140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3684382140
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.1054826956
Short name T158
Test name
Test status
Simulation time 6040992669 ps
CPU time 13.62 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:25 PM PDT 24
Peak memory 202464 kb
Host smart-fa89b028-a313-4cf5-b1d2-4c35fba43250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054826956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1054826956
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.622471346
Short name T650
Test name
Test status
Simulation time 27474791497 ps
CPU time 2277.98 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 02:04:13 PM PDT 24
Peak memory 379372 kb
Host smart-65d2fd54-a078-4f60-8e26-bb839af91720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622471346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_stress_all.622471346
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4062087997
Short name T696
Test name
Test status
Simulation time 1172343647 ps
CPU time 20.45 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:26:39 PM PDT 24
Peak memory 210684 kb
Host smart-da2e9ce1-0033-4590-aeef-12c71c5adb8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4062087997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.4062087997
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2385931973
Short name T816
Test name
Test status
Simulation time 2712313904 ps
CPU time 199.3 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:29:31 PM PDT 24
Peak memory 202332 kb
Host smart-80d7c631-d256-48d5-86da-702843231974
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385931973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.2385931973
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1927213090
Short name T442
Test name
Test status
Simulation time 822950368 ps
CPU time 164.76 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:28:57 PM PDT 24
Peak memory 368924 kb
Host smart-f42dac48-64a6-4525-9b05-93477e4c0001
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927213090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1927213090
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.217197403
Short name T623
Test name
Test status
Simulation time 4398123321 ps
CPU time 125.1 seconds
Started Mar 21 01:26:21 PM PDT 24
Finished Mar 21 01:28:26 PM PDT 24
Peak memory 337144 kb
Host smart-72beade3-dea7-4ba5-afeb-6419aec3ecad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217197403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.sram_ctrl_access_during_key_req.217197403
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.4245324549
Short name T917
Test name
Test status
Simulation time 17543166 ps
CPU time 0.67 seconds
Started Mar 21 01:26:22 PM PDT 24
Finished Mar 21 01:26:23 PM PDT 24
Peak memory 202296 kb
Host smart-e05ae763-3923-4001-b1c1-7ee1639f9546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245324549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.4245324549
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.1647878648
Short name T215
Test name
Test status
Simulation time 166939595905 ps
CPU time 2625.79 seconds
Started Mar 21 01:26:17 PM PDT 24
Finished Mar 21 02:10:04 PM PDT 24
Peak memory 202620 kb
Host smart-adc83681-831c-426d-babd-a8c5c0621fc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647878648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.1647878648
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.2305893640
Short name T689
Test name
Test status
Simulation time 68796778387 ps
CPU time 171.96 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:29:11 PM PDT 24
Peak memory 294796 kb
Host smart-f4ff2ab2-d750-433d-a5cd-31a07a87f0c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305893640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.2305893640
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.2227134969
Short name T51
Test name
Test status
Simulation time 10881118111 ps
CPU time 34.05 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:26:47 PM PDT 24
Peak memory 202364 kb
Host smart-508202df-5e97-4d1f-ac82-7e9edd82c614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227134969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.2227134969
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.1353498031
Short name T425
Test name
Test status
Simulation time 753742894 ps
CPU time 80.61 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:27:39 PM PDT 24
Peak memory 318836 kb
Host smart-3196f75e-ebce-4e99-af14-e906b03b4a76
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353498031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.1353498031
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1154596764
Short name T929
Test name
Test status
Simulation time 19734756737 ps
CPU time 152.02 seconds
Started Mar 21 01:26:11 PM PDT 24
Finished Mar 21 01:28:44 PM PDT 24
Peak memory 210556 kb
Host smart-8e50ac8b-723a-40e8-a62e-8856d25608e9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154596764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.1154596764
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.4247421453
Short name T236
Test name
Test status
Simulation time 7128059811 ps
CPU time 144.51 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:28:43 PM PDT 24
Peak memory 202744 kb
Host smart-9b33d4c0-72e2-4f0a-a566-9e7658c15a7c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247421453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.4247421453
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.3156836037
Short name T140
Test name
Test status
Simulation time 14067700599 ps
CPU time 1103.11 seconds
Started Mar 21 01:26:19 PM PDT 24
Finished Mar 21 01:44:42 PM PDT 24
Peak memory 379256 kb
Host smart-949c0794-0a06-4066-863d-bcb8bb206749
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156836037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.3156836037
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.3426630889
Short name T478
Test name
Test status
Simulation time 5166520020 ps
CPU time 143.8 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 01:28:41 PM PDT 24
Peak memory 365932 kb
Host smart-20e0fc14-faba-426b-809e-0af12a5350d2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426630889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.3426630889
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1143171128
Short name T703
Test name
Test status
Simulation time 59139658029 ps
CPU time 315.04 seconds
Started Mar 21 01:26:14 PM PDT 24
Finished Mar 21 01:31:29 PM PDT 24
Peak memory 202392 kb
Host smart-8860f927-18fb-468b-b375-611323ae6697
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143171128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.1143171128
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.1112913171
Short name T744
Test name
Test status
Simulation time 364697938 ps
CPU time 3.05 seconds
Started Mar 21 01:26:14 PM PDT 24
Finished Mar 21 01:26:17 PM PDT 24
Peak memory 202484 kb
Host smart-a7cf56ae-35af-4d20-aabb-b6f0ff0266b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112913171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1112913171
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.942287375
Short name T773
Test name
Test status
Simulation time 14294272502 ps
CPU time 1178.35 seconds
Started Mar 21 01:26:25 PM PDT 24
Finished Mar 21 01:46:03 PM PDT 24
Peak memory 375156 kb
Host smart-d45794dd-a089-4231-89b3-9aa71ff0bca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942287375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.942287375
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.4045578714
Short name T507
Test name
Test status
Simulation time 728787761 ps
CPU time 7.99 seconds
Started Mar 21 01:26:24 PM PDT 24
Finished Mar 21 01:26:33 PM PDT 24
Peak memory 202304 kb
Host smart-230c2329-d020-43f4-bea2-712134ef014c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045578714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.4045578714
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.3219868081
Short name T122
Test name
Test status
Simulation time 1260046170901 ps
CPU time 3142.92 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 02:18:40 PM PDT 24
Peak memory 379316 kb
Host smart-4f98d42b-816f-47df-a3b9-1cdae262886c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219868081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.3219868081
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.164944250
Short name T911
Test name
Test status
Simulation time 5614787075 ps
CPU time 38.61 seconds
Started Mar 21 01:26:10 PM PDT 24
Finished Mar 21 01:26:49 PM PDT 24
Peak memory 212132 kb
Host smart-cf6daa01-27ac-497c-b4aa-fc6084544363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=164944250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.164944250
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3676605101
Short name T685
Test name
Test status
Simulation time 12278769471 ps
CPU time 308.13 seconds
Started Mar 21 01:26:27 PM PDT 24
Finished Mar 21 01:31:35 PM PDT 24
Peak memory 202328 kb
Host smart-efc2eb28-2fcf-4735-8704-477da503639e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676605101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.3676605101
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2517645787
Short name T524
Test name
Test status
Simulation time 1106114742 ps
CPU time 110.63 seconds
Started Mar 21 01:26:13 PM PDT 24
Finished Mar 21 01:28:04 PM PDT 24
Peak memory 357788 kb
Host smart-a2b7d277-87b9-45ca-a862-370ce95bd833
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517645787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2517645787
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3479791202
Short name T64
Test name
Test status
Simulation time 33994592654 ps
CPU time 850.89 seconds
Started Mar 21 01:26:16 PM PDT 24
Finished Mar 21 01:40:28 PM PDT 24
Peak memory 362792 kb
Host smart-5e47b9b2-8d3e-4c32-8ab0-09bb4220725d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479791202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.3479791202
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.1910636615
Short name T462
Test name
Test status
Simulation time 41737449 ps
CPU time 0.64 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:26:21 PM PDT 24
Peak memory 202112 kb
Host smart-e5d2636a-716d-4a4c-8c35-b38429e44828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910636615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.1910636615
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.55910621
Short name T296
Test name
Test status
Simulation time 113116518799 ps
CPU time 1268.76 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:47:29 PM PDT 24
Peak memory 202764 kb
Host smart-5a1f78a7-df8d-4add-9834-ebfa5e89aad2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55910621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.55910621
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.341039465
Short name T901
Test name
Test status
Simulation time 11565192136 ps
CPU time 1457.05 seconds
Started Mar 21 01:26:21 PM PDT 24
Finished Mar 21 01:50:39 PM PDT 24
Peak memory 375272 kb
Host smart-f20dc486-2cce-464d-861b-00ac42661093
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341039465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executabl
e.341039465
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.1109636340
Short name T617
Test name
Test status
Simulation time 18403576753 ps
CPU time 45.21 seconds
Started Mar 21 01:26:31 PM PDT 24
Finished Mar 21 01:27:16 PM PDT 24
Peak memory 202400 kb
Host smart-953e30de-85aa-4899-afa6-565c3e8a08b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109636340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.1109636340
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.449244452
Short name T480
Test name
Test status
Simulation time 6967075597 ps
CPU time 18.16 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:26:31 PM PDT 24
Peak memory 251404 kb
Host smart-cad7f8a2-6b9f-489f-b523-d3fb165ea115
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449244452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.sram_ctrl_max_throughput.449244452
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2812072902
Short name T179
Test name
Test status
Simulation time 5129043238 ps
CPU time 79.64 seconds
Started Mar 21 01:26:29 PM PDT 24
Finished Mar 21 01:27:49 PM PDT 24
Peak memory 210584 kb
Host smart-ec367008-3c2f-4a55-82c8-cad6e73bf088
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812072902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.2812072902
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.3942779444
Short name T269
Test name
Test status
Simulation time 4109484049 ps
CPU time 244.44 seconds
Started Mar 21 01:26:21 PM PDT 24
Finished Mar 21 01:30:26 PM PDT 24
Peak memory 202488 kb
Host smart-bc1d74d9-2f79-428c-a1cc-2bcaac2941c9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942779444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.3942779444
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.2290801641
Short name T720
Test name
Test status
Simulation time 15004218025 ps
CPU time 702.62 seconds
Started Mar 21 01:26:21 PM PDT 24
Finished Mar 21 01:38:04 PM PDT 24
Peak memory 374140 kb
Host smart-10cd4397-9f98-468b-8388-26326bbc1be1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290801641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.2290801641
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.1709684401
Short name T359
Test name
Test status
Simulation time 2089318900 ps
CPU time 7.03 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:26:28 PM PDT 24
Peak memory 202308 kb
Host smart-05b02eed-2e34-4264-a228-9a4ca84aa43b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709684401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.1709684401
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3850463586
Short name T726
Test name
Test status
Simulation time 23888269378 ps
CPU time 279.68 seconds
Started Mar 21 01:26:18 PM PDT 24
Finished Mar 21 01:30:58 PM PDT 24
Peak memory 202408 kb
Host smart-32f695d7-d72b-4d60-a19d-9ee07fe3a1e0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850463586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.3850463586
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.4036248385
Short name T750
Test name
Test status
Simulation time 347043227 ps
CPU time 3.14 seconds
Started Mar 21 01:26:22 PM PDT 24
Finished Mar 21 01:26:26 PM PDT 24
Peak memory 202404 kb
Host smart-babc2832-c5d6-410b-8bf9-f292668862bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036248385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.4036248385
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.439502065
Short name T386
Test name
Test status
Simulation time 10591883695 ps
CPU time 980.51 seconds
Started Mar 21 01:26:27 PM PDT 24
Finished Mar 21 01:42:47 PM PDT 24
Peak memory 373668 kb
Host smart-f15cfa04-61ac-4fe6-a128-4a70facd5572
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439502065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.439502065
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.1917578232
Short name T298
Test name
Test status
Simulation time 1757724958 ps
CPU time 15.91 seconds
Started Mar 21 01:26:12 PM PDT 24
Finished Mar 21 01:26:29 PM PDT 24
Peak memory 202356 kb
Host smart-6616cc2e-3000-4441-8716-c54b4a04e0cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917578232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1917578232
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.3705669943
Short name T219
Test name
Test status
Simulation time 74713312170 ps
CPU time 3097.79 seconds
Started Mar 21 01:26:19 PM PDT 24
Finished Mar 21 02:17:57 PM PDT 24
Peak memory 379252 kb
Host smart-474848f1-35e6-4be6-ad70-de642f6db208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705669943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.3705669943
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.951379765
Short name T638
Test name
Test status
Simulation time 306060959 ps
CPU time 6.69 seconds
Started Mar 21 01:26:24 PM PDT 24
Finished Mar 21 01:26:31 PM PDT 24
Peak memory 210480 kb
Host smart-2592aed1-03de-4146-b6c6-5066af592477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=951379765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.951379765
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.4112151737
Short name T283
Test name
Test status
Simulation time 3162033365 ps
CPU time 154.85 seconds
Started Mar 21 01:26:19 PM PDT 24
Finished Mar 21 01:28:54 PM PDT 24
Peak memory 202368 kb
Host smart-5754ca0e-6b71-4147-be3f-601161ce7dbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112151737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.4112151737
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3547095996
Short name T618
Test name
Test status
Simulation time 733207797 ps
CPU time 20.77 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:26:41 PM PDT 24
Peak memory 270784 kb
Host smart-b176a565-ae0d-4522-83fa-66750d932688
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547095996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3547095996
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3318760384
Short name T265
Test name
Test status
Simulation time 18047823819 ps
CPU time 1199.62 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:46:21 PM PDT 24
Peak memory 378240 kb
Host smart-8ec898a1-0e61-4c64-8be2-6a279a50bc84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318760384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.3318760384
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.1520571984
Short name T18
Test name
Test status
Simulation time 31497331 ps
CPU time 0.64 seconds
Started Mar 21 01:26:31 PM PDT 24
Finished Mar 21 01:26:32 PM PDT 24
Peak memory 202040 kb
Host smart-443d234e-cc21-4b78-8d96-a2e28f0511d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520571984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.1520571984
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.3928235292
Short name T565
Test name
Test status
Simulation time 34502418858 ps
CPU time 2286.16 seconds
Started Mar 21 01:26:26 PM PDT 24
Finished Mar 21 02:04:32 PM PDT 24
Peak memory 202432 kb
Host smart-37ec0faa-9f5c-4980-bdf3-c87ef467c28d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928235292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.3928235292
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.4001719622
Short name T601
Test name
Test status
Simulation time 6951258636 ps
CPU time 13.2 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:26:34 PM PDT 24
Peak memory 233712 kb
Host smart-9887b295-094d-4653-9383-d2bae1e38d4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001719622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.4001719622
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.1020645435
Short name T192
Test name
Test status
Simulation time 6467955263 ps
CPU time 35.45 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:26:55 PM PDT 24
Peak memory 202416 kb
Host smart-6d6ca553-a418-4f82-a8f4-c42ad18dde23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020645435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.1020645435
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.2864471552
Short name T500
Test name
Test status
Simulation time 5829521813 ps
CPU time 138.6 seconds
Started Mar 21 01:26:24 PM PDT 24
Finished Mar 21 01:28:43 PM PDT 24
Peak memory 360796 kb
Host smart-6c620638-aaf8-429a-8d84-5c3e831c761e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864471552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.2864471552
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2158462825
Short name T204
Test name
Test status
Simulation time 2899233689 ps
CPU time 78.47 seconds
Started Mar 21 01:26:25 PM PDT 24
Finished Mar 21 01:27:44 PM PDT 24
Peak memory 210580 kb
Host smart-b41059c8-9645-4804-b33b-47f9b4d19ae2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158462825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.2158462825
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.2532521345
Short name T497
Test name
Test status
Simulation time 18643471012 ps
CPU time 306.28 seconds
Started Mar 21 01:26:22 PM PDT 24
Finished Mar 21 01:31:28 PM PDT 24
Peak memory 202928 kb
Host smart-3ef39484-66ef-4988-a10e-6d6d4b317ca3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532521345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.2532521345
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.2838936369
Short name T769
Test name
Test status
Simulation time 39948979423 ps
CPU time 1238.98 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:47:00 PM PDT 24
Peak memory 377208 kb
Host smart-9fa03c54-1897-4ba0-9f5b-6a70a3c912f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838936369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.2838936369
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.1254843133
Short name T807
Test name
Test status
Simulation time 1237652263 ps
CPU time 21.63 seconds
Started Mar 21 01:26:19 PM PDT 24
Finished Mar 21 01:26:42 PM PDT 24
Peak memory 202332 kb
Host smart-cfefe42f-ebc6-453c-a6cd-c553912e8ca2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254843133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.1254843133
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.610840635
Short name T220
Test name
Test status
Simulation time 15497076902 ps
CPU time 176.91 seconds
Started Mar 21 01:26:15 PM PDT 24
Finished Mar 21 01:29:13 PM PDT 24
Peak memory 202372 kb
Host smart-579c0b58-f818-449c-a063-75edd9929f50
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610840635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.sram_ctrl_partial_access_b2b.610840635
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.3940508793
Short name T728
Test name
Test status
Simulation time 360568668 ps
CPU time 3.07 seconds
Started Mar 21 01:26:23 PM PDT 24
Finished Mar 21 01:26:27 PM PDT 24
Peak memory 202416 kb
Host smart-b3eff34c-2179-49ae-bb85-a89f58fc5156
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940508793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3940508793
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.1207192954
Short name T669
Test name
Test status
Simulation time 19177133897 ps
CPU time 364.36 seconds
Started Mar 21 01:26:16 PM PDT 24
Finished Mar 21 01:32:21 PM PDT 24
Peak memory 370032 kb
Host smart-c93836c0-37c2-4ddb-980b-46e7b0535ad5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207192954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1207192954
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.3978104002
Short name T684
Test name
Test status
Simulation time 2756219523 ps
CPU time 90.31 seconds
Started Mar 21 01:26:23 PM PDT 24
Finished Mar 21 01:27:54 PM PDT 24
Peak memory 360872 kb
Host smart-af9c1528-627a-4c34-84bf-8ead9557717f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978104002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3978104002
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.947172973
Short name T227
Test name
Test status
Simulation time 248920037935 ps
CPU time 1291.87 seconds
Started Mar 21 01:26:28 PM PDT 24
Finished Mar 21 01:48:00 PM PDT 24
Peak memory 378172 kb
Host smart-cf192750-800b-43eb-ab25-a7b91add12b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947172973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_stress_all.947172973
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3998654623
Short name T48
Test name
Test status
Simulation time 1197509355 ps
CPU time 28.01 seconds
Started Mar 21 01:26:31 PM PDT 24
Finished Mar 21 01:26:59 PM PDT 24
Peak memory 210564 kb
Host smart-cf7e468a-c1fd-4c16-8b58-7458ebfcafd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3998654623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.3998654623
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2731592614
Short name T729
Test name
Test status
Simulation time 3741211566 ps
CPU time 245.52 seconds
Started Mar 21 01:26:17 PM PDT 24
Finished Mar 21 01:30:23 PM PDT 24
Peak memory 202428 kb
Host smart-a0ce001e-21cb-4de0-b811-6ca39502c592
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731592614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.2731592614
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1774259061
Short name T817
Test name
Test status
Simulation time 2700725386 ps
CPU time 8.57 seconds
Started Mar 21 01:26:20 PM PDT 24
Finished Mar 21 01:26:29 PM PDT 24
Peak memory 218784 kb
Host smart-bd4d5241-8151-4398-9b0e-6d5ec73a2a1d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774259061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1774259061
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3051749747
Short name T36
Test name
Test status
Simulation time 29137500464 ps
CPU time 431.91 seconds
Started Mar 21 01:26:29 PM PDT 24
Finished Mar 21 01:33:41 PM PDT 24
Peak memory 370076 kb
Host smart-894fb5f7-aab6-463c-851d-ccf0896eef08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051749747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.3051749747
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.791852734
Short name T486
Test name
Test status
Simulation time 44914173 ps
CPU time 0.67 seconds
Started Mar 21 01:26:41 PM PDT 24
Finished Mar 21 01:26:42 PM PDT 24
Peak memory 202136 kb
Host smart-7849666f-7b47-49aa-9b68-335c30b067e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791852734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.791852734
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.3300918241
Short name T165
Test name
Test status
Simulation time 413973681235 ps
CPU time 2369.93 seconds
Started Mar 21 01:26:22 PM PDT 24
Finished Mar 21 02:05:53 PM PDT 24
Peak memory 202576 kb
Host smart-36d3fd09-4347-471c-9dd4-748ee50d1a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300918241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.3300918241
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.2668545840
Short name T528
Test name
Test status
Simulation time 86870735059 ps
CPU time 1044.86 seconds
Started Mar 21 01:26:37 PM PDT 24
Finished Mar 21 01:44:02 PM PDT 24
Peak memory 371124 kb
Host smart-bbfbfc25-e04b-4767-9212-537c540ee5c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668545840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.2668545840
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.76009047
Short name T477
Test name
Test status
Simulation time 25186426765 ps
CPU time 39.88 seconds
Started Mar 21 01:26:30 PM PDT 24
Finished Mar 21 01:27:11 PM PDT 24
Peak memory 210588 kb
Host smart-b4148e6a-e4d0-4cb6-8562-8f239d3f9440
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76009047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esca
lation.76009047
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.589146753
Short name T391
Test name
Test status
Simulation time 762820010 ps
CPU time 52.32 seconds
Started Mar 21 01:26:29 PM PDT 24
Finished Mar 21 01:27:22 PM PDT 24
Peak memory 300524 kb
Host smart-67e2975b-648a-4764-b229-7c3e1ae3baf0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589146753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.sram_ctrl_max_throughput.589146753
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.662772644
Short name T495
Test name
Test status
Simulation time 26110534070 ps
CPU time 79.86 seconds
Started Mar 21 01:26:35 PM PDT 24
Finished Mar 21 01:27:55 PM PDT 24
Peak memory 210560 kb
Host smart-60722839-bd37-4a28-a2d3-49254bafeed5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662772644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_mem_partial_access.662772644
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.2570398481
Short name T845
Test name
Test status
Simulation time 18647914041 ps
CPU time 151.06 seconds
Started Mar 21 01:26:35 PM PDT 24
Finished Mar 21 01:29:07 PM PDT 24
Peak memory 202752 kb
Host smart-be805254-b216-4897-9163-298658cd3875
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570398481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.2570398481
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.1158224134
Short name T137
Test name
Test status
Simulation time 56378433600 ps
CPU time 701.03 seconds
Started Mar 21 01:26:23 PM PDT 24
Finished Mar 21 01:38:05 PM PDT 24
Peak memory 378940 kb
Host smart-018505ca-2890-4343-8175-71c67ac775bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158224134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.1158224134
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.3344428760
Short name T499
Test name
Test status
Simulation time 1455642686 ps
CPU time 5.08 seconds
Started Mar 21 01:26:26 PM PDT 24
Finished Mar 21 01:26:31 PM PDT 24
Peak memory 208012 kb
Host smart-d46ea64e-1a16-4a14-ac16-4f6547a118e8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344428760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.3344428760
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2373027584
Short name T763
Test name
Test status
Simulation time 20278880693 ps
CPU time 509.46 seconds
Started Mar 21 01:26:30 PM PDT 24
Finished Mar 21 01:35:00 PM PDT 24
Peak memory 201800 kb
Host smart-e0a7a8f7-affb-4fd5-b04a-3b6e96f45644
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373027584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.2373027584
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.1536326855
Short name T637
Test name
Test status
Simulation time 1349699171 ps
CPU time 3.32 seconds
Started Mar 21 01:26:30 PM PDT 24
Finished Mar 21 01:26:33 PM PDT 24
Peak memory 202420 kb
Host smart-7e539157-1f39-4628-ac30-9ccacaa78aa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536326855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1536326855
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.321622061
Short name T349
Test name
Test status
Simulation time 3819693365 ps
CPU time 1149.06 seconds
Started Mar 21 01:26:29 PM PDT 24
Finished Mar 21 01:45:39 PM PDT 24
Peak memory 376556 kb
Host smart-47714b7d-c3d0-4688-bad8-55913a18015d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321622061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.321622061
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.2138341071
Short name T448
Test name
Test status
Simulation time 2832662315 ps
CPU time 6.69 seconds
Started Mar 21 01:26:27 PM PDT 24
Finished Mar 21 01:26:34 PM PDT 24
Peak memory 202412 kb
Host smart-d3372c89-d3ba-45fc-9580-89346806536d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138341071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2138341071
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.2567651714
Short name T420
Test name
Test status
Simulation time 255993137309 ps
CPU time 1446.9 seconds
Started Mar 21 01:26:30 PM PDT 24
Finished Mar 21 01:50:38 PM PDT 24
Peak memory 211288 kb
Host smart-57639c5f-14a5-4c6a-9726-53c281280114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567651714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.2567651714
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3396630631
Short name T587
Test name
Test status
Simulation time 864360532 ps
CPU time 25.25 seconds
Started Mar 21 01:26:32 PM PDT 24
Finished Mar 21 01:26:57 PM PDT 24
Peak memory 210612 kb
Host smart-fde6bf6a-2435-4507-98b8-4da2ba5f8e3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3396630631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3396630631
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.513123
Short name T90
Test name
Test status
Simulation time 16784954330 ps
CPU time 307.41 seconds
Started Mar 21 01:26:22 PM PDT 24
Finished Mar 21 01:31:30 PM PDT 24
Peak memory 202388 kb
Host smart-86df02a3-271d-4540-ac56-9a4b94ac8710
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sra
m_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sr
am_ctrl_stress_pipeline.513123
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1132988561
Short name T431
Test name
Test status
Simulation time 4041573507 ps
CPU time 99.07 seconds
Started Mar 21 01:26:32 PM PDT 24
Finished Mar 21 01:28:11 PM PDT 24
Peak memory 350544 kb
Host smart-45a19846-9a70-40f2-a54c-890cbd94bc4f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132988561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1132988561
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.2499900890
Short name T704
Test name
Test status
Simulation time 29286140084 ps
CPU time 860.52 seconds
Started Mar 21 01:25:22 PM PDT 24
Finished Mar 21 01:39:43 PM PDT 24
Peak memory 377516 kb
Host smart-3dcd3a4f-0867-49d7-b26a-17667ab6afe7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499900890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.2499900890
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.1728821837
Short name T343
Test name
Test status
Simulation time 13553174 ps
CPU time 0.65 seconds
Started Mar 21 01:25:22 PM PDT 24
Finished Mar 21 01:25:23 PM PDT 24
Peak memory 202032 kb
Host smart-68e47e71-acb0-4748-985b-8084b5e83851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728821837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.1728821837
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.1968843488
Short name T889
Test name
Test status
Simulation time 121591038440 ps
CPU time 2017.57 seconds
Started Mar 21 01:25:28 PM PDT 24
Finished Mar 21 01:59:06 PM PDT 24
Peak memory 202572 kb
Host smart-c21d1868-08f0-4b25-ab06-ecad45d92a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968843488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
1968843488
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.2274195699
Short name T458
Test name
Test status
Simulation time 63602635378 ps
CPU time 1152.41 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:44:46 PM PDT 24
Peak memory 378340 kb
Host smart-4ccbd6ec-2e36-464a-85bb-5f65b141024c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274195699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.2274195699
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.3010798987
Short name T806
Test name
Test status
Simulation time 13041549426 ps
CPU time 35.37 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:26:10 PM PDT 24
Peak memory 202452 kb
Host smart-3bb67071-b3fc-4212-8859-0e24b53c727a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010798987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.3010798987
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.3764022697
Short name T711
Test name
Test status
Simulation time 1035457372 ps
CPU time 120.66 seconds
Started Mar 21 01:25:22 PM PDT 24
Finished Mar 21 01:27:23 PM PDT 24
Peak memory 357592 kb
Host smart-41a60ccb-dfe6-49e2-9eb9-f77c92efb175
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764022697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.3764022697
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1706351047
Short name T273
Test name
Test status
Simulation time 15686527278 ps
CPU time 64.86 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:26:39 PM PDT 24
Peak memory 210640 kb
Host smart-a67e60f2-b4cb-4212-b9da-139e01a42795
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706351047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.1706351047
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.2007991322
Short name T209
Test name
Test status
Simulation time 86051422170 ps
CPU time 317.99 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:30:41 PM PDT 24
Peak memory 203204 kb
Host smart-6d4e8fb9-e39d-4118-9a6c-b4bb6174b7e0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007991322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.2007991322
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.2902431845
Short name T515
Test name
Test status
Simulation time 17215112869 ps
CPU time 981.79 seconds
Started Mar 21 01:25:30 PM PDT 24
Finished Mar 21 01:41:52 PM PDT 24
Peak memory 375536 kb
Host smart-1fc666e5-f053-4293-88fb-111b72838e4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902431845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.2902431845
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.3414842342
Short name T83
Test name
Test status
Simulation time 550474265 ps
CPU time 14.82 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:25:36 PM PDT 24
Peak memory 202260 kb
Host smart-947994d6-2874-4058-a61a-b1d88f64e482
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414842342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.3414842342
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3568008590
Short name T460
Test name
Test status
Simulation time 21703839449 ps
CPU time 457.3 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:33:03 PM PDT 24
Peak memory 202300 kb
Host smart-c88ae346-3734-4c93-8c98-28a8c49124bb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568008590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.3568008590
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.506474636
Short name T615
Test name
Test status
Simulation time 351674950 ps
CPU time 3.26 seconds
Started Mar 21 01:25:30 PM PDT 24
Finished Mar 21 01:25:34 PM PDT 24
Peak memory 202512 kb
Host smart-7b380b91-7872-4798-9114-7bc325e90d18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506474636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.506474636
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1176354112
Short name T657
Test name
Test status
Simulation time 19027723842 ps
CPU time 1286.25 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:46:52 PM PDT 24
Peak memory 379480 kb
Host smart-a801eec3-451a-4609-8d75-05d137b847b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176354112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1176354112
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.4016050035
Short name T32
Test name
Test status
Simulation time 121077434 ps
CPU time 1.74 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 01:25:37 PM PDT 24
Peak memory 221584 kb
Host smart-6c18b576-b370-4cb3-ac01-e5b26e25545f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016050035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.4016050035
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.1285095647
Short name T213
Test name
Test status
Simulation time 10921925665 ps
CPU time 20.83 seconds
Started Mar 21 01:25:19 PM PDT 24
Finished Mar 21 01:25:40 PM PDT 24
Peak memory 202380 kb
Host smart-49787037-3261-4d7c-b58c-c2e1f978b889
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285095647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1285095647
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.1870746885
Short name T498
Test name
Test status
Simulation time 24389290807 ps
CPU time 2445.83 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 02:06:19 PM PDT 24
Peak memory 381396 kb
Host smart-7fcabd0d-40cc-47ed-8809-5473e50fc428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870746885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.1870746885
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.188284874
Short name T527
Test name
Test status
Simulation time 1338827675 ps
CPU time 59.72 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:26:21 PM PDT 24
Peak memory 210640 kb
Host smart-c862d406-c378-4086-a475-59b3589c0d88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=188284874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.188284874
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.201915803
Short name T614
Test name
Test status
Simulation time 11442121908 ps
CPU time 171.43 seconds
Started Mar 21 01:25:18 PM PDT 24
Finished Mar 21 01:28:10 PM PDT 24
Peak memory 202288 kb
Host smart-d50214a2-8d71-47cc-8665-85548a28d0c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201915803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
sram_ctrl_stress_pipeline.201915803
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4027396785
Short name T826
Test name
Test status
Simulation time 2815411131 ps
CPU time 85.79 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:26:51 PM PDT 24
Peak memory 335964 kb
Host smart-4d3dd95a-5b4d-4f87-ab0c-6768dc05d194
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027396785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.4027396785
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1000720913
Short name T311
Test name
Test status
Simulation time 12493546262 ps
CPU time 1150.18 seconds
Started Mar 21 01:26:31 PM PDT 24
Finished Mar 21 01:45:42 PM PDT 24
Peak memory 379288 kb
Host smart-ba0ed47d-ead0-4dae-b35a-3568a02fba50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000720913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.1000720913
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.227073291
Short name T762
Test name
Test status
Simulation time 35062664 ps
CPU time 0.65 seconds
Started Mar 21 01:26:48 PM PDT 24
Finished Mar 21 01:26:49 PM PDT 24
Peak memory 201840 kb
Host smart-aca3be31-c142-4c32-b3ee-119b07c0ab19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227073291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.227073291
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.2815304331
Short name T793
Test name
Test status
Simulation time 103514457003 ps
CPU time 1669.55 seconds
Started Mar 21 01:26:33 PM PDT 24
Finished Mar 21 01:54:23 PM PDT 24
Peak memory 202416 kb
Host smart-e47260f7-379b-415c-afda-04c8afaee3d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815304331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.2815304331
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.90740446
Short name T10
Test name
Test status
Simulation time 4738557253 ps
CPU time 906.78 seconds
Started Mar 21 01:26:43 PM PDT 24
Finished Mar 21 01:41:50 PM PDT 24
Peak memory 372232 kb
Host smart-6dc27857-fc09-41ef-9391-83c4b7f7efbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90740446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable
.90740446
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.2592461286
Short name T811
Test name
Test status
Simulation time 9667639137 ps
CPU time 55.22 seconds
Started Mar 21 01:26:31 PM PDT 24
Finished Mar 21 01:27:26 PM PDT 24
Peak memory 202356 kb
Host smart-f24026d0-a9b7-41c1-98a5-15de443e7789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592461286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.2592461286
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.859019347
Short name T395
Test name
Test status
Simulation time 767005012 ps
CPU time 52.11 seconds
Started Mar 21 01:26:32 PM PDT 24
Finished Mar 21 01:27:25 PM PDT 24
Peak memory 302584 kb
Host smart-08d8077b-a650-42c3-bbd6-0bbe9214ba79
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859019347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.sram_ctrl_max_throughput.859019347
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2626531891
Short name T69
Test name
Test status
Simulation time 9769642917 ps
CPU time 135.28 seconds
Started Mar 21 01:26:47 PM PDT 24
Finished Mar 21 01:29:02 PM PDT 24
Peak memory 210624 kb
Host smart-c151687e-1ca5-499a-9ae3-740438796653
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626531891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.2626531891
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.3758366413
Short name T255
Test name
Test status
Simulation time 8046875582 ps
CPU time 229.37 seconds
Started Mar 21 01:26:35 PM PDT 24
Finished Mar 21 01:30:24 PM PDT 24
Peak memory 202344 kb
Host smart-6eb79471-1194-4138-9838-8c80b127888d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758366413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.3758366413
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.73691094
Short name T128
Test name
Test status
Simulation time 39071615881 ps
CPU time 1564.09 seconds
Started Mar 21 01:26:38 PM PDT 24
Finished Mar 21 01:52:42 PM PDT 24
Peak memory 379368 kb
Host smart-1dc9f968-4fa9-4b1f-b614-95e38d47273a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73691094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multipl
e_keys.73691094
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.4289486060
Short name T863
Test name
Test status
Simulation time 2065411660 ps
CPU time 7.29 seconds
Started Mar 21 01:26:30 PM PDT 24
Finished Mar 21 01:26:38 PM PDT 24
Peak memory 202408 kb
Host smart-8b6c4510-829b-4b80-b662-e65e044124b2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289486060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.4289486060
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2660809127
Short name T91
Test name
Test status
Simulation time 20220384716 ps
CPU time 225.29 seconds
Started Mar 21 01:26:31 PM PDT 24
Finished Mar 21 01:30:17 PM PDT 24
Peak memory 202340 kb
Host smart-bd234855-145b-4839-91da-d33016613c00
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660809127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.2660809127
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.1377672952
Short name T310
Test name
Test status
Simulation time 372878215 ps
CPU time 3.25 seconds
Started Mar 21 01:26:33 PM PDT 24
Finished Mar 21 01:26:36 PM PDT 24
Peak memory 202468 kb
Host smart-07f38473-7e9b-498d-bb10-5da4729d7e6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377672952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1377672952
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.500942816
Short name T536
Test name
Test status
Simulation time 21611116666 ps
CPU time 654.86 seconds
Started Mar 21 01:26:31 PM PDT 24
Finished Mar 21 01:37:26 PM PDT 24
Peak memory 377276 kb
Host smart-81aaac2f-1e13-4d4e-b550-24b776762115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500942816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.500942816
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.255971441
Short name T564
Test name
Test status
Simulation time 10203680873 ps
CPU time 70.84 seconds
Started Mar 21 01:26:35 PM PDT 24
Finished Mar 21 01:27:46 PM PDT 24
Peak memory 317860 kb
Host smart-532b3229-f5e9-431c-8387-6b8b9f953901
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255971441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.255971441
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.1377977441
Short name T727
Test name
Test status
Simulation time 121548992178 ps
CPU time 6854.32 seconds
Started Mar 21 01:26:47 PM PDT 24
Finished Mar 21 03:21:02 PM PDT 24
Peak memory 381364 kb
Host smart-c5db2ab6-67e4-462b-af55-b6919ff21f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377977441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.sram_ctrl_stress_all.1377977441
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2492159814
Short name T890
Test name
Test status
Simulation time 1336616761 ps
CPU time 13.05 seconds
Started Mar 21 01:26:48 PM PDT 24
Finished Mar 21 01:27:01 PM PDT 24
Peak memory 211820 kb
Host smart-7d7b37de-1eef-4fca-a9d4-c2e2eeb9831d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2492159814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2492159814
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2501987110
Short name T742
Test name
Test status
Simulation time 6376522296 ps
CPU time 184.33 seconds
Started Mar 21 01:26:34 PM PDT 24
Finished Mar 21 01:29:38 PM PDT 24
Peak memory 202416 kb
Host smart-48201d36-2852-4fe3-a728-387a83ff7722
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501987110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.2501987110
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2259354445
Short name T789
Test name
Test status
Simulation time 1558708978 ps
CPU time 152.74 seconds
Started Mar 21 01:26:31 PM PDT 24
Finished Mar 21 01:29:05 PM PDT 24
Peak memory 364880 kb
Host smart-ace46341-d32c-4b85-8590-f8775261246c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259354445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.2259354445
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3203429073
Short name T627
Test name
Test status
Simulation time 14148060456 ps
CPU time 1612.76 seconds
Started Mar 21 01:26:48 PM PDT 24
Finished Mar 21 01:53:41 PM PDT 24
Peak memory 376208 kb
Host smart-ff7ee7d1-e493-4102-a579-680bc07b6e86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203429073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.3203429073
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.2312650275
Short name T286
Test name
Test status
Simulation time 42399228 ps
CPU time 0.66 seconds
Started Mar 21 01:26:50 PM PDT 24
Finished Mar 21 01:26:51 PM PDT 24
Peak memory 202144 kb
Host smart-1bc782b2-cfe7-4143-a07f-48ed73a8f67c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312650275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.2312650275
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.1743566563
Short name T145
Test name
Test status
Simulation time 33134907028 ps
CPU time 2225.33 seconds
Started Mar 21 01:26:49 PM PDT 24
Finished Mar 21 02:03:54 PM PDT 24
Peak memory 202432 kb
Host smart-87a031d5-5172-43c6-bd36-0e6bfc184869
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743566563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.1743566563
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.3746020614
Short name T751
Test name
Test status
Simulation time 11825116914 ps
CPU time 480.84 seconds
Started Mar 21 01:26:49 PM PDT 24
Finished Mar 21 01:34:50 PM PDT 24
Peak memory 375236 kb
Host smart-32506348-ccda-4417-a8eb-e9283c09b73a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746020614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.3746020614
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.3511101712
Short name T833
Test name
Test status
Simulation time 125204440568 ps
CPU time 104.9 seconds
Started Mar 21 01:26:48 PM PDT 24
Finished Mar 21 01:28:33 PM PDT 24
Peak memory 210696 kb
Host smart-26415968-1ec8-495a-adc5-4830d95d5ccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511101712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.3511101712
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.1789309708
Short name T35
Test name
Test status
Simulation time 817838424 ps
CPU time 101.78 seconds
Started Mar 21 01:26:48 PM PDT 24
Finished Mar 21 01:28:30 PM PDT 24
Peak memory 344420 kb
Host smart-ac7a8f97-66d7-4698-b443-173d98ac63f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789309708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.1789309708
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3056049174
Short name T757
Test name
Test status
Simulation time 5225147232 ps
CPU time 74.3 seconds
Started Mar 21 01:26:48 PM PDT 24
Finished Mar 21 01:28:03 PM PDT 24
Peak memory 210560 kb
Host smart-787f0d88-18d1-4981-8ebf-6a232a978e39
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056049174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.3056049174
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.2515222823
Short name T846
Test name
Test status
Simulation time 13781073993 ps
CPU time 287.48 seconds
Started Mar 21 01:26:49 PM PDT 24
Finished Mar 21 01:31:37 PM PDT 24
Peak memory 202436 kb
Host smart-2484e7e1-d11d-47d1-befb-7781dd68f49e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515222823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.2515222823
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.1468516646
Short name T648
Test name
Test status
Simulation time 12494995144 ps
CPU time 148.04 seconds
Started Mar 21 01:26:48 PM PDT 24
Finished Mar 21 01:29:16 PM PDT 24
Peak memory 376224 kb
Host smart-fdfececa-949c-413c-89de-9dc348edd03e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468516646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.1468516646
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.685865202
Short name T325
Test name
Test status
Simulation time 6535574483 ps
CPU time 27.15 seconds
Started Mar 21 01:26:47 PM PDT 24
Finished Mar 21 01:27:14 PM PDT 24
Peak memory 202476 kb
Host smart-01d5fceb-8f3b-4769-b6d9-50bf076f762a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685865202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.s
ram_ctrl_partial_access.685865202
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.974393927
Short name T253
Test name
Test status
Simulation time 191215159685 ps
CPU time 295.99 seconds
Started Mar 21 01:26:47 PM PDT 24
Finished Mar 21 01:31:43 PM PDT 24
Peak memory 202328 kb
Host smart-e801d937-2dc4-4a69-ad41-4d06556b57fc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974393927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.sram_ctrl_partial_access_b2b.974393927
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.2734109983
Short name T129
Test name
Test status
Simulation time 1401534503 ps
CPU time 3.47 seconds
Started Mar 21 01:26:48 PM PDT 24
Finished Mar 21 01:26:52 PM PDT 24
Peak memory 202404 kb
Host smart-93bc4a35-78b0-45ab-bbfc-8bba222a1be7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734109983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2734109983
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.2726387972
Short name T166
Test name
Test status
Simulation time 9586398028 ps
CPU time 306.28 seconds
Started Mar 21 01:26:47 PM PDT 24
Finished Mar 21 01:31:54 PM PDT 24
Peak memory 334244 kb
Host smart-44dff977-7317-49d2-893d-33a5dc2363c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726387972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2726387972
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.3469813782
Short name T242
Test name
Test status
Simulation time 646626643 ps
CPU time 3.95 seconds
Started Mar 21 01:26:49 PM PDT 24
Finished Mar 21 01:26:53 PM PDT 24
Peak memory 202468 kb
Host smart-ed15b4f8-9c0d-4c46-8fdf-e2d02e91e371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469813782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3469813782
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.3721934825
Short name T549
Test name
Test status
Simulation time 216599541505 ps
CPU time 3339.82 seconds
Started Mar 21 01:26:51 PM PDT 24
Finished Mar 21 02:22:31 PM PDT 24
Peak memory 379268 kb
Host smart-c4011568-5749-47d7-8fac-79dbaff89343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721934825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.3721934825
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.490532518
Short name T102
Test name
Test status
Simulation time 1327362933 ps
CPU time 89.06 seconds
Started Mar 21 01:26:47 PM PDT 24
Finished Mar 21 01:28:16 PM PDT 24
Peak memory 318012 kb
Host smart-af3a8e19-efd6-46ca-a845-cd31be769929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=490532518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.490532518
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3154656153
Short name T884
Test name
Test status
Simulation time 6912864566 ps
CPU time 151.19 seconds
Started Mar 21 01:26:47 PM PDT 24
Finished Mar 21 01:29:18 PM PDT 24
Peak memory 202332 kb
Host smart-00e3cf7d-0028-4593-975e-a088e531b5a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154656153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.3154656153
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.604422539
Short name T851
Test name
Test status
Simulation time 1626901544 ps
CPU time 147.57 seconds
Started Mar 21 01:26:58 PM PDT 24
Finished Mar 21 01:29:26 PM PDT 24
Peak memory 363724 kb
Host smart-2c690be8-706e-4d66-83f0-79c988fdc634
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604422539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.604422539
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.657958985
Short name T870
Test name
Test status
Simulation time 49078410505 ps
CPU time 1202.17 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:46:59 PM PDT 24
Peak memory 376248 kb
Host smart-5d2580ec-ec0f-49f1-8ad3-80532bd1941b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657958985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 32.sram_ctrl_access_during_key_req.657958985
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.225397189
Short name T155
Test name
Test status
Simulation time 54138366 ps
CPU time 0.68 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:26:58 PM PDT 24
Peak memory 202072 kb
Host smart-db3aac59-348c-4a7d-9029-49b868099205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225397189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.225397189
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.4277835994
Short name T765
Test name
Test status
Simulation time 49796588560 ps
CPU time 927.54 seconds
Started Mar 21 01:26:51 PM PDT 24
Finished Mar 21 01:42:18 PM PDT 24
Peak memory 202540 kb
Host smart-90190ffb-546e-4297-bdd0-87af2a4ee9c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277835994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.4277835994
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.1389535040
Short name T197
Test name
Test status
Simulation time 6748216894 ps
CPU time 822.42 seconds
Started Mar 21 01:26:50 PM PDT 24
Finished Mar 21 01:40:33 PM PDT 24
Peak memory 369164 kb
Host smart-ef9bd804-bdba-44fe-baf1-89a6aad82ae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389535040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.1389535040
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.308381895
Short name T5
Test name
Test status
Simulation time 13475786171 ps
CPU time 78.88 seconds
Started Mar 21 01:26:58 PM PDT 24
Finished Mar 21 01:28:17 PM PDT 24
Peak memory 210828 kb
Host smart-664f5de5-2248-43d4-9760-bc174498ba49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308381895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_esc
alation.308381895
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1514966891
Short name T767
Test name
Test status
Simulation time 2724609507 ps
CPU time 10.97 seconds
Started Mar 21 01:26:56 PM PDT 24
Finished Mar 21 01:27:07 PM PDT 24
Peak memory 227332 kb
Host smart-0a324b21-96a7-410d-bbc1-37372ebac434
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514966891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1514966891
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1153126656
Short name T211
Test name
Test status
Simulation time 3132557039 ps
CPU time 123.73 seconds
Started Mar 21 01:27:00 PM PDT 24
Finished Mar 21 01:29:04 PM PDT 24
Peak memory 210656 kb
Host smart-5cd71c01-7676-400a-9cd9-3fd9ed920cfc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153126656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.1153126656
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.1006089145
Short name T173
Test name
Test status
Simulation time 14352793674 ps
CPU time 279.93 seconds
Started Mar 21 01:26:51 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 202732 kb
Host smart-794c253f-07b7-498c-a60e-7aa691017ddf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006089145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.1006089145
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.2165858601
Short name T502
Test name
Test status
Simulation time 25232178609 ps
CPU time 752.59 seconds
Started Mar 21 01:26:50 PM PDT 24
Finished Mar 21 01:39:23 PM PDT 24
Peak memory 372832 kb
Host smart-808e28b1-8498-4aac-b080-c400f5e666fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165858601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.2165858601
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.2409434146
Short name T568
Test name
Test status
Simulation time 725006284 ps
CPU time 3.43 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:27:01 PM PDT 24
Peak memory 202400 kb
Host smart-37d377be-04e9-4785-add6-62bf0781956e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409434146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2409434146
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.2054317190
Short name T223
Test name
Test status
Simulation time 14460342959 ps
CPU time 1045 seconds
Started Mar 21 01:26:58 PM PDT 24
Finished Mar 21 01:44:23 PM PDT 24
Peak memory 379248 kb
Host smart-09bef5ee-a6a2-4217-858c-5caf52c49e3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054317190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2054317190
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.619811479
Short name T81
Test name
Test status
Simulation time 812040198 ps
CPU time 26.38 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:27:24 PM PDT 24
Peak memory 276956 kb
Host smart-6390201a-4f3a-4b3f-92ab-b52a4108239e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619811479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.619811479
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.755146328
Short name T118
Test name
Test status
Simulation time 214264194144 ps
CPU time 4742.08 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 02:46:00 PM PDT 24
Peak memory 381292 kb
Host smart-29f6c83e-7e84-4221-9728-d1bc4d2bbf28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755146328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_stress_all.755146328
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2358429010
Short name T307
Test name
Test status
Simulation time 1792181801 ps
CPU time 48.59 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:27:45 PM PDT 24
Peak memory 210676 kb
Host smart-9cbd99a8-66ab-4a77-8e64-d107f2cc29e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2358429010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.2358429010
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2729949464
Short name T266
Test name
Test status
Simulation time 6243738242 ps
CPU time 148.42 seconds
Started Mar 21 01:26:49 PM PDT 24
Finished Mar 21 01:29:17 PM PDT 24
Peak memory 202368 kb
Host smart-c1b03826-0578-43eb-9fcf-b3b6d0f20f1d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729949464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.2729949464
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2363851685
Short name T274
Test name
Test status
Simulation time 5164339492 ps
CPU time 37.28 seconds
Started Mar 21 01:26:48 PM PDT 24
Finished Mar 21 01:27:26 PM PDT 24
Peak memory 285140 kb
Host smart-d17822de-e821-4ed8-93b4-e7eb5c12b25a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363851685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2363851685
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2468040773
Short name T940
Test name
Test status
Simulation time 19028620178 ps
CPU time 1061.24 seconds
Started Mar 21 01:26:58 PM PDT 24
Finished Mar 21 01:44:39 PM PDT 24
Peak memory 375264 kb
Host smart-9abea967-4a5a-4f0d-add2-68ccaf1b08c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468040773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.2468040773
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.793770798
Short name T748
Test name
Test status
Simulation time 36380829 ps
CPU time 0.64 seconds
Started Mar 21 01:27:00 PM PDT 24
Finished Mar 21 01:27:01 PM PDT 24
Peak memory 202064 kb
Host smart-be3d71c5-ec21-438e-a4be-a1beb2e4d510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793770798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.793770798
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.3894643021
Short name T177
Test name
Test status
Simulation time 364632432818 ps
CPU time 2199.21 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 02:03:36 PM PDT 24
Peak memory 202824 kb
Host smart-28ca8385-f431-4df6-a6ef-923a666c9980
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894643021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.3894643021
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.203492071
Short name T34
Test name
Test status
Simulation time 12122520121 ps
CPU time 798.59 seconds
Started Mar 21 01:27:02 PM PDT 24
Finished Mar 21 01:40:20 PM PDT 24
Peak memory 375268 kb
Host smart-cb4fa371-51ed-474f-92e8-bd608e9c6013
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203492071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executabl
e.203492071
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.445434130
Short name T766
Test name
Test status
Simulation time 995111403 ps
CPU time 7.62 seconds
Started Mar 21 01:26:58 PM PDT 24
Finished Mar 21 01:27:06 PM PDT 24
Peak memory 202112 kb
Host smart-0b74ac67-8218-4657-a768-9f6c55f676ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445434130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esc
alation.445434130
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.3673340219
Short name T411
Test name
Test status
Simulation time 2701041733 ps
CPU time 7.53 seconds
Started Mar 21 01:26:58 PM PDT 24
Finished Mar 21 01:27:05 PM PDT 24
Peak memory 216036 kb
Host smart-7c71e0af-c985-4c21-8aeb-a7cd20f9394d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673340219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.3673340219
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.4171801294
Short name T869
Test name
Test status
Simulation time 17249480922 ps
CPU time 129.41 seconds
Started Mar 21 01:26:59 PM PDT 24
Finished Mar 21 01:29:09 PM PDT 24
Peak memory 210588 kb
Host smart-082a77f0-1770-4f5d-92bc-edd5493c7228
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171801294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.4171801294
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.3334214170
Short name T797
Test name
Test status
Simulation time 36812725847 ps
CPU time 156.76 seconds
Started Mar 21 01:26:59 PM PDT 24
Finished Mar 21 01:29:35 PM PDT 24
Peak memory 202984 kb
Host smart-045fb405-efec-4c17-a0c9-3b0658d3e526
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334214170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.3334214170
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.2782535037
Short name T582
Test name
Test status
Simulation time 10033245855 ps
CPU time 951.42 seconds
Started Mar 21 01:26:58 PM PDT 24
Finished Mar 21 01:42:50 PM PDT 24
Peak memory 374040 kb
Host smart-743db6db-f760-427a-b7d3-fba0bc383d57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782535037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.2782535037
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.1979594777
Short name T514
Test name
Test status
Simulation time 787035742 ps
CPU time 11.5 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:27:09 PM PDT 24
Peak memory 202288 kb
Host smart-12d82a6e-1430-45f6-86a1-ca2edf16551f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979594777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.1979594777
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1181904983
Short name T320
Test name
Test status
Simulation time 5293701499 ps
CPU time 297.91 seconds
Started Mar 21 01:27:01 PM PDT 24
Finished Mar 21 01:31:59 PM PDT 24
Peak memory 202456 kb
Host smart-d0eae3ce-96ce-4472-aafc-cde238042d73
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181904983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.1181904983
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.2697413997
Short name T842
Test name
Test status
Simulation time 3064682829 ps
CPU time 4.12 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:27:01 PM PDT 24
Peak memory 202484 kb
Host smart-d35ee558-e783-49e0-bbab-165872a0bc52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697413997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2697413997
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.303611780
Short name T697
Test name
Test status
Simulation time 6161342248 ps
CPU time 996.78 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:43:34 PM PDT 24
Peak memory 377240 kb
Host smart-4136945a-dba5-4793-a05a-3800f4b5f55d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303611780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.303611780
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.1449805289
Short name T551
Test name
Test status
Simulation time 551987546 ps
CPU time 19.34 seconds
Started Mar 21 01:26:56 PM PDT 24
Finished Mar 21 01:27:16 PM PDT 24
Peak memory 202296 kb
Host smart-e5ea7496-3d8e-473f-bf91-5720eb58d19f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449805289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1449805289
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.3394940851
Short name T485
Test name
Test status
Simulation time 499519127812 ps
CPU time 2548.57 seconds
Started Mar 21 01:27:00 PM PDT 24
Finished Mar 21 02:09:29 PM PDT 24
Peak memory 378232 kb
Host smart-ed403cac-2f6a-4a55-b8bc-e8c129a104f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394940851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.3394940851
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2026779688
Short name T29
Test name
Test status
Simulation time 9403348709 ps
CPU time 188.75 seconds
Started Mar 21 01:27:02 PM PDT 24
Finished Mar 21 01:30:10 PM PDT 24
Peak memory 368216 kb
Host smart-3358eb42-a779-42d4-a7ee-b0f6b362a35b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2026779688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2026779688
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2842409505
Short name T49
Test name
Test status
Simulation time 4573286373 ps
CPU time 222.16 seconds
Started Mar 21 01:27:00 PM PDT 24
Finished Mar 21 01:30:42 PM PDT 24
Peak memory 202364 kb
Host smart-fb369c44-7f0d-4fd9-95f4-a932d2bb9711
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842409505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.2842409505
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.462121209
Short name T760
Test name
Test status
Simulation time 1598362185 ps
CPU time 117.27 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:28:55 PM PDT 24
Peak memory 350492 kb
Host smart-51027547-416d-419f-9db7-bf4f9195571a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462121209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.462121209
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3992893848
Short name T70
Test name
Test status
Simulation time 16996656407 ps
CPU time 881.52 seconds
Started Mar 21 01:26:59 PM PDT 24
Finished Mar 21 01:41:41 PM PDT 24
Peak memory 379400 kb
Host smart-e4d92ce8-2bcb-49ab-877e-f1b125a2848f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992893848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.3992893848
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.656639530
Short name T933
Test name
Test status
Simulation time 12342564 ps
CPU time 0.67 seconds
Started Mar 21 01:27:25 PM PDT 24
Finished Mar 21 01:27:27 PM PDT 24
Peak memory 201904 kb
Host smart-ffc5ee20-33bf-48f7-9ee5-b4d27244ea94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656639530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.656639530
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.3462750763
Short name T475
Test name
Test status
Simulation time 14423928182 ps
CPU time 638.93 seconds
Started Mar 21 01:26:59 PM PDT 24
Finished Mar 21 01:37:38 PM PDT 24
Peak memory 202416 kb
Host smart-d030db1e-1b45-47f8-bb67-0cd8306e3aa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462750763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.3462750763
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.732449087
Short name T428
Test name
Test status
Simulation time 229701861802 ps
CPU time 1108.9 seconds
Started Mar 21 01:27:00 PM PDT 24
Finished Mar 21 01:45:29 PM PDT 24
Peak memory 374252 kb
Host smart-1c4998ee-2d42-49ac-b517-23b2be5d748c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732449087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executabl
e.732449087
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.147690939
Short name T936
Test name
Test status
Simulation time 14843288257 ps
CPU time 87.91 seconds
Started Mar 21 01:27:01 PM PDT 24
Finished Mar 21 01:28:29 PM PDT 24
Peak memory 202472 kb
Host smart-bead846b-4284-4a7d-9ed2-d107b26e9306
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147690939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc
alation.147690939
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.1282756389
Short name T252
Test name
Test status
Simulation time 3098864153 ps
CPU time 89.27 seconds
Started Mar 21 01:27:00 PM PDT 24
Finished Mar 21 01:28:30 PM PDT 24
Peak memory 334488 kb
Host smart-a6143a77-4f9f-47ec-8885-0fec41a05cd7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282756389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.1282756389
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3676548739
Short name T593
Test name
Test status
Simulation time 18146945336 ps
CPU time 159.2 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:30:06 PM PDT 24
Peak memory 210500 kb
Host smart-99991900-c596-4732-9799-6b03b7887956
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676548739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.3676548739
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.2494304874
Short name T531
Test name
Test status
Simulation time 16413664036 ps
CPU time 263.23 seconds
Started Mar 21 01:27:25 PM PDT 24
Finished Mar 21 01:31:49 PM PDT 24
Peak memory 202956 kb
Host smart-4c93fff9-e44a-4d1b-b789-d32e44840fda
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494304874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.2494304874
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.4053874230
Short name T353
Test name
Test status
Simulation time 72891724903 ps
CPU time 1682.11 seconds
Started Mar 21 01:27:01 PM PDT 24
Finished Mar 21 01:55:03 PM PDT 24
Peak memory 375240 kb
Host smart-f343de10-65eb-47e1-99d6-571365046955
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053874230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.4053874230
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.1679495001
Short name T691
Test name
Test status
Simulation time 1402998416 ps
CPU time 6.26 seconds
Started Mar 21 01:26:59 PM PDT 24
Finished Mar 21 01:27:05 PM PDT 24
Peak memory 202132 kb
Host smart-2f17c182-3bca-44c8-81a4-12ee4e84a55d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679495001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.1679495001
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2861181872
Short name T695
Test name
Test status
Simulation time 58737724911 ps
CPU time 384.25 seconds
Started Mar 21 01:27:00 PM PDT 24
Finished Mar 21 01:33:25 PM PDT 24
Peak memory 202472 kb
Host smart-0b897efc-1568-4aff-b1e3-299b4c6a0e2c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861181872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.2861181872
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.2444924789
Short name T922
Test name
Test status
Simulation time 1342310691 ps
CPU time 3.64 seconds
Started Mar 21 01:27:10 PM PDT 24
Finished Mar 21 01:27:13 PM PDT 24
Peak memory 202424 kb
Host smart-e01b33f9-5362-4339-a0b2-8864147b0ef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444924789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2444924789
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.3446869407
Short name T554
Test name
Test status
Simulation time 13340285685 ps
CPU time 1062.2 seconds
Started Mar 21 01:26:57 PM PDT 24
Finished Mar 21 01:44:40 PM PDT 24
Peak memory 380256 kb
Host smart-57b48f60-fd2a-48b7-a554-ae694e514a32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446869407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3446869407
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.1590441751
Short name T912
Test name
Test status
Simulation time 1971884803 ps
CPU time 7.38 seconds
Started Mar 21 01:27:01 PM PDT 24
Finished Mar 21 01:27:08 PM PDT 24
Peak memory 202328 kb
Host smart-887d9ee3-13b7-4bdc-b447-4ffa6871696f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590441751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1590441751
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.1968314638
Short name T584
Test name
Test status
Simulation time 143648073680 ps
CPU time 5232.69 seconds
Started Mar 21 01:27:25 PM PDT 24
Finished Mar 21 02:54:38 PM PDT 24
Peak memory 379448 kb
Host smart-9d494ef8-15e7-4b41-bf8f-567f91e51f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968314638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.1968314638
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1173974258
Short name T406
Test name
Test status
Simulation time 731898765 ps
CPU time 14.31 seconds
Started Mar 21 01:27:25 PM PDT 24
Finished Mar 21 01:27:40 PM PDT 24
Peak memory 210672 kb
Host smart-f0570d74-7c41-4c71-840f-669d19fac60a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1173974258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1173974258
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2562845420
Short name T642
Test name
Test status
Simulation time 10775314900 ps
CPU time 369.74 seconds
Started Mar 21 01:27:00 PM PDT 24
Finished Mar 21 01:33:10 PM PDT 24
Peak memory 202428 kb
Host smart-9470a60d-b5ae-451b-bd25-12c5c1add19f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562845420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.2562845420
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.485540216
Short name T152
Test name
Test status
Simulation time 729358440 ps
CPU time 32.27 seconds
Started Mar 21 01:26:59 PM PDT 24
Finished Mar 21 01:27:31 PM PDT 24
Peak memory 284256 kb
Host smart-334ea7e3-6018-4574-9cde-701714a414e5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485540216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_throughput_w_partial_write.485540216
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1059165127
Short name T694
Test name
Test status
Simulation time 15435629939 ps
CPU time 326.17 seconds
Started Mar 21 01:27:25 PM PDT 24
Finished Mar 21 01:32:53 PM PDT 24
Peak memory 359904 kb
Host smart-b8b10bbd-5a10-41b5-b579-35a3d9323a9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059165127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.1059165127
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.1342274613
Short name T250
Test name
Test status
Simulation time 160722137 ps
CPU time 0.68 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:27:28 PM PDT 24
Peak memory 202032 kb
Host smart-feba12d2-836c-413d-93b8-968eb3ac1b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342274613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.1342274613
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.210768514
Short name T675
Test name
Test status
Simulation time 503191645421 ps
CPU time 1007.58 seconds
Started Mar 21 01:27:25 PM PDT 24
Finished Mar 21 01:44:14 PM PDT 24
Peak memory 202728 kb
Host smart-6e7aedaf-01e3-430e-83ed-b9029b9cd6df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210768514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.
210768514
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.1622619230
Short name T838
Test name
Test status
Simulation time 32931992416 ps
CPU time 867.92 seconds
Started Mar 21 01:27:27 PM PDT 24
Finished Mar 21 01:41:56 PM PDT 24
Peak memory 377296 kb
Host smart-885337c0-8cd9-4391-8a76-20c3965c45a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622619230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.1622619230
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.2120923608
Short name T6
Test name
Test status
Simulation time 13554748959 ps
CPU time 38.82 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:28:07 PM PDT 24
Peak memory 202484 kb
Host smart-49589613-02d7-4c83-9865-550edb045a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120923608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.2120923608
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.1470127131
Short name T321
Test name
Test status
Simulation time 761403261 ps
CPU time 57.23 seconds
Started Mar 21 01:27:11 PM PDT 24
Finished Mar 21 01:28:09 PM PDT 24
Peak memory 300456 kb
Host smart-30b291ba-8995-4ceb-be1e-81d96c2a3413
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470127131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.1470127131
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2223608512
Short name T598
Test name
Test status
Simulation time 2560684744 ps
CPU time 77.19 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:28:44 PM PDT 24
Peak memory 210584 kb
Host smart-5a7675f0-c874-49a1-b4c7-9f69cd9239e4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223608512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.2223608512
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.2202175740
Short name T571
Test name
Test status
Simulation time 114985700708 ps
CPU time 300.68 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:32:27 PM PDT 24
Peak memory 203284 kb
Host smart-7db08cfc-e946-460f-b33e-9574778ea563
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202175740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.2202175740
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.1516619250
Short name T834
Test name
Test status
Simulation time 5061914571 ps
CPU time 61.35 seconds
Started Mar 21 01:27:24 PM PDT 24
Finished Mar 21 01:28:26 PM PDT 24
Peak memory 281100 kb
Host smart-6596dafb-07e0-4db1-963e-edf7c21a5222
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516619250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.1516619250
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.1005320844
Short name T149
Test name
Test status
Simulation time 882494705 ps
CPU time 17.68 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:27:45 PM PDT 24
Peak memory 202320 kb
Host smart-bcde3b0e-fa90-4454-abf5-9fc0bd2a25f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005320844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.1005320844
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.88012205
Short name T345
Test name
Test status
Simulation time 5168356268 ps
CPU time 261.39 seconds
Started Mar 21 01:27:25 PM PDT 24
Finished Mar 21 01:31:48 PM PDT 24
Peak memory 202308 kb
Host smart-8ee66258-5b18-498f-bcac-8cf31bf3bc0f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88012205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_partial_access_b2b.88012205
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.3837499653
Short name T879
Test name
Test status
Simulation time 370754596 ps
CPU time 3.03 seconds
Started Mar 21 01:27:25 PM PDT 24
Finished Mar 21 01:27:28 PM PDT 24
Peak memory 202476 kb
Host smart-01095e5c-c183-4b89-8dae-bc7c63944a06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837499653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3837499653
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.4160893254
Short name T141
Test name
Test status
Simulation time 4891259716 ps
CPU time 380.06 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:33:47 PM PDT 24
Peak memory 377276 kb
Host smart-e7b37da1-6da1-411f-974c-1829eb04e647
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160893254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.4160893254
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.3618499597
Short name T476
Test name
Test status
Simulation time 978366442 ps
CPU time 11.89 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:27:40 PM PDT 24
Peak memory 202308 kb
Host smart-2dae83fd-789d-4457-aa7e-704d74a03580
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618499597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3618499597
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.2622245552
Short name T221
Test name
Test status
Simulation time 645737866762 ps
CPU time 6389.91 seconds
Started Mar 21 01:27:27 PM PDT 24
Finished Mar 21 03:13:59 PM PDT 24
Peak memory 388736 kb
Host smart-775e1f96-e17f-4943-ba74-11e1ff62e63b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622245552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.2622245552
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1560739645
Short name T743
Test name
Test status
Simulation time 4122705079 ps
CPU time 255.38 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:31:43 PM PDT 24
Peak memory 202324 kb
Host smart-e703bfdb-0b27-4a51-8ec7-8c80777b2d1f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560739645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.1560739645
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1254534092
Short name T412
Test name
Test status
Simulation time 5159167176 ps
CPU time 134.71 seconds
Started Mar 21 01:27:25 PM PDT 24
Finished Mar 21 01:29:40 PM PDT 24
Peak memory 358812 kb
Host smart-b5404d94-c1f8-4a41-a87a-cad6aa171fbf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254534092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.1254534092
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3880915785
Short name T449
Test name
Test status
Simulation time 36238682863 ps
CPU time 2115.57 seconds
Started Mar 21 01:27:29 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 380312 kb
Host smart-cb8d8cff-c97f-4953-a67f-c43d56f3ca69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880915785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.3880915785
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.159160953
Short name T383
Test name
Test status
Simulation time 25792959 ps
CPU time 0.61 seconds
Started Mar 21 01:27:29 PM PDT 24
Finished Mar 21 01:27:30 PM PDT 24
Peak memory 202056 kb
Host smart-f0ff94a0-fdc4-40a7-9981-44c690d20c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159160953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.159160953
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.1739674585
Short name T125
Test name
Test status
Simulation time 207662666479 ps
CPU time 1396.09 seconds
Started Mar 21 01:27:27 PM PDT 24
Finished Mar 21 01:50:44 PM PDT 24
Peak memory 202720 kb
Host smart-fbac9a6a-f4ec-4eab-83da-bfbf4edb5bf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739674585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.1739674585
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.4174009155
Short name T147
Test name
Test status
Simulation time 40078013769 ps
CPU time 1454.42 seconds
Started Mar 21 01:27:27 PM PDT 24
Finished Mar 21 01:51:43 PM PDT 24
Peak memory 378156 kb
Host smart-e6b4ffac-eada-4728-ad36-3ff40532fe9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174009155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.4174009155
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.1681576062
Short name T632
Test name
Test status
Simulation time 5955028683 ps
CPU time 39.15 seconds
Started Mar 21 01:27:26 PM PDT 24
Finished Mar 21 01:28:07 PM PDT 24
Peak memory 210576 kb
Host smart-bab57544-7879-43e8-b40c-a5e420078737
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681576062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.1681576062
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.2986450545
Short name T171
Test name
Test status
Simulation time 4649836628 ps
CPU time 78.39 seconds
Started Mar 21 01:27:28 PM PDT 24
Finished Mar 21 01:28:47 PM PDT 24
Peak memory 338316 kb
Host smart-26517726-0d3b-4d0d-95ae-013030dbaefd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986450545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.2986450545
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3621504711
Short name T268
Test name
Test status
Simulation time 18241804502 ps
CPU time 149.28 seconds
Started Mar 21 01:27:32 PM PDT 24
Finished Mar 21 01:30:02 PM PDT 24
Peak memory 210632 kb
Host smart-62237b3c-df1d-4747-8d61-f7789a7fc7bc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621504711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.3621504711
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.1012656621
Short name T317
Test name
Test status
Simulation time 32885675825 ps
CPU time 125.89 seconds
Started Mar 21 01:27:31 PM PDT 24
Finished Mar 21 01:29:37 PM PDT 24
Peak memory 202388 kb
Host smart-d4357eab-63c1-44fa-925d-4cb7da61781e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012656621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.1012656621
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.3300809571
Short name T291
Test name
Test status
Simulation time 25520357728 ps
CPU time 784.63 seconds
Started Mar 21 01:27:27 PM PDT 24
Finished Mar 21 01:40:33 PM PDT 24
Peak memory 380288 kb
Host smart-5220ba25-d24e-460f-b24b-16831ca09eb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300809571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.3300809571
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.526073947
Short name T823
Test name
Test status
Simulation time 7905040255 ps
CPU time 16.72 seconds
Started Mar 21 01:27:29 PM PDT 24
Finished Mar 21 01:27:46 PM PDT 24
Peak memory 202448 kb
Host smart-b8c7a59b-b270-4558-a6a7-8ecd323fd2ce
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526073947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s
ram_ctrl_partial_access.526073947
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1609754762
Short name T935
Test name
Test status
Simulation time 4896452063 ps
CPU time 307.62 seconds
Started Mar 21 01:27:31 PM PDT 24
Finished Mar 21 01:32:39 PM PDT 24
Peak memory 202336 kb
Host smart-22cd12df-6687-46d2-9775-a2fe36e3de9b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609754762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.1609754762
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.3652350329
Short name T222
Test name
Test status
Simulation time 2106614865 ps
CPU time 3.4 seconds
Started Mar 21 01:27:28 PM PDT 24
Finished Mar 21 01:27:32 PM PDT 24
Peak memory 202540 kb
Host smart-21475411-7e3c-4575-9caf-7731d679a4d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652350329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3652350329
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.4248535186
Short name T199
Test name
Test status
Simulation time 5070426896 ps
CPU time 288.69 seconds
Started Mar 21 01:27:28 PM PDT 24
Finished Mar 21 01:32:17 PM PDT 24
Peak memory 372092 kb
Host smart-b79d5b70-9263-4fab-88ef-5a89c91424ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248535186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.4248535186
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.395749892
Short name T169
Test name
Test status
Simulation time 772966723 ps
CPU time 6.49 seconds
Started Mar 21 01:27:29 PM PDT 24
Finished Mar 21 01:27:35 PM PDT 24
Peak memory 202304 kb
Host smart-e04bf6d6-6da6-48c7-a4a8-5bb2f7aeb45a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395749892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.395749892
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.2075972324
Short name T868
Test name
Test status
Simulation time 173699534116 ps
CPU time 4471.33 seconds
Started Mar 21 01:27:29 PM PDT 24
Finished Mar 21 02:42:01 PM PDT 24
Peak memory 380244 kb
Host smart-d9ebf023-81cc-4a15-8a97-17736b732992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075972324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.2075972324
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.341411302
Short name T293
Test name
Test status
Simulation time 3223539825 ps
CPU time 17.08 seconds
Started Mar 21 01:27:27 PM PDT 24
Finished Mar 21 01:27:45 PM PDT 24
Peak memory 210648 kb
Host smart-ab6751d6-d312-44bb-b254-c3baa4736bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=341411302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.341411302
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.834596037
Short name T556
Test name
Test status
Simulation time 4307360397 ps
CPU time 238.78 seconds
Started Mar 21 01:27:27 PM PDT 24
Finished Mar 21 01:31:27 PM PDT 24
Peak memory 202332 kb
Host smart-e754861e-7e5b-4047-98d1-239214c7ef72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834596037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_stress_pipeline.834596037
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3083614746
Short name T130
Test name
Test status
Simulation time 2985975186 ps
CPU time 25.1 seconds
Started Mar 21 01:27:33 PM PDT 24
Finished Mar 21 01:27:58 PM PDT 24
Peak memory 273988 kb
Host smart-0ca12d35-2128-4197-af61-2d80cd1c37f7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083614746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.3083614746
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.369640192
Short name T315
Test name
Test status
Simulation time 19516718562 ps
CPU time 443.46 seconds
Started Mar 21 01:27:34 PM PDT 24
Finished Mar 21 01:34:58 PM PDT 24
Peak memory 377188 kb
Host smart-47004195-26c1-4b2c-ac46-8fe168bf6805
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369640192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.sram_ctrl_access_during_key_req.369640192
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.3218612515
Short name T747
Test name
Test status
Simulation time 46027515 ps
CPU time 0.68 seconds
Started Mar 21 01:27:31 PM PDT 24
Finished Mar 21 01:27:32 PM PDT 24
Peak memory 202144 kb
Host smart-9e4b4405-1659-4a21-91d4-1463bd905ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218612515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.3218612515
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.2090484278
Short name T686
Test name
Test status
Simulation time 344938279044 ps
CPU time 2882.46 seconds
Started Mar 21 01:27:28 PM PDT 24
Finished Mar 21 02:15:31 PM PDT 24
Peak memory 202392 kb
Host smart-47c4b19c-1c96-458b-8e0a-5ab2ad0df932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090484278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.2090484278
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.2330599160
Short name T655
Test name
Test status
Simulation time 45448935184 ps
CPU time 806.66 seconds
Started Mar 21 01:27:28 PM PDT 24
Finished Mar 21 01:40:55 PM PDT 24
Peak memory 368008 kb
Host smart-436f8742-488c-4b7b-b5c8-80973aa80f15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330599160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.2330599160
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.4153288985
Short name T854
Test name
Test status
Simulation time 28307868406 ps
CPU time 35.65 seconds
Started Mar 21 01:27:30 PM PDT 24
Finished Mar 21 01:28:06 PM PDT 24
Peak memory 202356 kb
Host smart-aba42a72-72ed-41b7-9b0d-ca2810344771
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153288985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.4153288985
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.219526781
Short name T561
Test name
Test status
Simulation time 1606280312 ps
CPU time 122.5 seconds
Started Mar 21 01:27:34 PM PDT 24
Finished Mar 21 01:29:37 PM PDT 24
Peak memory 353548 kb
Host smart-78c5f1cd-456b-4f32-a3f4-371f0751a589
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219526781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.sram_ctrl_max_throughput.219526781
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2563058042
Short name T631
Test name
Test status
Simulation time 2689283075 ps
CPU time 78.88 seconds
Started Mar 21 01:27:31 PM PDT 24
Finished Mar 21 01:28:50 PM PDT 24
Peak memory 210600 kb
Host smart-a379e64f-84a5-4464-b91c-62fe4e4af821
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563058042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.2563058042
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.4094805116
Short name T341
Test name
Test status
Simulation time 28719587408 ps
CPU time 148.08 seconds
Started Mar 21 01:27:34 PM PDT 24
Finished Mar 21 01:30:02 PM PDT 24
Peak memory 202508 kb
Host smart-6c22363c-de21-4185-ac6a-5bd229fb3d10
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094805116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.4094805116
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.1947304965
Short name T537
Test name
Test status
Simulation time 23678022135 ps
CPU time 1244.24 seconds
Started Mar 21 01:27:29 PM PDT 24
Finished Mar 21 01:48:13 PM PDT 24
Peak memory 373196 kb
Host smart-995bbf0a-78eb-4e66-9235-9a7e7a8d2398
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947304965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.1947304965
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.2521343832
Short name T827
Test name
Test status
Simulation time 2973562930 ps
CPU time 13.28 seconds
Started Mar 21 01:27:29 PM PDT 24
Finished Mar 21 01:27:43 PM PDT 24
Peak memory 202384 kb
Host smart-e3bebf1c-6492-4fdb-9f96-39938d1f78fa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521343832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.2521343832
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3772061915
Short name T699
Test name
Test status
Simulation time 32493236119 ps
CPU time 413.91 seconds
Started Mar 21 01:27:32 PM PDT 24
Finished Mar 21 01:34:26 PM PDT 24
Peak memory 202332 kb
Host smart-8bce4bcd-2e96-48ff-af5b-1ae192fbe1f4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772061915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.3772061915
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.1141772009
Short name T407
Test name
Test status
Simulation time 573102913 ps
CPU time 3.29 seconds
Started Mar 21 01:27:32 PM PDT 24
Finished Mar 21 01:27:35 PM PDT 24
Peak memory 202488 kb
Host smart-0638179a-dcdd-4d79-bb7a-6b689eb6eb89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141772009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1141772009
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.1879543145
Short name T488
Test name
Test status
Simulation time 15301370620 ps
CPU time 929.71 seconds
Started Mar 21 01:27:31 PM PDT 24
Finished Mar 21 01:43:02 PM PDT 24
Peak memory 377196 kb
Host smart-8b7b97dc-fa64-40de-b297-3965ed1bab6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879543145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1879543145
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.3309866817
Short name T284
Test name
Test status
Simulation time 499919446 ps
CPU time 12.46 seconds
Started Mar 21 01:27:29 PM PDT 24
Finished Mar 21 01:27:41 PM PDT 24
Peak memory 202300 kb
Host smart-e9084632-4a6f-4cab-a3f6-f2212a680250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309866817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3309866817
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3896483792
Short name T103
Test name
Test status
Simulation time 588851752 ps
CPU time 8.02 seconds
Started Mar 21 01:27:32 PM PDT 24
Finished Mar 21 01:27:40 PM PDT 24
Peak memory 210596 kb
Host smart-92a484ab-5510-40dc-90a0-2094809ecc08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3896483792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3896483792
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1344951209
Short name T577
Test name
Test status
Simulation time 23283679800 ps
CPU time 379.61 seconds
Started Mar 21 01:27:30 PM PDT 24
Finished Mar 21 01:33:50 PM PDT 24
Peak memory 202312 kb
Host smart-7e22ae35-0687-4f10-b2c9-ba5e2ff6db81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344951209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.1344951209
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1078594702
Short name T435
Test name
Test status
Simulation time 1501037222 ps
CPU time 32.82 seconds
Started Mar 21 01:27:28 PM PDT 24
Finished Mar 21 01:28:01 PM PDT 24
Peak memory 278920 kb
Host smart-d88b7854-f181-4fb6-bdd4-445ddb94c1f8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078594702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1078594702
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3711497074
Short name T895
Test name
Test status
Simulation time 33262980003 ps
CPU time 849.5 seconds
Started Mar 21 01:27:35 PM PDT 24
Finished Mar 21 01:41:45 PM PDT 24
Peak memory 378108 kb
Host smart-f4500a89-8c7c-4f33-83a9-0c3d012f071d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711497074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.3711497074
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.2174891690
Short name T932
Test name
Test status
Simulation time 21119158 ps
CPU time 0.66 seconds
Started Mar 21 01:27:36 PM PDT 24
Finished Mar 21 01:27:37 PM PDT 24
Peak memory 202080 kb
Host smart-06687ae9-9823-4cc5-bad6-e8e2d76731a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174891690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.2174891690
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.2330279188
Short name T14
Test name
Test status
Simulation time 49203239352 ps
CPU time 986.36 seconds
Started Mar 21 01:27:32 PM PDT 24
Finished Mar 21 01:43:59 PM PDT 24
Peak memory 202456 kb
Host smart-45299b36-98ba-4ad5-a4af-fb756ca7f17a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330279188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.2330279188
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.3546687342
Short name T841
Test name
Test status
Simulation time 4878817095 ps
CPU time 281.91 seconds
Started Mar 21 01:27:35 PM PDT 24
Finished Mar 21 01:32:17 PM PDT 24
Peak memory 313860 kb
Host smart-7f909d72-d019-40be-8c31-1e48b2265dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546687342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.3546687342
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.2917901616
Short name T882
Test name
Test status
Simulation time 6296815570 ps
CPU time 42.78 seconds
Started Mar 21 01:27:37 PM PDT 24
Finished Mar 21 01:28:20 PM PDT 24
Peak memory 202428 kb
Host smart-98900129-f557-4b5a-a03c-23650e293332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917901616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.2917901616
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.320378929
Short name T902
Test name
Test status
Simulation time 4020509443 ps
CPU time 42.37 seconds
Started Mar 21 01:27:32 PM PDT 24
Finished Mar 21 01:28:14 PM PDT 24
Peak memory 300548 kb
Host smart-b849f6bd-4ac4-4eae-97f7-e2bfe50bfd4f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320378929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.sram_ctrl_max_throughput.320378929
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2788419653
Short name T68
Test name
Test status
Simulation time 20364004127 ps
CPU time 144.66 seconds
Started Mar 21 01:27:32 PM PDT 24
Finished Mar 21 01:29:57 PM PDT 24
Peak memory 210700 kb
Host smart-f3cd5031-8639-4e60-a387-0b0f5594cda3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788419653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.2788419653
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.1145300316
Short name T517
Test name
Test status
Simulation time 6894607042 ps
CPU time 143.68 seconds
Started Mar 21 01:27:37 PM PDT 24
Finished Mar 21 01:30:01 PM PDT 24
Peak memory 202348 kb
Host smart-7666fe0b-0c6d-4f30-b96e-45c7c7e0a643
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145300316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.1145300316
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.1068356522
Short name T153
Test name
Test status
Simulation time 45979976776 ps
CPU time 827.05 seconds
Started Mar 21 01:27:32 PM PDT 24
Finished Mar 21 01:41:19 PM PDT 24
Peak memory 376216 kb
Host smart-10880d51-d48e-4d1a-9ab8-4dce47840730
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068356522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.1068356522
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.2379211173
Short name T224
Test name
Test status
Simulation time 2515557069 ps
CPU time 77.81 seconds
Started Mar 21 01:27:32 PM PDT 24
Finished Mar 21 01:28:50 PM PDT 24
Peak memory 328276 kb
Host smart-a72314c1-59ae-4b3b-a623-88795c7de41b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379211173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.2379211173
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3322284969
Short name T201
Test name
Test status
Simulation time 28640346120 ps
CPU time 366.44 seconds
Started Mar 21 01:27:34 PM PDT 24
Finished Mar 21 01:33:40 PM PDT 24
Peak memory 202424 kb
Host smart-f3af18c2-669b-4c00-a10c-079d0f1d9c0b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322284969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.3322284969
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.1859139714
Short name T535
Test name
Test status
Simulation time 1341564536 ps
CPU time 3.51 seconds
Started Mar 21 01:27:35 PM PDT 24
Finished Mar 21 01:27:39 PM PDT 24
Peak memory 202544 kb
Host smart-b6a0f68c-5f7b-4e25-bf24-6ef86e935f78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859139714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1859139714
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.4088831441
Short name T656
Test name
Test status
Simulation time 15740047496 ps
CPU time 714.93 seconds
Started Mar 21 01:27:37 PM PDT 24
Finished Mar 21 01:39:32 PM PDT 24
Peak memory 376184 kb
Host smart-838e070b-4f02-4af9-9e5d-753f1479a71d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088831441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.4088831441
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.590434767
Short name T605
Test name
Test status
Simulation time 821108205 ps
CPU time 7.09 seconds
Started Mar 21 01:27:31 PM PDT 24
Finished Mar 21 01:27:39 PM PDT 24
Peak memory 202308 kb
Host smart-8eb2bbcb-6420-42b9-8759-076eef24f31e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590434767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.590434767
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.692265415
Short name T226
Test name
Test status
Simulation time 44205756632 ps
CPU time 4248.2 seconds
Started Mar 21 01:27:31 PM PDT 24
Finished Mar 21 02:38:21 PM PDT 24
Peak memory 382372 kb
Host smart-60345610-3e06-4401-8e92-6160a8aae507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692265415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_stress_all.692265415
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.407179457
Short name T934
Test name
Test status
Simulation time 46303626393 ps
CPU time 200.14 seconds
Started Mar 21 01:27:31 PM PDT 24
Finished Mar 21 01:30:52 PM PDT 24
Peak memory 202412 kb
Host smart-f1fd545c-3652-41a9-8595-c47181f7a8f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407179457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_stress_pipeline.407179457
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2616452146
Short name T872
Test name
Test status
Simulation time 3103460159 ps
CPU time 49.22 seconds
Started Mar 21 01:27:33 PM PDT 24
Finished Mar 21 01:28:22 PM PDT 24
Peak memory 312116 kb
Host smart-89a1c3f1-b7d3-434f-909b-0c0abddf0c92
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616452146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2616452146
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2199088672
Short name T910
Test name
Test status
Simulation time 19928305825 ps
CPU time 341.31 seconds
Started Mar 21 01:27:35 PM PDT 24
Finished Mar 21 01:33:17 PM PDT 24
Peak memory 348108 kb
Host smart-2fcda121-5ac2-4b23-9741-c56a9a747bdd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199088672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.2199088672
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.926017756
Short name T530
Test name
Test status
Simulation time 28561502 ps
CPU time 0.65 seconds
Started Mar 21 01:27:48 PM PDT 24
Finished Mar 21 01:27:48 PM PDT 24
Peak memory 201928 kb
Host smart-8464f33e-1815-469e-b287-891762a7c5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926017756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.926017756
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.3254286738
Short name T604
Test name
Test status
Simulation time 29031927366 ps
CPU time 614.58 seconds
Started Mar 21 01:27:38 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 202420 kb
Host smart-9cbfc788-9ede-412c-9a19-a5f6e658f7ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254286738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.3254286738
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.884990704
Short name T208
Test name
Test status
Simulation time 54650132061 ps
CPU time 1048.7 seconds
Started Mar 21 01:27:50 PM PDT 24
Finished Mar 21 01:45:20 PM PDT 24
Peak memory 377244 kb
Host smart-fcf82e0a-becd-440c-b8ba-35e04e48a55b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884990704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executabl
e.884990704
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.3112340129
Short name T278
Test name
Test status
Simulation time 37425695135 ps
CPU time 45.09 seconds
Started Mar 21 01:27:38 PM PDT 24
Finished Mar 21 01:28:24 PM PDT 24
Peak memory 210552 kb
Host smart-01df4530-8dee-474a-9a18-e2a9e393ebf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112340129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.3112340129
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.1296874597
Short name T473
Test name
Test status
Simulation time 1403349699 ps
CPU time 19.09 seconds
Started Mar 21 01:27:38 PM PDT 24
Finished Mar 21 01:27:57 PM PDT 24
Peak memory 255600 kb
Host smart-bc35af70-eab6-45fa-a120-053756123c50
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296874597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.1296874597
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3987220548
Short name T668
Test name
Test status
Simulation time 2466730417 ps
CPU time 78.72 seconds
Started Mar 21 01:27:40 PM PDT 24
Finished Mar 21 01:28:59 PM PDT 24
Peak memory 210624 kb
Host smart-c13ca39f-18b1-40b8-bde8-c69e361d1a2e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987220548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.3987220548
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.3796177311
Short name T782
Test name
Test status
Simulation time 17934323792 ps
CPU time 124.8 seconds
Started Mar 21 01:27:43 PM PDT 24
Finished Mar 21 01:29:48 PM PDT 24
Peak memory 202432 kb
Host smart-708c0c24-c6d9-4869-8e82-f3247226c01b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796177311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.3796177311
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.3158516266
Short name T82
Test name
Test status
Simulation time 62692490590 ps
CPU time 592.74 seconds
Started Mar 21 01:27:38 PM PDT 24
Finished Mar 21 01:37:32 PM PDT 24
Peak memory 372180 kb
Host smart-010f079c-2ad1-4214-9bc5-3d3969101057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158516266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.3158516266
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.116666160
Short name T894
Test name
Test status
Simulation time 397623893 ps
CPU time 5.27 seconds
Started Mar 21 01:27:43 PM PDT 24
Finished Mar 21 01:27:48 PM PDT 24
Peak memory 202348 kb
Host smart-3a15f6cf-61ca-4381-b9ac-eb39ef84bdb1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116666160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s
ram_ctrl_partial_access.116666160
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.76348975
Short name T93
Test name
Test status
Simulation time 8639810182 ps
CPU time 438.12 seconds
Started Mar 21 01:27:36 PM PDT 24
Finished Mar 21 01:34:54 PM PDT 24
Peak memory 202332 kb
Host smart-23cbd1a8-5b41-449d-8f8b-57aab22c1107
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76348975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_partial_access_b2b.76348975
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.2908350124
Short name T692
Test name
Test status
Simulation time 1411158696 ps
CPU time 3.29 seconds
Started Mar 21 01:27:38 PM PDT 24
Finished Mar 21 01:27:42 PM PDT 24
Peak memory 202552 kb
Host smart-f82affa3-ab32-4afb-81c0-7965222eae25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908350124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2908350124
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.1799637225
Short name T120
Test name
Test status
Simulation time 24074174624 ps
CPU time 998.22 seconds
Started Mar 21 01:27:35 PM PDT 24
Finished Mar 21 01:44:13 PM PDT 24
Peak memory 373144 kb
Host smart-58d9e54e-ea7d-4086-bf30-701e31b17fcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799637225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1799637225
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.2484287585
Short name T248
Test name
Test status
Simulation time 966461790 ps
CPU time 6.81 seconds
Started Mar 21 01:27:36 PM PDT 24
Finished Mar 21 01:27:44 PM PDT 24
Peak memory 202396 kb
Host smart-1c7455d1-8937-4e52-b8dd-040e6fc9b4b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484287585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2484287585
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.4025373411
Short name T416
Test name
Test status
Simulation time 415203150881 ps
CPU time 2985.85 seconds
Started Mar 21 01:27:37 PM PDT 24
Finished Mar 21 02:17:23 PM PDT 24
Peak memory 374112 kb
Host smart-46619f43-60dc-4386-8515-e7a203a6f0e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025373411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.4025373411
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2997154094
Short name T579
Test name
Test status
Simulation time 1398053698 ps
CPU time 38.85 seconds
Started Mar 21 01:27:36 PM PDT 24
Finished Mar 21 01:28:15 PM PDT 24
Peak memory 210560 kb
Host smart-55180ada-e8ad-452a-bad0-5c0041be6a65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2997154094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2997154094
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.995579719
Short name T871
Test name
Test status
Simulation time 5151541444 ps
CPU time 157.78 seconds
Started Mar 21 01:27:38 PM PDT 24
Finished Mar 21 01:30:16 PM PDT 24
Peak memory 202324 kb
Host smart-3fae5f1e-9cb0-467b-bc09-0ba8cc636489
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995579719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_stress_pipeline.995579719
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1456038207
Short name T852
Test name
Test status
Simulation time 9232495144 ps
CPU time 58.78 seconds
Started Mar 21 01:27:39 PM PDT 24
Finished Mar 21 01:28:38 PM PDT 24
Peak memory 308300 kb
Host smart-cff6f627-e88c-4d31-ae31-5d511a63e4ff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456038207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1456038207
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.2661166259
Short name T365
Test name
Test status
Simulation time 31628397473 ps
CPU time 640.42 seconds
Started Mar 21 01:25:31 PM PDT 24
Finished Mar 21 01:36:12 PM PDT 24
Peak memory 372076 kb
Host smart-d3538d35-fac7-443e-b636-414590a88f48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661166259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.2661166259
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.2177514559
Short name T347
Test name
Test status
Simulation time 22209545333 ps
CPU time 1438.55 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:49:32 PM PDT 24
Peak memory 202692 kb
Host smart-5cee48ba-7727-4ed5-92a3-1c3a2405b2bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177514559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
2177514559
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.791727649
Short name T924
Test name
Test status
Simulation time 37979099950 ps
CPU time 624.55 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:35:57 PM PDT 24
Peak memory 378256 kb
Host smart-31a05b0d-804b-40ba-8fc0-5bc14dfcf544
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791727649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable
.791727649
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.4004749215
Short name T422
Test name
Test status
Simulation time 57310325613 ps
CPU time 60.26 seconds
Started Mar 21 01:25:30 PM PDT 24
Finished Mar 21 01:26:31 PM PDT 24
Peak memory 202512 kb
Host smart-1cbd99ba-2003-410c-9cc9-db4483d4f878
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004749215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.4004749215
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.3243391538
Short name T666
Test name
Test status
Simulation time 1454925985 ps
CPU time 27.04 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:25:53 PM PDT 24
Peak memory 278696 kb
Host smart-87306cff-6936-45f2-8a5e-3efd3279c7d9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243391538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.3243391538
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1083935617
Short name T305
Test name
Test status
Simulation time 5788615315 ps
CPU time 130.25 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:27:33 PM PDT 24
Peak memory 210620 kb
Host smart-217e72bf-0152-45a3-95f1-27f7a1220e86
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083935617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.1083935617
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.3161459842
Short name T808
Test name
Test status
Simulation time 21535384373 ps
CPU time 319.45 seconds
Started Mar 21 01:25:28 PM PDT 24
Finished Mar 21 01:30:48 PM PDT 24
Peak memory 202968 kb
Host smart-517a3241-acda-4a5d-9302-27e90af82059
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161459842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.3161459842
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.1984124114
Short name T550
Test name
Test status
Simulation time 50356530255 ps
CPU time 1672.58 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:53:16 PM PDT 24
Peak memory 380492 kb
Host smart-cc67e4ee-91d4-4f0b-b5f3-acebdc09e5c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984124114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.1984124114
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.803796788
Short name T516
Test name
Test status
Simulation time 2100392059 ps
CPU time 8.95 seconds
Started Mar 21 01:25:27 PM PDT 24
Finished Mar 21 01:25:36 PM PDT 24
Peak memory 202240 kb
Host smart-58d5bb81-8f3e-4008-b28a-8e26a7ba3361
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803796788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr
am_ctrl_partial_access.803796788
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1680859509
Short name T264
Test name
Test status
Simulation time 7376736106 ps
CPU time 435.7 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:32:40 PM PDT 24
Peak memory 202064 kb
Host smart-96b535f5-5ad1-4793-ac71-ec9d8b3f15b6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680859509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.1680859509
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.3209322124
Short name T770
Test name
Test status
Simulation time 1777207567 ps
CPU time 3.13 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:25:26 PM PDT 24
Peak memory 202436 kb
Host smart-13ee0f9a-72de-4ad8-9cad-c666719e37f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209322124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3209322124
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.4145862068
Short name T313
Test name
Test status
Simulation time 22287097188 ps
CPU time 853.8 seconds
Started Mar 21 01:25:18 PM PDT 24
Finished Mar 21 01:39:39 PM PDT 24
Peak memory 380328 kb
Host smart-1c4f9c50-3d81-409f-94bc-8d1e7630aaad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145862068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.4145862068
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3679314041
Short name T31
Test name
Test status
Simulation time 251702983 ps
CPU time 2.84 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:25:28 PM PDT 24
Peak memory 221440 kb
Host smart-c0811c95-7799-4638-b86c-349590fb4193
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679314041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3679314041
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.37744970
Short name T559
Test name
Test status
Simulation time 2681501155 ps
CPU time 5.32 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:25:37 PM PDT 24
Peak memory 211404 kb
Host smart-3c3dfbc7-9ca5-4c27-b849-e8d3fd17ea1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37744970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.37744970
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.1492918271
Short name T599
Test name
Test status
Simulation time 18906098881 ps
CPU time 1838.56 seconds
Started Mar 21 01:25:20 PM PDT 24
Finished Mar 21 01:55:59 PM PDT 24
Peak memory 373144 kb
Host smart-b0a1e76d-62ec-4ee0-8ff3-840c69c02933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492918271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.1492918271
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.501154416
Short name T805
Test name
Test status
Simulation time 1777481495 ps
CPU time 46.83 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:26:12 PM PDT 24
Peak memory 211592 kb
Host smart-2cd4eba3-1e2d-4404-99d5-1413fd7422c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=501154416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.501154416
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.566611209
Short name T453
Test name
Test status
Simulation time 17297125168 ps
CPU time 241.88 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:29:28 PM PDT 24
Peak memory 202340 kb
Host smart-a6e74a8f-bede-4b0c-917b-85e3f07bd085
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566611209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_stress_pipeline.566611209
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3699748434
Short name T372
Test name
Test status
Simulation time 3060199299 ps
CPU time 82.87 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:26:48 PM PDT 24
Peak memory 346740 kb
Host smart-6e74e0d5-48f6-4194-8f2f-0c348ecc7672
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699748434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3699748434
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1869684918
Short name T819
Test name
Test status
Simulation time 5318944287 ps
CPU time 295.57 seconds
Started Mar 21 01:27:47 PM PDT 24
Finished Mar 21 01:32:42 PM PDT 24
Peak memory 352612 kb
Host smart-e71e225b-3b1c-4d1f-9a8b-e53b0ec653eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869684918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.1869684918
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.3817705456
Short name T414
Test name
Test status
Simulation time 14595581 ps
CPU time 0.66 seconds
Started Mar 21 01:27:48 PM PDT 24
Finished Mar 21 01:27:49 PM PDT 24
Peak memory 202120 kb
Host smart-84cab4ca-848a-4e28-8c05-a4b2e81a5d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817705456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.3817705456
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.3187307262
Short name T679
Test name
Test status
Simulation time 493536330960 ps
CPU time 1313.52 seconds
Started Mar 21 01:27:47 PM PDT 24
Finished Mar 21 01:49:41 PM PDT 24
Peak memory 202520 kb
Host smart-46f2f417-c576-4359-96d1-97b168501ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187307262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.3187307262
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.3205632626
Short name T190
Test name
Test status
Simulation time 13622921237 ps
CPU time 683.96 seconds
Started Mar 21 01:27:48 PM PDT 24
Finished Mar 21 01:39:13 PM PDT 24
Peak memory 369064 kb
Host smart-6ac7c394-0cc2-4b4e-9ebd-8008a505f303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205632626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.3205632626
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.2349964008
Short name T921
Test name
Test status
Simulation time 6702942727 ps
CPU time 32.2 seconds
Started Mar 21 01:27:54 PM PDT 24
Finished Mar 21 01:28:27 PM PDT 24
Peak memory 214596 kb
Host smart-9809d228-283d-49a6-bf96-ff38af7d3c01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349964008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.2349964008
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.565862470
Short name T630
Test name
Test status
Simulation time 696400692 ps
CPU time 6.52 seconds
Started Mar 21 01:27:48 PM PDT 24
Finished Mar 21 01:27:55 PM PDT 24
Peak memory 210504 kb
Host smart-6ec21963-a305-44c8-8dfd-f0889a82a5c2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565862470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_max_throughput.565862470
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3756448619
Short name T721
Test name
Test status
Simulation time 13022832931 ps
CPU time 135.68 seconds
Started Mar 21 01:27:47 PM PDT 24
Finished Mar 21 01:30:03 PM PDT 24
Peak memory 210496 kb
Host smart-f1efbc35-abc2-4fe7-af32-64f4bf0d2afa
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756448619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.3756448619
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.2495349991
Short name T645
Test name
Test status
Simulation time 8974639019 ps
CPU time 125.92 seconds
Started Mar 21 01:27:47 PM PDT 24
Finished Mar 21 01:29:53 PM PDT 24
Peak memory 202696 kb
Host smart-70f43963-27fd-450f-981b-e48b5a57d71a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495349991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.2495349991
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.4215011073
Short name T239
Test name
Test status
Simulation time 14403745261 ps
CPU time 402.98 seconds
Started Mar 21 01:27:46 PM PDT 24
Finished Mar 21 01:34:30 PM PDT 24
Peak memory 353408 kb
Host smart-61ca10b8-39bb-4d09-b242-3ca27f0a0c35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215011073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.4215011073
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.2465255688
Short name T156
Test name
Test status
Simulation time 3602585690 ps
CPU time 16.19 seconds
Started Mar 21 01:27:45 PM PDT 24
Finished Mar 21 01:28:01 PM PDT 24
Peak memory 247292 kb
Host smart-c20ff56a-db15-431b-a931-380dd4f4457b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465255688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.2465255688
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3014735745
Short name T472
Test name
Test status
Simulation time 7366488145 ps
CPU time 344.84 seconds
Started Mar 21 01:27:49 PM PDT 24
Finished Mar 21 01:33:34 PM PDT 24
Peak memory 202332 kb
Host smart-3fd3d955-89ac-4e3c-bfdc-02a46315c5cd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014735745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.3014735745
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.3151371413
Short name T374
Test name
Test status
Simulation time 349387366 ps
CPU time 2.99 seconds
Started Mar 21 01:27:48 PM PDT 24
Finished Mar 21 01:27:51 PM PDT 24
Peak memory 202320 kb
Host smart-8940a3ba-2698-4a6e-b575-b5eadb4e8a06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151371413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3151371413
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3110147840
Short name T441
Test name
Test status
Simulation time 22446539132 ps
CPU time 700.04 seconds
Started Mar 21 01:27:47 PM PDT 24
Finished Mar 21 01:39:27 PM PDT 24
Peak memory 373172 kb
Host smart-1561b4ed-c141-4440-8737-81da9a33853e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110147840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3110147840
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.3908522886
Short name T33
Test name
Test status
Simulation time 1553041437 ps
CPU time 73.03 seconds
Started Mar 21 01:27:47 PM PDT 24
Finished Mar 21 01:29:00 PM PDT 24
Peak memory 319884 kb
Host smart-56ea2c94-1520-4fba-905b-b8f8b7b5379b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908522886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3908522886
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.1207562970
Short name T688
Test name
Test status
Simulation time 283830440875 ps
CPU time 2536.69 seconds
Started Mar 21 01:27:49 PM PDT 24
Finished Mar 21 02:10:06 PM PDT 24
Peak memory 373176 kb
Host smart-b1209d99-c801-4a37-9d52-a26249b54686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207562970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.1207562970
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1875083005
Short name T43
Test name
Test status
Simulation time 513726566 ps
CPU time 12.62 seconds
Started Mar 21 01:27:47 PM PDT 24
Finished Mar 21 01:28:00 PM PDT 24
Peak memory 210664 kb
Host smart-30f84d26-5132-4ebd-92db-49720dbeca6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1875083005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1875083005
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2034152111
Short name T705
Test name
Test status
Simulation time 4489240717 ps
CPU time 327.3 seconds
Started Mar 21 01:27:49 PM PDT 24
Finished Mar 21 01:33:17 PM PDT 24
Peak memory 202224 kb
Host smart-0647da37-7797-45d7-9faa-51fbdea9f519
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034152111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.2034152111
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1512434033
Short name T619
Test name
Test status
Simulation time 712948012 ps
CPU time 7.15 seconds
Started Mar 21 01:27:52 PM PDT 24
Finished Mar 21 01:28:00 PM PDT 24
Peak memory 217200 kb
Host smart-6c52a287-854b-4e9f-8b14-3649ae22ba15
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512434033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1512434033
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1036715688
Short name T13
Test name
Test status
Simulation time 12686563427 ps
CPU time 50.24 seconds
Started Mar 21 01:28:00 PM PDT 24
Finished Mar 21 01:28:51 PM PDT 24
Peak memory 284200 kb
Host smart-de8fc683-60d4-46a5-8089-6cfa34a3a05f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036715688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.1036715688
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.4110838593
Short name T154
Test name
Test status
Simulation time 50500371 ps
CPU time 0.64 seconds
Started Mar 21 01:27:59 PM PDT 24
Finished Mar 21 01:28:00 PM PDT 24
Peak memory 202148 kb
Host smart-19d8dc7e-5216-4ff3-909e-cd5a68ba3b10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110838593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.4110838593
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.2354665911
Short name T80
Test name
Test status
Simulation time 51661037347 ps
CPU time 1733.15 seconds
Started Mar 21 01:27:49 PM PDT 24
Finished Mar 21 01:56:42 PM PDT 24
Peak memory 202660 kb
Host smart-b7aa852f-003d-4225-ad20-1337e8c7566f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354665911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.2354665911
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.974336876
Short name T608
Test name
Test status
Simulation time 69983662448 ps
CPU time 651.56 seconds
Started Mar 21 01:27:59 PM PDT 24
Finished Mar 21 01:38:51 PM PDT 24
Peak memory 358924 kb
Host smart-ae96c7d3-5c7c-408e-8758-efdaa31b153d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974336876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executabl
e.974336876
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.3079465073
Short name T522
Test name
Test status
Simulation time 30712825230 ps
CPU time 44.01 seconds
Started Mar 21 01:27:54 PM PDT 24
Finished Mar 21 01:28:38 PM PDT 24
Peak memory 202344 kb
Host smart-9e80a20c-b7e5-4d2e-88e3-acd182f2d1e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079465073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.3079465073
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.3792669404
Short name T908
Test name
Test status
Simulation time 814707018 ps
CPU time 128.62 seconds
Started Mar 21 01:27:53 PM PDT 24
Finished Mar 21 01:30:02 PM PDT 24
Peak memory 369952 kb
Host smart-196df6a7-04d7-4029-9c36-a1d9496d9339
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792669404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.3792669404
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3202787562
Short name T187
Test name
Test status
Simulation time 2544150964 ps
CPU time 72.39 seconds
Started Mar 21 01:27:56 PM PDT 24
Finished Mar 21 01:29:09 PM PDT 24
Peak memory 210604 kb
Host smart-873bdadd-d42e-46c1-90c0-66018b6244dd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202787562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.3202787562
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.773496981
Short name T371
Test name
Test status
Simulation time 9863925101 ps
CPU time 126.88 seconds
Started Mar 21 01:27:55 PM PDT 24
Finished Mar 21 01:30:03 PM PDT 24
Peak memory 202848 kb
Host smart-51902803-7578-42db-be50-0d2e6faf9037
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773496981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl
_mem_walk.773496981
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.1149269585
Short name T336
Test name
Test status
Simulation time 41652472465 ps
CPU time 1433.09 seconds
Started Mar 21 01:27:47 PM PDT 24
Finished Mar 21 01:51:40 PM PDT 24
Peak memory 373244 kb
Host smart-397af311-cd5c-4335-be7c-dab869b40b6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149269585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.1149269585
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.2856962297
Short name T907
Test name
Test status
Simulation time 1392213557 ps
CPU time 9.99 seconds
Started Mar 21 01:27:56 PM PDT 24
Finished Mar 21 01:28:07 PM PDT 24
Peak memory 224700 kb
Host smart-a8415e81-9843-4a84-87c0-7da02a8aa06f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856962297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.2856962297
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.284274986
Short name T399
Test name
Test status
Simulation time 5472021714 ps
CPU time 352.14 seconds
Started Mar 21 01:27:56 PM PDT 24
Finished Mar 21 01:33:48 PM PDT 24
Peak memory 202344 kb
Host smart-39e183cc-ea4a-42fe-a3cf-0ec70b3050d0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284274986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.sram_ctrl_partial_access_b2b.284274986
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.4195365182
Short name T314
Test name
Test status
Simulation time 724646676 ps
CPU time 2.95 seconds
Started Mar 21 01:27:53 PM PDT 24
Finished Mar 21 01:27:57 PM PDT 24
Peak memory 202404 kb
Host smart-7d482015-a7f8-4430-b6dc-4d8cc211343d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195365182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.4195365182
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.3053825429
Short name T117
Test name
Test status
Simulation time 4909070751 ps
CPU time 486.2 seconds
Started Mar 21 01:27:54 PM PDT 24
Finished Mar 21 01:36:01 PM PDT 24
Peak memory 374104 kb
Host smart-ca7bba89-09bc-4214-b9fe-93f9eee2d750
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053825429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3053825429
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.1833285447
Short name T251
Test name
Test status
Simulation time 555985562 ps
CPU time 38.17 seconds
Started Mar 21 01:27:50 PM PDT 24
Finished Mar 21 01:28:28 PM PDT 24
Peak memory 284164 kb
Host smart-64e4489e-37d0-464a-bf2b-f162205969c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833285447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1833285447
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.4053630634
Short name T344
Test name
Test status
Simulation time 48988539656 ps
CPU time 6044.71 seconds
Started Mar 21 01:27:53 PM PDT 24
Finished Mar 21 03:08:39 PM PDT 24
Peak memory 381588 kb
Host smart-23399f8a-2366-412f-94eb-4081fb55d7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053630634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.4053630634
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.1075185309
Short name T281
Test name
Test status
Simulation time 11112447934 ps
CPU time 144.89 seconds
Started Mar 21 01:27:49 PM PDT 24
Finished Mar 21 01:30:14 PM PDT 24
Peak memory 202436 kb
Host smart-cb1b475b-64c1-4bc7-b17c-108f174f7b50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075185309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.1075185309
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2914835225
Short name T469
Test name
Test status
Simulation time 3068598104 ps
CPU time 34.87 seconds
Started Mar 21 01:27:54 PM PDT 24
Finished Mar 21 01:28:30 PM PDT 24
Peak memory 300568 kb
Host smart-6bc2b372-3dd3-495c-87e7-d70d118805f7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914835225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2914835225
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3384924742
Short name T186
Test name
Test status
Simulation time 130422026135 ps
CPU time 1224.28 seconds
Started Mar 21 01:28:04 PM PDT 24
Finished Mar 21 01:48:29 PM PDT 24
Peak memory 377284 kb
Host smart-77ea3ba1-808d-4297-9444-1e3af9bcd996
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384924742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.3384924742
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.3190943276
Short name T712
Test name
Test status
Simulation time 20430801 ps
CPU time 0.69 seconds
Started Mar 21 01:28:04 PM PDT 24
Finished Mar 21 01:28:05 PM PDT 24
Peak memory 201932 kb
Host smart-d01dfc04-800f-40af-b738-3ced14fdbf2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190943276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.3190943276
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.1440444320
Short name T545
Test name
Test status
Simulation time 151766452962 ps
CPU time 2382.6 seconds
Started Mar 21 01:27:55 PM PDT 24
Finished Mar 21 02:07:39 PM PDT 24
Peak memory 202304 kb
Host smart-2e3275aa-0f9a-4c37-860e-66fd17fc96b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440444320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.1440444320
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.3535324300
Short name T772
Test name
Test status
Simulation time 28757232308 ps
CPU time 37.4 seconds
Started Mar 21 01:28:05 PM PDT 24
Finished Mar 21 01:28:42 PM PDT 24
Peak memory 240016 kb
Host smart-12678030-db73-4e4d-a31f-2fcb6b2aae05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535324300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.3535324300
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.3098577150
Short name T611
Test name
Test status
Simulation time 32679515334 ps
CPU time 47.31 seconds
Started Mar 21 01:28:04 PM PDT 24
Finished Mar 21 01:28:52 PM PDT 24
Peak memory 202380 kb
Host smart-d9d22e1f-8c7a-4923-bc5d-64dcbca5168b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098577150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.3098577150
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.3293852946
Short name T233
Test name
Test status
Simulation time 875467707 ps
CPU time 67.78 seconds
Started Mar 21 01:27:55 PM PDT 24
Finished Mar 21 01:29:03 PM PDT 24
Peak memory 314904 kb
Host smart-5287f104-7bcd-40ac-9fca-ded2fa1f659e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293852946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.3293852946
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1517292241
Short name T777
Test name
Test status
Simulation time 2661390408 ps
CPU time 77.99 seconds
Started Mar 21 01:28:05 PM PDT 24
Finished Mar 21 01:29:23 PM PDT 24
Peak memory 210628 kb
Host smart-190752fc-d829-4d22-b152-54b554340a47
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517292241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.1517292241
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.1514174563
Short name T698
Test name
Test status
Simulation time 20658108386 ps
CPU time 322.17 seconds
Started Mar 21 01:28:05 PM PDT 24
Finished Mar 21 01:33:27 PM PDT 24
Peak memory 202848 kb
Host smart-ac7429a7-2c2c-4089-b3ac-fa1b2222cf09
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514174563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.1514174563
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.3380803678
Short name T136
Test name
Test status
Simulation time 45932025281 ps
CPU time 477.02 seconds
Started Mar 21 01:27:53 PM PDT 24
Finished Mar 21 01:35:51 PM PDT 24
Peak memory 367020 kb
Host smart-6f7668f5-8581-4666-9bfc-f396eb3bf39e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380803678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.3380803678
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.530212887
Short name T778
Test name
Test status
Simulation time 1665007796 ps
CPU time 124.97 seconds
Started Mar 21 01:27:55 PM PDT 24
Finished Mar 21 01:30:01 PM PDT 24
Peak memory 357936 kb
Host smart-dd677f34-f7eb-4b7f-a46f-c58ad805d125
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530212887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s
ram_ctrl_partial_access.530212887
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3466267873
Short name T575
Test name
Test status
Simulation time 13809325024 ps
CPU time 281.96 seconds
Started Mar 21 01:27:55 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 202336 kb
Host smart-70c1f8bd-d21a-4199-ab42-f9473ed22e31
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466267873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.3466267873
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.120183881
Short name T350
Test name
Test status
Simulation time 1771699451 ps
CPU time 3.47 seconds
Started Mar 21 01:28:05 PM PDT 24
Finished Mar 21 01:28:08 PM PDT 24
Peak memory 202508 kb
Host smart-3079be6f-ea24-4595-96bc-72f4c009c619
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120183881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.120183881
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.231536507
Short name T471
Test name
Test status
Simulation time 80491430744 ps
CPU time 1662.04 seconds
Started Mar 21 01:28:08 PM PDT 24
Finished Mar 21 01:55:50 PM PDT 24
Peak memory 379320 kb
Host smart-e35d87fa-d570-4a8f-8581-54c586e26a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231536507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.231536507
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.2378087220
Short name T501
Test name
Test status
Simulation time 5675375741 ps
CPU time 26.4 seconds
Started Mar 21 01:27:54 PM PDT 24
Finished Mar 21 01:28:20 PM PDT 24
Peak memory 202376 kb
Host smart-debda048-bbeb-4277-b93b-bee14a74da58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378087220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2378087220
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1606236224
Short name T861
Test name
Test status
Simulation time 8968275201 ps
CPU time 127.35 seconds
Started Mar 21 01:28:04 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 370540 kb
Host smart-41ede40b-c460-4cb6-9a96-fa14f21b38c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1606236224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.1606236224
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3853019000
Short name T207
Test name
Test status
Simulation time 3303237916 ps
CPU time 183.56 seconds
Started Mar 21 01:27:56 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 202324 kb
Host smart-d38ff34b-7354-47b6-92eb-e373d279fb19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853019000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.3853019000
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2748949172
Short name T163
Test name
Test status
Simulation time 721396573 ps
CPU time 33.88 seconds
Started Mar 21 01:27:59 PM PDT 24
Finished Mar 21 01:28:33 PM PDT 24
Peak memory 276516 kb
Host smart-a09a2175-6451-4552-9bdd-3ec886782483
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748949172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2748949172
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3923600312
Short name T512
Test name
Test status
Simulation time 25601875770 ps
CPU time 1735.27 seconds
Started Mar 21 01:28:13 PM PDT 24
Finished Mar 21 01:57:09 PM PDT 24
Peak memory 378200 kb
Host smart-9e31e874-007b-4d2e-8ff8-82718bb7ddb8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923600312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.3923600312
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.2651878470
Short name T792
Test name
Test status
Simulation time 13711243 ps
CPU time 0.65 seconds
Started Mar 21 01:28:13 PM PDT 24
Finished Mar 21 01:28:13 PM PDT 24
Peak memory 202148 kb
Host smart-b7f177ac-fff8-461a-96be-9cfe7bfb2a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651878470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.2651878470
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.4004567640
Short name T326
Test name
Test status
Simulation time 660957919047 ps
CPU time 2765.42 seconds
Started Mar 21 01:28:12 PM PDT 24
Finished Mar 21 02:14:18 PM PDT 24
Peak memory 202796 kb
Host smart-1992216a-1922-4350-84ae-2412044a89b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004567640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.4004567640
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.1765516709
Short name T40
Test name
Test status
Simulation time 89248144224 ps
CPU time 866.8 seconds
Started Mar 21 01:28:12 PM PDT 24
Finished Mar 21 01:42:39 PM PDT 24
Peak memory 361828 kb
Host smart-2f0aa7b5-8754-4497-932f-50dfa69b19f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765516709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.1765516709
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.2534145265
Short name T132
Test name
Test status
Simulation time 77048621354 ps
CPU time 95.44 seconds
Started Mar 21 01:28:10 PM PDT 24
Finished Mar 21 01:29:46 PM PDT 24
Peak memory 202424 kb
Host smart-c0608f75-8518-424c-9921-fc4900fde26f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534145265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.2534145265
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.1216485457
Short name T815
Test name
Test status
Simulation time 3120002585 ps
CPU time 110.81 seconds
Started Mar 21 01:28:11 PM PDT 24
Finished Mar 21 01:30:02 PM PDT 24
Peak memory 349148 kb
Host smart-649ee9dd-4a85-4363-b2ed-b04164485cbe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216485457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.1216485457
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2365565712
Short name T71
Test name
Test status
Simulation time 4498061490 ps
CPU time 139.54 seconds
Started Mar 21 01:28:11 PM PDT 24
Finished Mar 21 01:30:30 PM PDT 24
Peak memory 210556 kb
Host smart-93517933-9bd3-4f5d-88aa-ce90c57919f8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365565712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.2365565712
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.1194688223
Short name T795
Test name
Test status
Simulation time 71540948051 ps
CPU time 321.32 seconds
Started Mar 21 01:28:12 PM PDT 24
Finished Mar 21 01:33:34 PM PDT 24
Peak memory 202496 kb
Host smart-d88d5b51-7b94-4cf1-be7d-ac19e78dcacf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194688223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.1194688223
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.2742498018
Short name T443
Test name
Test status
Simulation time 12577769775 ps
CPU time 1148.45 seconds
Started Mar 21 01:28:04 PM PDT 24
Finished Mar 21 01:47:13 PM PDT 24
Peak memory 380240 kb
Host smart-fed57c9c-d27f-4d86-822e-87fce4be9ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742498018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.2742498018
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.4027704579
Short name T790
Test name
Test status
Simulation time 5798808281 ps
CPU time 153.84 seconds
Started Mar 21 01:28:11 PM PDT 24
Finished Mar 21 01:30:45 PM PDT 24
Peak memory 365904 kb
Host smart-53fbc402-c274-4a2b-9791-28fcecc2ee96
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027704579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.4027704579
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3640577072
Short name T706
Test name
Test status
Simulation time 4051514068 ps
CPU time 237.16 seconds
Started Mar 21 01:28:11 PM PDT 24
Finished Mar 21 01:32:09 PM PDT 24
Peak memory 202380 kb
Host smart-6e9b94c1-9204-43a0-b60b-d8f9c42d9101
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640577072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.3640577072
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.1876832087
Short name T641
Test name
Test status
Simulation time 6666403117 ps
CPU time 5.13 seconds
Started Mar 21 01:28:11 PM PDT 24
Finished Mar 21 01:28:16 PM PDT 24
Peak memory 202548 kb
Host smart-6c1c4c99-fc9c-4b68-a3e9-630d3cc2d1dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876832087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1876832087
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.3032566824
Short name T774
Test name
Test status
Simulation time 27740372685 ps
CPU time 1318.93 seconds
Started Mar 21 01:28:12 PM PDT 24
Finished Mar 21 01:50:11 PM PDT 24
Peak memory 380456 kb
Host smart-d92b7a01-2201-4607-bd53-60ed1651dd91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032566824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3032566824
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.3376756163
Short name T337
Test name
Test status
Simulation time 746572137 ps
CPU time 4.81 seconds
Started Mar 21 01:28:03 PM PDT 24
Finished Mar 21 01:28:09 PM PDT 24
Peak memory 202364 kb
Host smart-e9ac69a6-55d8-4693-ac7a-333465f45ff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376756163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3376756163
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.1526461971
Short name T829
Test name
Test status
Simulation time 73820192954 ps
CPU time 3769.31 seconds
Started Mar 21 01:28:13 PM PDT 24
Finished Mar 21 02:31:03 PM PDT 24
Peak memory 380308 kb
Host smart-19b446d0-02a1-46da-9fa3-b4f6715fda6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526461971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.sram_ctrl_stress_all.1526461971
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3843812205
Short name T840
Test name
Test status
Simulation time 633326067 ps
CPU time 10.22 seconds
Started Mar 21 01:28:13 PM PDT 24
Finished Mar 21 01:28:24 PM PDT 24
Peak memory 210536 kb
Host smart-b3cd0b07-20ae-4202-b681-41d9cfc5c7ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3843812205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3843812205
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2824282445
Short name T540
Test name
Test status
Simulation time 5763036596 ps
CPU time 363.8 seconds
Started Mar 21 01:28:13 PM PDT 24
Finished Mar 21 01:34:17 PM PDT 24
Peak memory 202264 kb
Host smart-1ea2e754-f169-404d-bb2c-5b67a9e28652
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824282445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.2824282445
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3807646190
Short name T466
Test name
Test status
Simulation time 804944077 ps
CPU time 90.21 seconds
Started Mar 21 01:28:12 PM PDT 24
Finished Mar 21 01:29:42 PM PDT 24
Peak memory 335156 kb
Host smart-9e1e25da-1ee1-4f96-86d8-104de77d9fc1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807646190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3807646190
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1497293422
Short name T508
Test name
Test status
Simulation time 17576789694 ps
CPU time 835.29 seconds
Started Mar 21 01:28:23 PM PDT 24
Finished Mar 21 01:42:18 PM PDT 24
Peak memory 377160 kb
Host smart-7fecb082-4c2f-4cdb-ab51-186fd1cf0422
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497293422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.1497293422
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.1447581284
Short name T492
Test name
Test status
Simulation time 40824145 ps
CPU time 0.7 seconds
Started Mar 21 01:28:22 PM PDT 24
Finished Mar 21 01:28:23 PM PDT 24
Peak memory 201920 kb
Host smart-48ee2ced-86b5-404f-aa31-6bf279fb3228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447581284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.1447581284
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.1297706278
Short name T433
Test name
Test status
Simulation time 119645904159 ps
CPU time 2245.56 seconds
Started Mar 21 01:28:27 PM PDT 24
Finished Mar 21 02:05:52 PM PDT 24
Peak memory 202412 kb
Host smart-c629080e-c7ed-44e6-a67b-3ceadfb40268
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297706278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.1297706278
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.2648256417
Short name T230
Test name
Test status
Simulation time 18618964227 ps
CPU time 546.04 seconds
Started Mar 21 01:28:26 PM PDT 24
Finished Mar 21 01:37:32 PM PDT 24
Peak memory 370044 kb
Host smart-564e04a9-d86f-4ef5-af69-5b69a21efc30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648256417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab
le.2648256417
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.4028271649
Short name T622
Test name
Test status
Simulation time 43316490781 ps
CPU time 63.27 seconds
Started Mar 21 01:28:23 PM PDT 24
Finished Mar 21 01:29:26 PM PDT 24
Peak memory 202372 kb
Host smart-b8b57c1e-2448-4884-bb60-fa10350866bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028271649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.4028271649
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.927402091
Short name T820
Test name
Test status
Simulation time 7616877768 ps
CPU time 140.68 seconds
Started Mar 21 01:28:21 PM PDT 24
Finished Mar 21 01:30:42 PM PDT 24
Peak memory 367008 kb
Host smart-fbcbd5f3-2076-4ab6-b4f5-119ee289bbb9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927402091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.sram_ctrl_max_throughput.927402091
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.398075387
Short name T65
Test name
Test status
Simulation time 8692049019 ps
CPU time 123.71 seconds
Started Mar 21 01:28:21 PM PDT 24
Finished Mar 21 01:30:25 PM PDT 24
Peak memory 210512 kb
Host smart-f9569b10-4c17-4b0c-9fc0-f491c6015f28
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398075387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.sram_ctrl_mem_partial_access.398075387
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.769223826
Short name T262
Test name
Test status
Simulation time 20643990962 ps
CPU time 152.31 seconds
Started Mar 21 01:28:27 PM PDT 24
Finished Mar 21 01:30:59 PM PDT 24
Peak memory 202688 kb
Host smart-cde0dd1f-48cc-4c48-b86c-966393d976d2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769223826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl
_mem_walk.769223826
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.4165841861
Short name T900
Test name
Test status
Simulation time 14189264282 ps
CPU time 577.43 seconds
Started Mar 21 01:28:21 PM PDT 24
Finished Mar 21 01:37:59 PM PDT 24
Peak memory 372308 kb
Host smart-f21e1e3f-50c8-4271-b616-ff6e35a5e107
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165841861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.4165841861
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.571463121
Short name T646
Test name
Test status
Simulation time 1334640188 ps
CPU time 128.06 seconds
Started Mar 21 01:28:26 PM PDT 24
Finished Mar 21 01:30:34 PM PDT 24
Peak memory 361868 kb
Host smart-bd99da37-49af-4139-bc7f-0f847036d93f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571463121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s
ram_ctrl_partial_access.571463121
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3224601891
Short name T546
Test name
Test status
Simulation time 9927461396 ps
CPU time 298.49 seconds
Started Mar 21 01:28:23 PM PDT 24
Finished Mar 21 01:33:21 PM PDT 24
Peak memory 202384 kb
Host smart-3fac43a8-cfdc-445d-b18b-ef0501cb955d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224601891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.3224601891
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.499846715
Short name T210
Test name
Test status
Simulation time 710556612 ps
CPU time 3.23 seconds
Started Mar 21 01:28:28 PM PDT 24
Finished Mar 21 01:28:31 PM PDT 24
Peak memory 202484 kb
Host smart-abf9479f-b168-4861-a86e-9b28f4035e7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499846715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.499846715
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.3212550867
Short name T888
Test name
Test status
Simulation time 7305591297 ps
CPU time 479.25 seconds
Started Mar 21 01:28:22 PM PDT 24
Finished Mar 21 01:36:21 PM PDT 24
Peak memory 373056 kb
Host smart-18171a7a-c931-41c5-8949-72a65e6e2bff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212550867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3212550867
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.3223413480
Short name T212
Test name
Test status
Simulation time 2146432194 ps
CPU time 8.14 seconds
Started Mar 21 01:28:13 PM PDT 24
Finished Mar 21 01:28:21 PM PDT 24
Peak memory 202312 kb
Host smart-86cffc97-bfbf-4b32-b709-207827adbb9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223413480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3223413480
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.1808753206
Short name T358
Test name
Test status
Simulation time 67108280241 ps
CPU time 3501.48 seconds
Started Mar 21 01:28:21 PM PDT 24
Finished Mar 21 02:26:43 PM PDT 24
Peak memory 379272 kb
Host smart-644ee77b-43ab-473d-bc73-400f3a1d2a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808753206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.1808753206
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4102749705
Short name T715
Test name
Test status
Simulation time 10303167870 ps
CPU time 231.45 seconds
Started Mar 21 01:28:25 PM PDT 24
Finished Mar 21 01:32:17 PM PDT 24
Peak memory 382440 kb
Host smart-5e601606-7360-4c47-9295-ef2977110fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4102749705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.4102749705
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.51521898
Short name T162
Test name
Test status
Simulation time 4210779473 ps
CPU time 223.39 seconds
Started Mar 21 01:28:29 PM PDT 24
Finished Mar 21 01:32:12 PM PDT 24
Peak memory 202448 kb
Host smart-8197d9fa-30b0-4d01-8b9b-5381ac57ef8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51521898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_stress_pipeline.51521898
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1730327879
Short name T259
Test name
Test status
Simulation time 6488350849 ps
CPU time 112.73 seconds
Started Mar 21 01:28:21 PM PDT 24
Finished Mar 21 01:30:14 PM PDT 24
Peak memory 362860 kb
Host smart-388cfe9c-78d9-43c1-8b5f-b8a339f3af92
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730327879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1730327879
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.824444183
Short name T172
Test name
Test status
Simulation time 60217289178 ps
CPU time 983.31 seconds
Started Mar 21 01:28:28 PM PDT 24
Finished Mar 21 01:44:52 PM PDT 24
Peak memory 376220 kb
Host smart-31804e6c-97fb-4433-96c9-eda9e6c25a1d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824444183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.sram_ctrl_access_during_key_req.824444183
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.1660402213
Short name T282
Test name
Test status
Simulation time 12915376 ps
CPU time 0.67 seconds
Started Mar 21 01:28:33 PM PDT 24
Finished Mar 21 01:28:33 PM PDT 24
Peak memory 202120 kb
Host smart-f735c0ee-5e56-4ff9-a44c-49f0c21316ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660402213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.1660402213
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.3912116944
Short name T23
Test name
Test status
Simulation time 115095574638 ps
CPU time 2613.91 seconds
Started Mar 21 01:28:26 PM PDT 24
Finished Mar 21 02:12:00 PM PDT 24
Peak memory 202708 kb
Host smart-633e7a99-1211-4320-b4ae-cc750597e723
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912116944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.3912116944
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.3802436305
Short name T124
Test name
Test status
Simulation time 21096724772 ps
CPU time 1065.61 seconds
Started Mar 21 01:28:31 PM PDT 24
Finished Mar 21 01:46:17 PM PDT 24
Peak memory 377280 kb
Host smart-1268fab0-2368-4b2b-8840-fce7cc4e136b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802436305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.3802436305
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.4120087024
Short name T526
Test name
Test status
Simulation time 6657144194 ps
CPU time 18.06 seconds
Started Mar 21 01:28:32 PM PDT 24
Finished Mar 21 01:28:50 PM PDT 24
Peak memory 202236 kb
Host smart-caccb0b0-f065-4ff8-8cba-60a811cf9491
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120087024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.4120087024
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.1838262447
Short name T930
Test name
Test status
Simulation time 2963344309 ps
CPU time 79.69 seconds
Started Mar 21 01:28:30 PM PDT 24
Finished Mar 21 01:29:50 PM PDT 24
Peak memory 329300 kb
Host smart-feb67421-a8ba-438e-95aa-5693cd1bf634
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838262447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.1838262447
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.430232781
Short name T749
Test name
Test status
Simulation time 3959684242 ps
CPU time 62.84 seconds
Started Mar 21 01:28:32 PM PDT 24
Finished Mar 21 01:29:34 PM PDT 24
Peak memory 210516 kb
Host smart-013d2ffb-691f-4fae-b539-2347eaad8145
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430232781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_mem_partial_access.430232781
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.2099600052
Short name T328
Test name
Test status
Simulation time 39454363894 ps
CPU time 125.31 seconds
Started Mar 21 01:28:39 PM PDT 24
Finished Mar 21 01:30:44 PM PDT 24
Peak memory 202760 kb
Host smart-665cf4db-735e-4db2-a43c-3d7bb499f1c0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099600052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.2099600052
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.2185526839
Short name T541
Test name
Test status
Simulation time 30902873968 ps
CPU time 693.17 seconds
Started Mar 21 01:28:24 PM PDT 24
Finished Mar 21 01:39:57 PM PDT 24
Peak memory 356780 kb
Host smart-cb441a6c-a97b-4cbd-b537-f4fbed1b3681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185526839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.2185526839
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.695130910
Short name T258
Test name
Test status
Simulation time 1738431780 ps
CPU time 9.01 seconds
Started Mar 21 01:28:30 PM PDT 24
Finished Mar 21 01:28:39 PM PDT 24
Peak memory 202276 kb
Host smart-16a4bc50-f6f6-4da9-81e2-380412f1b034
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695130910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.s
ram_ctrl_partial_access.695130910
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2992407352
Short name T180
Test name
Test status
Simulation time 12922985662 ps
CPU time 242.46 seconds
Started Mar 21 01:28:38 PM PDT 24
Finished Mar 21 01:32:41 PM PDT 24
Peak memory 202420 kb
Host smart-a384ab7b-1c6e-4b36-ba1d-92d6995bd9d4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992407352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.2992407352
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.2700020451
Short name T785
Test name
Test status
Simulation time 691844865 ps
CPU time 3.34 seconds
Started Mar 21 01:28:38 PM PDT 24
Finished Mar 21 01:28:41 PM PDT 24
Peak memory 202508 kb
Host smart-2a4c5ea4-a181-43d4-908f-09d9cfed2b4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700020451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2700020451
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.2919871583
Short name T903
Test name
Test status
Simulation time 28610660784 ps
CPU time 520.97 seconds
Started Mar 21 01:28:30 PM PDT 24
Finished Mar 21 01:37:11 PM PDT 24
Peak memory 338440 kb
Host smart-6ebf1b3b-2626-453c-8808-12a5730ea207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919871583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2919871583
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.693073653
Short name T606
Test name
Test status
Simulation time 1842290464 ps
CPU time 15.21 seconds
Started Mar 21 01:28:25 PM PDT 24
Finished Mar 21 01:28:40 PM PDT 24
Peak memory 242036 kb
Host smart-591413ea-be17-4bf8-a5b3-923122e67837
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693073653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.693073653
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.2850063289
Short name T714
Test name
Test status
Simulation time 68686418636 ps
CPU time 6703.03 seconds
Started Mar 21 01:28:29 PM PDT 24
Finished Mar 21 03:20:13 PM PDT 24
Peak memory 387424 kb
Host smart-529ccd90-0879-4736-a563-21cb68d9ba83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850063289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.2850063289
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2668126940
Short name T98
Test name
Test status
Simulation time 1629533938 ps
CPU time 11.23 seconds
Started Mar 21 01:28:39 PM PDT 24
Finished Mar 21 01:28:50 PM PDT 24
Peak memory 210676 kb
Host smart-94ec9f51-6444-4ca0-91e8-670f4c489317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2668126940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.2668126940
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2207119166
Short name T474
Test name
Test status
Simulation time 16108229057 ps
CPU time 324.12 seconds
Started Mar 21 01:28:31 PM PDT 24
Finished Mar 21 01:33:55 PM PDT 24
Peak memory 202408 kb
Host smart-0b6a1d9b-f8c0-4263-a76b-c28a0ab80c5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207119166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.2207119166
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2034196988
Short name T188
Test name
Test status
Simulation time 1505109065 ps
CPU time 152.16 seconds
Started Mar 21 01:28:35 PM PDT 24
Finished Mar 21 01:31:07 PM PDT 24
Peak memory 367964 kb
Host smart-868f7cf8-3834-45d8-9eb7-df63a6ddfde9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034196988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.2034196988
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.2624558270
Short name T914
Test name
Test status
Simulation time 13538187 ps
CPU time 0.67 seconds
Started Mar 21 01:28:43 PM PDT 24
Finished Mar 21 01:28:44 PM PDT 24
Peak memory 201824 kb
Host smart-b21dfe9f-af6b-450b-b976-94b564f86868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624558270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.2624558270
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.3648531969
Short name T783
Test name
Test status
Simulation time 51330617905 ps
CPU time 1159.13 seconds
Started Mar 21 01:28:31 PM PDT 24
Finished Mar 21 01:47:50 PM PDT 24
Peak memory 202404 kb
Host smart-b59523e0-5370-478d-97c4-45fb3b72ec84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648531969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.3648531969
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.1551429947
Short name T228
Test name
Test status
Simulation time 59008866897 ps
CPU time 971.59 seconds
Started Mar 21 01:28:41 PM PDT 24
Finished Mar 21 01:44:53 PM PDT 24
Peak memory 373368 kb
Host smart-1c8b2dc0-104d-4d93-94a4-1acf5c21b4a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551429947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.1551429947
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.511199933
Short name T752
Test name
Test status
Simulation time 61385107337 ps
CPU time 58.4 seconds
Started Mar 21 01:28:41 PM PDT 24
Finished Mar 21 01:29:40 PM PDT 24
Peak memory 214908 kb
Host smart-8f37c430-1106-4cd1-bc2c-5208c51ff4c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511199933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_esc
alation.511199933
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.885192145
Short name T339
Test name
Test status
Simulation time 2929764655 ps
CPU time 15.67 seconds
Started Mar 21 01:28:38 PM PDT 24
Finished Mar 21 01:28:54 PM PDT 24
Peak memory 251504 kb
Host smart-b426a11b-0b45-4eeb-8de5-71342d1544c5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885192145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.sram_ctrl_max_throughput.885192145
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1076641303
Short name T923
Test name
Test status
Simulation time 4091012662 ps
CPU time 67.14 seconds
Started Mar 21 01:28:39 PM PDT 24
Finished Mar 21 01:29:46 PM PDT 24
Peak memory 210532 kb
Host smart-be4cd25d-f983-4097-9ba0-2276b3f92511
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076641303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.1076641303
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.2018220168
Short name T680
Test name
Test status
Simulation time 4160449220 ps
CPU time 254.44 seconds
Started Mar 21 01:28:50 PM PDT 24
Finished Mar 21 01:33:05 PM PDT 24
Peak memory 202508 kb
Host smart-82c51919-a423-46e7-999e-7fd37522f560
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018220168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.2018220168
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.3858295732
Short name T410
Test name
Test status
Simulation time 14521301584 ps
CPU time 862.52 seconds
Started Mar 21 01:28:30 PM PDT 24
Finished Mar 21 01:42:53 PM PDT 24
Peak memory 379288 kb
Host smart-c75a5f03-2d4c-409c-aa1a-d3174d978401
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858295732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.3858295732
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.1013254861
Short name T836
Test name
Test status
Simulation time 2212563219 ps
CPU time 7.78 seconds
Started Mar 21 01:28:30 PM PDT 24
Finished Mar 21 01:28:37 PM PDT 24
Peak memory 202348 kb
Host smart-5fc2e6aa-23ac-4300-9b32-0ef180843958
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013254861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.1013254861
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1249643027
Short name T364
Test name
Test status
Simulation time 7102387748 ps
CPU time 408.07 seconds
Started Mar 21 01:28:33 PM PDT 24
Finished Mar 21 01:35:21 PM PDT 24
Peak memory 202380 kb
Host smart-f299d846-f1aa-46cb-93e5-5fb90b8760ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249643027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.1249643027
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.1674803974
Short name T787
Test name
Test status
Simulation time 874373828 ps
CPU time 3.08 seconds
Started Mar 21 01:28:51 PM PDT 24
Finished Mar 21 01:28:54 PM PDT 24
Peak memory 202512 kb
Host smart-da80b3e3-c29a-42eb-be40-012cb1a60754
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674803974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1674803974
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.2757964461
Short name T438
Test name
Test status
Simulation time 28828686835 ps
CPU time 919.91 seconds
Started Mar 21 01:28:40 PM PDT 24
Finished Mar 21 01:44:00 PM PDT 24
Peak memory 372052 kb
Host smart-ab2effb6-65e4-404e-a87d-38c080af52bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757964461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2757964461
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.1154934579
Short name T105
Test name
Test status
Simulation time 543282057 ps
CPU time 17.11 seconds
Started Mar 21 01:28:31 PM PDT 24
Finished Mar 21 01:28:48 PM PDT 24
Peak memory 202412 kb
Host smart-158c5df5-65d9-4276-8e19-d1e5579f172a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154934579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1154934579
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.3724427383
Short name T482
Test name
Test status
Simulation time 131265880999 ps
CPU time 6627.9 seconds
Started Mar 21 01:28:43 PM PDT 24
Finished Mar 21 03:19:12 PM PDT 24
Peak memory 385412 kb
Host smart-68b063f6-7168-4714-9e38-d5dca4782caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724427383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.3724427383
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.353004701
Short name T44
Test name
Test status
Simulation time 3476724278 ps
CPU time 63.54 seconds
Started Mar 21 01:28:50 PM PDT 24
Finished Mar 21 01:29:54 PM PDT 24
Peak memory 269116 kb
Host smart-7e2c4743-a766-462c-ab2a-46045c74c994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=353004701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.353004701
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.702002431
Short name T342
Test name
Test status
Simulation time 22926917789 ps
CPU time 265.61 seconds
Started Mar 21 01:28:32 PM PDT 24
Finished Mar 21 01:32:58 PM PDT 24
Peak memory 202324 kb
Host smart-d800deac-ad08-4cd7-bcd3-551a589d1f0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702002431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_stress_pipeline.702002431
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.877514078
Short name T837
Test name
Test status
Simulation time 713770354 ps
CPU time 9.64 seconds
Started Mar 21 01:28:40 PM PDT 24
Finished Mar 21 01:28:50 PM PDT 24
Peak memory 227904 kb
Host smart-44f7258e-58a1-4fb3-9b7e-0b7400e922f8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877514078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_throughput_w_partial_write.877514078
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1319956764
Short name T229
Test name
Test status
Simulation time 15081463057 ps
CPU time 1260.49 seconds
Started Mar 21 01:28:51 PM PDT 24
Finished Mar 21 01:49:51 PM PDT 24
Peak memory 377300 kb
Host smart-79c3fec9-cfa9-4185-bc66-ffb58f40ccbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319956764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.1319956764
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.1345246030
Short name T323
Test name
Test status
Simulation time 17065507 ps
CPU time 0.65 seconds
Started Mar 21 01:28:47 PM PDT 24
Finished Mar 21 01:28:48 PM PDT 24
Peak memory 202092 kb
Host smart-2768b5e5-fe79-4be2-b9b5-c12517235b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345246030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.1345246030
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.3993481698
Short name T235
Test name
Test status
Simulation time 230717735106 ps
CPU time 1186.11 seconds
Started Mar 21 01:28:51 PM PDT 24
Finished Mar 21 01:48:37 PM PDT 24
Peak memory 202404 kb
Host smart-e34dde03-ad92-4fbd-ac24-8246c22f7af8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993481698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.3993481698
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.1161587797
Short name T928
Test name
Test status
Simulation time 18374737903 ps
CPU time 1143.56 seconds
Started Mar 21 01:28:39 PM PDT 24
Finished Mar 21 01:47:43 PM PDT 24
Peak memory 378368 kb
Host smart-f559b599-ed2d-4b64-bab9-88d4f34d2b51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161587797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.1161587797
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.3787807985
Short name T927
Test name
Test status
Simulation time 6185746184 ps
CPU time 38.3 seconds
Started Mar 21 01:28:41 PM PDT 24
Finished Mar 21 01:29:20 PM PDT 24
Peak memory 202404 kb
Host smart-0c62d4b9-bfdb-4c05-83b4-cdc795d0108b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787807985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.3787807985
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.3123362839
Short name T333
Test name
Test status
Simulation time 2694412559 ps
CPU time 6.91 seconds
Started Mar 21 01:28:41 PM PDT 24
Finished Mar 21 01:28:48 PM PDT 24
Peak memory 210648 kb
Host smart-1ff0a4c1-af59-46b6-aea7-949939896dbb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123362839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.3123362839
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1076301954
Short name T267
Test name
Test status
Simulation time 4445983284 ps
CPU time 151.63 seconds
Started Mar 21 01:28:48 PM PDT 24
Finished Mar 21 01:31:20 PM PDT 24
Peak memory 210476 kb
Host smart-34b13f0a-5d67-49bc-9a09-95fe433b30e0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076301954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.1076301954
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.206978854
Short name T590
Test name
Test status
Simulation time 43004399522 ps
CPU time 303.09 seconds
Started Mar 21 01:28:49 PM PDT 24
Finished Mar 21 01:33:52 PM PDT 24
Peak memory 202892 kb
Host smart-1fec2297-81de-43e5-8f1f-b1081f8ef4e1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206978854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl
_mem_walk.206978854
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.782392770
Short name T366
Test name
Test status
Simulation time 6310043530 ps
CPU time 869.21 seconds
Started Mar 21 01:28:39 PM PDT 24
Finished Mar 21 01:43:08 PM PDT 24
Peak memory 374180 kb
Host smart-06813198-1e0c-41aa-9ac6-f19c8083ec27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782392770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip
le_keys.782392770
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.376768349
Short name T653
Test name
Test status
Simulation time 4797476946 ps
CPU time 31.77 seconds
Started Mar 21 01:28:40 PM PDT 24
Finished Mar 21 01:29:12 PM PDT 24
Peak memory 276640 kb
Host smart-74ed37e1-15ce-4d2e-95c6-9bfb3b5f8bb0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376768349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s
ram_ctrl_partial_access.376768349
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2861131815
Short name T634
Test name
Test status
Simulation time 7078435689 ps
CPU time 346.08 seconds
Started Mar 21 01:28:39 PM PDT 24
Finished Mar 21 01:34:25 PM PDT 24
Peak memory 202392 kb
Host smart-bead8b66-dc20-4c52-99bc-222cf0da8356
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861131815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.2861131815
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.3972870156
Short name T300
Test name
Test status
Simulation time 542785920 ps
CPU time 3.25 seconds
Started Mar 21 01:28:46 PM PDT 24
Finished Mar 21 01:28:49 PM PDT 24
Peak memory 202428 kb
Host smart-4e76698c-145d-4617-ad38-f5bae000b381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972870156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3972870156
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.3949085157
Short name T491
Test name
Test status
Simulation time 13001785969 ps
CPU time 390.1 seconds
Started Mar 21 01:28:47 PM PDT 24
Finished Mar 21 01:35:18 PM PDT 24
Peak memory 295528 kb
Host smart-a252b37a-5ec5-4cf6-8c05-687f1cd6ced1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949085157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3949085157
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.466591674
Short name T249
Test name
Test status
Simulation time 1381000210 ps
CPU time 142.84 seconds
Started Mar 21 01:28:41 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 358772 kb
Host smart-e41e4a48-048f-46ad-8006-4a7db2d8a6a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466591674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.466591674
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.1831510286
Short name T126
Test name
Test status
Simulation time 1169505688637 ps
CPU time 10529.1 seconds
Started Mar 21 01:28:51 PM PDT 24
Finished Mar 21 04:24:21 PM PDT 24
Peak memory 382312 kb
Host smart-c6124d8d-08ab-4213-a77e-a7fac0f251e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831510286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.1831510286
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1571601073
Short name T576
Test name
Test status
Simulation time 11925006327 ps
CPU time 215.32 seconds
Started Mar 21 01:28:49 PM PDT 24
Finished Mar 21 01:32:25 PM PDT 24
Peak memory 377260 kb
Host smart-22a4b510-6038-4c59-9f3a-162d396ad1fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1571601073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1571601073
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.557264449
Short name T558
Test name
Test status
Simulation time 7455908936 ps
CPU time 213.12 seconds
Started Mar 21 01:28:40 PM PDT 24
Finished Mar 21 01:32:13 PM PDT 24
Peak memory 202380 kb
Host smart-27537fd3-8295-4955-a027-dee7abc7ec8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557264449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.sram_ctrl_stress_pipeline.557264449
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1464807156
Short name T830
Test name
Test status
Simulation time 734883197 ps
CPU time 43.93 seconds
Started Mar 21 01:28:38 PM PDT 24
Finished Mar 21 01:29:22 PM PDT 24
Peak memory 290644 kb
Host smart-270e25a9-4fcd-423c-b72b-da9ac3b6d462
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464807156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1464807156
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3920276678
Short name T682
Test name
Test status
Simulation time 25077145129 ps
CPU time 740.39 seconds
Started Mar 21 01:28:46 PM PDT 24
Finished Mar 21 01:41:07 PM PDT 24
Peak memory 349572 kb
Host smart-1ff68982-87bf-405b-b011-cc1912e2c920
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920276678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.3920276678
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.335878968
Short name T913
Test name
Test status
Simulation time 14890800 ps
CPU time 0.67 seconds
Started Mar 21 01:28:56 PM PDT 24
Finished Mar 21 01:28:57 PM PDT 24
Peak memory 202032 kb
Host smart-5c527ff2-991f-4eed-b446-262a5d024c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335878968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.335878968
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.2579711913
Short name T573
Test name
Test status
Simulation time 110887254301 ps
CPU time 1301.32 seconds
Started Mar 21 01:28:46 PM PDT 24
Finished Mar 21 01:50:27 PM PDT 24
Peak memory 202704 kb
Host smart-03786c27-6301-401b-a73d-372f10f2ec89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579711913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.2579711913
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.3615333300
Short name T368
Test name
Test status
Simulation time 47672515233 ps
CPU time 736.05 seconds
Started Mar 21 01:28:50 PM PDT 24
Finished Mar 21 01:41:06 PM PDT 24
Peak memory 372236 kb
Host smart-3c114783-16db-4300-9cad-f73420e34813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615333300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab
le.3615333300
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.702845315
Short name T382
Test name
Test status
Simulation time 26457810395 ps
CPU time 51.95 seconds
Started Mar 21 01:28:49 PM PDT 24
Finished Mar 21 01:29:41 PM PDT 24
Peak memory 214872 kb
Host smart-c4d3ad5a-d01c-4a88-873c-c9d0adf14f1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702845315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_esc
alation.702845315
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.4216822405
Short name T544
Test name
Test status
Simulation time 715473664 ps
CPU time 8.75 seconds
Started Mar 21 01:28:47 PM PDT 24
Finished Mar 21 01:28:56 PM PDT 24
Peak memory 220632 kb
Host smart-8b69c851-3eeb-4cd3-b340-2fff7e426b5d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216822405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.4216822405
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.455615598
Short name T454
Test name
Test status
Simulation time 4822308514 ps
CPU time 77.75 seconds
Started Mar 21 01:28:57 PM PDT 24
Finished Mar 21 01:30:15 PM PDT 24
Peak memory 210528 kb
Host smart-c4a8e655-ed2c-45ef-9db4-89ed3d64cdb0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455615598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_mem_partial_access.455615598
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.1098770365
Short name T509
Test name
Test status
Simulation time 82542491863 ps
CPU time 312.63 seconds
Started Mar 21 01:28:55 PM PDT 24
Finished Mar 21 01:34:08 PM PDT 24
Peak memory 202804 kb
Host smart-1c305ce4-8e0f-4dec-85cb-09b36bede710
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098770365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.1098770365
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.2683694146
Short name T794
Test name
Test status
Simulation time 17613996310 ps
CPU time 1266.31 seconds
Started Mar 21 01:28:48 PM PDT 24
Finished Mar 21 01:49:55 PM PDT 24
Peak memory 373224 kb
Host smart-c5ddc37a-6ead-4df6-88fd-2e5e59e9427d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683694146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.2683694146
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.1170699965
Short name T791
Test name
Test status
Simulation time 6535471194 ps
CPU time 23.01 seconds
Started Mar 21 01:28:48 PM PDT 24
Finished Mar 21 01:29:12 PM PDT 24
Peak memory 202356 kb
Host smart-851dd21e-8713-4b5e-8bdd-973a2df07726
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170699965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.1170699965
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.20930220
Short name T176
Test name
Test status
Simulation time 12635070085 ps
CPU time 287.33 seconds
Started Mar 21 01:28:48 PM PDT 24
Finished Mar 21 01:33:35 PM PDT 24
Peak memory 202356 kb
Host smart-84333757-ad1d-4794-96b1-cd2b355bff08
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20930220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_partial_access_b2b.20930220
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.1635562140
Short name T30
Test name
Test status
Simulation time 360585035 ps
CPU time 2.96 seconds
Started Mar 21 01:28:58 PM PDT 24
Finished Mar 21 01:29:01 PM PDT 24
Peak memory 202432 kb
Host smart-6348de11-1533-4ea8-af8f-1634809b57ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635562140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1635562140
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.2517352760
Short name T50
Test name
Test status
Simulation time 23440734729 ps
CPU time 1480.22 seconds
Started Mar 21 01:28:57 PM PDT 24
Finished Mar 21 01:53:37 PM PDT 24
Peak memory 374176 kb
Host smart-87ecf4b3-0b79-4fee-bc17-cc42b7ccde0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517352760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2517352760
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.3234149156
Short name T681
Test name
Test status
Simulation time 3577108837 ps
CPU time 15.19 seconds
Started Mar 21 01:28:47 PM PDT 24
Finished Mar 21 01:29:02 PM PDT 24
Peak memory 251900 kb
Host smart-9cffef36-193a-463b-a249-4369cddfa607
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234149156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3234149156
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.4023730171
Short name T799
Test name
Test status
Simulation time 536915207090 ps
CPU time 2425.77 seconds
Started Mar 21 01:28:57 PM PDT 24
Finished Mar 21 02:09:23 PM PDT 24
Peak memory 210588 kb
Host smart-ffcde6a5-3ace-467a-9011-cb601930d7ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023730171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.4023730171
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3149690585
Short name T849
Test name
Test status
Simulation time 2436814475 ps
CPU time 68.53 seconds
Started Mar 21 01:28:56 PM PDT 24
Finished Mar 21 01:30:05 PM PDT 24
Peak memory 264772 kb
Host smart-f994c4bc-cb97-446f-a756-bd45711161e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3149690585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3149690585
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.288967949
Short name T583
Test name
Test status
Simulation time 17886706898 ps
CPU time 274.8 seconds
Started Mar 21 01:28:49 PM PDT 24
Finished Mar 21 01:33:24 PM PDT 24
Peak memory 202360 kb
Host smart-a67bf4da-d659-4886-8b05-72414445df46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288967949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_stress_pipeline.288967949
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.388640080
Short name T664
Test name
Test status
Simulation time 1329811475 ps
CPU time 7.03 seconds
Started Mar 21 01:28:50 PM PDT 24
Finished Mar 21 01:28:58 PM PDT 24
Peak memory 211608 kb
Host smart-4776b16f-6a9e-48bb-9149-a2892b95457a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388640080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.388640080
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.475856647
Short name T519
Test name
Test status
Simulation time 32373255399 ps
CPU time 1459.41 seconds
Started Mar 21 01:28:56 PM PDT 24
Finished Mar 21 01:53:16 PM PDT 24
Peak memory 370052 kb
Host smart-b6e8086e-610b-4a3b-ba7f-ba22d9402554
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475856647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 49.sram_ctrl_access_during_key_req.475856647
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.935349496
Short name T635
Test name
Test status
Simulation time 39365933 ps
CPU time 0.66 seconds
Started Mar 21 01:29:04 PM PDT 24
Finished Mar 21 01:29:05 PM PDT 24
Peak memory 201908 kb
Host smart-675923d3-007b-4911-8a0f-ef9cf0e3538f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935349496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.935349496
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.2657249189
Short name T160
Test name
Test status
Simulation time 528620802947 ps
CPU time 2651.44 seconds
Started Mar 21 01:28:55 PM PDT 24
Finished Mar 21 02:13:07 PM PDT 24
Peak memory 202796 kb
Host smart-7e7f57fc-0cc8-4c93-939a-3866363b79fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657249189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.2657249189
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.1463958584
Short name T504
Test name
Test status
Simulation time 10650533427 ps
CPU time 60 seconds
Started Mar 21 01:28:56 PM PDT 24
Finished Mar 21 01:29:56 PM PDT 24
Peak memory 202388 kb
Host smart-35b8ddb7-519d-47ec-b095-c6fc00462ced
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463958584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.1463958584
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.80160221
Short name T390
Test name
Test status
Simulation time 842487974 ps
CPU time 82.39 seconds
Started Mar 21 01:28:56 PM PDT 24
Finished Mar 21 01:30:19 PM PDT 24
Peak memory 326096 kb
Host smart-6d38845f-72f8-4a88-9bd1-3b60d71c4795
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80160221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.sram_ctrl_max_throughput.80160221
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3842666586
Short name T671
Test name
Test status
Simulation time 1946449322 ps
CPU time 63.34 seconds
Started Mar 21 01:29:06 PM PDT 24
Finished Mar 21 01:30:10 PM PDT 24
Peak memory 210548 kb
Host smart-2b08f57e-7d6e-49d2-9b8c-8aa7a3b0b935
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842666586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.3842666586
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.41377034
Short name T245
Test name
Test status
Simulation time 4114098230 ps
CPU time 123.18 seconds
Started Mar 21 01:29:03 PM PDT 24
Finished Mar 21 01:31:07 PM PDT 24
Peak memory 202392 kb
Host smart-ada62381-ec15-4309-a2e3-dab0e29fb66d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41377034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_
mem_walk.41377034
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.2034827750
Short name T324
Test name
Test status
Simulation time 32727197003 ps
CPU time 1951.5 seconds
Started Mar 21 01:28:56 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 378288 kb
Host smart-51bd85c1-de71-47ab-acc1-6ce2b7c765c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034827750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.2034827750
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.191210493
Short name T876
Test name
Test status
Simulation time 1802700522 ps
CPU time 200.58 seconds
Started Mar 21 01:28:56 PM PDT 24
Finished Mar 21 01:32:17 PM PDT 24
Peak memory 369180 kb
Host smart-61829650-9793-4bdd-a71b-937d39c08fb5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191210493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.s
ram_ctrl_partial_access.191210493
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1335248289
Short name T677
Test name
Test status
Simulation time 5774185908 ps
CPU time 286.43 seconds
Started Mar 21 01:28:54 PM PDT 24
Finished Mar 21 01:33:41 PM PDT 24
Peak memory 202404 kb
Host smart-b86a46a9-a7c7-4ceb-81bf-d6bb8210b5a9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335248289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.1335248289
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.1386116182
Short name T178
Test name
Test status
Simulation time 360432962 ps
CPU time 3.43 seconds
Started Mar 21 01:29:02 PM PDT 24
Finished Mar 21 01:29:06 PM PDT 24
Peak memory 202420 kb
Host smart-20bd9045-b6ab-48d7-a33d-d0efb10e8e0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386116182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1386116182
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.3901231531
Short name T279
Test name
Test status
Simulation time 16580049436 ps
CPU time 896.63 seconds
Started Mar 21 01:29:04 PM PDT 24
Finished Mar 21 01:44:01 PM PDT 24
Peak memory 375228 kb
Host smart-ac785de8-fe16-431d-8f29-0c751d295d1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901231531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3901231531
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.2785431956
Short name T467
Test name
Test status
Simulation time 3611681773 ps
CPU time 121.22 seconds
Started Mar 21 01:28:58 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 351620 kb
Host smart-22b3cc15-66a9-49b9-8c25-185acf240ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785431956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2785431956
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.168384797
Short name T660
Test name
Test status
Simulation time 96118076650 ps
CPU time 3673.31 seconds
Started Mar 21 01:29:03 PM PDT 24
Finished Mar 21 02:30:18 PM PDT 24
Peak memory 381212 kb
Host smart-b7ffc5ed-6748-4f21-9d8a-6b0d6f373880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168384797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_stress_all.168384797
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1272183945
Short name T858
Test name
Test status
Simulation time 7771442259 ps
CPU time 57.78 seconds
Started Mar 21 01:29:04 PM PDT 24
Finished Mar 21 01:30:02 PM PDT 24
Peak memory 210688 kb
Host smart-ff4b2ad8-2f56-4883-96b3-87c134e05b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1272183945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1272183945
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.827656600
Short name T644
Test name
Test status
Simulation time 71564345515 ps
CPU time 382.43 seconds
Started Mar 21 01:28:56 PM PDT 24
Finished Mar 21 01:35:18 PM PDT 24
Peak memory 202412 kb
Host smart-d4a833d5-9120-452d-88fa-c9cbfd37ac45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827656600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_stress_pipeline.827656600
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1490994872
Short name T839
Test name
Test status
Simulation time 1508445460 ps
CPU time 67.66 seconds
Started Mar 21 01:28:56 PM PDT 24
Finished Mar 21 01:30:04 PM PDT 24
Peak memory 319860 kb
Host smart-b30d5b59-aa37-461e-af44-9a7062c9607d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490994872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1490994872
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2471138337
Short name T316
Test name
Test status
Simulation time 17243940841 ps
CPU time 753.99 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:38:07 PM PDT 24
Peak memory 365024 kb
Host smart-fe8c221d-dde3-4f0a-b1bc-db2131ee04b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471138337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.2471138337
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.151343690
Short name T331
Test name
Test status
Simulation time 45493409 ps
CPU time 0.64 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:25:33 PM PDT 24
Peak memory 201924 kb
Host smart-2d332778-f271-40ae-9cea-c6742f397984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151343690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.151343690
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.454413966
Short name T896
Test name
Test status
Simulation time 121576553003 ps
CPU time 2056.4 seconds
Started Mar 21 01:25:30 PM PDT 24
Finished Mar 21 01:59:47 PM PDT 24
Peak memory 202548 kb
Host smart-3cbd329b-d7b6-4e9c-92b0-1bf20836542b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454413966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.454413966
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.1388990436
Short name T170
Test name
Test status
Simulation time 9292167018 ps
CPU time 476.41 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:33:21 PM PDT 24
Peak memory 374468 kb
Host smart-96a5b3ac-62f1-4e7a-a46a-8b23b6f68294
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388990436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.1388990436
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.354225924
Short name T800
Test name
Test status
Simulation time 9255415451 ps
CPU time 15.87 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:25:40 PM PDT 24
Peak memory 202388 kb
Host smart-b1b23919-ca7a-4605-8ef6-1814ee70ea98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354225924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esca
lation.354225924
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.747649512
Short name T174
Test name
Test status
Simulation time 3147231201 ps
CPU time 118.71 seconds
Started Mar 21 01:25:27 PM PDT 24
Finished Mar 21 01:27:26 PM PDT 24
Peak memory 360932 kb
Host smart-3f96afdd-2ae6-4c8e-b9f8-bdcb39406570
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747649512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.sram_ctrl_max_throughput.747649512
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2932393583
Short name T580
Test name
Test status
Simulation time 10235293498 ps
CPU time 81.97 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:26:59 PM PDT 24
Peak memory 210636 kb
Host smart-875b4ec3-0382-4f32-a9fe-d04609bb84b5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932393583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.2932393583
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.2755098132
Short name T581
Test name
Test status
Simulation time 4205360050 ps
CPU time 126.67 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:27:41 PM PDT 24
Peak memory 202476 kb
Host smart-267c4e2f-3305-4db4-a46c-08750a42e652
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755098132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.2755098132
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.1552717648
Short name T275
Test name
Test status
Simulation time 1744196596 ps
CPU time 50.45 seconds
Started Mar 21 01:25:29 PM PDT 24
Finished Mar 21 01:26:20 PM PDT 24
Peak memory 296364 kb
Host smart-c28391f6-3351-4cc3-8d0e-c1a1ce7bd3be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552717648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.1552717648
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.1717484265
Short name T355
Test name
Test status
Simulation time 1685257809 ps
CPU time 4.62 seconds
Started Mar 21 01:25:29 PM PDT 24
Finished Mar 21 01:25:33 PM PDT 24
Peak memory 202296 kb
Host smart-77a26c91-3fe3-4bbb-b483-2f97e24cc782
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717484265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.1717484265
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2799503310
Short name T670
Test name
Test status
Simulation time 89479078358 ps
CPU time 507.95 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:33:53 PM PDT 24
Peak memory 202416 kb
Host smart-9461e571-1df1-4ff5-ad93-6b66535c2ed1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799503310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.2799503310
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.3301720337
Short name T843
Test name
Test status
Simulation time 350219249 ps
CPU time 3.23 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:25:28 PM PDT 24
Peak memory 202404 kb
Host smart-b3ace319-3531-43c9-81a8-cf94d9b0d02a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301720337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3301720337
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.3980799622
Short name T658
Test name
Test status
Simulation time 29114284475 ps
CPU time 175.64 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:28:29 PM PDT 24
Peak memory 339380 kb
Host smart-8484599f-7720-4ff1-a06f-6e7c265c93d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980799622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3980799622
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.115677769
Short name T408
Test name
Test status
Simulation time 1384260385 ps
CPU time 3.33 seconds
Started Mar 21 01:25:38 PM PDT 24
Finished Mar 21 01:25:43 PM PDT 24
Peak memory 202512 kb
Host smart-e2339164-0e63-40fb-b76b-1c229bf1c47e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115677769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.115677769
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1089699726
Short name T104
Test name
Test status
Simulation time 820380138 ps
CPU time 7.38 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:25:30 PM PDT 24
Peak memory 210700 kb
Host smart-28fd0e48-513e-48e4-bd56-78a098d517b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1089699726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1089699726
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.338408840
Short name T898
Test name
Test status
Simulation time 5553379453 ps
CPU time 258.6 seconds
Started Mar 21 01:25:30 PM PDT 24
Finished Mar 21 01:29:48 PM PDT 24
Peak memory 202472 kb
Host smart-b5239711-ff0c-41f3-aab1-0d1a3530b88f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338408840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
sram_ctrl_stress_pipeline.338408840
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.976353416
Short name T737
Test name
Test status
Simulation time 774016213 ps
CPU time 120.69 seconds
Started Mar 21 01:25:49 PM PDT 24
Finished Mar 21 01:27:50 PM PDT 24
Peak memory 356652 kb
Host smart-c897c297-70bf-40cf-820c-80f4640ba795
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976353416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.976353416
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2098429879
Short name T625
Test name
Test status
Simulation time 7371459102 ps
CPU time 609.13 seconds
Started Mar 21 01:25:47 PM PDT 24
Finished Mar 21 01:35:57 PM PDT 24
Peak memory 373264 kb
Host smart-bfbf66a9-ccb5-4233-8526-c32bc5f9a9f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098429879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.2098429879
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.374906215
Short name T719
Test name
Test status
Simulation time 14620385 ps
CPU time 0.64 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:25:37 PM PDT 24
Peak memory 201876 kb
Host smart-a603d13f-416a-4ba3-9b2e-4c419779c83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374906215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.374906215
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.2320110538
Short name T415
Test name
Test status
Simulation time 230164033814 ps
CPU time 2657.07 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 02:09:42 PM PDT 24
Peak memory 202788 kb
Host smart-dfe67e4a-80aa-46dd-965d-d937bdb7e750
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320110538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
2320110538
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.4125175426
Short name T39
Test name
Test status
Simulation time 38498135996 ps
CPU time 1474.6 seconds
Started Mar 21 01:26:06 PM PDT 24
Finished Mar 21 01:50:41 PM PDT 24
Peak memory 371032 kb
Host smart-b89a5f25-5af7-47d0-9fef-759483bf2b18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125175426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.4125175426
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.3023178378
Short name T135
Test name
Test status
Simulation time 5465123970 ps
CPU time 28.73 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:26:05 PM PDT 24
Peak memory 202368 kb
Host smart-ca640479-ad30-47db-a0e6-d555b81605b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023178378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.3023178378
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.1171371785
Short name T181
Test name
Test status
Simulation time 714547661 ps
CPU time 15.21 seconds
Started Mar 21 01:25:31 PM PDT 24
Finished Mar 21 01:25:46 PM PDT 24
Peak memory 251460 kb
Host smart-aae08844-0c06-419c-8d1d-12cefb99bda7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171371785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.1171371785
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3384684704
Short name T904
Test name
Test status
Simulation time 4957658419 ps
CPU time 74.91 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:26:42 PM PDT 24
Peak memory 210516 kb
Host smart-f027ac8b-aff4-4df5-9b24-f8b218696d65
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384684704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.3384684704
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.1337744229
Short name T131
Test name
Test status
Simulation time 27498255911 ps
CPU time 286.37 seconds
Started Mar 21 01:25:55 PM PDT 24
Finished Mar 21 01:30:41 PM PDT 24
Peak memory 202352 kb
Host smart-773782ab-adca-401f-bf6f-1fbf70c85e2d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337744229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.1337744229
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.1567137647
Short name T456
Test name
Test status
Simulation time 23146953609 ps
CPU time 762.7 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:38:16 PM PDT 24
Peak memory 377228 kb
Host smart-42639a25-f790-408e-bc53-cd11dcef5f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567137647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.1567137647
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.509709031
Short name T437
Test name
Test status
Simulation time 1649854540 ps
CPU time 101.5 seconds
Started Mar 21 01:25:38 PM PDT 24
Finished Mar 21 01:27:21 PM PDT 24
Peak memory 349528 kb
Host smart-2616c33c-18c7-4579-a1ce-12f19e61403b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509709031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr
am_ctrl_partial_access.509709031
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.845377575
Short name T121
Test name
Test status
Simulation time 97163279093 ps
CPU time 363.95 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:31:28 PM PDT 24
Peak memory 202364 kb
Host smart-a323087a-649e-4bdd-9fb0-636f8d3d1a5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845377575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.sram_ctrl_partial_access_b2b.845377575
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.1539799856
Short name T713
Test name
Test status
Simulation time 1407675689 ps
CPU time 3.23 seconds
Started Mar 21 01:25:31 PM PDT 24
Finished Mar 21 01:25:34 PM PDT 24
Peak memory 202476 kb
Host smart-15a99bb3-abb9-4b10-8e7b-5fd25548a5ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539799856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1539799856
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.36609242
Short name T690
Test name
Test status
Simulation time 17498788468 ps
CPU time 2226.31 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 02:02:41 PM PDT 24
Peak memory 380236 kb
Host smart-2d110bd2-103c-4322-b1d1-1655b72417e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36609242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.36609242
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.1825035506
Short name T543
Test name
Test status
Simulation time 3964531774 ps
CPU time 105.26 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:27:12 PM PDT 24
Peak memory 355700 kb
Host smart-8f4a3cf9-526f-42e2-a59f-1bb82401cc9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825035506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1825035506
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.1334722114
Short name T938
Test name
Test status
Simulation time 541999486207 ps
CPU time 7960.86 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 03:38:16 PM PDT 24
Peak memory 380404 kb
Host smart-1e1ed78c-c61e-4c8e-b353-6c7c780832e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334722114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.1334722114
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1386295718
Short name T289
Test name
Test status
Simulation time 767380618 ps
CPU time 20.6 seconds
Started Mar 21 01:25:52 PM PDT 24
Finished Mar 21 01:26:13 PM PDT 24
Peak memory 216660 kb
Host smart-7f7f0df5-386a-4338-8f1e-306f27f10980
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1386295718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1386295718
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3273513473
Short name T367
Test name
Test status
Simulation time 12879146927 ps
CPU time 162.92 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:28:15 PM PDT 24
Peak memory 202356 kb
Host smart-9bde75d1-012c-4129-a8e9-3b3749a2e78b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273513473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.3273513473
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2831274087
Short name T292
Test name
Test status
Simulation time 2066241003 ps
CPU time 141.44 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 01:27:57 PM PDT 24
Peak memory 365880 kb
Host smart-3ff54cf7-ac79-4c90-9a52-ea9997ee87ee
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831274087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.2831274087
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.593480585
Short name T701
Test name
Test status
Simulation time 7492401571 ps
CPU time 375.07 seconds
Started Mar 21 01:25:42 PM PDT 24
Finished Mar 21 01:31:58 PM PDT 24
Peak memory 361556 kb
Host smart-d683a8ea-2fab-4ba6-a95e-1c7a9fe59396
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593480585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_access_during_key_req.593480585
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.1463319750
Short name T17
Test name
Test status
Simulation time 15540551 ps
CPU time 0.68 seconds
Started Mar 21 01:25:58 PM PDT 24
Finished Mar 21 01:25:59 PM PDT 24
Peak memory 202060 kb
Host smart-8ba2cfb0-5d6e-49c6-b231-4de6a21258b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463319750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.1463319750
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.2436019853
Short name T649
Test name
Test status
Simulation time 14760678321 ps
CPU time 1033.03 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:42:46 PM PDT 24
Peak memory 202444 kb
Host smart-2f75a389-6f4f-4095-aa81-bba54f2dc39c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436019853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
2436019853
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.613479494
Short name T594
Test name
Test status
Simulation time 56533614680 ps
CPU time 959.36 seconds
Started Mar 21 01:25:31 PM PDT 24
Finished Mar 21 01:41:30 PM PDT 24
Peak memory 378360 kb
Host smart-ffa34df4-b252-4cae-b4c8-8edcc21da808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613479494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable
.613479494
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.2189279748
Short name T560
Test name
Test status
Simulation time 25019794798 ps
CPU time 67.89 seconds
Started Mar 21 01:25:29 PM PDT 24
Finished Mar 21 01:26:37 PM PDT 24
Peak memory 202464 kb
Host smart-35d02f72-de5b-48be-b100-bb2cd4b7e111
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189279748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.2189279748
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.227951998
Short name T710
Test name
Test status
Simulation time 763813345 ps
CPU time 93.83 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 01:27:34 PM PDT 24
Peak memory 336312 kb
Host smart-0743ae68-ef31-420b-b2c0-0a83c1546573
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227951998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.sram_ctrl_max_throughput.227951998
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.540617216
Short name T195
Test name
Test status
Simulation time 1946947058 ps
CPU time 60.09 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:26:34 PM PDT 24
Peak memory 210564 kb
Host smart-9eb75699-7dc1-4ef2-a110-124f4b85a646
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540617216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
sram_ctrl_mem_partial_access.540617216
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.2502265992
Short name T552
Test name
Test status
Simulation time 3948653427 ps
CPU time 133.41 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:27:38 PM PDT 24
Peak memory 202728 kb
Host smart-ff6d9326-d853-4b51-abea-5c7f769bb8f4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502265992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.2502265992
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.245914610
Short name T596
Test name
Test status
Simulation time 5213166505 ps
CPU time 400.92 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:32:15 PM PDT 24
Peak memory 378280 kb
Host smart-498041e3-1244-41cc-b688-fe1034c43e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245914610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multipl
e_keys.245914610
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.3589392506
Short name T189
Test name
Test status
Simulation time 3065263101 ps
CPU time 24.62 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:25:58 PM PDT 24
Peak memory 262696 kb
Host smart-00cc2b58-9257-4f3f-af6b-7b597abeeab7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589392506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.3589392506
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.736984727
Short name T557
Test name
Test status
Simulation time 6012310799 ps
CPU time 371.21 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 01:31:46 PM PDT 24
Peak memory 202408 kb
Host smart-6caf9d41-7925-4371-9190-ebc371733607
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736984727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.sram_ctrl_partial_access_b2b.736984727
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3708800868
Short name T607
Test name
Test status
Simulation time 377132813 ps
CPU time 2.97 seconds
Started Mar 21 01:25:26 PM PDT 24
Finished Mar 21 01:25:29 PM PDT 24
Peak memory 202496 kb
Host smart-0e5293b5-c03d-445a-a80e-336f961dc02f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708800868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3708800868
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.2234461437
Short name T164
Test name
Test status
Simulation time 13968048830 ps
CPU time 198.86 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:28:42 PM PDT 24
Peak memory 369108 kb
Host smart-8c1dc2ab-750d-4e60-b43e-7708f88638cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234461437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2234461437
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.4267975850
Short name T725
Test name
Test status
Simulation time 619207748 ps
CPU time 7.69 seconds
Started Mar 21 01:25:28 PM PDT 24
Finished Mar 21 01:25:36 PM PDT 24
Peak memory 202364 kb
Host smart-a4687b7a-22f3-4441-b075-19097b5e8163
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267975850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.4267975850
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.1924715604
Short name T329
Test name
Test status
Simulation time 60639360760 ps
CPU time 2637.93 seconds
Started Mar 21 01:25:37 PM PDT 24
Finished Mar 21 02:09:35 PM PDT 24
Peak memory 381232 kb
Host smart-c244bf6a-9260-4367-940f-67174b7caf4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924715604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.1924715604
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2917386812
Short name T280
Test name
Test status
Simulation time 313430097 ps
CPU time 5.66 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:25:38 PM PDT 24
Peak memory 210696 kb
Host smart-fde6e2f5-2f78-4442-ae88-8a2915977f1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2917386812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2917386812
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1172458912
Short name T369
Test name
Test status
Simulation time 4781058192 ps
CPU time 244.26 seconds
Started Mar 21 01:25:30 PM PDT 24
Finished Mar 21 01:29:34 PM PDT 24
Peak memory 202416 kb
Host smart-4acaf7d5-0d88-4e2b-b903-3bde915ecaf9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172458912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.1172458912
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.63791875
Short name T185
Test name
Test status
Simulation time 774360161 ps
CPU time 102.27 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 01:27:18 PM PDT 24
Peak memory 347208 kb
Host smart-2db98e18-dfb8-4ce5-8860-933ba827cd7d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63791875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.sram_ctrl_throughput_w_partial_write.63791875
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2634752856
Short name T302
Test name
Test status
Simulation time 24230413511 ps
CPU time 1437.91 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:49:30 PM PDT 24
Peak memory 379240 kb
Host smart-bb301d7e-8bb7-49e2-983e-96c486d78970
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634752856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.2634752856
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.2246107870
Short name T457
Test name
Test status
Simulation time 33268536 ps
CPU time 0.62 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:25:34 PM PDT 24
Peak memory 202468 kb
Host smart-b2b4358b-9094-4114-8dbf-0e9646ec8f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246107870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.2246107870
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.4021207123
Short name T194
Test name
Test status
Simulation time 184925200566 ps
CPU time 1059.9 seconds
Started Mar 21 01:25:54 PM PDT 24
Finished Mar 21 01:43:34 PM PDT 24
Peak memory 202512 kb
Host smart-753e6a1f-3f92-41f4-aa70-f5b7ac789861
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021207123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
4021207123
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.1766083007
Short name T555
Test name
Test status
Simulation time 22088736848 ps
CPU time 664.1 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:36:37 PM PDT 24
Peak memory 377272 kb
Host smart-41d37926-effd-49be-9eb6-6676b8170b53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766083007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.1766083007
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.1380489479
Short name T676
Test name
Test status
Simulation time 14685440774 ps
CPU time 73.02 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:26:45 PM PDT 24
Peak memory 202472 kb
Host smart-6a83f097-f657-46ad-91bb-e673a3ccadb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380489479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.1380489479
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.2492049416
Short name T812
Test name
Test status
Simulation time 694195088 ps
CPU time 9.78 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:25:46 PM PDT 24
Peak memory 235048 kb
Host smart-a0db8a94-4281-4e48-83d2-e7b19f7edeb2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492049416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.2492049416
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3935804475
Short name T409
Test name
Test status
Simulation time 3198690164 ps
CPU time 118.04 seconds
Started Mar 21 01:25:36 PM PDT 24
Finished Mar 21 01:27:35 PM PDT 24
Peak memory 210956 kb
Host smart-38fe9a7a-4e3d-424a-b600-5bb2b32d6cec
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935804475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.3935804475
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.2761829068
Short name T202
Test name
Test status
Simulation time 7031533247 ps
CPU time 149.26 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 01:28:30 PM PDT 24
Peak memory 202748 kb
Host smart-09aae2ec-a3a1-40ac-8334-cd67d6760696
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761829068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.2761829068
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.1023689281
Short name T377
Test name
Test status
Simulation time 15740200343 ps
CPU time 310.33 seconds
Started Mar 21 01:25:30 PM PDT 24
Finished Mar 21 01:30:40 PM PDT 24
Peak memory 354700 kb
Host smart-f80fb4cd-253d-4008-beef-ae8469fec377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023689281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.1023689281
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.2363876241
Short name T822
Test name
Test status
Simulation time 2794620371 ps
CPU time 14.8 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:25:40 PM PDT 24
Peak memory 202412 kb
Host smart-31252d81-26b9-4f36-b87c-d6302d7fb1b7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363876241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.2363876241
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1827993283
Short name T626
Test name
Test status
Simulation time 57733339383 ps
CPU time 356.62 seconds
Started Mar 21 01:25:27 PM PDT 24
Finished Mar 21 01:31:24 PM PDT 24
Peak memory 202320 kb
Host smart-2b84457d-d9ab-4ca3-a84d-35b11560fcb5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827993283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.1827993283
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.3236774719
Short name T756
Test name
Test status
Simulation time 372963471 ps
CPU time 2.99 seconds
Started Mar 21 01:25:34 PM PDT 24
Finished Mar 21 01:25:37 PM PDT 24
Peak memory 202508 kb
Host smart-59512b19-fdbe-48ce-a4d0-15cefedca61a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236774719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3236774719
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.185616878
Short name T440
Test name
Test status
Simulation time 84531995530 ps
CPU time 595.42 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:35:21 PM PDT 24
Peak memory 365072 kb
Host smart-717c1440-15bd-46de-8763-078f284b2651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185616878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.185616878
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.3173190410
Short name T138
Test name
Test status
Simulation time 13407658304 ps
CPU time 21.93 seconds
Started Mar 21 01:25:50 PM PDT 24
Finished Mar 21 01:26:13 PM PDT 24
Peak memory 202468 kb
Host smart-6d313717-31d9-4da4-a835-c80a7dc184dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173190410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3173190410
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.3708051055
Short name T16
Test name
Test status
Simulation time 62233523826 ps
CPU time 6147.58 seconds
Started Mar 21 01:25:28 PM PDT 24
Finished Mar 21 03:07:57 PM PDT 24
Peak memory 380152 kb
Host smart-69407d71-4829-4062-8149-016466ce3e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708051055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.3708051055
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.175117871
Short name T42
Test name
Test status
Simulation time 2006968031 ps
CPU time 16.28 seconds
Started Mar 21 01:25:35 PM PDT 24
Finished Mar 21 01:25:51 PM PDT 24
Peak memory 210648 kb
Host smart-d95ed67f-b14b-4009-909d-28adc78a3968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=175117871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.175117871
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3768476449
Short name T276
Test name
Test status
Simulation time 3147107556 ps
CPU time 184.79 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:28:37 PM PDT 24
Peak memory 202320 kb
Host smart-ba1f7cf4-4236-49b0-8045-37f8d9ddc7ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768476449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.3768476449
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2698117753
Short name T612
Test name
Test status
Simulation time 744382848 ps
CPU time 27.41 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:26:01 PM PDT 24
Peak memory 279788 kb
Host smart-55d3ab3d-c495-4bfc-85bf-6c8ca3eb0493
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698117753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2698117753
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.940549169
Short name T891
Test name
Test status
Simulation time 54634415331 ps
CPU time 772.69 seconds
Started Mar 21 01:25:54 PM PDT 24
Finished Mar 21 01:38:47 PM PDT 24
Peak memory 375176 kb
Host smart-ace112fb-3115-4f83-8b20-6c92a73086af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940549169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_access_during_key_req.940549169
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.95825297
Short name T732
Test name
Test status
Simulation time 17500742 ps
CPU time 0.59 seconds
Started Mar 21 01:25:51 PM PDT 24
Finished Mar 21 01:25:52 PM PDT 24
Peak memory 202028 kb
Host smart-78c1dce7-c2c0-4d6f-8b92-d80f30829df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95825297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_alert_test.95825297
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.146653698
Short name T764
Test name
Test status
Simulation time 143943288873 ps
CPU time 2394.91 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 02:05:27 PM PDT 24
Peak memory 202824 kb
Host smart-20541c05-b8e0-4191-a23a-d6e14f6aa969
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146653698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.146653698
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.4232989911
Short name T856
Test name
Test status
Simulation time 28070914694 ps
CPU time 1410.39 seconds
Started Mar 21 01:25:56 PM PDT 24
Finished Mar 21 01:49:27 PM PDT 24
Peak memory 375216 kb
Host smart-dda87fe2-73f0-4d57-99d0-94459f6516ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232989911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.4232989911
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.2409590269
Short name T447
Test name
Test status
Simulation time 75506938390 ps
CPU time 117.81 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:27:30 PM PDT 24
Peak memory 202548 kb
Host smart-c2a035b1-7761-43f1-a5ac-335d5c443075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409590269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.2409590269
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.4137976769
Short name T378
Test name
Test status
Simulation time 1859377030 ps
CPU time 23.65 seconds
Started Mar 21 01:25:32 PM PDT 24
Finished Mar 21 01:25:55 PM PDT 24
Peak memory 270864 kb
Host smart-70c7d418-134e-4fc6-a2dc-5f0701c4a8f4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137976769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.4137976769
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2669037775
Short name T427
Test name
Test status
Simulation time 7595630184 ps
CPU time 75.09 seconds
Started Mar 21 01:25:46 PM PDT 24
Finished Mar 21 01:27:03 PM PDT 24
Peak memory 210604 kb
Host smart-5310c89d-cbab-4dd6-8d44-3af8e11fbb60
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669037775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.2669037775
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.820334964
Short name T261
Test name
Test status
Simulation time 20695523650 ps
CPU time 141.95 seconds
Started Mar 21 01:25:38 PM PDT 24
Finished Mar 21 01:28:00 PM PDT 24
Peak memory 202708 kb
Host smart-b0b9d6e0-d15b-4ac7-a9fd-3e478555326f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820334964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_
mem_walk.820334964
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.3939412193
Short name T418
Test name
Test status
Simulation time 26395026162 ps
CPU time 776.47 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:38:30 PM PDT 24
Peak memory 373152 kb
Host smart-f2c9c670-cd41-49ed-b4ec-b4bce0caab6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939412193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.3939412193
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.2597934516
Short name T702
Test name
Test status
Simulation time 4111244947 ps
CPU time 17.52 seconds
Started Mar 21 01:25:37 PM PDT 24
Finished Mar 21 01:25:54 PM PDT 24
Peak memory 202360 kb
Host smart-da80caac-c915-40f0-946f-6f37e55d7580
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597934516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.2597934516
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.136005391
Short name T628
Test name
Test status
Simulation time 10629638753 ps
CPU time 266.37 seconds
Started Mar 21 01:25:50 PM PDT 24
Finished Mar 21 01:30:16 PM PDT 24
Peak memory 202416 kb
Host smart-d3e6ed35-b107-4e3e-b1dd-b65466884d32
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136005391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.sram_ctrl_partial_access_b2b.136005391
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.2304039983
Short name T667
Test name
Test status
Simulation time 1410060109 ps
CPU time 3.26 seconds
Started Mar 21 01:25:38 PM PDT 24
Finished Mar 21 01:25:41 PM PDT 24
Peak memory 202376 kb
Host smart-7f3bd96f-f305-4081-83ed-4ddbf13433bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304039983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2304039983
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.1437208778
Short name T814
Test name
Test status
Simulation time 9076175994 ps
CPU time 752.09 seconds
Started Mar 21 01:25:31 PM PDT 24
Finished Mar 21 01:38:03 PM PDT 24
Peak memory 379332 kb
Host smart-efaa345a-9049-40cf-a73f-7941e8b395d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437208778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1437208778
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.313249914
Short name T373
Test name
Test status
Simulation time 3340604380 ps
CPU time 11.5 seconds
Started Mar 21 01:25:38 PM PDT 24
Finished Mar 21 01:25:51 PM PDT 24
Peak memory 202372 kb
Host smart-10796e84-9fac-4cdb-acfc-e78130143feb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313249914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.313249914
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.2910369640
Short name T589
Test name
Test status
Simulation time 40439684051 ps
CPU time 5901.42 seconds
Started Mar 21 01:26:00 PM PDT 24
Finished Mar 21 03:04:22 PM PDT 24
Peak memory 380264 kb
Host smart-2e20840e-68f4-4764-8af4-e7b254c6ed5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910369640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.2910369640
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.89372299
Short name T892
Test name
Test status
Simulation time 1025945898 ps
CPU time 14.09 seconds
Started Mar 21 01:25:37 PM PDT 24
Finished Mar 21 01:25:51 PM PDT 24
Peak memory 212184 kb
Host smart-9ae59b2c-5c18-4b92-b331-6b4713644f66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=89372299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.89372299
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.4256280115
Short name T920
Test name
Test status
Simulation time 68346999523 ps
CPU time 358.35 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:31:22 PM PDT 24
Peak memory 202312 kb
Host smart-2f06cfa0-c773-44a1-bd36-d3b77efdc292
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256280115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.4256280115
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1295032792
Short name T11
Test name
Test status
Simulation time 752751250 ps
CPU time 40.68 seconds
Started Mar 21 01:25:37 PM PDT 24
Finished Mar 21 01:26:18 PM PDT 24
Peak memory 300452 kb
Host smart-e3e70654-7ece-4c96-b14d-fe3c43f3ed13
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295032792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.1295032792
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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