| T790 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1701399883 |
|
|
Mar 26 01:03:33 PM PDT 24 |
Mar 26 01:03:46 PM PDT 24 |
687148091 ps |
| T791 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.304850930 |
|
|
Mar 26 01:03:07 PM PDT 24 |
Mar 26 01:03:10 PM PDT 24 |
1413168554 ps |
| T792 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3080427862 |
|
|
Mar 26 01:06:51 PM PDT 24 |
Mar 26 01:07:04 PM PDT 24 |
2891902892 ps |
| T793 |
/workspace/coverage/default/22.sram_ctrl_executable.1671766736 |
|
|
Mar 26 01:02:25 PM PDT 24 |
Mar 26 01:08:10 PM PDT 24 |
3225820856 ps |
| T794 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.1388891420 |
|
|
Mar 26 01:02:10 PM PDT 24 |
Mar 26 01:07:07 PM PDT 24 |
18261585323 ps |
| T795 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.893623724 |
|
|
Mar 26 01:05:36 PM PDT 24 |
Mar 26 01:08:15 PM PDT 24 |
11793979418 ps |
| T796 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1156931645 |
|
|
Mar 26 01:02:10 PM PDT 24 |
Mar 26 01:02:11 PM PDT 24 |
13017745 ps |
| T797 |
/workspace/coverage/default/31.sram_ctrl_partial_access.166359881 |
|
|
Mar 26 01:04:22 PM PDT 24 |
Mar 26 01:06:40 PM PDT 24 |
1612144594 ps |
| T798 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1467993271 |
|
|
Mar 26 01:05:07 PM PDT 24 |
Mar 26 01:05:10 PM PDT 24 |
732001801 ps |
| T799 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3709768682 |
|
|
Mar 26 01:00:17 PM PDT 24 |
Mar 26 01:00:26 PM PDT 24 |
3761929716 ps |
| T800 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3585475857 |
|
|
Mar 26 12:59:32 PM PDT 24 |
Mar 26 12:59:51 PM PDT 24 |
1750335709 ps |
| T801 |
/workspace/coverage/default/9.sram_ctrl_bijection.1440509078 |
|
|
Mar 26 12:59:43 PM PDT 24 |
Mar 26 01:20:25 PM PDT 24 |
57198267699 ps |
| T802 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.199019771 |
|
|
Mar 26 01:04:26 PM PDT 24 |
Mar 26 01:05:10 PM PDT 24 |
17831906447 ps |
| T803 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3802698317 |
|
|
Mar 26 12:58:35 PM PDT 24 |
Mar 26 01:04:24 PM PDT 24 |
6365402597 ps |
| T804 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2665521187 |
|
|
Mar 26 01:03:08 PM PDT 24 |
Mar 26 01:22:33 PM PDT 24 |
61369149060 ps |
| T805 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1508540865 |
|
|
Mar 26 01:05:34 PM PDT 24 |
Mar 26 01:20:36 PM PDT 24 |
14780751857 ps |
| T806 |
/workspace/coverage/default/43.sram_ctrl_alert_test.4286442155 |
|
|
Mar 26 01:07:45 PM PDT 24 |
Mar 26 01:07:46 PM PDT 24 |
95736460 ps |
| T807 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1190797825 |
|
|
Mar 26 01:04:35 PM PDT 24 |
Mar 26 01:21:03 PM PDT 24 |
91303814922 ps |
| T808 |
/workspace/coverage/default/5.sram_ctrl_partial_access.2348191514 |
|
|
Mar 26 12:59:00 PM PDT 24 |
Mar 26 12:59:20 PM PDT 24 |
1876254621 ps |
| T809 |
/workspace/coverage/default/33.sram_ctrl_stress_all.252533782 |
|
|
Mar 26 01:04:52 PM PDT 24 |
Mar 26 02:35:24 PM PDT 24 |
269719699922 ps |
| T810 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3460977716 |
|
|
Mar 26 12:59:54 PM PDT 24 |
Mar 26 01:02:22 PM PDT 24 |
1427033755 ps |
| T811 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.942490955 |
|
|
Mar 26 01:04:51 PM PDT 24 |
Mar 26 01:06:41 PM PDT 24 |
1719857934 ps |
| T812 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.4229776212 |
|
|
Mar 26 01:02:13 PM PDT 24 |
Mar 26 01:04:52 PM PDT 24 |
25822013607 ps |
| T813 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1480317475 |
|
|
Mar 26 01:05:49 PM PDT 24 |
Mar 26 01:07:01 PM PDT 24 |
18006167273 ps |
| T814 |
/workspace/coverage/default/17.sram_ctrl_bijection.377585116 |
|
|
Mar 26 01:01:29 PM PDT 24 |
Mar 26 01:21:10 PM PDT 24 |
72817025691 ps |
| T815 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2290137373 |
|
|
Mar 26 01:04:56 PM PDT 24 |
Mar 26 01:08:58 PM PDT 24 |
15823290349 ps |
| T816 |
/workspace/coverage/default/42.sram_ctrl_executable.1094750642 |
|
|
Mar 26 01:07:05 PM PDT 24 |
Mar 26 01:13:55 PM PDT 24 |
3283267786 ps |
| T817 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3894416132 |
|
|
Mar 26 01:01:13 PM PDT 24 |
Mar 26 01:06:49 PM PDT 24 |
21517114622 ps |
| T818 |
/workspace/coverage/default/14.sram_ctrl_regwen.3362950192 |
|
|
Mar 26 01:00:59 PM PDT 24 |
Mar 26 01:08:30 PM PDT 24 |
33087716621 ps |
| T819 |
/workspace/coverage/default/42.sram_ctrl_alert_test.2080755639 |
|
|
Mar 26 01:07:18 PM PDT 24 |
Mar 26 01:07:20 PM PDT 24 |
16097495 ps |
| T820 |
/workspace/coverage/default/23.sram_ctrl_executable.1145038730 |
|
|
Mar 26 01:02:41 PM PDT 24 |
Mar 26 01:06:40 PM PDT 24 |
22587295492 ps |
| T821 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.2024508748 |
|
|
Mar 26 01:03:51 PM PDT 24 |
Mar 26 01:04:54 PM PDT 24 |
10308403020 ps |
| T822 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3018777096 |
|
|
Mar 26 01:07:56 PM PDT 24 |
Mar 26 01:09:28 PM PDT 24 |
1995249620 ps |
| T823 |
/workspace/coverage/default/38.sram_ctrl_executable.1366297962 |
|
|
Mar 26 01:06:04 PM PDT 24 |
Mar 26 01:10:35 PM PDT 24 |
37891639057 ps |
| T824 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1760208019 |
|
|
Mar 26 01:05:35 PM PDT 24 |
Mar 26 01:05:36 PM PDT 24 |
24015923 ps |
| T825 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2028508785 |
|
|
Mar 26 01:01:59 PM PDT 24 |
Mar 26 01:04:25 PM PDT 24 |
788335572 ps |
| T826 |
/workspace/coverage/default/12.sram_ctrl_partial_access.563471472 |
|
|
Mar 26 01:00:18 PM PDT 24 |
Mar 26 01:00:39 PM PDT 24 |
4746199168 ps |
| T827 |
/workspace/coverage/default/40.sram_ctrl_bijection.939382281 |
|
|
Mar 26 01:06:35 PM PDT 24 |
Mar 26 01:22:07 PM PDT 24 |
41637647938 ps |
| T828 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3241224198 |
|
|
Mar 26 01:07:57 PM PDT 24 |
Mar 26 01:18:39 PM PDT 24 |
76923665044 ps |
| T829 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.399578203 |
|
|
Mar 26 12:59:13 PM PDT 24 |
Mar 26 01:14:41 PM PDT 24 |
219902645607 ps |
| T830 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1886672597 |
|
|
Mar 26 01:01:56 PM PDT 24 |
Mar 26 01:10:25 PM PDT 24 |
90386978012 ps |
| T831 |
/workspace/coverage/default/44.sram_ctrl_stress_all.2242428077 |
|
|
Mar 26 01:07:29 PM PDT 24 |
Mar 26 01:48:16 PM PDT 24 |
47586128676 ps |
| T832 |
/workspace/coverage/default/13.sram_ctrl_alert_test.4211581177 |
|
|
Mar 26 01:01:01 PM PDT 24 |
Mar 26 01:01:03 PM PDT 24 |
11845481 ps |
| T833 |
/workspace/coverage/default/17.sram_ctrl_stress_all.496975940 |
|
|
Mar 26 01:01:46 PM PDT 24 |
Mar 26 02:35:30 PM PDT 24 |
287881472027 ps |
| T834 |
/workspace/coverage/default/29.sram_ctrl_bijection.1751737116 |
|
|
Mar 26 01:03:51 PM PDT 24 |
Mar 26 01:24:55 PM PDT 24 |
19477338241 ps |
| T835 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.2388772286 |
|
|
Mar 26 01:01:58 PM PDT 24 |
Mar 26 01:02:01 PM PDT 24 |
366780905 ps |
| T836 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2855677461 |
|
|
Mar 26 01:04:52 PM PDT 24 |
Mar 26 01:23:59 PM PDT 24 |
57727023848 ps |
| T837 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1559691608 |
|
|
Mar 26 01:06:34 PM PDT 24 |
Mar 26 01:08:44 PM PDT 24 |
8160676804 ps |
| T838 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.4080943137 |
|
|
Mar 26 12:58:47 PM PDT 24 |
Mar 26 12:58:50 PM PDT 24 |
436500791 ps |
| T839 |
/workspace/coverage/default/18.sram_ctrl_executable.2598670663 |
|
|
Mar 26 01:01:45 PM PDT 24 |
Mar 26 01:17:10 PM PDT 24 |
31197930188 ps |
| T840 |
/workspace/coverage/default/38.sram_ctrl_regwen.2057530262 |
|
|
Mar 26 01:06:04 PM PDT 24 |
Mar 26 01:09:22 PM PDT 24 |
691642985 ps |
| T841 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1854767812 |
|
|
Mar 26 01:04:35 PM PDT 24 |
Mar 26 01:04:43 PM PDT 24 |
2499225756 ps |
| T842 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.2322138995 |
|
|
Mar 26 01:02:41 PM PDT 24 |
Mar 26 01:07:21 PM PDT 24 |
4389043670 ps |
| T843 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.4054819572 |
|
|
Mar 26 01:01:45 PM PDT 24 |
Mar 26 01:03:20 PM PDT 24 |
33484904572 ps |
| T844 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2721646240 |
|
|
Mar 26 01:08:22 PM PDT 24 |
Mar 26 01:28:56 PM PDT 24 |
21342698472 ps |
| T845 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2271088406 |
|
|
Mar 26 01:00:30 PM PDT 24 |
Mar 26 01:04:55 PM PDT 24 |
7287373941 ps |
| T846 |
/workspace/coverage/default/3.sram_ctrl_bijection.3115157020 |
|
|
Mar 26 12:58:36 PM PDT 24 |
Mar 26 01:10:27 PM PDT 24 |
64819116201 ps |
| T847 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.3325536110 |
|
|
Mar 26 01:01:58 PM PDT 24 |
Mar 26 01:02:09 PM PDT 24 |
1403496222 ps |
| T848 |
/workspace/coverage/default/11.sram_ctrl_bijection.1378080301 |
|
|
Mar 26 01:00:06 PM PDT 24 |
Mar 26 01:10:32 PM PDT 24 |
108644846664 ps |
| T849 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2417983241 |
|
|
Mar 26 01:07:57 PM PDT 24 |
Mar 26 01:08:01 PM PDT 24 |
373839894 ps |
| T850 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.498394503 |
|
|
Mar 26 12:58:37 PM PDT 24 |
Mar 26 01:20:58 PM PDT 24 |
51169920304 ps |
| T851 |
/workspace/coverage/default/30.sram_ctrl_smoke.1650775946 |
|
|
Mar 26 01:04:11 PM PDT 24 |
Mar 26 01:04:23 PM PDT 24 |
473000741 ps |
| T852 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.874393586 |
|
|
Mar 26 01:00:05 PM PDT 24 |
Mar 26 01:02:37 PM PDT 24 |
7110099575 ps |
| T853 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1920565847 |
|
|
Mar 26 01:04:34 PM PDT 24 |
Mar 26 01:11:46 PM PDT 24 |
16449020041 ps |
| T854 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3197374166 |
|
|
Mar 26 01:05:34 PM PDT 24 |
Mar 26 01:05:39 PM PDT 24 |
345066236 ps |
| T855 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.199356994 |
|
|
Mar 26 01:02:55 PM PDT 24 |
Mar 26 01:08:13 PM PDT 24 |
4633984149 ps |
| T856 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.368537862 |
|
|
Mar 26 12:59:42 PM PDT 24 |
Mar 26 01:01:13 PM PDT 24 |
6830237659 ps |
| T857 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.247286120 |
|
|
Mar 26 01:05:20 PM PDT 24 |
Mar 26 01:10:28 PM PDT 24 |
20308841201 ps |
| T858 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.312383334 |
|
|
Mar 26 12:59:21 PM PDT 24 |
Mar 26 12:59:25 PM PDT 24 |
359133432 ps |
| T859 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1108690084 |
|
|
Mar 26 01:00:21 PM PDT 24 |
Mar 26 01:00:44 PM PDT 24 |
7491849213 ps |
| T860 |
/workspace/coverage/default/32.sram_ctrl_executable.720808189 |
|
|
Mar 26 01:04:35 PM PDT 24 |
Mar 26 01:23:02 PM PDT 24 |
12860024879 ps |
| T861 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.371877072 |
|
|
Mar 26 01:06:04 PM PDT 24 |
Mar 26 01:22:17 PM PDT 24 |
12443257544 ps |
| T862 |
/workspace/coverage/default/24.sram_ctrl_smoke.826299119 |
|
|
Mar 26 01:02:57 PM PDT 24 |
Mar 26 01:03:07 PM PDT 24 |
2948513078 ps |
| T863 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1565436312 |
|
|
Mar 26 01:06:04 PM PDT 24 |
Mar 26 01:08:34 PM PDT 24 |
75822701955 ps |
| T864 |
/workspace/coverage/default/28.sram_ctrl_bijection.439222379 |
|
|
Mar 26 01:03:33 PM PDT 24 |
Mar 26 01:25:38 PM PDT 24 |
113110431244 ps |
| T865 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.873947795 |
|
|
Mar 26 12:58:26 PM PDT 24 |
Mar 26 12:58:35 PM PDT 24 |
252080227 ps |
| T866 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.571545740 |
|
|
Mar 26 01:03:20 PM PDT 24 |
Mar 26 01:06:55 PM PDT 24 |
13371155249 ps |
| T867 |
/workspace/coverage/default/37.sram_ctrl_alert_test.1223410105 |
|
|
Mar 26 01:05:50 PM PDT 24 |
Mar 26 01:05:51 PM PDT 24 |
15400343 ps |
| T868 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.265898960 |
|
|
Mar 26 01:06:32 PM PDT 24 |
Mar 26 01:11:59 PM PDT 24 |
5321103945 ps |
| T869 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.43286851 |
|
|
Mar 26 01:05:24 PM PDT 24 |
Mar 26 01:15:20 PM PDT 24 |
3318948627 ps |
| T870 |
/workspace/coverage/default/29.sram_ctrl_regwen.3108818023 |
|
|
Mar 26 01:04:12 PM PDT 24 |
Mar 26 01:20:02 PM PDT 24 |
18512272454 ps |
| T871 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2943360427 |
|
|
Mar 26 01:04:38 PM PDT 24 |
Mar 26 01:12:33 PM PDT 24 |
8494806405 ps |
| T872 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3499730873 |
|
|
Mar 26 12:58:48 PM PDT 24 |
Mar 26 01:00:15 PM PDT 24 |
4570305781 ps |
| T873 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1241611835 |
|
|
Mar 26 01:07:42 PM PDT 24 |
Mar 26 01:24:29 PM PDT 24 |
95925769827 ps |
| T874 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.537227597 |
|
|
Mar 26 01:00:41 PM PDT 24 |
Mar 26 01:00:58 PM PDT 24 |
724427127 ps |
| T875 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1868147180 |
|
|
Mar 26 01:01:45 PM PDT 24 |
Mar 26 01:12:11 PM PDT 24 |
15314438206 ps |
| T876 |
/workspace/coverage/default/44.sram_ctrl_executable.91757231 |
|
|
Mar 26 01:07:28 PM PDT 24 |
Mar 26 01:15:41 PM PDT 24 |
56951968510 ps |
| T877 |
/workspace/coverage/default/30.sram_ctrl_alert_test.2629918844 |
|
|
Mar 26 01:04:23 PM PDT 24 |
Mar 26 01:04:25 PM PDT 24 |
14943254 ps |
| T878 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3210149005 |
|
|
Mar 26 01:05:49 PM PDT 24 |
Mar 26 01:10:02 PM PDT 24 |
9806309054 ps |
| T879 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1800916259 |
|
|
Mar 26 01:04:36 PM PDT 24 |
Mar 26 01:05:13 PM PDT 24 |
5943479589 ps |
| T880 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3145937584 |
|
|
Mar 26 01:06:49 PM PDT 24 |
Mar 26 01:06:53 PM PDT 24 |
1971123444 ps |
| T881 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1398400130 |
|
|
Mar 26 01:04:52 PM PDT 24 |
Mar 26 01:05:05 PM PDT 24 |
1856161073 ps |
| T882 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3511232558 |
|
|
Mar 26 01:02:43 PM PDT 24 |
Mar 26 01:03:07 PM PDT 24 |
1703612845 ps |
| T883 |
/workspace/coverage/default/5.sram_ctrl_bijection.3910649446 |
|
|
Mar 26 12:59:01 PM PDT 24 |
Mar 26 01:36:46 PM PDT 24 |
33121847558 ps |
| T884 |
/workspace/coverage/default/41.sram_ctrl_partial_access.2361718321 |
|
|
Mar 26 01:06:50 PM PDT 24 |
Mar 26 01:07:17 PM PDT 24 |
7452105933 ps |
| T885 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1742104956 |
|
|
Mar 26 01:08:21 PM PDT 24 |
Mar 26 01:09:13 PM PDT 24 |
25592961222 ps |
| T886 |
/workspace/coverage/default/25.sram_ctrl_executable.2784930234 |
|
|
Mar 26 01:02:58 PM PDT 24 |
Mar 26 01:15:00 PM PDT 24 |
13237530818 ps |
| T887 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.806534391 |
|
|
Mar 26 12:59:21 PM PDT 24 |
Mar 26 01:06:01 PM PDT 24 |
6738739893 ps |
| T888 |
/workspace/coverage/default/25.sram_ctrl_partial_access.1999105544 |
|
|
Mar 26 01:02:56 PM PDT 24 |
Mar 26 01:03:20 PM PDT 24 |
4664482631 ps |
| T889 |
/workspace/coverage/default/22.sram_ctrl_partial_access.2982002791 |
|
|
Mar 26 01:02:23 PM PDT 24 |
Mar 26 01:02:51 PM PDT 24 |
723152550 ps |
| T890 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.770434049 |
|
|
Mar 26 01:00:31 PM PDT 24 |
Mar 26 01:05:09 PM PDT 24 |
28669568873 ps |
| T891 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.82429016 |
|
|
Mar 26 01:05:25 PM PDT 24 |
Mar 26 01:05:42 PM PDT 24 |
962825903 ps |
| T892 |
/workspace/coverage/default/2.sram_ctrl_partial_access.918808319 |
|
|
Mar 26 12:58:37 PM PDT 24 |
Mar 26 12:58:57 PM PDT 24 |
2583712660 ps |
| T893 |
/workspace/coverage/default/21.sram_ctrl_regwen.2145405056 |
|
|
Mar 26 01:02:15 PM PDT 24 |
Mar 26 01:20:56 PM PDT 24 |
64170790793 ps |
| T894 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2601818978 |
|
|
Mar 26 12:59:54 PM PDT 24 |
Mar 26 01:01:55 PM PDT 24 |
7549869655 ps |
| T895 |
/workspace/coverage/default/39.sram_ctrl_alert_test.649383848 |
|
|
Mar 26 01:06:19 PM PDT 24 |
Mar 26 01:06:21 PM PDT 24 |
12931026 ps |
| T896 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4228698881 |
|
|
Mar 26 01:02:10 PM PDT 24 |
Mar 26 01:03:02 PM PDT 24 |
5361833443 ps |
| T897 |
/workspace/coverage/default/34.sram_ctrl_regwen.3944392373 |
|
|
Mar 26 01:05:06 PM PDT 24 |
Mar 26 01:17:37 PM PDT 24 |
6486600054 ps |
| T898 |
/workspace/coverage/default/9.sram_ctrl_executable.3845420593 |
|
|
Mar 26 12:59:48 PM PDT 24 |
Mar 26 01:02:23 PM PDT 24 |
9105680880 ps |
| T899 |
/workspace/coverage/default/43.sram_ctrl_smoke.1312100738 |
|
|
Mar 26 01:07:17 PM PDT 24 |
Mar 26 01:08:36 PM PDT 24 |
4727247742 ps |
| T900 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2193881798 |
|
|
Mar 26 01:07:55 PM PDT 24 |
Mar 26 01:09:03 PM PDT 24 |
778745016 ps |
| T901 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2842921166 |
|
|
Mar 26 01:06:34 PM PDT 24 |
Mar 26 01:06:37 PM PDT 24 |
441708291 ps |
| T902 |
/workspace/coverage/default/37.sram_ctrl_bijection.1425043009 |
|
|
Mar 26 01:05:49 PM PDT 24 |
Mar 26 01:19:01 PM PDT 24 |
50530320910 ps |
| T903 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2038196646 |
|
|
Mar 26 01:05:22 PM PDT 24 |
Mar 26 01:07:23 PM PDT 24 |
7316287724 ps |
| T904 |
/workspace/coverage/default/5.sram_ctrl_executable.1110859949 |
|
|
Mar 26 12:59:00 PM PDT 24 |
Mar 26 01:03:05 PM PDT 24 |
2129264703 ps |
| T905 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2994051135 |
|
|
Mar 26 01:03:52 PM PDT 24 |
Mar 26 01:08:15 PM PDT 24 |
5098651003 ps |
| T906 |
/workspace/coverage/default/20.sram_ctrl_executable.3826716764 |
|
|
Mar 26 01:01:59 PM PDT 24 |
Mar 26 01:12:37 PM PDT 24 |
10671575898 ps |
| T907 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2962482863 |
|
|
Mar 26 01:05:09 PM PDT 24 |
Mar 26 01:06:49 PM PDT 24 |
1559158492 ps |
| T908 |
/workspace/coverage/default/15.sram_ctrl_regwen.4029576864 |
|
|
Mar 26 01:01:13 PM PDT 24 |
Mar 26 01:18:11 PM PDT 24 |
49248886422 ps |
| T909 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.850567569 |
|
|
Mar 26 12:59:32 PM PDT 24 |
Mar 26 01:21:22 PM PDT 24 |
10723042935 ps |
| T910 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.1991535488 |
|
|
Mar 26 01:02:42 PM PDT 24 |
Mar 26 01:03:23 PM PDT 24 |
53028136907 ps |
| T911 |
/workspace/coverage/default/29.sram_ctrl_stress_all.3666882692 |
|
|
Mar 26 01:04:12 PM PDT 24 |
Mar 26 01:24:58 PM PDT 24 |
42845671832 ps |
| T912 |
/workspace/coverage/default/2.sram_ctrl_executable.2987935627 |
|
|
Mar 26 12:58:39 PM PDT 24 |
Mar 26 01:12:55 PM PDT 24 |
9839136595 ps |
| T913 |
/workspace/coverage/default/43.sram_ctrl_executable.4171658301 |
|
|
Mar 26 01:07:17 PM PDT 24 |
Mar 26 01:28:39 PM PDT 24 |
17517797130 ps |
| T914 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2828202965 |
|
|
Mar 26 01:01:02 PM PDT 24 |
Mar 26 01:09:59 PM PDT 24 |
99950925022 ps |
| T915 |
/workspace/coverage/default/6.sram_ctrl_smoke.3684589710 |
|
|
Mar 26 12:59:03 PM PDT 24 |
Mar 26 12:59:28 PM PDT 24 |
3775149727 ps |
| T916 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1488971659 |
|
|
Mar 26 12:59:43 PM PDT 24 |
Mar 26 01:00:29 PM PDT 24 |
14214001422 ps |
| T917 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1674225590 |
|
|
Mar 26 01:04:37 PM PDT 24 |
Mar 26 01:07:33 PM PDT 24 |
11003482086 ps |
| T918 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.2251879482 |
|
|
Mar 26 12:58:36 PM PDT 24 |
Mar 26 01:00:27 PM PDT 24 |
2366229517 ps |
| T919 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1875561979 |
|
|
Mar 26 12:59:43 PM PDT 24 |
Mar 26 01:01:07 PM PDT 24 |
10069417306 ps |
| T920 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2518139013 |
|
|
Mar 26 01:01:31 PM PDT 24 |
Mar 26 01:08:36 PM PDT 24 |
16629252935 ps |
| T921 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.3552416024 |
|
|
Mar 26 12:58:24 PM PDT 24 |
Mar 26 01:00:55 PM PDT 24 |
29941550828 ps |
| T922 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3384724985 |
|
|
Mar 26 12:59:36 PM PDT 24 |
Mar 26 12:59:56 PM PDT 24 |
6653747974 ps |
| T923 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1626877483 |
|
|
Mar 26 01:05:07 PM PDT 24 |
Mar 26 01:08:28 PM PDT 24 |
3181117732 ps |
| T924 |
/workspace/coverage/default/27.sram_ctrl_alert_test.423127194 |
|
|
Mar 26 01:03:33 PM PDT 24 |
Mar 26 01:03:34 PM PDT 24 |
22643566 ps |
| T925 |
/workspace/coverage/default/49.sram_ctrl_smoke.1781101232 |
|
|
Mar 26 01:08:33 PM PDT 24 |
Mar 26 01:08:53 PM PDT 24 |
927626691 ps |
| T34 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.3810050327 |
|
|
Mar 26 12:58:35 PM PDT 24 |
Mar 26 12:58:37 PM PDT 24 |
242978044 ps |
| T926 |
/workspace/coverage/default/10.sram_ctrl_bijection.183572061 |
|
|
Mar 26 12:59:55 PM PDT 24 |
Mar 26 01:42:48 PM PDT 24 |
689938077958 ps |
| T927 |
/workspace/coverage/default/10.sram_ctrl_smoke.3166239988 |
|
|
Mar 26 12:59:54 PM PDT 24 |
Mar 26 01:00:06 PM PDT 24 |
926426909 ps |
| T928 |
/workspace/coverage/default/32.sram_ctrl_partial_access.1835302418 |
|
|
Mar 26 01:04:33 PM PDT 24 |
Mar 26 01:06:52 PM PDT 24 |
13610108809 ps |
| T929 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3646600830 |
|
|
Mar 26 01:08:06 PM PDT 24 |
Mar 26 01:09:00 PM PDT 24 |
16957346457 ps |
| T930 |
/workspace/coverage/default/36.sram_ctrl_regwen.2465304216 |
|
|
Mar 26 01:05:35 PM PDT 24 |
Mar 26 01:22:27 PM PDT 24 |
16319043699 ps |
| T931 |
/workspace/coverage/default/46.sram_ctrl_smoke.2659930487 |
|
|
Mar 26 01:07:55 PM PDT 24 |
Mar 26 01:08:08 PM PDT 24 |
3627640330 ps |
| T932 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3630586891 |
|
|
Mar 26 01:01:13 PM PDT 24 |
Mar 26 01:03:53 PM PDT 24 |
4379432295 ps |
| T933 |
/workspace/coverage/default/1.sram_ctrl_smoke.3741019737 |
|
|
Mar 26 12:58:24 PM PDT 24 |
Mar 26 12:58:47 PM PDT 24 |
2688470161 ps |
| T934 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2168334115 |
|
|
Mar 26 01:01:03 PM PDT 24 |
Mar 26 01:03:25 PM PDT 24 |
4814538468 ps |
| T935 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3470806099 |
|
|
Mar 26 01:01:57 PM PDT 24 |
Mar 26 01:02:21 PM PDT 24 |
720581404 ps |
| T936 |
/workspace/coverage/default/27.sram_ctrl_stress_all.1288908678 |
|
|
Mar 26 01:03:33 PM PDT 24 |
Mar 26 02:05:54 PM PDT 24 |
199406702727 ps |
| T937 |
/workspace/coverage/default/13.sram_ctrl_bijection.3187836040 |
|
|
Mar 26 01:00:32 PM PDT 24 |
Mar 26 01:31:12 PM PDT 24 |
531019515466 ps |
| T938 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3595477902 |
|
|
Mar 26 01:00:21 PM PDT 24 |
Mar 26 01:06:52 PM PDT 24 |
11707441750 ps |
| T98 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3987456947 |
|
|
Mar 26 12:39:30 PM PDT 24 |
Mar 26 12:39:32 PM PDT 24 |
25611647 ps |
| T50 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2052580600 |
|
|
Mar 26 12:39:48 PM PDT 24 |
Mar 26 12:39:49 PM PDT 24 |
26805213 ps |
| T100 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.67102538 |
|
|
Mar 26 12:39:46 PM PDT 24 |
Mar 26 12:39:49 PM PDT 24 |
211428434 ps |
| T51 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1631471596 |
|
|
Mar 26 12:39:45 PM PDT 24 |
Mar 26 12:40:11 PM PDT 24 |
14235372412 ps |
| T52 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4075697317 |
|
|
Mar 26 12:39:48 PM PDT 24 |
Mar 26 12:40:39 PM PDT 24 |
10382337705 ps |
| T53 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.667062916 |
|
|
Mar 26 12:39:47 PM PDT 24 |
Mar 26 12:39:48 PM PDT 24 |
69315899 ps |
| T101 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1624782410 |
|
|
Mar 26 12:39:46 PM PDT 24 |
Mar 26 12:39:48 PM PDT 24 |
281869184 ps |
| T81 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2542390620 |
|
|
Mar 26 12:39:34 PM PDT 24 |
Mar 26 12:39:36 PM PDT 24 |
107599831 ps |
| T939 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2866660133 |
|
|
Mar 26 12:39:45 PM PDT 24 |
Mar 26 12:39:49 PM PDT 24 |
618651684 ps |
| T102 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3600300360 |
|
|
Mar 26 12:39:50 PM PDT 24 |
Mar 26 12:39:52 PM PDT 24 |
2337800505 ps |
| T54 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2673166510 |
|
|
Mar 26 12:39:41 PM PDT 24 |
Mar 26 12:40:06 PM PDT 24 |
3758129336 ps |
| T55 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2770367371 |
|
|
Mar 26 12:39:40 PM PDT 24 |
Mar 26 12:39:41 PM PDT 24 |
52707120 ps |
| T56 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3770936580 |
|
|
Mar 26 12:39:35 PM PDT 24 |
Mar 26 12:39:36 PM PDT 24 |
60698179 ps |
| T57 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.26292524 |
|
|
Mar 26 12:39:42 PM PDT 24 |
Mar 26 12:39:43 PM PDT 24 |
40455785 ps |
| T940 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1371182560 |
|
|
Mar 26 12:39:28 PM PDT 24 |
Mar 26 12:39:32 PM PDT 24 |
1423393486 ps |
| T82 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2353570642 |
|
|
Mar 26 12:39:45 PM PDT 24 |
Mar 26 12:39:46 PM PDT 24 |
55874077 ps |
| T58 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2609420773 |
|
|
Mar 26 12:39:37 PM PDT 24 |
Mar 26 12:39:38 PM PDT 24 |
41981034 ps |
| T941 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1394085654 |
|
|
Mar 26 12:39:49 PM PDT 24 |
Mar 26 12:39:52 PM PDT 24 |
728577988 ps |
| T942 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2004938418 |
|
|
Mar 26 12:39:46 PM PDT 24 |
Mar 26 12:39:50 PM PDT 24 |
723918502 ps |
| T108 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2836321339 |
|
|
Mar 26 12:39:47 PM PDT 24 |
Mar 26 12:39:49 PM PDT 24 |
864105833 ps |
| T943 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2130753557 |
|
|
Mar 26 12:39:29 PM PDT 24 |
Mar 26 12:39:31 PM PDT 24 |
119586019 ps |
| T944 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.741430499 |
|
|
Mar 26 12:39:33 PM PDT 24 |
Mar 26 12:39:37 PM PDT 24 |
354085242 ps |
| T59 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3473400527 |
|
|
Mar 26 12:39:31 PM PDT 24 |
Mar 26 12:39:33 PM PDT 24 |
135965894 ps |
| T83 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3837465895 |
|
|
Mar 26 12:39:29 PM PDT 24 |
Mar 26 12:39:30 PM PDT 24 |
33630861 ps |
| T945 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3272940018 |
|
|
Mar 26 12:39:49 PM PDT 24 |
Mar 26 12:39:50 PM PDT 24 |
12980286 ps |
| T946 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2729954468 |
|
|
Mar 26 12:39:52 PM PDT 24 |
Mar 26 12:39:56 PM PDT 24 |
723234433 ps |
| T84 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3712152247 |
|
|
Mar 26 12:39:39 PM PDT 24 |
Mar 26 12:39:40 PM PDT 24 |
51327830 ps |
| T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2634019470 |
|
|
Mar 26 12:39:44 PM PDT 24 |
Mar 26 12:39:47 PM PDT 24 |
357048042 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3905824931 |
|
|
Mar 26 12:39:33 PM PDT 24 |
Mar 26 12:39:34 PM PDT 24 |
132766419 ps |
| T110 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1508252064 |
|
|
Mar 26 12:39:58 PM PDT 24 |
Mar 26 12:40:00 PM PDT 24 |
630348825 ps |
| T949 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1081297687 |
|
|
Mar 26 12:39:47 PM PDT 24 |
Mar 26 12:39:49 PM PDT 24 |
241029567 ps |
| T61 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3830022473 |
|
|
Mar 26 12:39:31 PM PDT 24 |
Mar 26 12:39:33 PM PDT 24 |
45632906 ps |
| T950 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3920944327 |
|
|
Mar 26 12:39:30 PM PDT 24 |
Mar 26 12:39:33 PM PDT 24 |
296665737 ps |
| T951 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1696888879 |
|
|
Mar 26 12:39:32 PM PDT 24 |
Mar 26 12:39:35 PM PDT 24 |
1504787813 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3932343276 |
|
|
Mar 26 12:39:28 PM PDT 24 |
Mar 26 12:39:33 PM PDT 24 |
671682908 ps |
| T953 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.686569078 |
|
|
Mar 26 12:39:33 PM PDT 24 |
Mar 26 12:39:37 PM PDT 24 |
714889357 ps |
| T954 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2239550587 |
|
|
Mar 26 12:39:59 PM PDT 24 |
Mar 26 12:40:02 PM PDT 24 |
85364517 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2683710201 |
|
|
Mar 26 12:39:47 PM PDT 24 |
Mar 26 12:39:50 PM PDT 24 |
398133510 ps |
| T112 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2918103501 |
|
|
Mar 26 12:39:32 PM PDT 24 |
Mar 26 12:39:35 PM PDT 24 |
652635529 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.642663099 |
|
|
Mar 26 12:39:45 PM PDT 24 |
Mar 26 12:39:49 PM PDT 24 |
2653153603 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.808753082 |
|
|
Mar 26 12:39:36 PM PDT 24 |
Mar 26 12:39:38 PM PDT 24 |
97442438 ps |
| T957 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1554345182 |
|
|
Mar 26 12:39:44 PM PDT 24 |
Mar 26 12:39:45 PM PDT 24 |
60115017 ps |
| T62 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3759975595 |
|
|
Mar 26 12:39:41 PM PDT 24 |
Mar 26 12:39:42 PM PDT 24 |
41792639 ps |
| T958 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2748295261 |
|
|
Mar 26 12:39:58 PM PDT 24 |
Mar 26 12:40:02 PM PDT 24 |
1492061418 ps |
| T959 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2532208573 |
|
|
Mar 26 12:39:52 PM PDT 24 |
Mar 26 12:39:53 PM PDT 24 |
43689981 ps |
| T63 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3268239029 |
|
|
Mar 26 12:39:37 PM PDT 24 |
Mar 26 12:40:05 PM PDT 24 |
3873677480 ps |
| T64 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2129022109 |
|
|
Mar 26 12:39:40 PM PDT 24 |
Mar 26 12:40:30 PM PDT 24 |
58867405894 ps |
| T113 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1566865280 |
|
|
Mar 26 12:39:40 PM PDT 24 |
Mar 26 12:39:43 PM PDT 24 |
184322737 ps |
| T65 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2442447339 |
|
|
Mar 26 12:39:30 PM PDT 24 |
Mar 26 12:39:32 PM PDT 24 |
47014177 ps |
| T66 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.995453686 |
|
|
Mar 26 12:39:34 PM PDT 24 |
Mar 26 12:39:35 PM PDT 24 |
54035957 ps |
| T67 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1507815119 |
|
|
Mar 26 12:39:53 PM PDT 24 |
Mar 26 12:40:45 PM PDT 24 |
14683281145 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.353766614 |
|
|
Mar 26 12:39:31 PM PDT 24 |
Mar 26 12:40:05 PM PDT 24 |
19424886413 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.541644535 |
|
|
Mar 26 12:39:38 PM PDT 24 |
Mar 26 12:40:05 PM PDT 24 |
7383246019 ps |
| T961 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.243467063 |
|
|
Mar 26 12:39:52 PM PDT 24 |
Mar 26 12:39:56 PM PDT 24 |
735060621 ps |
| T962 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3984314534 |
|
|
Mar 26 12:39:54 PM PDT 24 |
Mar 26 12:39:55 PM PDT 24 |
12701993 ps |
| T963 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2078298327 |
|
|
Mar 26 12:40:07 PM PDT 24 |
Mar 26 12:40:10 PM PDT 24 |
1419791924 ps |
| T964 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3462677997 |
|
|
Mar 26 12:39:49 PM PDT 24 |
Mar 26 12:39:50 PM PDT 24 |
63102877 ps |
| T965 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4231301753 |
|
|
Mar 26 12:39:27 PM PDT 24 |
Mar 26 12:39:31 PM PDT 24 |
348783491 ps |
| T966 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1820296710 |
|
|
Mar 26 12:39:31 PM PDT 24 |
Mar 26 12:39:59 PM PDT 24 |
3778296767 ps |
| T967 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.709782750 |
|
|
Mar 26 12:39:38 PM PDT 24 |
Mar 26 12:39:42 PM PDT 24 |
530150895 ps |
| T968 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2317271900 |
|
|
Mar 26 12:39:42 PM PDT 24 |
Mar 26 12:39:43 PM PDT 24 |
37549117 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1917419465 |
|
|
Mar 26 12:39:29 PM PDT 24 |
Mar 26 12:39:30 PM PDT 24 |
15761380 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2148692109 |
|
|
Mar 26 12:39:29 PM PDT 24 |
Mar 26 12:39:31 PM PDT 24 |
398901239 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3210157048 |
|
|
Mar 26 12:39:42 PM PDT 24 |
Mar 26 12:39:45 PM PDT 24 |
130344738 ps |
| T972 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1174300668 |
|
|
Mar 26 12:39:49 PM PDT 24 |
Mar 26 12:39:52 PM PDT 24 |
487751380 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2848615611 |
|
|
Mar 26 12:39:30 PM PDT 24 |
Mar 26 12:39:33 PM PDT 24 |
163615829 ps |
| T974 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2416518942 |
|
|
Mar 26 12:39:56 PM PDT 24 |
Mar 26 12:39:57 PM PDT 24 |
113245988 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3757424363 |
|
|
Mar 26 12:39:31 PM PDT 24 |
Mar 26 12:39:34 PM PDT 24 |
256806476 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.373970698 |
|
|
Mar 26 12:39:46 PM PDT 24 |
Mar 26 12:39:47 PM PDT 24 |
27779148 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1165742319 |
|
|
Mar 26 12:39:29 PM PDT 24 |
Mar 26 12:39:33 PM PDT 24 |
760219267 ps |
| T978 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2328346054 |
|
|
Mar 26 12:39:33 PM PDT 24 |
Mar 26 12:39:36 PM PDT 24 |
61513171 ps |
| T979 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2128136828 |
|
|
Mar 26 12:39:46 PM PDT 24 |
Mar 26 12:39:47 PM PDT 24 |
129523519 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1610194104 |
|
|
Mar 26 12:39:41 PM PDT 24 |
Mar 26 12:39:42 PM PDT 24 |
212520194 ps |
| T981 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2195053357 |
|
|
Mar 26 12:39:47 PM PDT 24 |
Mar 26 12:39:49 PM PDT 24 |
205364553 ps |
| T982 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.487938870 |
|
|
Mar 26 12:39:39 PM PDT 24 |
Mar 26 12:39:40 PM PDT 24 |
34389580 ps |
| T75 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1058453625 |
|
|
Mar 26 12:39:45 PM PDT 24 |
Mar 26 12:39:46 PM PDT 24 |
39607804 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.235508781 |
|
|
Mar 26 12:39:42 PM PDT 24 |
Mar 26 12:39:45 PM PDT 24 |
717509035 ps |
| T109 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.302879548 |
|
|
Mar 26 12:39:41 PM PDT 24 |
Mar 26 12:39:44 PM PDT 24 |
817768534 ps |
| T76 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.599287832 |
|
|
Mar 26 12:39:32 PM PDT 24 |
Mar 26 12:39:33 PM PDT 24 |
36722213 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1256607033 |
|
|
Mar 26 12:39:29 PM PDT 24 |
Mar 26 12:39:32 PM PDT 24 |
72875324 ps |
| T111 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1426789510 |
|
|
Mar 26 12:39:26 PM PDT 24 |
Mar 26 12:39:29 PM PDT 24 |
192302173 ps |
| T985 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2595702242 |
|
|
Mar 26 12:39:44 PM PDT 24 |
Mar 26 12:40:12 PM PDT 24 |
7387940258 ps |
| T986 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3842971070 |
|
|
Mar 26 12:39:33 PM PDT 24 |
Mar 26 12:40:00 PM PDT 24 |
14823882064 ps |
| T987 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3405088933 |
|
|
Mar 26 12:39:31 PM PDT 24 |
Mar 26 12:39:36 PM PDT 24 |
358360483 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3663922691 |
|
|
Mar 26 12:39:37 PM PDT 24 |
Mar 26 12:39:38 PM PDT 24 |
34640597 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1545632548 |
|
|
Mar 26 12:39:38 PM PDT 24 |
Mar 26 12:39:41 PM PDT 24 |
1381224060 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3487259503 |
|
|
Mar 26 12:39:36 PM PDT 24 |
Mar 26 12:39:37 PM PDT 24 |
27691897 ps |
| T991 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4126038772 |
|
|
Mar 26 12:39:39 PM PDT 24 |
Mar 26 12:39:40 PM PDT 24 |
18825851 ps |
| T77 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.641222044 |
|
|
Mar 26 12:39:47 PM PDT 24 |
Mar 26 12:40:13 PM PDT 24 |
7548689762 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2203589141 |
|
|
Mar 26 12:39:37 PM PDT 24 |
Mar 26 12:39:38 PM PDT 24 |
22485444 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.151817021 |
|
|
Mar 26 12:39:41 PM PDT 24 |
Mar 26 12:39:43 PM PDT 24 |
220519495 ps |
| T994 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3626112060 |
|
|
Mar 26 12:39:29 PM PDT 24 |
Mar 26 12:39:31 PM PDT 24 |
188348269 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1878573212 |
|
|
Mar 26 12:39:52 PM PDT 24 |
Mar 26 12:39:54 PM PDT 24 |
601823690 ps |
| T72 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2786904262 |
|
|
Mar 26 12:39:36 PM PDT 24 |
Mar 26 12:39:37 PM PDT 24 |
24268568 ps |
| T996 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.725993306 |
|
|
Mar 26 12:39:33 PM PDT 24 |
Mar 26 12:39:34 PM PDT 24 |
36499121 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2915147785 |
|
|
Mar 26 12:39:48 PM PDT 24 |
Mar 26 12:40:18 PM PDT 24 |
20486825331 ps |
| T114 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3188558071 |
|
|
Mar 26 12:39:42 PM PDT 24 |
Mar 26 12:39:43 PM PDT 24 |
112220912 ps |
| T998 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3167042984 |
|
|
Mar 26 12:39:49 PM PDT 24 |
Mar 26 12:39:51 PM PDT 24 |
74107492 ps |
| T999 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2573573973 |
|
|
Mar 26 12:39:36 PM PDT 24 |
Mar 26 12:39:37 PM PDT 24 |
18889540 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.460249669 |
|
|
Mar 26 12:39:36 PM PDT 24 |
Mar 26 12:39:37 PM PDT 24 |
37845421 ps |