| T302 |
/workspace/coverage/default/38.sram_ctrl_smoke.1374820004 |
|
|
Mar 28 02:50:32 PM PDT 24 |
Mar 28 02:52:47 PM PDT 24 |
1297071665 ps |
| T303 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3360512845 |
|
|
Mar 28 02:44:12 PM PDT 24 |
Mar 28 02:54:34 PM PDT 24 |
18708722612 ps |
| T304 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.3026509309 |
|
|
Mar 28 02:47:12 PM PDT 24 |
Mar 28 02:57:02 PM PDT 24 |
26692390993 ps |
| T305 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2414712730 |
|
|
Mar 28 02:52:58 PM PDT 24 |
Mar 28 02:59:18 PM PDT 24 |
27487893929 ps |
| T306 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2160468511 |
|
|
Mar 28 02:47:10 PM PDT 24 |
Mar 28 02:51:46 PM PDT 24 |
28714596919 ps |
| T307 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1608644791 |
|
|
Mar 28 02:52:56 PM PDT 24 |
Mar 28 02:53:00 PM PDT 24 |
355087001 ps |
| T308 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1578088832 |
|
|
Mar 28 02:44:33 PM PDT 24 |
Mar 28 02:48:47 PM PDT 24 |
4026001641 ps |
| T309 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2591076803 |
|
|
Mar 28 02:44:49 PM PDT 24 |
Mar 28 02:46:28 PM PDT 24 |
15455902699 ps |
| T310 |
/workspace/coverage/default/4.sram_ctrl_smoke.3542621189 |
|
|
Mar 28 02:44:02 PM PDT 24 |
Mar 28 02:44:41 PM PDT 24 |
1107542581 ps |
| T311 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.235778555 |
|
|
Mar 28 02:49:43 PM PDT 24 |
Mar 28 02:56:54 PM PDT 24 |
278755150431 ps |
| T312 |
/workspace/coverage/default/13.sram_ctrl_stress_all.725947078 |
|
|
Mar 28 02:45:53 PM PDT 24 |
Mar 28 03:18:48 PM PDT 24 |
38636271398 ps |
| T313 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2638938531 |
|
|
Mar 28 02:48:22 PM PDT 24 |
Mar 28 02:50:31 PM PDT 24 |
12330520333 ps |
| T314 |
/workspace/coverage/default/14.sram_ctrl_executable.1397689796 |
|
|
Mar 28 02:45:49 PM PDT 24 |
Mar 28 03:05:39 PM PDT 24 |
3781787676 ps |
| T315 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2730320379 |
|
|
Mar 28 02:45:26 PM PDT 24 |
Mar 28 02:51:03 PM PDT 24 |
11054186715 ps |
| T316 |
/workspace/coverage/default/16.sram_ctrl_smoke.412538866 |
|
|
Mar 28 02:46:12 PM PDT 24 |
Mar 28 02:46:30 PM PDT 24 |
562070548 ps |
| T317 |
/workspace/coverage/default/0.sram_ctrl_smoke.2176611581 |
|
|
Mar 28 02:43:22 PM PDT 24 |
Mar 28 02:44:14 PM PDT 24 |
445855993 ps |
| T134 |
/workspace/coverage/default/28.sram_ctrl_partial_access.2659083274 |
|
|
Mar 28 02:48:22 PM PDT 24 |
Mar 28 02:49:01 PM PDT 24 |
2075526208 ps |
| T108 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1403654942 |
|
|
Mar 28 02:44:03 PM PDT 24 |
Mar 28 02:44:37 PM PDT 24 |
2788206213 ps |
| T318 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.225876317 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 02:49:11 PM PDT 24 |
30795624094 ps |
| T319 |
/workspace/coverage/default/20.sram_ctrl_regwen.2699816030 |
|
|
Mar 28 02:46:47 PM PDT 24 |
Mar 28 03:05:31 PM PDT 24 |
2949392532 ps |
| T320 |
/workspace/coverage/default/4.sram_ctrl_stress_all.3291881049 |
|
|
Mar 28 02:44:17 PM PDT 24 |
Mar 28 04:16:00 PM PDT 24 |
614993094855 ps |
| T321 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2053290695 |
|
|
Mar 28 02:47:26 PM PDT 24 |
Mar 28 02:50:08 PM PDT 24 |
17129856157 ps |
| T322 |
/workspace/coverage/default/8.sram_ctrl_executable.3542869519 |
|
|
Mar 28 02:44:30 PM PDT 24 |
Mar 28 02:53:08 PM PDT 24 |
4809723935 ps |
| T323 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1199954645 |
|
|
Mar 28 02:45:08 PM PDT 24 |
Mar 28 02:45:23 PM PDT 24 |
1877243546 ps |
| T324 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.3978682464 |
|
|
Mar 28 02:46:49 PM PDT 24 |
Mar 28 02:46:52 PM PDT 24 |
1356940112 ps |
| T109 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3458854041 |
|
|
Mar 28 02:48:19 PM PDT 24 |
Mar 28 02:48:53 PM PDT 24 |
824200101 ps |
| T325 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3846628444 |
|
|
Mar 28 02:47:55 PM PDT 24 |
Mar 28 02:49:03 PM PDT 24 |
1178713778 ps |
| T326 |
/workspace/coverage/default/29.sram_ctrl_stress_all.1461822260 |
|
|
Mar 28 02:48:38 PM PDT 24 |
Mar 28 04:53:12 PM PDT 24 |
398364351839 ps |
| T327 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2354546365 |
|
|
Mar 28 02:47:28 PM PDT 24 |
Mar 28 02:48:05 PM PDT 24 |
758278930 ps |
| T328 |
/workspace/coverage/default/21.sram_ctrl_smoke.2435137369 |
|
|
Mar 28 02:46:48 PM PDT 24 |
Mar 28 02:49:32 PM PDT 24 |
836302077 ps |
| T329 |
/workspace/coverage/default/42.sram_ctrl_partial_access.46863262 |
|
|
Mar 28 02:51:59 PM PDT 24 |
Mar 28 02:52:17 PM PDT 24 |
2333717359 ps |
| T330 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1052596602 |
|
|
Mar 28 02:53:39 PM PDT 24 |
Mar 28 02:58:54 PM PDT 24 |
5201464212 ps |
| T331 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.2716337843 |
|
|
Mar 28 02:46:26 PM PDT 24 |
Mar 28 03:20:32 PM PDT 24 |
191874383665 ps |
| T332 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2857162562 |
|
|
Mar 28 02:48:23 PM PDT 24 |
Mar 28 02:49:37 PM PDT 24 |
920659749 ps |
| T333 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3310923453 |
|
|
Mar 28 02:49:00 PM PDT 24 |
Mar 28 02:50:05 PM PDT 24 |
3815356265 ps |
| T334 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2152360147 |
|
|
Mar 28 02:44:13 PM PDT 24 |
Mar 28 02:44:30 PM PDT 24 |
1748241422 ps |
| T335 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2559310370 |
|
|
Mar 28 02:52:59 PM PDT 24 |
Mar 28 02:53:27 PM PDT 24 |
3924917384 ps |
| T336 |
/workspace/coverage/default/31.sram_ctrl_partial_access.4058135024 |
|
|
Mar 28 02:49:08 PM PDT 24 |
Mar 28 02:49:28 PM PDT 24 |
1264830806 ps |
| T337 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.920009020 |
|
|
Mar 28 02:43:56 PM PDT 24 |
Mar 28 02:44:00 PM PDT 24 |
1361607738 ps |
| T338 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.3588104825 |
|
|
Mar 28 02:43:59 PM PDT 24 |
Mar 28 02:47:58 PM PDT 24 |
3983672247 ps |
| T339 |
/workspace/coverage/default/2.sram_ctrl_executable.1420257087 |
|
|
Mar 28 02:43:57 PM PDT 24 |
Mar 28 02:47:39 PM PDT 24 |
37137690182 ps |
| T340 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2329272723 |
|
|
Mar 28 02:48:21 PM PDT 24 |
Mar 28 02:51:42 PM PDT 24 |
14573826019 ps |
| T341 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1581785553 |
|
|
Mar 28 02:45:53 PM PDT 24 |
Mar 28 02:51:49 PM PDT 24 |
24905314168 ps |
| T342 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3520004809 |
|
|
Mar 28 02:52:32 PM PDT 24 |
Mar 28 02:53:53 PM PDT 24 |
4683525946 ps |
| T343 |
/workspace/coverage/default/48.sram_ctrl_stress_all.136011447 |
|
|
Mar 28 02:53:37 PM PDT 24 |
Mar 28 03:43:11 PM PDT 24 |
65582814219 ps |
| T344 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3223407322 |
|
|
Mar 28 02:46:37 PM PDT 24 |
Mar 28 02:50:27 PM PDT 24 |
22272598288 ps |
| T345 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1854105759 |
|
|
Mar 28 02:52:56 PM PDT 24 |
Mar 28 02:53:10 PM PDT 24 |
4282144109 ps |
| T346 |
/workspace/coverage/default/27.sram_ctrl_executable.942558668 |
|
|
Mar 28 02:48:22 PM PDT 24 |
Mar 28 03:05:59 PM PDT 24 |
349880574566 ps |
| T347 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2003924302 |
|
|
Mar 28 02:53:00 PM PDT 24 |
Mar 28 02:53:01 PM PDT 24 |
33782129 ps |
| T348 |
/workspace/coverage/default/25.sram_ctrl_smoke.1063712396 |
|
|
Mar 28 02:47:38 PM PDT 24 |
Mar 28 02:47:54 PM PDT 24 |
1722380355 ps |
| T349 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.4091292279 |
|
|
Mar 28 02:51:57 PM PDT 24 |
Mar 28 02:54:09 PM PDT 24 |
7896550258 ps |
| T350 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2630283353 |
|
|
Mar 28 02:53:36 PM PDT 24 |
Mar 28 02:56:47 PM PDT 24 |
14969922852 ps |
| T351 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.4025806081 |
|
|
Mar 28 02:51:59 PM PDT 24 |
Mar 28 02:52:02 PM PDT 24 |
353747366 ps |
| T352 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.3344482512 |
|
|
Mar 28 02:44:13 PM PDT 24 |
Mar 28 02:44:26 PM PDT 24 |
1412882067 ps |
| T353 |
/workspace/coverage/default/40.sram_ctrl_smoke.2938867413 |
|
|
Mar 28 02:51:12 PM PDT 24 |
Mar 28 02:51:34 PM PDT 24 |
2460308835 ps |
| T354 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.976289313 |
|
|
Mar 28 02:44:32 PM PDT 24 |
Mar 28 02:44:58 PM PDT 24 |
2935977156 ps |
| T355 |
/workspace/coverage/default/0.sram_ctrl_bijection.1194028562 |
|
|
Mar 28 02:43:21 PM PDT 24 |
Mar 28 03:04:28 PM PDT 24 |
69214657066 ps |
| T356 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1649561415 |
|
|
Mar 28 02:50:36 PM PDT 24 |
Mar 28 02:54:18 PM PDT 24 |
23755396031 ps |
| T357 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.638987624 |
|
|
Mar 28 02:50:36 PM PDT 24 |
Mar 28 02:50:44 PM PDT 24 |
459250173 ps |
| T358 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.179943747 |
|
|
Mar 28 02:43:56 PM PDT 24 |
Mar 28 02:44:18 PM PDT 24 |
2816390282 ps |
| T359 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.1716238596 |
|
|
Mar 28 02:50:35 PM PDT 24 |
Mar 28 02:52:03 PM PDT 24 |
2066469822 ps |
| T360 |
/workspace/coverage/default/38.sram_ctrl_partial_access.3186165148 |
|
|
Mar 28 02:50:35 PM PDT 24 |
Mar 28 02:52:16 PM PDT 24 |
7177545604 ps |
| T361 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.2956403026 |
|
|
Mar 28 02:52:00 PM PDT 24 |
Mar 28 02:52:13 PM PDT 24 |
852476307 ps |
| T362 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3499765079 |
|
|
Mar 28 02:45:06 PM PDT 24 |
Mar 28 02:48:53 PM PDT 24 |
4142300501 ps |
| T363 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3276107034 |
|
|
Mar 28 02:44:31 PM PDT 24 |
Mar 28 02:44:32 PM PDT 24 |
49479607 ps |
| T364 |
/workspace/coverage/default/45.sram_ctrl_bijection.386487 |
|
|
Mar 28 02:52:37 PM PDT 24 |
Mar 28 03:26:02 PM PDT 24 |
29703189769 ps |
| T365 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.907442047 |
|
|
Mar 28 02:50:34 PM PDT 24 |
Mar 28 02:53:06 PM PDT 24 |
10551942848 ps |
| T366 |
/workspace/coverage/default/34.sram_ctrl_stress_all.758328258 |
|
|
Mar 28 02:50:09 PM PDT 24 |
Mar 28 05:09:39 PM PDT 24 |
225316981435 ps |
| T367 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2735563909 |
|
|
Mar 28 02:44:16 PM PDT 24 |
Mar 28 02:46:19 PM PDT 24 |
4818676128 ps |
| T368 |
/workspace/coverage/default/34.sram_ctrl_regwen.2648839166 |
|
|
Mar 28 02:50:10 PM PDT 24 |
Mar 28 03:10:25 PM PDT 24 |
14097253031 ps |
| T369 |
/workspace/coverage/default/39.sram_ctrl_bijection.3656283994 |
|
|
Mar 28 02:50:50 PM PDT 24 |
Mar 28 03:05:11 PM PDT 24 |
24769441880 ps |
| T370 |
/workspace/coverage/default/35.sram_ctrl_smoke.1125465747 |
|
|
Mar 28 02:50:12 PM PDT 24 |
Mar 28 02:50:35 PM PDT 24 |
6164960354 ps |
| T371 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.1779500891 |
|
|
Mar 28 02:48:41 PM PDT 24 |
Mar 28 02:48:58 PM PDT 24 |
18494677927 ps |
| T372 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3179951274 |
|
|
Mar 28 02:47:55 PM PDT 24 |
Mar 28 02:48:48 PM PDT 24 |
17411082456 ps |
| T373 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3396392809 |
|
|
Mar 28 02:51:58 PM PDT 24 |
Mar 28 02:52:07 PM PDT 24 |
579084583 ps |
| T374 |
/workspace/coverage/default/20.sram_ctrl_alert_test.97499196 |
|
|
Mar 28 02:46:48 PM PDT 24 |
Mar 28 02:46:48 PM PDT 24 |
12478169 ps |
| T375 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2443636178 |
|
|
Mar 28 02:43:58 PM PDT 24 |
Mar 28 02:46:19 PM PDT 24 |
338250672559 ps |
| T376 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1868384138 |
|
|
Mar 28 02:45:06 PM PDT 24 |
Mar 28 02:50:02 PM PDT 24 |
12289477157 ps |
| T377 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3896736427 |
|
|
Mar 28 02:47:11 PM PDT 24 |
Mar 28 02:51:55 PM PDT 24 |
10156552875 ps |
| T378 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2368213573 |
|
|
Mar 28 02:47:55 PM PDT 24 |
Mar 28 02:58:44 PM PDT 24 |
99547517556 ps |
| T379 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2417809626 |
|
|
Mar 28 02:46:49 PM PDT 24 |
Mar 28 02:48:33 PM PDT 24 |
76323565393 ps |
| T380 |
/workspace/coverage/default/32.sram_ctrl_alert_test.67649316 |
|
|
Mar 28 02:49:19 PM PDT 24 |
Mar 28 02:49:19 PM PDT 24 |
12457181 ps |
| T381 |
/workspace/coverage/default/28.sram_ctrl_executable.497853972 |
|
|
Mar 28 02:48:21 PM PDT 24 |
Mar 28 03:10:27 PM PDT 24 |
24240411559 ps |
| T382 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.147311244 |
|
|
Mar 28 02:43:17 PM PDT 24 |
Mar 28 02:49:28 PM PDT 24 |
18918772003 ps |
| T383 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1820820958 |
|
|
Mar 28 02:45:09 PM PDT 24 |
Mar 28 02:47:44 PM PDT 24 |
1794838715 ps |
| T384 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1272997535 |
|
|
Mar 28 02:52:59 PM PDT 24 |
Mar 28 02:55:23 PM PDT 24 |
18062544209 ps |
| T385 |
/workspace/coverage/default/8.sram_ctrl_smoke.1205118930 |
|
|
Mar 28 02:44:30 PM PDT 24 |
Mar 28 02:44:38 PM PDT 24 |
832971371 ps |
| T386 |
/workspace/coverage/default/28.sram_ctrl_regwen.2024947407 |
|
|
Mar 28 02:48:22 PM PDT 24 |
Mar 28 02:48:43 PM PDT 24 |
635064528 ps |
| T387 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.2021591361 |
|
|
Mar 28 02:47:36 PM PDT 24 |
Mar 28 02:52:33 PM PDT 24 |
81016517193 ps |
| T388 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2658567804 |
|
|
Mar 28 02:51:18 PM PDT 24 |
Mar 28 02:51:27 PM PDT 24 |
703328143 ps |
| T389 |
/workspace/coverage/default/24.sram_ctrl_smoke.3065554080 |
|
|
Mar 28 02:47:26 PM PDT 24 |
Mar 28 02:49:35 PM PDT 24 |
1383036713 ps |
| T390 |
/workspace/coverage/default/14.sram_ctrl_alert_test.995832863 |
|
|
Mar 28 02:45:48 PM PDT 24 |
Mar 28 02:45:49 PM PDT 24 |
42418578 ps |
| T391 |
/workspace/coverage/default/49.sram_ctrl_regwen.610212444 |
|
|
Mar 28 02:53:36 PM PDT 24 |
Mar 28 03:21:19 PM PDT 24 |
45287208426 ps |
| T82 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2383546577 |
|
|
Mar 28 02:48:37 PM PDT 24 |
Mar 28 02:50:48 PM PDT 24 |
19416090885 ps |
| T392 |
/workspace/coverage/default/21.sram_ctrl_regwen.3479669901 |
|
|
Mar 28 02:46:49 PM PDT 24 |
Mar 28 02:58:50 PM PDT 24 |
3069335415 ps |
| T393 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.190783850 |
|
|
Mar 28 02:47:13 PM PDT 24 |
Mar 28 02:48:00 PM PDT 24 |
7766333021 ps |
| T394 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1827644195 |
|
|
Mar 28 02:45:07 PM PDT 24 |
Mar 28 02:45:36 PM PDT 24 |
6547072129 ps |
| T395 |
/workspace/coverage/default/8.sram_ctrl_bijection.655858991 |
|
|
Mar 28 02:44:32 PM PDT 24 |
Mar 28 03:18:22 PM PDT 24 |
119654174867 ps |
| T133 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1714476626 |
|
|
Mar 28 02:44:31 PM PDT 24 |
Mar 28 02:47:53 PM PDT 24 |
10257063440 ps |
| T396 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1084961743 |
|
|
Mar 28 02:52:58 PM PDT 24 |
Mar 28 02:53:01 PM PDT 24 |
357331795 ps |
| T397 |
/workspace/coverage/default/47.sram_ctrl_regwen.3304503948 |
|
|
Mar 28 02:53:14 PM PDT 24 |
Mar 28 03:10:02 PM PDT 24 |
15841780220 ps |
| T398 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3438025201 |
|
|
Mar 28 02:50:32 PM PDT 24 |
Mar 28 02:50:36 PM PDT 24 |
1345381974 ps |
| T399 |
/workspace/coverage/default/15.sram_ctrl_executable.2221777238 |
|
|
Mar 28 02:45:49 PM PDT 24 |
Mar 28 02:48:34 PM PDT 24 |
6696080367 ps |
| T400 |
/workspace/coverage/default/21.sram_ctrl_bijection.2928523663 |
|
|
Mar 28 02:46:48 PM PDT 24 |
Mar 28 02:56:12 PM PDT 24 |
39057839351 ps |
| T401 |
/workspace/coverage/default/42.sram_ctrl_bijection.2076155130 |
|
|
Mar 28 02:51:34 PM PDT 24 |
Mar 28 03:26:39 PM PDT 24 |
112912374297 ps |
| T402 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3086849513 |
|
|
Mar 28 02:53:38 PM PDT 24 |
Mar 28 02:53:41 PM PDT 24 |
666939963 ps |
| T403 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.631064976 |
|
|
Mar 28 02:51:11 PM PDT 24 |
Mar 28 02:51:23 PM PDT 24 |
501420211 ps |
| T404 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3901566253 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:44:30 PM PDT 24 |
1468343956 ps |
| T405 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4221843672 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 02:53:15 PM PDT 24 |
23598480227 ps |
| T406 |
/workspace/coverage/default/39.sram_ctrl_executable.2284627783 |
|
|
Mar 28 02:50:50 PM PDT 24 |
Mar 28 02:54:49 PM PDT 24 |
6640611664 ps |
| T407 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2612979336 |
|
|
Mar 28 02:45:47 PM PDT 24 |
Mar 28 02:49:04 PM PDT 24 |
33345778110 ps |
| T408 |
/workspace/coverage/default/25.sram_ctrl_partial_access.1177201547 |
|
|
Mar 28 02:47:27 PM PDT 24 |
Mar 28 02:47:56 PM PDT 24 |
697297517 ps |
| T409 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3781515660 |
|
|
Mar 28 02:51:13 PM PDT 24 |
Mar 28 03:03:17 PM PDT 24 |
21439551996 ps |
| T410 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3164165134 |
|
|
Mar 28 02:43:16 PM PDT 24 |
Mar 28 03:01:08 PM PDT 24 |
48138461433 ps |
| T411 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.294381722 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 02:53:14 PM PDT 24 |
12054099589 ps |
| T412 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4035525023 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 02:46:11 PM PDT 24 |
1286439581 ps |
| T413 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1132820083 |
|
|
Mar 28 02:51:34 PM PDT 24 |
Mar 28 02:54:05 PM PDT 24 |
10342602845 ps |
| T414 |
/workspace/coverage/default/38.sram_ctrl_bijection.2943904422 |
|
|
Mar 28 02:50:35 PM PDT 24 |
Mar 28 03:21:56 PM PDT 24 |
398779912771 ps |
| T415 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3482360370 |
|
|
Mar 28 02:49:08 PM PDT 24 |
Mar 28 02:50:02 PM PDT 24 |
25150156863 ps |
| T416 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1770570495 |
|
|
Mar 28 02:52:58 PM PDT 24 |
Mar 28 02:53:07 PM PDT 24 |
1354417791 ps |
| T417 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3031473168 |
|
|
Mar 28 02:51:13 PM PDT 24 |
Mar 28 02:56:01 PM PDT 24 |
4221851665 ps |
| T418 |
/workspace/coverage/default/37.sram_ctrl_stress_all.3164731169 |
|
|
Mar 28 02:50:36 PM PDT 24 |
Mar 28 03:44:00 PM PDT 24 |
434658663879 ps |
| T419 |
/workspace/coverage/default/13.sram_ctrl_bijection.2912092913 |
|
|
Mar 28 02:45:27 PM PDT 24 |
Mar 28 02:53:02 PM PDT 24 |
26514540787 ps |
| T420 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2369095286 |
|
|
Mar 28 02:44:49 PM PDT 24 |
Mar 28 02:44:52 PM PDT 24 |
1406286965 ps |
| T421 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.635171463 |
|
|
Mar 28 02:44:31 PM PDT 24 |
Mar 28 02:48:31 PM PDT 24 |
47509171663 ps |
| T422 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.3122918468 |
|
|
Mar 28 02:51:13 PM PDT 24 |
Mar 28 02:52:01 PM PDT 24 |
15403968891 ps |
| T423 |
/workspace/coverage/default/43.sram_ctrl_regwen.2130861213 |
|
|
Mar 28 02:51:58 PM PDT 24 |
Mar 28 03:19:33 PM PDT 24 |
21209061300 ps |
| T424 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.576412180 |
|
|
Mar 28 02:47:55 PM PDT 24 |
Mar 28 02:47:59 PM PDT 24 |
1354972716 ps |
| T425 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2230083696 |
|
|
Mar 28 02:46:12 PM PDT 24 |
Mar 28 02:47:23 PM PDT 24 |
812404688 ps |
| T426 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2748195246 |
|
|
Mar 28 02:44:50 PM PDT 24 |
Mar 28 02:49:54 PM PDT 24 |
4986337588 ps |
| T427 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.2194070031 |
|
|
Mar 28 02:47:13 PM PDT 24 |
Mar 28 02:48:02 PM PDT 24 |
761890098 ps |
| T428 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2806954084 |
|
|
Mar 28 02:45:51 PM PDT 24 |
Mar 28 02:47:56 PM PDT 24 |
3174878096 ps |
| T429 |
/workspace/coverage/default/41.sram_ctrl_partial_access.2940478693 |
|
|
Mar 28 02:51:36 PM PDT 24 |
Mar 28 02:51:56 PM PDT 24 |
2757059649 ps |
| T430 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1995485646 |
|
|
Mar 28 02:52:32 PM PDT 24 |
Mar 28 02:58:05 PM PDT 24 |
82546334809 ps |
| T431 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.686251175 |
|
|
Mar 28 02:46:11 PM PDT 24 |
Mar 28 02:48:47 PM PDT 24 |
1569384036 ps |
| T432 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3552449159 |
|
|
Mar 28 02:53:16 PM PDT 24 |
Mar 28 02:56:41 PM PDT 24 |
22970364966 ps |
| T433 |
/workspace/coverage/default/11.sram_ctrl_smoke.1939535208 |
|
|
Mar 28 02:45:06 PM PDT 24 |
Mar 28 02:45:22 PM PDT 24 |
1683833503 ps |
| T434 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1779357915 |
|
|
Mar 28 02:45:26 PM PDT 24 |
Mar 28 02:48:05 PM PDT 24 |
2817002555 ps |
| T435 |
/workspace/coverage/default/44.sram_ctrl_regwen.1486513903 |
|
|
Mar 28 02:52:32 PM PDT 24 |
Mar 28 03:04:49 PM PDT 24 |
11974961609 ps |
| T436 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3229681909 |
|
|
Mar 28 02:46:48 PM PDT 24 |
Mar 28 02:47:20 PM PDT 24 |
3032456373 ps |
| T437 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.134216077 |
|
|
Mar 28 02:48:24 PM PDT 24 |
Mar 28 03:03:36 PM PDT 24 |
114024150393 ps |
| T438 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2929054660 |
|
|
Mar 28 02:51:59 PM PDT 24 |
Mar 28 02:53:06 PM PDT 24 |
748559105 ps |
| T439 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2206330428 |
|
|
Mar 28 02:46:46 PM PDT 24 |
Mar 28 02:51:06 PM PDT 24 |
4888457634 ps |
| T440 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.166616438 |
|
|
Mar 28 02:52:57 PM PDT 24 |
Mar 28 03:11:37 PM PDT 24 |
15192489596 ps |
| T441 |
/workspace/coverage/default/7.sram_ctrl_regwen.3706563254 |
|
|
Mar 28 02:44:32 PM PDT 24 |
Mar 28 03:05:45 PM PDT 24 |
5066665092 ps |
| T442 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2394800564 |
|
|
Mar 28 02:46:08 PM PDT 24 |
Mar 28 02:46:10 PM PDT 24 |
41209094 ps |
| T443 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3030844735 |
|
|
Mar 28 02:47:27 PM PDT 24 |
Mar 28 02:47:44 PM PDT 24 |
5892253996 ps |
| T444 |
/workspace/coverage/default/44.sram_ctrl_smoke.3484237289 |
|
|
Mar 28 02:52:32 PM PDT 24 |
Mar 28 02:52:50 PM PDT 24 |
658519774 ps |
| T445 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1962599456 |
|
|
Mar 28 02:49:08 PM PDT 24 |
Mar 28 02:49:11 PM PDT 24 |
1409046800 ps |
| T446 |
/workspace/coverage/default/37.sram_ctrl_alert_test.2231118217 |
|
|
Mar 28 02:50:39 PM PDT 24 |
Mar 28 02:50:39 PM PDT 24 |
18092081 ps |
| T447 |
/workspace/coverage/default/1.sram_ctrl_smoke.732818315 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:43:57 PM PDT 24 |
2641620979 ps |
| T448 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.950467828 |
|
|
Mar 28 02:46:27 PM PDT 24 |
Mar 28 02:56:02 PM PDT 24 |
92298229453 ps |
| T110 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1690842184 |
|
|
Mar 28 02:49:20 PM PDT 24 |
Mar 28 02:50:31 PM PDT 24 |
41150455254 ps |
| T449 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3003352773 |
|
|
Mar 28 02:46:15 PM PDT 24 |
Mar 28 02:46:22 PM PDT 24 |
1502857578 ps |
| T450 |
/workspace/coverage/default/38.sram_ctrl_regwen.2265325006 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 03:18:10 PM PDT 24 |
4263452534 ps |
| T451 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2247482512 |
|
|
Mar 28 02:50:35 PM PDT 24 |
Mar 28 03:07:27 PM PDT 24 |
58083986725 ps |
| T452 |
/workspace/coverage/default/49.sram_ctrl_bijection.4090174094 |
|
|
Mar 28 02:53:36 PM PDT 24 |
Mar 28 03:23:06 PM PDT 24 |
112668931642 ps |
| T453 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3034813600 |
|
|
Mar 28 02:48:37 PM PDT 24 |
Mar 28 02:49:08 PM PDT 24 |
27512659948 ps |
| T454 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.4223368196 |
|
|
Mar 28 02:49:43 PM PDT 24 |
Mar 28 02:51:02 PM PDT 24 |
796410723 ps |
| T455 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4257247447 |
|
|
Mar 28 02:43:41 PM PDT 24 |
Mar 28 02:44:30 PM PDT 24 |
7258779707 ps |
| T456 |
/workspace/coverage/default/26.sram_ctrl_partial_access.706865349 |
|
|
Mar 28 02:47:53 PM PDT 24 |
Mar 28 02:50:36 PM PDT 24 |
2597856216 ps |
| T457 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3235073641 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:43:46 PM PDT 24 |
2415194698 ps |
| T458 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.286713028 |
|
|
Mar 28 02:45:08 PM PDT 24 |
Mar 28 02:46:08 PM PDT 24 |
7356317444 ps |
| T459 |
/workspace/coverage/default/7.sram_ctrl_executable.2402316209 |
|
|
Mar 28 02:44:29 PM PDT 24 |
Mar 28 02:53:24 PM PDT 24 |
3043288900 ps |
| T460 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4249447986 |
|
|
Mar 28 02:47:13 PM PDT 24 |
Mar 28 02:49:40 PM PDT 24 |
16575646824 ps |
| T461 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3335935558 |
|
|
Mar 28 02:46:11 PM PDT 24 |
Mar 28 02:46:31 PM PDT 24 |
1177261665 ps |
| T462 |
/workspace/coverage/default/40.sram_ctrl_executable.2627501497 |
|
|
Mar 28 02:51:18 PM PDT 24 |
Mar 28 02:57:13 PM PDT 24 |
6438128972 ps |
| T463 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1553498292 |
|
|
Mar 28 02:51:36 PM PDT 24 |
Mar 28 02:58:40 PM PDT 24 |
23215946576 ps |
| T464 |
/workspace/coverage/default/34.sram_ctrl_executable.3403633496 |
|
|
Mar 28 02:50:09 PM PDT 24 |
Mar 28 03:07:21 PM PDT 24 |
27401217830 ps |
| T465 |
/workspace/coverage/default/48.sram_ctrl_executable.2722206590 |
|
|
Mar 28 02:53:36 PM PDT 24 |
Mar 28 03:20:15 PM PDT 24 |
18841833468 ps |
| T466 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.34343892 |
|
|
Mar 28 02:46:09 PM PDT 24 |
Mar 28 02:47:21 PM PDT 24 |
69169730013 ps |
| T467 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.4185523042 |
|
|
Mar 28 02:51:35 PM PDT 24 |
Mar 28 02:53:01 PM PDT 24 |
16308462493 ps |
| T468 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2139255452 |
|
|
Mar 28 02:46:08 PM PDT 24 |
Mar 28 02:48:55 PM PDT 24 |
44717977593 ps |
| T469 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2092367080 |
|
|
Mar 28 02:52:31 PM PDT 24 |
Mar 28 02:52:32 PM PDT 24 |
12888906 ps |
| T470 |
/workspace/coverage/default/16.sram_ctrl_bijection.154169077 |
|
|
Mar 28 02:46:12 PM PDT 24 |
Mar 28 03:22:21 PM PDT 24 |
92114362370 ps |
| T471 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2096596614 |
|
|
Mar 28 02:44:30 PM PDT 24 |
Mar 28 02:46:57 PM PDT 24 |
1559102073 ps |
| T472 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.232278377 |
|
|
Mar 28 02:44:32 PM PDT 24 |
Mar 28 02:44:40 PM PDT 24 |
1390350790 ps |
| T473 |
/workspace/coverage/default/3.sram_ctrl_alert_test.339061688 |
|
|
Mar 28 02:44:03 PM PDT 24 |
Mar 28 02:44:04 PM PDT 24 |
22209108 ps |
| T474 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.2862973707 |
|
|
Mar 28 02:48:23 PM PDT 24 |
Mar 28 02:49:37 PM PDT 24 |
2483840632 ps |
| T475 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3592447748 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:51:08 PM PDT 24 |
39044359090 ps |
| T476 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2796207719 |
|
|
Mar 28 02:52:57 PM PDT 24 |
Mar 28 02:59:02 PM PDT 24 |
14338933542 ps |
| T477 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.641782657 |
|
|
Mar 28 02:45:27 PM PDT 24 |
Mar 28 02:47:32 PM PDT 24 |
3785630540 ps |
| T478 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3016450558 |
|
|
Mar 28 02:44:30 PM PDT 24 |
Mar 28 02:44:39 PM PDT 24 |
3037329301 ps |
| T479 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.388832181 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 02:47:39 PM PDT 24 |
10226805294 ps |
| T480 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.4222179914 |
|
|
Mar 28 02:46:48 PM PDT 24 |
Mar 28 02:57:01 PM PDT 24 |
22424516651 ps |
| T481 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1477715585 |
|
|
Mar 28 02:53:15 PM PDT 24 |
Mar 28 02:53:34 PM PDT 24 |
2186369541 ps |
| T482 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1230783741 |
|
|
Mar 28 02:43:41 PM PDT 24 |
Mar 28 02:46:09 PM PDT 24 |
7142286433 ps |
| T483 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.747694854 |
|
|
Mar 28 02:48:23 PM PDT 24 |
Mar 28 02:48:26 PM PDT 24 |
1350850455 ps |
| T484 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3937981834 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 02:43:49 PM PDT 24 |
2802941339 ps |
| T485 |
/workspace/coverage/default/32.sram_ctrl_bijection.1231100827 |
|
|
Mar 28 02:49:02 PM PDT 24 |
Mar 28 03:02:47 PM PDT 24 |
25288754745 ps |
| T486 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.2543395441 |
|
|
Mar 28 02:52:56 PM PDT 24 |
Mar 28 02:54:05 PM PDT 24 |
759904650 ps |
| T487 |
/workspace/coverage/default/12.sram_ctrl_bijection.3300119562 |
|
|
Mar 28 02:45:26 PM PDT 24 |
Mar 28 03:20:48 PM PDT 24 |
61188079251 ps |
| T488 |
/workspace/coverage/default/17.sram_ctrl_stress_all.3010116444 |
|
|
Mar 28 02:46:08 PM PDT 24 |
Mar 28 04:22:06 PM PDT 24 |
313943277363 ps |
| T489 |
/workspace/coverage/default/28.sram_ctrl_bijection.1553506676 |
|
|
Mar 28 02:48:24 PM PDT 24 |
Mar 28 03:12:29 PM PDT 24 |
83353946867 ps |
| T490 |
/workspace/coverage/default/9.sram_ctrl_bijection.796510408 |
|
|
Mar 28 02:44:48 PM PDT 24 |
Mar 28 02:54:18 PM PDT 24 |
51771414106 ps |
| T491 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2624812453 |
|
|
Mar 28 02:53:17 PM PDT 24 |
Mar 28 02:54:20 PM PDT 24 |
4941022831 ps |
| T492 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.174018196 |
|
|
Mar 28 02:49:19 PM PDT 24 |
Mar 28 02:49:36 PM PDT 24 |
2787621638 ps |
| T493 |
/workspace/coverage/default/10.sram_ctrl_regwen.2901084990 |
|
|
Mar 28 02:45:05 PM PDT 24 |
Mar 28 03:03:39 PM PDT 24 |
3432288118 ps |
| T494 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.498670613 |
|
|
Mar 28 02:52:58 PM PDT 24 |
Mar 28 02:53:24 PM PDT 24 |
717598039 ps |
| T495 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3087836525 |
|
|
Mar 28 02:49:42 PM PDT 24 |
Mar 28 02:51:20 PM PDT 24 |
1883545210 ps |
| T496 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3115856300 |
|
|
Mar 28 02:48:38 PM PDT 24 |
Mar 28 02:48:44 PM PDT 24 |
2788461777 ps |
| T497 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2094836171 |
|
|
Mar 28 02:53:14 PM PDT 24 |
Mar 28 03:11:20 PM PDT 24 |
149160786461 ps |
| T498 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1373151749 |
|
|
Mar 28 02:48:22 PM PDT 24 |
Mar 28 02:50:41 PM PDT 24 |
844372484 ps |
| T499 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.602944456 |
|
|
Mar 28 02:48:41 PM PDT 24 |
Mar 28 02:50:05 PM PDT 24 |
747707235 ps |
| T500 |
/workspace/coverage/default/34.sram_ctrl_smoke.3145716455 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:49:46 PM PDT 24 |
379926079 ps |
| T501 |
/workspace/coverage/default/46.sram_ctrl_smoke.2949872129 |
|
|
Mar 28 02:52:56 PM PDT 24 |
Mar 28 02:53:12 PM PDT 24 |
3232365441 ps |
| T502 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2577762375 |
|
|
Mar 28 02:46:27 PM PDT 24 |
Mar 28 02:48:22 PM PDT 24 |
776083764 ps |
| T503 |
/workspace/coverage/default/37.sram_ctrl_partial_access.1356832400 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 02:50:50 PM PDT 24 |
4510986031 ps |
| T504 |
/workspace/coverage/default/23.sram_ctrl_bijection.54862949 |
|
|
Mar 28 02:47:14 PM PDT 24 |
Mar 28 03:09:46 PM PDT 24 |
61215224238 ps |
| T505 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.415130815 |
|
|
Mar 28 02:45:47 PM PDT 24 |
Mar 28 02:47:11 PM PDT 24 |
9376331404 ps |
| T506 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2232214066 |
|
|
Mar 28 02:49:20 PM PDT 24 |
Mar 28 02:54:13 PM PDT 24 |
14348154203 ps |
| T507 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3224824701 |
|
|
Mar 28 02:46:46 PM PDT 24 |
Mar 28 02:48:01 PM PDT 24 |
6031741658 ps |
| T508 |
/workspace/coverage/default/1.sram_ctrl_partial_access.515600151 |
|
|
Mar 28 02:43:40 PM PDT 24 |
Mar 28 02:43:58 PM PDT 24 |
4487345798 ps |
| T509 |
/workspace/coverage/default/30.sram_ctrl_alert_test.2171864725 |
|
|
Mar 28 02:49:03 PM PDT 24 |
Mar 28 02:49:04 PM PDT 24 |
17488098 ps |
| T510 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.30497499 |
|
|
Mar 28 02:50:30 PM PDT 24 |
Mar 28 02:51:38 PM PDT 24 |
14881729178 ps |
| T511 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3600665014 |
|
|
Mar 28 02:44:33 PM PDT 24 |
Mar 28 02:46:33 PM PDT 24 |
1621596253 ps |
| T512 |
/workspace/coverage/default/11.sram_ctrl_stress_all.115124590 |
|
|
Mar 28 02:45:10 PM PDT 24 |
Mar 28 04:08:34 PM PDT 24 |
522511943740 ps |
| T513 |
/workspace/coverage/default/27.sram_ctrl_stress_all.4293026511 |
|
|
Mar 28 02:48:22 PM PDT 24 |
Mar 28 03:56:00 PM PDT 24 |
190711482372 ps |
| T514 |
/workspace/coverage/default/22.sram_ctrl_regwen.1993310840 |
|
|
Mar 28 02:47:09 PM PDT 24 |
Mar 28 03:04:25 PM PDT 24 |
2326838159 ps |
| T515 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.896686953 |
|
|
Mar 28 02:51:34 PM PDT 24 |
Mar 28 02:51:58 PM PDT 24 |
606994609 ps |
| T516 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3354254727 |
|
|
Mar 28 02:52:57 PM PDT 24 |
Mar 28 02:55:22 PM PDT 24 |
7184520159 ps |
| T517 |
/workspace/coverage/default/14.sram_ctrl_regwen.2102346449 |
|
|
Mar 28 02:45:47 PM PDT 24 |
Mar 28 02:48:42 PM PDT 24 |
4819368943 ps |
| T518 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.249877426 |
|
|
Mar 28 02:52:31 PM PDT 24 |
Mar 28 02:53:06 PM PDT 24 |
6480982766 ps |
| T519 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3275611845 |
|
|
Mar 28 02:44:47 PM PDT 24 |
Mar 28 02:46:03 PM PDT 24 |
2852185943 ps |
| T520 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.530090364 |
|
|
Mar 28 02:44:50 PM PDT 24 |
Mar 28 02:47:29 PM PDT 24 |
4666732484 ps |
| T521 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1958707175 |
|
|
Mar 28 02:50:34 PM PDT 24 |
Mar 28 02:50:37 PM PDT 24 |
2099885895 ps |
| T522 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1671049722 |
|
|
Mar 28 02:49:20 PM PDT 24 |
Mar 28 02:53:23 PM PDT 24 |
17322625661 ps |
| T523 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3499215731 |
|
|
Mar 28 02:50:36 PM PDT 24 |
Mar 28 02:52:41 PM PDT 24 |
1555126502 ps |
| T524 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1639199788 |
|
|
Mar 28 02:46:11 PM PDT 24 |
Mar 28 02:51:16 PM PDT 24 |
47358150625 ps |
| T525 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2028907733 |
|
|
Mar 28 02:49:19 PM PDT 24 |
Mar 28 02:52:40 PM PDT 24 |
2979723676 ps |
| T526 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1929449653 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:43:54 PM PDT 24 |
1376487343 ps |
| T527 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.295546054 |
|
|
Mar 28 02:48:21 PM PDT 24 |
Mar 28 02:55:57 PM PDT 24 |
74212865587 ps |
| T34 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.543791747 |
|
|
Mar 28 02:43:58 PM PDT 24 |
Mar 28 02:44:01 PM PDT 24 |
240174571 ps |
| T528 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4156614308 |
|
|
Mar 28 02:45:07 PM PDT 24 |
Mar 28 02:53:12 PM PDT 24 |
240429803354 ps |
| T529 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1475480714 |
|
|
Mar 28 02:44:49 PM PDT 24 |
Mar 28 02:44:50 PM PDT 24 |
22875255 ps |
| T530 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.1722361887 |
|
|
Mar 28 02:46:46 PM PDT 24 |
Mar 28 02:47:29 PM PDT 24 |
13747190870 ps |
| T531 |
/workspace/coverage/default/2.sram_ctrl_bijection.2715930680 |
|
|
Mar 28 02:43:44 PM PDT 24 |
Mar 28 03:19:06 PM PDT 24 |
383864841086 ps |
| T532 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2786163835 |
|
|
Mar 28 02:50:53 PM PDT 24 |
Mar 28 02:54:10 PM PDT 24 |
33805480112 ps |
| T533 |
/workspace/coverage/default/0.sram_ctrl_partial_access.1551329964 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 02:43:55 PM PDT 24 |
3365119752 ps |
| T534 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.102083178 |
|
|
Mar 28 02:52:56 PM PDT 24 |
Mar 28 02:59:05 PM PDT 24 |
9919006169 ps |
| T535 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1598592675 |
|
|
Mar 28 02:48:40 PM PDT 24 |
Mar 28 02:53:48 PM PDT 24 |
19337147040 ps |
| T536 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.4014795463 |
|
|
Mar 28 02:48:57 PM PDT 24 |
Mar 28 02:52:26 PM PDT 24 |
13125406579 ps |
| T537 |
/workspace/coverage/default/44.sram_ctrl_executable.1854420869 |
|
|
Mar 28 02:52:32 PM PDT 24 |
Mar 28 03:16:39 PM PDT 24 |
31399250347 ps |
| T538 |
/workspace/coverage/default/32.sram_ctrl_smoke.2715753902 |
|
|
Mar 28 02:49:03 PM PDT 24 |
Mar 28 02:49:24 PM PDT 24 |
13203313117 ps |
| T539 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3860818697 |
|
|
Mar 28 02:46:08 PM PDT 24 |
Mar 28 02:47:25 PM PDT 24 |
9793095053 ps |
| T540 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.338407032 |
|
|
Mar 28 02:47:10 PM PDT 24 |
Mar 28 02:48:22 PM PDT 24 |
15669911161 ps |
| T541 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1942039965 |
|
|
Mar 28 02:47:28 PM PDT 24 |
Mar 28 02:53:53 PM PDT 24 |
16712173274 ps |
| T542 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2698323145 |
|
|
Mar 28 02:46:47 PM PDT 24 |
Mar 28 03:00:29 PM PDT 24 |
26850687642 ps |
| T543 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1660746843 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:51:23 PM PDT 24 |
6013029414 ps |
| T544 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1500595699 |
|
|
Mar 28 02:44:17 PM PDT 24 |
Mar 28 02:46:49 PM PDT 24 |
1604301142 ps |