| T795 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1929407199 |
|
|
Mar 28 02:51:14 PM PDT 24 |
Mar 28 02:51:18 PM PDT 24 |
1404929075 ps |
| T796 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2666278634 |
|
|
Mar 28 02:51:36 PM PDT 24 |
Mar 28 02:51:37 PM PDT 24 |
17499694 ps |
| T797 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.312588882 |
|
|
Mar 28 02:48:23 PM PDT 24 |
Mar 28 02:48:31 PM PDT 24 |
256643491 ps |
| T798 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.2571461443 |
|
|
Mar 28 02:51:13 PM PDT 24 |
Mar 28 03:06:05 PM PDT 24 |
12006190762 ps |
| T799 |
/workspace/coverage/default/3.sram_ctrl_stress_all.2588551333 |
|
|
Mar 28 02:44:01 PM PDT 24 |
Mar 28 04:28:43 PM PDT 24 |
78579891246 ps |
| T800 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1511591795 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 02:54:11 PM PDT 24 |
8571922952 ps |
| T801 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1438276901 |
|
|
Mar 28 02:46:12 PM PDT 24 |
Mar 28 02:48:14 PM PDT 24 |
1024487514 ps |
| T802 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1579865101 |
|
|
Mar 28 02:46:07 PM PDT 24 |
Mar 28 02:46:08 PM PDT 24 |
43748951 ps |
| T803 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.4127020886 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 02:52:27 PM PDT 24 |
765521601 ps |
| T804 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3562531530 |
|
|
Mar 28 02:46:47 PM PDT 24 |
Mar 28 02:47:54 PM PDT 24 |
4124827370 ps |
| T805 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.1254779654 |
|
|
Mar 28 02:46:10 PM PDT 24 |
Mar 28 03:06:44 PM PDT 24 |
261519837530 ps |
| T806 |
/workspace/coverage/default/23.sram_ctrl_partial_access.1953420098 |
|
|
Mar 28 02:47:11 PM PDT 24 |
Mar 28 02:48:58 PM PDT 24 |
9895376153 ps |
| T807 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1268435711 |
|
|
Mar 28 02:49:42 PM PDT 24 |
Mar 28 02:50:43 PM PDT 24 |
40893082164 ps |
| T808 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.1629877635 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:51:58 PM PDT 24 |
110778529753 ps |
| T809 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.294296773 |
|
|
Mar 28 02:51:35 PM PDT 24 |
Mar 28 02:53:43 PM PDT 24 |
11287439748 ps |
| T810 |
/workspace/coverage/default/3.sram_ctrl_regwen.3414667552 |
|
|
Mar 28 02:44:02 PM PDT 24 |
Mar 28 03:01:10 PM PDT 24 |
10710117740 ps |
| T811 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.4062690553 |
|
|
Mar 28 02:44:48 PM PDT 24 |
Mar 28 02:57:15 PM PDT 24 |
37762639639 ps |
| T812 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1196438787 |
|
|
Mar 28 02:44:34 PM PDT 24 |
Mar 28 02:45:39 PM PDT 24 |
18831157210 ps |
| T813 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.589971215 |
|
|
Mar 28 02:44:33 PM PDT 24 |
Mar 28 02:46:00 PM PDT 24 |
15814447801 ps |
| T814 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1093390031 |
|
|
Mar 28 02:44:01 PM PDT 24 |
Mar 28 03:00:08 PM PDT 24 |
16143141292 ps |
| T815 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1197453682 |
|
|
Mar 28 02:46:11 PM PDT 24 |
Mar 28 02:53:22 PM PDT 24 |
29829693400 ps |
| T816 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1029207235 |
|
|
Mar 28 02:44:50 PM PDT 24 |
Mar 28 03:02:13 PM PDT 24 |
62695425287 ps |
| T817 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.3736029309 |
|
|
Mar 28 02:45:48 PM PDT 24 |
Mar 28 02:45:51 PM PDT 24 |
352329897 ps |
| T818 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2125889181 |
|
|
Mar 28 02:48:57 PM PDT 24 |
Mar 28 03:08:21 PM PDT 24 |
13503144783 ps |
| T819 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.2524341087 |
|
|
Mar 28 02:48:26 PM PDT 24 |
Mar 28 02:49:31 PM PDT 24 |
10672809121 ps |
| T820 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3668692663 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 02:53:48 PM PDT 24 |
1941919400 ps |
| T821 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.665599096 |
|
|
Mar 28 02:44:31 PM PDT 24 |
Mar 28 02:47:52 PM PDT 24 |
3691339206 ps |
| T822 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.4197636821 |
|
|
Mar 28 02:45:47 PM PDT 24 |
Mar 28 02:47:55 PM PDT 24 |
2060772677 ps |
| T823 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2560005478 |
|
|
Mar 28 02:44:36 PM PDT 24 |
Mar 28 04:30:11 PM PDT 24 |
679135163208 ps |
| T824 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3238672143 |
|
|
Mar 28 02:44:49 PM PDT 24 |
Mar 28 02:49:01 PM PDT 24 |
10067367031 ps |
| T825 |
/workspace/coverage/default/36.sram_ctrl_partial_access.3145269958 |
|
|
Mar 28 02:50:11 PM PDT 24 |
Mar 28 02:52:16 PM PDT 24 |
1667368932 ps |
| T826 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.915088373 |
|
|
Mar 28 02:45:25 PM PDT 24 |
Mar 28 02:52:29 PM PDT 24 |
83028923863 ps |
| T827 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.4164541975 |
|
|
Mar 28 02:50:10 PM PDT 24 |
Mar 28 02:51:02 PM PDT 24 |
9229451602 ps |
| T828 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3269565935 |
|
|
Mar 28 02:52:00 PM PDT 24 |
Mar 28 03:09:34 PM PDT 24 |
79519549860 ps |
| T829 |
/workspace/coverage/default/42.sram_ctrl_smoke.1677058487 |
|
|
Mar 28 02:51:36 PM PDT 24 |
Mar 28 02:51:43 PM PDT 24 |
1860489679 ps |
| T830 |
/workspace/coverage/default/45.sram_ctrl_regwen.4078048540 |
|
|
Mar 28 02:52:58 PM PDT 24 |
Mar 28 03:08:20 PM PDT 24 |
12053181561 ps |
| T831 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2991213642 |
|
|
Mar 28 02:48:22 PM PDT 24 |
Mar 28 03:11:20 PM PDT 24 |
50077161488 ps |
| T832 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3986508300 |
|
|
Mar 28 02:48:43 PM PDT 24 |
Mar 28 02:53:28 PM PDT 24 |
9667292377 ps |
| T833 |
/workspace/coverage/default/4.sram_ctrl_executable.1647388835 |
|
|
Mar 28 02:44:01 PM PDT 24 |
Mar 28 02:53:21 PM PDT 24 |
71238938522 ps |
| T834 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2655746379 |
|
|
Mar 28 02:50:53 PM PDT 24 |
Mar 28 02:58:14 PM PDT 24 |
36662979456 ps |
| T835 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1858048971 |
|
|
Mar 28 02:45:50 PM PDT 24 |
Mar 28 02:55:57 PM PDT 24 |
23666391320 ps |
| T836 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1799484325 |
|
|
Mar 28 02:52:34 PM PDT 24 |
Mar 28 03:00:41 PM PDT 24 |
15522921781 ps |
| T837 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1224013874 |
|
|
Mar 28 02:50:10 PM PDT 24 |
Mar 28 02:50:17 PM PDT 24 |
3059215286 ps |
| T838 |
/workspace/coverage/default/11.sram_ctrl_executable.3767088947 |
|
|
Mar 28 02:45:08 PM PDT 24 |
Mar 28 03:07:45 PM PDT 24 |
29012272535 ps |
| T839 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1871076731 |
|
|
Mar 28 02:53:56 PM PDT 24 |
Mar 28 02:54:00 PM PDT 24 |
351791880 ps |
| T840 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3508821277 |
|
|
Mar 28 02:45:05 PM PDT 24 |
Mar 28 02:45:09 PM PDT 24 |
1404036440 ps |
| T841 |
/workspace/coverage/default/0.sram_ctrl_regwen.549017558 |
|
|
Mar 28 02:43:44 PM PDT 24 |
Mar 28 02:53:31 PM PDT 24 |
9153873852 ps |
| T842 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3536373830 |
|
|
Mar 28 02:50:10 PM PDT 24 |
Mar 28 02:51:42 PM PDT 24 |
1411686628 ps |
| T843 |
/workspace/coverage/default/39.sram_ctrl_partial_access.1202700624 |
|
|
Mar 28 02:50:50 PM PDT 24 |
Mar 28 02:50:58 PM PDT 24 |
1735635242 ps |
| T844 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.4080667845 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:50:58 PM PDT 24 |
2478980374 ps |
| T845 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.2474407067 |
|
|
Mar 28 02:46:48 PM PDT 24 |
Mar 28 02:48:55 PM PDT 24 |
8217578278 ps |
| T846 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2473206824 |
|
|
Mar 28 02:45:53 PM PDT 24 |
Mar 28 02:50:05 PM PDT 24 |
4119268030 ps |
| T847 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.548878475 |
|
|
Mar 28 02:50:11 PM PDT 24 |
Mar 28 02:51:35 PM PDT 24 |
2637754942 ps |
| T848 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.894180839 |
|
|
Mar 28 02:45:47 PM PDT 24 |
Mar 28 02:46:34 PM PDT 24 |
26041467293 ps |
| T849 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1845726345 |
|
|
Mar 28 02:49:19 PM PDT 24 |
Mar 28 02:49:40 PM PDT 24 |
826462304 ps |
| T850 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3030964926 |
|
|
Mar 28 02:48:46 PM PDT 24 |
Mar 28 02:48:48 PM PDT 24 |
99287998 ps |
| T851 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3316776186 |
|
|
Mar 28 02:53:36 PM PDT 24 |
Mar 28 02:54:11 PM PDT 24 |
42101759795 ps |
| T852 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.217343151 |
|
|
Mar 28 02:50:34 PM PDT 24 |
Mar 28 02:54:34 PM PDT 24 |
3944085843 ps |
| T853 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.596664793 |
|
|
Mar 28 02:45:06 PM PDT 24 |
Mar 28 02:50:46 PM PDT 24 |
42186359275 ps |
| T854 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.667066424 |
|
|
Mar 28 02:44:50 PM PDT 24 |
Mar 28 02:44:58 PM PDT 24 |
777350453 ps |
| T855 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2085207341 |
|
|
Mar 28 02:51:57 PM PDT 24 |
Mar 28 02:57:17 PM PDT 24 |
10480253249 ps |
| T856 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2970254651 |
|
|
Mar 28 02:48:41 PM PDT 24 |
Mar 28 02:51:09 PM PDT 24 |
3113096067 ps |
| T857 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.209437645 |
|
|
Mar 28 02:48:21 PM PDT 24 |
Mar 28 02:52:29 PM PDT 24 |
4108040169 ps |
| T858 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1897064437 |
|
|
Mar 28 02:48:19 PM PDT 24 |
Mar 28 02:49:44 PM PDT 24 |
1538503419 ps |
| T859 |
/workspace/coverage/default/48.sram_ctrl_bijection.698380516 |
|
|
Mar 28 02:53:14 PM PDT 24 |
Mar 28 03:31:37 PM PDT 24 |
130859972949 ps |
| T860 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3821179156 |
|
|
Mar 28 02:46:26 PM PDT 24 |
Mar 28 02:50:31 PM PDT 24 |
27459573542 ps |
| T861 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.1414597467 |
|
|
Mar 28 02:46:27 PM PDT 24 |
Mar 28 02:46:30 PM PDT 24 |
393068338 ps |
| T862 |
/workspace/coverage/default/36.sram_ctrl_executable.175823027 |
|
|
Mar 28 02:50:30 PM PDT 24 |
Mar 28 03:06:51 PM PDT 24 |
90714596838 ps |
| T863 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2990708255 |
|
|
Mar 28 02:50:11 PM PDT 24 |
Mar 28 02:50:14 PM PDT 24 |
353984055 ps |
| T864 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1364604539 |
|
|
Mar 28 02:46:11 PM PDT 24 |
Mar 28 02:46:19 PM PDT 24 |
777428689 ps |
| T865 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.1333354978 |
|
|
Mar 28 02:44:00 PM PDT 24 |
Mar 28 02:44:24 PM PDT 24 |
3995417610 ps |
| T866 |
/workspace/coverage/default/18.sram_ctrl_smoke.2872942229 |
|
|
Mar 28 02:46:13 PM PDT 24 |
Mar 28 02:46:17 PM PDT 24 |
352086509 ps |
| T867 |
/workspace/coverage/default/47.sram_ctrl_executable.3034780144 |
|
|
Mar 28 02:53:18 PM PDT 24 |
Mar 28 03:13:43 PM PDT 24 |
21688481987 ps |
| T868 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1821478327 |
|
|
Mar 28 02:51:59 PM PDT 24 |
Mar 28 02:52:00 PM PDT 24 |
18881172 ps |
| T869 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2977520085 |
|
|
Mar 28 02:44:12 PM PDT 24 |
Mar 28 02:49:05 PM PDT 24 |
17588229520 ps |
| T870 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2017696581 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 03:03:08 PM PDT 24 |
67221869369 ps |
| T871 |
/workspace/coverage/default/7.sram_ctrl_bijection.2754023153 |
|
|
Mar 28 02:44:32 PM PDT 24 |
Mar 28 03:21:33 PM PDT 24 |
31803409560 ps |
| T872 |
/workspace/coverage/default/35.sram_ctrl_regwen.2642786678 |
|
|
Mar 28 02:50:09 PM PDT 24 |
Mar 28 03:05:51 PM PDT 24 |
3303584833 ps |
| T873 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2181395068 |
|
|
Mar 28 02:45:25 PM PDT 24 |
Mar 28 02:45:28 PM PDT 24 |
1358842442 ps |
| T874 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2678259588 |
|
|
Mar 28 02:46:15 PM PDT 24 |
Mar 28 02:46:22 PM PDT 24 |
1621936000 ps |
| T875 |
/workspace/coverage/default/48.sram_ctrl_regwen.3110638525 |
|
|
Mar 28 02:53:37 PM PDT 24 |
Mar 28 03:02:32 PM PDT 24 |
3729145982 ps |
| T876 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.94997508 |
|
|
Mar 28 02:44:32 PM PDT 24 |
Mar 28 02:48:59 PM PDT 24 |
61904254837 ps |
| T877 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4170369022 |
|
|
Mar 28 02:52:57 PM PDT 24 |
Mar 28 02:54:07 PM PDT 24 |
789750304 ps |
| T878 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2553204338 |
|
|
Mar 28 02:51:34 PM PDT 24 |
Mar 28 02:55:52 PM PDT 24 |
13077369606 ps |
| T879 |
/workspace/coverage/default/29.sram_ctrl_regwen.1178754032 |
|
|
Mar 28 02:48:39 PM PDT 24 |
Mar 28 03:07:52 PM PDT 24 |
47042649737 ps |
| T880 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2300373221 |
|
|
Mar 28 02:44:22 PM PDT 24 |
Mar 28 02:44:47 PM PDT 24 |
4693784349 ps |
| T881 |
/workspace/coverage/default/36.sram_ctrl_regwen.1335496721 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 03:10:59 PM PDT 24 |
24762662282 ps |
| T882 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.1466759808 |
|
|
Mar 28 02:44:01 PM PDT 24 |
Mar 28 02:44:19 PM PDT 24 |
10334143884 ps |
| T883 |
/workspace/coverage/default/1.sram_ctrl_alert_test.4042823189 |
|
|
Mar 28 02:43:40 PM PDT 24 |
Mar 28 02:43:41 PM PDT 24 |
34734260 ps |
| T884 |
/workspace/coverage/default/10.sram_ctrl_executable.865685902 |
|
|
Mar 28 02:45:07 PM PDT 24 |
Mar 28 02:54:53 PM PDT 24 |
8846941169 ps |
| T885 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2047278760 |
|
|
Mar 28 02:51:33 PM PDT 24 |
Mar 28 03:08:29 PM PDT 24 |
7987015515 ps |
| T886 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.1253827839 |
|
|
Mar 28 02:51:19 PM PDT 24 |
Mar 28 02:53:21 PM PDT 24 |
8237508636 ps |
| T35 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2859708708 |
|
|
Mar 28 02:43:41 PM PDT 24 |
Mar 28 02:43:44 PM PDT 24 |
296807698 ps |
| T887 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3521180353 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 03:01:33 PM PDT 24 |
30549761893 ps |
| T888 |
/workspace/coverage/default/6.sram_ctrl_bijection.459576005 |
|
|
Mar 28 02:44:15 PM PDT 24 |
Mar 28 03:20:54 PM PDT 24 |
135272535156 ps |
| T889 |
/workspace/coverage/default/40.sram_ctrl_alert_test.4123267062 |
|
|
Mar 28 02:51:18 PM PDT 24 |
Mar 28 02:51:19 PM PDT 24 |
44136315 ps |
| T890 |
/workspace/coverage/default/16.sram_ctrl_regwen.2794992810 |
|
|
Mar 28 02:46:08 PM PDT 24 |
Mar 28 03:01:41 PM PDT 24 |
12562282995 ps |
| T891 |
/workspace/coverage/default/29.sram_ctrl_executable.688267952 |
|
|
Mar 28 02:48:40 PM PDT 24 |
Mar 28 03:16:10 PM PDT 24 |
19527575709 ps |
| T892 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.218232129 |
|
|
Mar 28 02:47:28 PM PDT 24 |
Mar 28 02:47:36 PM PDT 24 |
2693719009 ps |
| T893 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1462009525 |
|
|
Mar 28 02:49:19 PM PDT 24 |
Mar 28 03:17:13 PM PDT 24 |
101618449383 ps |
| T894 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.640679089 |
|
|
Mar 28 02:45:50 PM PDT 24 |
Mar 28 02:54:22 PM PDT 24 |
89103624145 ps |
| T895 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1753922521 |
|
|
Mar 28 02:49:00 PM PDT 24 |
Mar 28 03:10:27 PM PDT 24 |
113842460071 ps |
| T896 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.367945833 |
|
|
Mar 28 02:53:56 PM PDT 24 |
Mar 28 02:56:40 PM PDT 24 |
22947541907 ps |
| T897 |
/workspace/coverage/default/36.sram_ctrl_smoke.3313235237 |
|
|
Mar 28 02:50:12 PM PDT 24 |
Mar 28 02:50:28 PM PDT 24 |
3151696870 ps |
| T898 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3198040686 |
|
|
Mar 28 02:45:04 PM PDT 24 |
Mar 28 03:02:58 PM PDT 24 |
14178208616 ps |
| T899 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.2681667096 |
|
|
Mar 28 02:46:49 PM PDT 24 |
Mar 28 02:49:26 PM PDT 24 |
776548368 ps |
| T900 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3372717904 |
|
|
Mar 28 02:44:49 PM PDT 24 |
Mar 28 02:45:04 PM PDT 24 |
1395798444 ps |
| T901 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2233642094 |
|
|
Mar 28 02:53:14 PM PDT 24 |
Mar 28 02:54:05 PM PDT 24 |
16743565963 ps |
| T902 |
/workspace/coverage/default/10.sram_ctrl_stress_all.3364587880 |
|
|
Mar 28 02:45:06 PM PDT 24 |
Mar 28 03:46:37 PM PDT 24 |
224986746424 ps |
| T903 |
/workspace/coverage/default/27.sram_ctrl_smoke.1000332910 |
|
|
Mar 28 02:48:20 PM PDT 24 |
Mar 28 02:49:54 PM PDT 24 |
884469783 ps |
| T904 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2123382938 |
|
|
Mar 28 02:44:32 PM PDT 24 |
Mar 28 02:45:39 PM PDT 24 |
3181950533 ps |
| T905 |
/workspace/coverage/default/12.sram_ctrl_smoke.1461782673 |
|
|
Mar 28 02:45:06 PM PDT 24 |
Mar 28 02:45:58 PM PDT 24 |
750109474 ps |
| T906 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3778654340 |
|
|
Mar 28 02:51:13 PM PDT 24 |
Mar 28 02:56:24 PM PDT 24 |
17655497767 ps |
| T907 |
/workspace/coverage/default/17.sram_ctrl_smoke.3040949727 |
|
|
Mar 28 02:46:10 PM PDT 24 |
Mar 28 02:47:13 PM PDT 24 |
2686147549 ps |
| T908 |
/workspace/coverage/default/14.sram_ctrl_smoke.1193976589 |
|
|
Mar 28 02:45:50 PM PDT 24 |
Mar 28 02:46:05 PM PDT 24 |
2193660417 ps |
| T909 |
/workspace/coverage/default/31.sram_ctrl_alert_test.1285782717 |
|
|
Mar 28 02:48:57 PM PDT 24 |
Mar 28 02:48:58 PM PDT 24 |
40515150 ps |
| T910 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.456353961 |
|
|
Mar 28 02:48:41 PM PDT 24 |
Mar 28 02:52:44 PM PDT 24 |
10533365008 ps |
| T911 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.3604066203 |
|
|
Mar 28 02:47:37 PM PDT 24 |
Mar 28 02:48:42 PM PDT 24 |
44208247464 ps |
| T912 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.660887195 |
|
|
Mar 28 02:53:14 PM PDT 24 |
Mar 28 02:55:41 PM PDT 24 |
11569017744 ps |
| T913 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.916361611 |
|
|
Mar 28 02:50:36 PM PDT 24 |
Mar 28 03:01:48 PM PDT 24 |
21511811416 ps |
| T914 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2548373343 |
|
|
Mar 28 02:44:03 PM PDT 24 |
Mar 28 02:44:06 PM PDT 24 |
1298054866 ps |
| T915 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3695312081 |
|
|
Mar 28 02:50:39 PM PDT 24 |
Mar 28 03:17:59 PM PDT 24 |
69223336340 ps |
| T916 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3744263016 |
|
|
Mar 28 02:53:21 PM PDT 24 |
Mar 28 02:58:48 PM PDT 24 |
5860577573 ps |
| T917 |
/workspace/coverage/default/49.sram_ctrl_alert_test.4268993644 |
|
|
Mar 28 02:53:59 PM PDT 24 |
Mar 28 02:53:59 PM PDT 24 |
24688212 ps |
| T918 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2897475167 |
|
|
Mar 28 02:53:37 PM PDT 24 |
Mar 28 02:55:21 PM PDT 24 |
1590495494 ps |
| T919 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2953733912 |
|
|
Mar 28 02:43:58 PM PDT 24 |
Mar 28 02:44:17 PM PDT 24 |
6212217666 ps |
| T920 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4198010771 |
|
|
Mar 28 02:44:17 PM PDT 24 |
Mar 28 02:49:12 PM PDT 24 |
17153732596 ps |
| T921 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.797306752 |
|
|
Mar 28 02:48:58 PM PDT 24 |
Mar 28 02:50:53 PM PDT 24 |
3421950114 ps |
| T922 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3899747843 |
|
|
Mar 28 02:48:57 PM PDT 24 |
Mar 28 03:02:33 PM PDT 24 |
84134018503 ps |
| T923 |
/workspace/coverage/default/15.sram_ctrl_stress_all.74411057 |
|
|
Mar 28 02:46:09 PM PDT 24 |
Mar 28 03:32:25 PM PDT 24 |
89360423603 ps |
| T924 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1705294388 |
|
|
Mar 28 02:50:09 PM PDT 24 |
Mar 28 02:57:44 PM PDT 24 |
21902684092 ps |
| T925 |
/workspace/coverage/default/12.sram_ctrl_partial_access.157790355 |
|
|
Mar 28 02:45:26 PM PDT 24 |
Mar 28 02:45:35 PM PDT 24 |
1640575585 ps |
| T926 |
/workspace/coverage/default/3.sram_ctrl_smoke.4320052 |
|
|
Mar 28 02:43:59 PM PDT 24 |
Mar 28 02:44:06 PM PDT 24 |
376598095 ps |
| T927 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3468479382 |
|
|
Mar 28 02:45:49 PM PDT 24 |
Mar 28 02:47:03 PM PDT 24 |
2818385295 ps |
| T928 |
/workspace/coverage/default/37.sram_ctrl_smoke.101232005 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 02:50:43 PM PDT 24 |
802934332 ps |
| T929 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1981416457 |
|
|
Mar 28 02:49:42 PM PDT 24 |
Mar 28 02:49:59 PM PDT 24 |
4694674258 ps |
| T930 |
/workspace/coverage/default/30.sram_ctrl_smoke.2052928313 |
|
|
Mar 28 02:48:46 PM PDT 24 |
Mar 28 02:49:14 PM PDT 24 |
2010980845 ps |
| T931 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3228424090 |
|
|
Mar 28 02:45:26 PM PDT 24 |
Mar 28 04:26:03 PM PDT 24 |
383366825732 ps |
| T932 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1500070848 |
|
|
Mar 28 02:44:31 PM PDT 24 |
Mar 28 02:49:04 PM PDT 24 |
10049397689 ps |
| T933 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.330584879 |
|
|
Mar 28 02:52:59 PM PDT 24 |
Mar 28 03:17:33 PM PDT 24 |
101430286127 ps |
| T934 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2108256505 |
|
|
Mar 28 02:50:30 PM PDT 24 |
Mar 28 02:52:54 PM PDT 24 |
13764546436 ps |
| T935 |
/workspace/coverage/default/32.sram_ctrl_partial_access.3055417981 |
|
|
Mar 28 02:49:18 PM PDT 24 |
Mar 28 02:50:01 PM PDT 24 |
715292279 ps |
| T936 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3134298074 |
|
|
Mar 28 02:51:34 PM PDT 24 |
Mar 28 03:10:13 PM PDT 24 |
62258550743 ps |
| T937 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2775013927 |
|
|
Mar 28 02:46:09 PM PDT 24 |
Mar 28 02:46:20 PM PDT 24 |
688640137 ps |
| T938 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2221400847 |
|
|
Mar 28 02:47:10 PM PDT 24 |
Mar 28 02:47:16 PM PDT 24 |
2795461430 ps |
| T91 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2579469722 |
|
|
Mar 28 12:36:30 PM PDT 24 |
Mar 28 12:36:31 PM PDT 24 |
23725027 ps |
| T939 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3632328802 |
|
|
Mar 28 12:36:24 PM PDT 24 |
Mar 28 12:36:28 PM PDT 24 |
1909498503 ps |
| T60 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2278435033 |
|
|
Mar 28 12:36:23 PM PDT 24 |
Mar 28 12:36:24 PM PDT 24 |
13530568 ps |
| T101 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2088214185 |
|
|
Mar 28 12:35:41 PM PDT 24 |
Mar 28 12:35:44 PM PDT 24 |
12726187 ps |
| T102 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3613151904 |
|
|
Mar 28 12:35:39 PM PDT 24 |
Mar 28 12:35:43 PM PDT 24 |
156455757 ps |
| T940 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2857179210 |
|
|
Mar 28 12:36:19 PM PDT 24 |
Mar 28 12:36:21 PM PDT 24 |
30138152 ps |
| T61 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2310578954 |
|
|
Mar 28 12:36:00 PM PDT 24 |
Mar 28 12:36:00 PM PDT 24 |
26048996 ps |
| T92 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3901956390 |
|
|
Mar 28 12:36:26 PM PDT 24 |
Mar 28 12:36:27 PM PDT 24 |
55286016 ps |
| T62 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1240118828 |
|
|
Mar 28 12:35:55 PM PDT 24 |
Mar 28 12:35:57 PM PDT 24 |
38622839 ps |
| T63 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1729587732 |
|
|
Mar 28 12:35:45 PM PDT 24 |
Mar 28 12:36:43 PM PDT 24 |
20731186945 ps |
| T941 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2336836014 |
|
|
Mar 28 12:36:18 PM PDT 24 |
Mar 28 12:36:22 PM PDT 24 |
383479766 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1053264741 |
|
|
Mar 28 12:35:49 PM PDT 24 |
Mar 28 12:36:38 PM PDT 24 |
7040700078 ps |
| T942 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.389254583 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:36:27 PM PDT 24 |
29906116 ps |
| T103 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2265864437 |
|
|
Mar 28 12:35:47 PM PDT 24 |
Mar 28 12:35:50 PM PDT 24 |
252825249 ps |
| T943 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3198487936 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:36:27 PM PDT 24 |
93110970 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.217087657 |
|
|
Mar 28 12:36:19 PM PDT 24 |
Mar 28 12:36:23 PM PDT 24 |
365303175 ps |
| T945 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2167490462 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:36:30 PM PDT 24 |
846028923 ps |
| T946 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.190536803 |
|
|
Mar 28 12:36:31 PM PDT 24 |
Mar 28 12:36:36 PM PDT 24 |
222749853 ps |
| T104 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2017208532 |
|
|
Mar 28 12:36:22 PM PDT 24 |
Mar 28 12:36:25 PM PDT 24 |
1375564213 ps |
| T947 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1081056872 |
|
|
Mar 28 12:36:19 PM PDT 24 |
Mar 28 12:36:22 PM PDT 24 |
1406637726 ps |
| T93 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.487953597 |
|
|
Mar 28 12:35:41 PM PDT 24 |
Mar 28 12:35:44 PM PDT 24 |
80121131 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2622294819 |
|
|
Mar 28 12:36:03 PM PDT 24 |
Mar 28 12:36:07 PM PDT 24 |
775629672 ps |
| T116 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3455312740 |
|
|
Mar 28 12:36:21 PM PDT 24 |
Mar 28 12:36:24 PM PDT 24 |
350204371 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1477232065 |
|
|
Mar 28 12:36:05 PM PDT 24 |
Mar 28 12:36:06 PM PDT 24 |
78110895 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1484097280 |
|
|
Mar 28 12:36:00 PM PDT 24 |
Mar 28 12:36:01 PM PDT 24 |
98460404 ps |
| T65 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3779147168 |
|
|
Mar 28 12:36:12 PM PDT 24 |
Mar 28 12:36:13 PM PDT 24 |
29437946 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3160922376 |
|
|
Mar 28 12:36:00 PM PDT 24 |
Mar 28 12:36:01 PM PDT 24 |
36335102 ps |
| T66 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.696536870 |
|
|
Mar 28 12:36:33 PM PDT 24 |
Mar 28 12:36:34 PM PDT 24 |
26791599 ps |
| T67 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2414723168 |
|
|
Mar 28 12:36:03 PM PDT 24 |
Mar 28 12:36:04 PM PDT 24 |
26886960 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1616952245 |
|
|
Mar 28 12:35:45 PM PDT 24 |
Mar 28 12:35:49 PM PDT 24 |
193780891 ps |
| T68 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.150837400 |
|
|
Mar 28 12:35:47 PM PDT 24 |
Mar 28 12:35:50 PM PDT 24 |
336620685 ps |
| T69 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1320691271 |
|
|
Mar 28 12:36:24 PM PDT 24 |
Mar 28 12:36:25 PM PDT 24 |
15167090 ps |
| T953 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2342973593 |
|
|
Mar 28 12:35:59 PM PDT 24 |
Mar 28 12:36:03 PM PDT 24 |
369744801 ps |
| T94 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2859885484 |
|
|
Mar 28 12:36:23 PM PDT 24 |
Mar 28 12:36:24 PM PDT 24 |
32624406 ps |
| T954 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4238363324 |
|
|
Mar 28 12:36:21 PM PDT 24 |
Mar 28 12:36:25 PM PDT 24 |
752858588 ps |
| T955 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3951253031 |
|
|
Mar 28 12:35:48 PM PDT 24 |
Mar 28 12:35:52 PM PDT 24 |
360705597 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1505743337 |
|
|
Mar 28 12:35:59 PM PDT 24 |
Mar 28 12:36:01 PM PDT 24 |
125012837 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3608671016 |
|
|
Mar 28 12:36:22 PM PDT 24 |
Mar 28 12:37:09 PM PDT 24 |
7379973807 ps |
| T958 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3169187933 |
|
|
Mar 28 12:36:21 PM PDT 24 |
Mar 28 12:36:22 PM PDT 24 |
37397159 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2654564760 |
|
|
Mar 28 12:35:51 PM PDT 24 |
Mar 28 12:35:52 PM PDT 24 |
25754763 ps |
| T960 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3580502764 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:36:29 PM PDT 24 |
356119199 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.96513378 |
|
|
Mar 28 12:35:47 PM PDT 24 |
Mar 28 12:35:49 PM PDT 24 |
45144578 ps |
| T119 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1919299400 |
|
|
Mar 28 12:36:27 PM PDT 24 |
Mar 28 12:36:30 PM PDT 24 |
161998726 ps |
| T962 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3844520887 |
|
|
Mar 28 12:35:42 PM PDT 24 |
Mar 28 12:35:50 PM PDT 24 |
79506483 ps |
| T963 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3428725713 |
|
|
Mar 28 12:36:24 PM PDT 24 |
Mar 28 12:36:26 PM PDT 24 |
27871160 ps |
| T71 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3258716044 |
|
|
Mar 28 12:36:00 PM PDT 24 |
Mar 28 12:36:01 PM PDT 24 |
16669933 ps |
| T964 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3997125789 |
|
|
Mar 28 12:36:19 PM PDT 24 |
Mar 28 12:36:20 PM PDT 24 |
13143024 ps |
| T72 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2544175154 |
|
|
Mar 28 12:36:21 PM PDT 24 |
Mar 28 12:37:10 PM PDT 24 |
14666878640 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4105268669 |
|
|
Mar 28 12:36:20 PM PDT 24 |
Mar 28 12:36:21 PM PDT 24 |
46625072 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1078067814 |
|
|
Mar 28 12:36:21 PM PDT 24 |
Mar 28 12:36:25 PM PDT 24 |
1188516322 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2169466222 |
|
|
Mar 28 12:35:49 PM PDT 24 |
Mar 28 12:35:52 PM PDT 24 |
581898466 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3576710447 |
|
|
Mar 28 12:36:20 PM PDT 24 |
Mar 28 12:36:23 PM PDT 24 |
148774298 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1520630499 |
|
|
Mar 28 12:35:46 PM PDT 24 |
Mar 28 12:35:49 PM PDT 24 |
157131033 ps |
| T969 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.397176415 |
|
|
Mar 28 12:36:22 PM PDT 24 |
Mar 28 12:36:27 PM PDT 24 |
163500197 ps |
| T970 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.133655594 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:36:28 PM PDT 24 |
242935401 ps |
| T73 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3377909000 |
|
|
Mar 28 12:36:21 PM PDT 24 |
Mar 28 12:36:47 PM PDT 24 |
3909667850 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3478862331 |
|
|
Mar 28 12:35:48 PM PDT 24 |
Mar 28 12:35:49 PM PDT 24 |
18702647 ps |
| T74 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.638875417 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:37:15 PM PDT 24 |
15286418715 ps |
| T972 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1580973831 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:36:31 PM PDT 24 |
2543344928 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3792976799 |
|
|
Mar 28 12:36:14 PM PDT 24 |
Mar 28 12:36:18 PM PDT 24 |
94470352 ps |
| T75 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1237788113 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:36:26 PM PDT 24 |
39705173 ps |
| T974 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2933246049 |
|
|
Mar 28 12:36:26 PM PDT 24 |
Mar 28 12:36:27 PM PDT 24 |
39278690 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1934285236 |
|
|
Mar 28 12:36:01 PM PDT 24 |
Mar 28 12:36:02 PM PDT 24 |
43299187 ps |
| T976 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4114801544 |
|
|
Mar 28 12:36:23 PM PDT 24 |
Mar 28 12:37:13 PM PDT 24 |
7282959615 ps |
| T112 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.975307044 |
|
|
Mar 28 12:36:23 PM PDT 24 |
Mar 28 12:36:26 PM PDT 24 |
252741994 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2800905373 |
|
|
Mar 28 12:36:11 PM PDT 24 |
Mar 28 12:36:15 PM PDT 24 |
1419708530 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3985382919 |
|
|
Mar 28 12:36:47 PM PDT 24 |
Mar 28 12:36:51 PM PDT 24 |
24552701 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2036397690 |
|
|
Mar 28 12:36:24 PM PDT 24 |
Mar 28 12:36:25 PM PDT 24 |
16521858 ps |
| T980 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4075971928 |
|
|
Mar 28 12:36:00 PM PDT 24 |
Mar 28 12:36:04 PM PDT 24 |
1370606546 ps |
| T981 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2666534547 |
|
|
Mar 28 12:36:23 PM PDT 24 |
Mar 28 12:36:28 PM PDT 24 |
359142404 ps |
| T982 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3811392130 |
|
|
Mar 28 12:36:03 PM PDT 24 |
Mar 28 12:36:33 PM PDT 24 |
15400676010 ps |
| T983 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3960989447 |
|
|
Mar 28 12:36:24 PM PDT 24 |
Mar 28 12:36:24 PM PDT 24 |
20641468 ps |
| T120 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.772439593 |
|
|
Mar 28 12:36:31 PM PDT 24 |
Mar 28 12:36:34 PM PDT 24 |
195589379 ps |
| T76 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.161291058 |
|
|
Mar 28 12:36:24 PM PDT 24 |
Mar 28 12:36:25 PM PDT 24 |
16840173 ps |
| T984 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1448324332 |
|
|
Mar 28 12:36:22 PM PDT 24 |
Mar 28 12:36:24 PM PDT 24 |
793196552 ps |
| T86 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2378355760 |
|
|
Mar 28 12:35:46 PM PDT 24 |
Mar 28 12:35:48 PM PDT 24 |
11935681 ps |
| T77 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4137425174 |
|
|
Mar 28 12:36:20 PM PDT 24 |
Mar 28 12:37:21 PM PDT 24 |
54279290922 ps |
| T985 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4196801332 |
|
|
Mar 28 12:36:30 PM PDT 24 |
Mar 28 12:36:30 PM PDT 24 |
24966549 ps |
| T87 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3505670008 |
|
|
Mar 28 12:36:20 PM PDT 24 |
Mar 28 12:36:21 PM PDT 24 |
12142572 ps |
| T83 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1696837109 |
|
|
Mar 28 12:36:27 PM PDT 24 |
Mar 28 12:36:56 PM PDT 24 |
15400624297 ps |
| T117 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.656884316 |
|
|
Mar 28 12:36:23 PM PDT 24 |
Mar 28 12:36:24 PM PDT 24 |
104640926 ps |
| T986 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3928960917 |
|
|
Mar 28 12:35:40 PM PDT 24 |
Mar 28 12:36:33 PM PDT 24 |
7370436829 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1912116545 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:36:27 PM PDT 24 |
342273459 ps |
| T988 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3335124976 |
|
|
Mar 28 12:36:24 PM PDT 24 |
Mar 28 12:36:27 PM PDT 24 |
441377803 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2653040944 |
|
|
Mar 28 12:36:13 PM PDT 24 |
Mar 28 12:36:13 PM PDT 24 |
53928727 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3538876935 |
|
|
Mar 28 12:36:27 PM PDT 24 |
Mar 28 12:36:28 PM PDT 24 |
31800056 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1203406604 |
|
|
Mar 28 12:36:22 PM PDT 24 |
Mar 28 12:36:25 PM PDT 24 |
356295544 ps |
| T992 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2248950807 |
|
|
Mar 28 12:36:24 PM PDT 24 |
Mar 28 12:36:25 PM PDT 24 |
18751384 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1530851060 |
|
|
Mar 28 12:36:24 PM PDT 24 |
Mar 28 12:37:15 PM PDT 24 |
37140700552 ps |
| T994 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.842955284 |
|
|
Mar 28 12:36:20 PM PDT 24 |
Mar 28 12:36:21 PM PDT 24 |
127472275 ps |
| T995 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3397309514 |
|
|
Mar 28 12:36:20 PM PDT 24 |
Mar 28 12:36:21 PM PDT 24 |
102010814 ps |
| T84 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2369531963 |
|
|
Mar 28 12:36:25 PM PDT 24 |
Mar 28 12:37:15 PM PDT 24 |
7274201417 ps |
| T996 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.881640242 |
|
|
Mar 28 12:36:22 PM PDT 24 |
Mar 28 12:36:26 PM PDT 24 |
150342032 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.253605651 |
|
|
Mar 28 12:35:42 PM PDT 24 |
Mar 28 12:35:47 PM PDT 24 |
13304372 ps |
| T998 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3479742121 |
|
|
Mar 28 12:36:30 PM PDT 24 |
Mar 28 12:36:33 PM PDT 24 |
1442264858 ps |
| T113 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3568087624 |
|
|
Mar 28 12:36:19 PM PDT 24 |
Mar 28 12:36:21 PM PDT 24 |
645962400 ps |
| T85 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3033618922 |
|
|
Mar 28 12:35:43 PM PDT 24 |
Mar 28 12:36:39 PM PDT 24 |
44030615592 ps |
| T999 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3805831332 |
|
|
Mar 28 12:36:20 PM PDT 24 |
Mar 28 12:36:21 PM PDT 24 |
61795165 ps |
| T88 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2123245874 |
|
|
Mar 28 12:36:02 PM PDT 24 |
Mar 28 12:36:03 PM PDT 24 |
36834661 ps |
| T1000 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3160454575 |
|
|
Mar 28 12:36:27 PM PDT 24 |
Mar 28 12:36:58 PM PDT 24 |
15393462510 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4176896437 |
|
|
Mar 28 12:36:19 PM PDT 24 |
Mar 28 12:36:24 PM PDT 24 |
687199678 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.433468750 |
|
|
Mar 28 12:36:23 PM PDT 24 |
Mar 28 12:36:24 PM PDT 24 |
54211219 ps |
| T121 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.690563533 |
|
|
Mar 28 12:36:02 PM PDT 24 |
Mar 28 12:36:04 PM PDT 24 |
2638015334 ps |
| T122 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4289435367 |
|
|
Mar 28 12:36:19 PM PDT 24 |
Mar 28 12:36:21 PM PDT 24 |
212217528 ps |
| T1003 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4212528657 |
|
|
Mar 28 12:36:17 PM PDT 24 |
Mar 28 12:36:18 PM PDT 24 |
72950735 ps |