| T306 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3522102419 |
|
|
Mar 31 03:09:31 PM PDT 24 |
Mar 31 03:11:27 PM PDT 24 |
3131217010 ps |
| T307 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4190941901 |
|
|
Mar 31 03:12:26 PM PDT 24 |
Mar 31 03:29:28 PM PDT 24 |
8274068404 ps |
| T308 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2559767078 |
|
|
Mar 31 03:03:55 PM PDT 24 |
Mar 31 03:04:02 PM PDT 24 |
674066264 ps |
| T309 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1959963400 |
|
|
Mar 31 03:11:49 PM PDT 24 |
Mar 31 03:12:03 PM PDT 24 |
601538242 ps |
| T310 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.474113134 |
|
|
Mar 31 03:00:30 PM PDT 24 |
Mar 31 03:01:02 PM PDT 24 |
736490805 ps |
| T311 |
/workspace/coverage/default/7.sram_ctrl_smoke.3159958371 |
|
|
Mar 31 03:01:21 PM PDT 24 |
Mar 31 03:01:35 PM PDT 24 |
3413005521 ps |
| T312 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.387621197 |
|
|
Mar 31 03:08:00 PM PDT 24 |
Mar 31 03:08:03 PM PDT 24 |
1411925836 ps |
| T313 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2281038570 |
|
|
Mar 31 03:06:21 PM PDT 24 |
Mar 31 03:08:24 PM PDT 24 |
1979271442 ps |
| T314 |
/workspace/coverage/default/23.sram_ctrl_alert_test.3956113989 |
|
|
Mar 31 03:05:10 PM PDT 24 |
Mar 31 03:05:10 PM PDT 24 |
53394161 ps |
| T315 |
/workspace/coverage/default/15.sram_ctrl_stress_all.2715198080 |
|
|
Mar 31 03:03:01 PM PDT 24 |
Mar 31 04:19:32 PM PDT 24 |
813699310615 ps |
| T316 |
/workspace/coverage/default/35.sram_ctrl_partial_access.509282842 |
|
|
Mar 31 03:08:39 PM PDT 24 |
Mar 31 03:09:51 PM PDT 24 |
1707010240 ps |
| T317 |
/workspace/coverage/default/38.sram_ctrl_executable.2575033255 |
|
|
Mar 31 03:09:46 PM PDT 24 |
Mar 31 03:10:41 PM PDT 24 |
16632347441 ps |
| T318 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3009535689 |
|
|
Mar 31 03:10:48 PM PDT 24 |
Mar 31 03:15:47 PM PDT 24 |
33262616595 ps |
| T319 |
/workspace/coverage/default/16.sram_ctrl_alert_test.1970693768 |
|
|
Mar 31 03:03:19 PM PDT 24 |
Mar 31 03:03:19 PM PDT 24 |
13498737 ps |
| T320 |
/workspace/coverage/default/20.sram_ctrl_bijection.2943656711 |
|
|
Mar 31 03:04:01 PM PDT 24 |
Mar 31 03:20:32 PM PDT 24 |
70307739011 ps |
| T321 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1900431474 |
|
|
Mar 31 03:00:59 PM PDT 24 |
Mar 31 03:10:12 PM PDT 24 |
54643178981 ps |
| T322 |
/workspace/coverage/default/31.sram_ctrl_regwen.1190771573 |
|
|
Mar 31 03:07:41 PM PDT 24 |
Mar 31 03:17:54 PM PDT 24 |
24614396457 ps |
| T323 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2261087014 |
|
|
Mar 31 03:08:22 PM PDT 24 |
Mar 31 03:08:23 PM PDT 24 |
31649366 ps |
| T324 |
/workspace/coverage/default/25.sram_ctrl_smoke.1436885911 |
|
|
Mar 31 03:05:31 PM PDT 24 |
Mar 31 03:05:58 PM PDT 24 |
665693584 ps |
| T325 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1848347991 |
|
|
Mar 31 03:02:31 PM PDT 24 |
Mar 31 03:07:04 PM PDT 24 |
39227174343 ps |
| T326 |
/workspace/coverage/default/24.sram_ctrl_regwen.3494939976 |
|
|
Mar 31 03:05:26 PM PDT 24 |
Mar 31 03:15:59 PM PDT 24 |
3309882987 ps |
| T327 |
/workspace/coverage/default/39.sram_ctrl_regwen.1537341021 |
|
|
Mar 31 03:10:06 PM PDT 24 |
Mar 31 03:17:37 PM PDT 24 |
11807782675 ps |
| T328 |
/workspace/coverage/default/0.sram_ctrl_regwen.631180721 |
|
|
Mar 31 03:00:11 PM PDT 24 |
Mar 31 03:13:10 PM PDT 24 |
4241572337 ps |
| T329 |
/workspace/coverage/default/31.sram_ctrl_partial_access.760826964 |
|
|
Mar 31 03:07:31 PM PDT 24 |
Mar 31 03:07:39 PM PDT 24 |
452636325 ps |
| T330 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2686957533 |
|
|
Mar 31 03:04:01 PM PDT 24 |
Mar 31 03:04:02 PM PDT 24 |
29279825 ps |
| T331 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3392686809 |
|
|
Mar 31 03:00:11 PM PDT 24 |
Mar 31 03:00:21 PM PDT 24 |
1063185910 ps |
| T332 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.624178761 |
|
|
Mar 31 03:03:56 PM PDT 24 |
Mar 31 03:07:34 PM PDT 24 |
20938615199 ps |
| T333 |
/workspace/coverage/default/38.sram_ctrl_bijection.2651101198 |
|
|
Mar 31 03:09:41 PM PDT 24 |
Mar 31 03:30:42 PM PDT 24 |
134617280868 ps |
| T334 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.130191980 |
|
|
Mar 31 03:04:12 PM PDT 24 |
Mar 31 03:10:21 PM PDT 24 |
36533171743 ps |
| T335 |
/workspace/coverage/default/0.sram_ctrl_smoke.3700374745 |
|
|
Mar 31 03:00:02 PM PDT 24 |
Mar 31 03:00:17 PM PDT 24 |
3369145581 ps |
| T336 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.4052893840 |
|
|
Mar 31 03:04:05 PM PDT 24 |
Mar 31 03:05:16 PM PDT 24 |
2344418788 ps |
| T337 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.2071356966 |
|
|
Mar 31 03:10:05 PM PDT 24 |
Mar 31 03:10:09 PM PDT 24 |
1404923778 ps |
| T338 |
/workspace/coverage/default/30.sram_ctrl_partial_access.1232251638 |
|
|
Mar 31 03:07:10 PM PDT 24 |
Mar 31 03:09:17 PM PDT 24 |
1282961949 ps |
| T339 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1218637178 |
|
|
Mar 31 03:03:10 PM PDT 24 |
Mar 31 03:03:11 PM PDT 24 |
32652548 ps |
| T340 |
/workspace/coverage/default/12.sram_ctrl_regwen.1751524529 |
|
|
Mar 31 03:02:32 PM PDT 24 |
Mar 31 03:08:48 PM PDT 24 |
6806458516 ps |
| T341 |
/workspace/coverage/default/19.sram_ctrl_bijection.2005500841 |
|
|
Mar 31 03:03:55 PM PDT 24 |
Mar 31 03:24:13 PM PDT 24 |
266148498871 ps |
| T342 |
/workspace/coverage/default/9.sram_ctrl_alert_test.3409814360 |
|
|
Mar 31 03:01:59 PM PDT 24 |
Mar 31 03:01:59 PM PDT 24 |
74936791 ps |
| T343 |
/workspace/coverage/default/28.sram_ctrl_alert_test.595782432 |
|
|
Mar 31 03:06:54 PM PDT 24 |
Mar 31 03:06:55 PM PDT 24 |
45106047 ps |
| T344 |
/workspace/coverage/default/47.sram_ctrl_bijection.3499435284 |
|
|
Mar 31 03:12:48 PM PDT 24 |
Mar 31 03:24:10 PM PDT 24 |
72245796243 ps |
| T345 |
/workspace/coverage/default/14.sram_ctrl_alert_test.1400591979 |
|
|
Mar 31 03:02:47 PM PDT 24 |
Mar 31 03:02:47 PM PDT 24 |
23676578 ps |
| T346 |
/workspace/coverage/default/27.sram_ctrl_smoke.2862514360 |
|
|
Mar 31 03:06:10 PM PDT 24 |
Mar 31 03:07:39 PM PDT 24 |
1627366718 ps |
| T347 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3130188600 |
|
|
Mar 31 03:01:28 PM PDT 24 |
Mar 31 03:23:59 PM PDT 24 |
40729872708 ps |
| T348 |
/workspace/coverage/default/10.sram_ctrl_stress_all.2590214853 |
|
|
Mar 31 03:02:16 PM PDT 24 |
Mar 31 04:51:05 PM PDT 24 |
434106882455 ps |
| T349 |
/workspace/coverage/default/24.sram_ctrl_bijection.1482843426 |
|
|
Mar 31 03:05:10 PM PDT 24 |
Mar 31 03:36:55 PM PDT 24 |
106217020209 ps |
| T350 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1476373266 |
|
|
Mar 31 03:09:54 PM PDT 24 |
Mar 31 03:14:32 PM PDT 24 |
4462917795 ps |
| T351 |
/workspace/coverage/default/14.sram_ctrl_bijection.471682009 |
|
|
Mar 31 03:02:39 PM PDT 24 |
Mar 31 03:50:08 PM PDT 24 |
661913800525 ps |
| T352 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.798168497 |
|
|
Mar 31 03:07:40 PM PDT 24 |
Mar 31 03:07:51 PM PDT 24 |
2973742753 ps |
| T353 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.736995266 |
|
|
Mar 31 03:02:06 PM PDT 24 |
Mar 31 03:02:10 PM PDT 24 |
886798134 ps |
| T354 |
/workspace/coverage/default/44.sram_ctrl_smoke.3496675013 |
|
|
Mar 31 03:11:43 PM PDT 24 |
Mar 31 03:11:47 PM PDT 24 |
1431698809 ps |
| T355 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.324856990 |
|
|
Mar 31 03:13:52 PM PDT 24 |
Mar 31 03:14:07 PM PDT 24 |
1587379313 ps |
| T356 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2308806277 |
|
|
Mar 31 03:06:44 PM PDT 24 |
Mar 31 03:06:48 PM PDT 24 |
5604353171 ps |
| T357 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.2819372086 |
|
|
Mar 31 03:06:16 PM PDT 24 |
Mar 31 03:07:27 PM PDT 24 |
12204028434 ps |
| T358 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.451353244 |
|
|
Mar 31 03:01:24 PM PDT 24 |
Mar 31 03:04:02 PM PDT 24 |
2493170470 ps |
| T359 |
/workspace/coverage/default/8.sram_ctrl_partial_access.45444693 |
|
|
Mar 31 03:01:30 PM PDT 24 |
Mar 31 03:02:22 PM PDT 24 |
2391537417 ps |
| T360 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.267936264 |
|
|
Mar 31 03:11:53 PM PDT 24 |
Mar 31 03:12:41 PM PDT 24 |
102282055852 ps |
| T361 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.3547297569 |
|
|
Mar 31 03:00:43 PM PDT 24 |
Mar 31 03:30:50 PM PDT 24 |
26850381634 ps |
| T362 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1291748744 |
|
|
Mar 31 03:03:41 PM PDT 24 |
Mar 31 03:16:55 PM PDT 24 |
125239231764 ps |
| T363 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.3050820103 |
|
|
Mar 31 03:06:11 PM PDT 24 |
Mar 31 03:12:40 PM PDT 24 |
6379942979 ps |
| T364 |
/workspace/coverage/default/30.sram_ctrl_stress_all.1777669760 |
|
|
Mar 31 03:07:31 PM PDT 24 |
Mar 31 04:17:45 PM PDT 24 |
174630561565 ps |
| T365 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1420144775 |
|
|
Mar 31 03:01:33 PM PDT 24 |
Mar 31 03:03:29 PM PDT 24 |
3264494879 ps |
| T366 |
/workspace/coverage/default/34.sram_ctrl_alert_test.3378521661 |
|
|
Mar 31 03:08:34 PM PDT 24 |
Mar 31 03:08:36 PM PDT 24 |
12128491 ps |
| T367 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.3568076479 |
|
|
Mar 31 03:09:58 PM PDT 24 |
Mar 31 03:11:08 PM PDT 24 |
12442991709 ps |
| T368 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.271929787 |
|
|
Mar 31 03:02:13 PM PDT 24 |
Mar 31 03:03:18 PM PDT 24 |
763151784 ps |
| T369 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.1411350812 |
|
|
Mar 31 03:08:39 PM PDT 24 |
Mar 31 03:10:00 PM PDT 24 |
25422157195 ps |
| T370 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3579592804 |
|
|
Mar 31 03:07:59 PM PDT 24 |
Mar 31 03:09:17 PM PDT 24 |
2679440558 ps |
| T371 |
/workspace/coverage/default/40.sram_ctrl_alert_test.3356782628 |
|
|
Mar 31 03:10:40 PM PDT 24 |
Mar 31 03:10:41 PM PDT 24 |
12618132 ps |
| T372 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.832448471 |
|
|
Mar 31 03:05:27 PM PDT 24 |
Mar 31 03:06:25 PM PDT 24 |
37306909096 ps |
| T373 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3851451184 |
|
|
Mar 31 03:02:53 PM PDT 24 |
Mar 31 03:08:50 PM PDT 24 |
9283856546 ps |
| T374 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.256897790 |
|
|
Mar 31 03:04:34 PM PDT 24 |
Mar 31 03:24:53 PM PDT 24 |
10638718414 ps |
| T375 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3352367820 |
|
|
Mar 31 03:12:07 PM PDT 24 |
Mar 31 03:12:21 PM PDT 24 |
821375326 ps |
| T376 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.52094056 |
|
|
Mar 31 03:05:43 PM PDT 24 |
Mar 31 03:06:42 PM PDT 24 |
9528842521 ps |
| T377 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3331960855 |
|
|
Mar 31 03:02:23 PM PDT 24 |
Mar 31 03:02:40 PM PDT 24 |
2323554788 ps |
| T378 |
/workspace/coverage/default/14.sram_ctrl_regwen.1792229474 |
|
|
Mar 31 03:02:48 PM PDT 24 |
Mar 31 03:06:57 PM PDT 24 |
1776973030 ps |
| T379 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1309501787 |
|
|
Mar 31 03:04:24 PM PDT 24 |
Mar 31 03:04:32 PM PDT 24 |
3743072750 ps |
| T380 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1234295839 |
|
|
Mar 31 03:03:12 PM PDT 24 |
Mar 31 03:03:38 PM PDT 24 |
1444314043 ps |
| T381 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2930173987 |
|
|
Mar 31 03:01:59 PM PDT 24 |
Mar 31 03:14:04 PM PDT 24 |
132102188554 ps |
| T382 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.2718172421 |
|
|
Mar 31 03:08:07 PM PDT 24 |
Mar 31 03:27:17 PM PDT 24 |
93729865069 ps |
| T383 |
/workspace/coverage/default/1.sram_ctrl_executable.743236220 |
|
|
Mar 31 03:00:23 PM PDT 24 |
Mar 31 03:25:40 PM PDT 24 |
39634403509 ps |
| T384 |
/workspace/coverage/default/49.sram_ctrl_regwen.3230539268 |
|
|
Mar 31 03:13:44 PM PDT 24 |
Mar 31 03:23:39 PM PDT 24 |
7249090199 ps |
| T385 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.3735660065 |
|
|
Mar 31 03:09:58 PM PDT 24 |
Mar 31 03:11:21 PM PDT 24 |
1566666656 ps |
| T386 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3171907374 |
|
|
Mar 31 03:02:16 PM PDT 24 |
Mar 31 03:08:34 PM PDT 24 |
22462223739 ps |
| T387 |
/workspace/coverage/default/36.sram_ctrl_stress_all.55111912 |
|
|
Mar 31 03:09:11 PM PDT 24 |
Mar 31 04:18:15 PM PDT 24 |
177034819436 ps |
| T388 |
/workspace/coverage/default/38.sram_ctrl_stress_all.711250272 |
|
|
Mar 31 03:09:52 PM PDT 24 |
Mar 31 04:13:39 PM PDT 24 |
235625063578 ps |
| T389 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1601471412 |
|
|
Mar 31 03:01:35 PM PDT 24 |
Mar 31 03:03:25 PM PDT 24 |
3212616921 ps |
| T390 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.325216359 |
|
|
Mar 31 03:08:34 PM PDT 24 |
Mar 31 03:22:25 PM PDT 24 |
76227721599 ps |
| T391 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1913970814 |
|
|
Mar 31 03:08:35 PM PDT 24 |
Mar 31 03:13:19 PM PDT 24 |
28080195153 ps |
| T392 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.440066233 |
|
|
Mar 31 03:12:28 PM PDT 24 |
Mar 31 03:19:03 PM PDT 24 |
207497880662 ps |
| T393 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2579431555 |
|
|
Mar 31 03:05:59 PM PDT 24 |
Mar 31 03:17:52 PM PDT 24 |
52802876668 ps |
| T394 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1680872563 |
|
|
Mar 31 03:09:10 PM PDT 24 |
Mar 31 03:09:11 PM PDT 24 |
24117231 ps |
| T395 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3327139928 |
|
|
Mar 31 03:02:00 PM PDT 24 |
Mar 31 03:10:34 PM PDT 24 |
65700834777 ps |
| T396 |
/workspace/coverage/default/0.sram_ctrl_partial_access.679445490 |
|
|
Mar 31 03:00:11 PM PDT 24 |
Mar 31 03:00:19 PM PDT 24 |
492807466 ps |
| T397 |
/workspace/coverage/default/35.sram_ctrl_executable.246699534 |
|
|
Mar 31 03:08:45 PM PDT 24 |
Mar 31 03:09:12 PM PDT 24 |
10785045605 ps |
| T398 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1523383743 |
|
|
Mar 31 03:07:03 PM PDT 24 |
Mar 31 03:07:04 PM PDT 24 |
35614190 ps |
| T399 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3061354037 |
|
|
Mar 31 03:07:31 PM PDT 24 |
Mar 31 03:08:03 PM PDT 24 |
1800340595 ps |
| T400 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2494817030 |
|
|
Mar 31 03:00:53 PM PDT 24 |
Mar 31 03:09:05 PM PDT 24 |
21351756577 ps |
| T401 |
/workspace/coverage/default/40.sram_ctrl_executable.751065556 |
|
|
Mar 31 03:10:27 PM PDT 24 |
Mar 31 03:27:03 PM PDT 24 |
17129524424 ps |
| T402 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.479818879 |
|
|
Mar 31 03:02:37 PM PDT 24 |
Mar 31 03:04:34 PM PDT 24 |
2139413683 ps |
| T403 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.750954842 |
|
|
Mar 31 03:02:23 PM PDT 24 |
Mar 31 03:04:51 PM PDT 24 |
10742658241 ps |
| T404 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3922196665 |
|
|
Mar 31 03:00:29 PM PDT 24 |
Mar 31 03:04:18 PM PDT 24 |
4097868179 ps |
| T405 |
/workspace/coverage/default/45.sram_ctrl_alert_test.1009525297 |
|
|
Mar 31 03:12:25 PM PDT 24 |
Mar 31 03:12:26 PM PDT 24 |
12939492 ps |
| T406 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1576950563 |
|
|
Mar 31 03:01:12 PM PDT 24 |
Mar 31 03:18:18 PM PDT 24 |
52051293499 ps |
| T407 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3993657776 |
|
|
Mar 31 03:09:45 PM PDT 24 |
Mar 31 03:09:53 PM PDT 24 |
685405745 ps |
| T408 |
/workspace/coverage/default/48.sram_ctrl_stress_all.1830839821 |
|
|
Mar 31 03:13:33 PM PDT 24 |
Mar 31 04:27:50 PM PDT 24 |
224824448749 ps |
| T409 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.489499276 |
|
|
Mar 31 03:04:10 PM PDT 24 |
Mar 31 03:08:10 PM PDT 24 |
4696728627 ps |
| T410 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2870620138 |
|
|
Mar 31 03:10:34 PM PDT 24 |
Mar 31 03:10:38 PM PDT 24 |
710267238 ps |
| T411 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1558977067 |
|
|
Mar 31 03:06:11 PM PDT 24 |
Mar 31 03:06:26 PM PDT 24 |
2212582804 ps |
| T412 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1001921206 |
|
|
Mar 31 03:12:00 PM PDT 24 |
Mar 31 03:12:11 PM PDT 24 |
306644633 ps |
| T413 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.802602918 |
|
|
Mar 31 03:05:44 PM PDT 24 |
Mar 31 03:05:49 PM PDT 24 |
1402801998 ps |
| T414 |
/workspace/coverage/default/10.sram_ctrl_executable.3257150489 |
|
|
Mar 31 03:02:06 PM PDT 24 |
Mar 31 03:06:17 PM PDT 24 |
2653913064 ps |
| T415 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1517032027 |
|
|
Mar 31 03:11:25 PM PDT 24 |
Mar 31 03:11:51 PM PDT 24 |
11132702164 ps |
| T416 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3720723042 |
|
|
Mar 31 03:08:03 PM PDT 24 |
Mar 31 03:08:11 PM PDT 24 |
155298958 ps |
| T417 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3479546036 |
|
|
Mar 31 03:12:47 PM PDT 24 |
Mar 31 03:12:57 PM PDT 24 |
913739423 ps |
| T418 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.114816163 |
|
|
Mar 31 03:00:11 PM PDT 24 |
Mar 31 03:00:14 PM PDT 24 |
359435698 ps |
| T105 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3782159779 |
|
|
Mar 31 03:02:31 PM PDT 24 |
Mar 31 03:03:28 PM PDT 24 |
2517805234 ps |
| T419 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1465328926 |
|
|
Mar 31 03:01:29 PM PDT 24 |
Mar 31 03:26:21 PM PDT 24 |
266235348110 ps |
| T420 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1524022875 |
|
|
Mar 31 03:07:52 PM PDT 24 |
Mar 31 03:14:11 PM PDT 24 |
30306275173 ps |
| T421 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.1848846147 |
|
|
Mar 31 03:05:44 PM PDT 24 |
Mar 31 03:06:28 PM PDT 24 |
38635520886 ps |
| T422 |
/workspace/coverage/default/45.sram_ctrl_executable.430040079 |
|
|
Mar 31 03:12:15 PM PDT 24 |
Mar 31 03:28:34 PM PDT 24 |
35634820904 ps |
| T423 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2095560375 |
|
|
Mar 31 03:09:17 PM PDT 24 |
Mar 31 03:12:54 PM PDT 24 |
14876860103 ps |
| T424 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2776541777 |
|
|
Mar 31 03:10:22 PM PDT 24 |
Mar 31 03:14:59 PM PDT 24 |
47496908966 ps |
| T425 |
/workspace/coverage/default/19.sram_ctrl_stress_all.4183722786 |
|
|
Mar 31 03:04:01 PM PDT 24 |
Mar 31 04:43:58 PM PDT 24 |
813421980916 ps |
| T106 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4123156266 |
|
|
Mar 31 03:01:09 PM PDT 24 |
Mar 31 03:01:55 PM PDT 24 |
5186139780 ps |
| T426 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2086533354 |
|
|
Mar 31 03:03:33 PM PDT 24 |
Mar 31 03:04:14 PM PDT 24 |
6941031271 ps |
| T427 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.511437898 |
|
|
Mar 31 03:11:53 PM PDT 24 |
Mar 31 03:11:57 PM PDT 24 |
358750978 ps |
| T428 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.724344459 |
|
|
Mar 31 03:10:28 PM PDT 24 |
Mar 31 03:11:25 PM PDT 24 |
97184985832 ps |
| T429 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.968166391 |
|
|
Mar 31 03:02:24 PM PDT 24 |
Mar 31 03:03:04 PM PDT 24 |
7395289671 ps |
| T430 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.4260790626 |
|
|
Mar 31 03:11:35 PM PDT 24 |
Mar 31 03:16:47 PM PDT 24 |
82558965250 ps |
| T431 |
/workspace/coverage/default/28.sram_ctrl_regwen.1157184980 |
|
|
Mar 31 03:06:44 PM PDT 24 |
Mar 31 03:15:26 PM PDT 24 |
3508290179 ps |
| T432 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2678634401 |
|
|
Mar 31 03:07:31 PM PDT 24 |
Mar 31 03:10:44 PM PDT 24 |
9185215034 ps |
| T433 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.687473133 |
|
|
Mar 31 03:06:04 PM PDT 24 |
Mar 31 03:08:27 PM PDT 24 |
17558813098 ps |
| T434 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3850246302 |
|
|
Mar 31 03:13:16 PM PDT 24 |
Mar 31 03:32:42 PM PDT 24 |
13821447099 ps |
| T435 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.4219966332 |
|
|
Mar 31 03:02:30 PM PDT 24 |
Mar 31 03:08:00 PM PDT 24 |
33455000608 ps |
| T436 |
/workspace/coverage/default/16.sram_ctrl_smoke.2267089426 |
|
|
Mar 31 03:03:09 PM PDT 24 |
Mar 31 03:03:30 PM PDT 24 |
7141277141 ps |
| T437 |
/workspace/coverage/default/18.sram_ctrl_partial_access.292029669 |
|
|
Mar 31 03:03:40 PM PDT 24 |
Mar 31 03:03:53 PM PDT 24 |
2130943532 ps |
| T438 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1974525923 |
|
|
Mar 31 03:04:25 PM PDT 24 |
Mar 31 03:08:04 PM PDT 24 |
9630789458 ps |
| T439 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2540667179 |
|
|
Mar 31 03:06:51 PM PDT 24 |
Mar 31 03:16:46 PM PDT 24 |
14131981829 ps |
| T440 |
/workspace/coverage/default/21.sram_ctrl_smoke.1177859230 |
|
|
Mar 31 03:04:14 PM PDT 24 |
Mar 31 03:04:23 PM PDT 24 |
733076398 ps |
| T441 |
/workspace/coverage/default/38.sram_ctrl_regwen.19530902 |
|
|
Mar 31 03:09:46 PM PDT 24 |
Mar 31 03:14:38 PM PDT 24 |
5910858408 ps |
| T442 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3258097207 |
|
|
Mar 31 03:12:34 PM PDT 24 |
Mar 31 03:21:55 PM PDT 24 |
10575011195 ps |
| T443 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.100216861 |
|
|
Mar 31 03:11:19 PM PDT 24 |
Mar 31 03:11:39 PM PDT 24 |
655780243 ps |
| T444 |
/workspace/coverage/default/39.sram_ctrl_executable.3450327121 |
|
|
Mar 31 03:09:58 PM PDT 24 |
Mar 31 03:18:42 PM PDT 24 |
2608256714 ps |
| T445 |
/workspace/coverage/default/46.sram_ctrl_partial_access.812391480 |
|
|
Mar 31 03:12:22 PM PDT 24 |
Mar 31 03:12:38 PM PDT 24 |
2102023055 ps |
| T446 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.1679553237 |
|
|
Mar 31 03:00:30 PM PDT 24 |
Mar 31 03:14:50 PM PDT 24 |
8104259951 ps |
| T447 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.409890342 |
|
|
Mar 31 03:03:02 PM PDT 24 |
Mar 31 03:04:09 PM PDT 24 |
1007511928 ps |
| T448 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.760954669 |
|
|
Mar 31 03:09:59 PM PDT 24 |
Mar 31 03:17:19 PM PDT 24 |
17670636725 ps |
| T449 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1615014182 |
|
|
Mar 31 03:03:01 PM PDT 24 |
Mar 31 03:03:04 PM PDT 24 |
356648431 ps |
| T450 |
/workspace/coverage/default/32.sram_ctrl_partial_access.2551417448 |
|
|
Mar 31 03:07:55 PM PDT 24 |
Mar 31 03:08:08 PM PDT 24 |
1691773843 ps |
| T451 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.1296068831 |
|
|
Mar 31 03:09:11 PM PDT 24 |
Mar 31 03:11:09 PM PDT 24 |
3961618500 ps |
| T452 |
/workspace/coverage/default/35.sram_ctrl_stress_all.2628621775 |
|
|
Mar 31 03:08:46 PM PDT 24 |
Mar 31 03:42:17 PM PDT 24 |
118418884255 ps |
| T453 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1291456247 |
|
|
Mar 31 03:00:17 PM PDT 24 |
Mar 31 03:18:00 PM PDT 24 |
62215813295 ps |
| T454 |
/workspace/coverage/default/40.sram_ctrl_regwen.1733165563 |
|
|
Mar 31 03:10:34 PM PDT 24 |
Mar 31 03:12:55 PM PDT 24 |
9418247971 ps |
| T455 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.2557328475 |
|
|
Mar 31 03:05:03 PM PDT 24 |
Mar 31 03:05:44 PM PDT 24 |
12333887951 ps |
| T456 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.1748298134 |
|
|
Mar 31 03:08:16 PM PDT 24 |
Mar 31 03:22:14 PM PDT 24 |
8068245762 ps |
| T457 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.218902116 |
|
|
Mar 31 03:02:32 PM PDT 24 |
Mar 31 03:04:16 PM PDT 24 |
3110493069 ps |
| T458 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.2432195625 |
|
|
Mar 31 03:04:55 PM PDT 24 |
Mar 31 03:07:27 PM PDT 24 |
5184875934 ps |
| T459 |
/workspace/coverage/default/42.sram_ctrl_partial_access.4236895070 |
|
|
Mar 31 03:11:07 PM PDT 24 |
Mar 31 03:11:19 PM PDT 24 |
3042209291 ps |
| T460 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2556442992 |
|
|
Mar 31 03:05:10 PM PDT 24 |
Mar 31 03:07:09 PM PDT 24 |
1638524058 ps |
| T461 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3678709830 |
|
|
Mar 31 03:00:40 PM PDT 24 |
Mar 31 03:08:27 PM PDT 24 |
26313336349 ps |
| T462 |
/workspace/coverage/default/43.sram_ctrl_executable.314768181 |
|
|
Mar 31 03:11:30 PM PDT 24 |
Mar 31 03:20:40 PM PDT 24 |
7788663099 ps |
| T463 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.4070797649 |
|
|
Mar 31 03:08:39 PM PDT 24 |
Mar 31 03:12:19 PM PDT 24 |
7753316330 ps |
| T464 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.3688104419 |
|
|
Mar 31 03:00:53 PM PDT 24 |
Mar 31 03:00:57 PM PDT 24 |
1350677079 ps |
| T465 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1023770422 |
|
|
Mar 31 03:09:38 PM PDT 24 |
Mar 31 03:10:05 PM PDT 24 |
926496653 ps |
| T466 |
/workspace/coverage/default/36.sram_ctrl_regwen.3068151280 |
|
|
Mar 31 03:09:06 PM PDT 24 |
Mar 31 03:19:19 PM PDT 24 |
23289586594 ps |
| T467 |
/workspace/coverage/default/23.sram_ctrl_executable.418564136 |
|
|
Mar 31 03:05:04 PM PDT 24 |
Mar 31 03:21:22 PM PDT 24 |
8022836233 ps |
| T468 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.2956769329 |
|
|
Mar 31 03:04:08 PM PDT 24 |
Mar 31 03:04:11 PM PDT 24 |
1769481103 ps |
| T26 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1938586044 |
|
|
Mar 31 03:00:41 PM PDT 24 |
Mar 31 03:00:43 PM PDT 24 |
222548838 ps |
| T469 |
/workspace/coverage/default/25.sram_ctrl_alert_test.3006948624 |
|
|
Mar 31 03:05:44 PM PDT 24 |
Mar 31 03:05:46 PM PDT 24 |
23708264 ps |
| T470 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.971860287 |
|
|
Mar 31 03:04:28 PM PDT 24 |
Mar 31 03:09:26 PM PDT 24 |
21294493549 ps |
| T471 |
/workspace/coverage/default/14.sram_ctrl_executable.366784492 |
|
|
Mar 31 03:02:45 PM PDT 24 |
Mar 31 03:34:02 PM PDT 24 |
110545093484 ps |
| T472 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2164838593 |
|
|
Mar 31 03:12:58 PM PDT 24 |
Mar 31 03:15:19 PM PDT 24 |
33432239498 ps |
| T473 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2492713888 |
|
|
Mar 31 03:01:14 PM PDT 24 |
Mar 31 03:02:31 PM PDT 24 |
3118871722 ps |
| T474 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1125034308 |
|
|
Mar 31 03:03:23 PM PDT 24 |
Mar 31 03:16:33 PM PDT 24 |
39994907745 ps |
| T475 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3954605191 |
|
|
Mar 31 03:08:39 PM PDT 24 |
Mar 31 03:10:56 PM PDT 24 |
11629694899 ps |
| T476 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3458253763 |
|
|
Mar 31 03:13:40 PM PDT 24 |
Mar 31 03:18:40 PM PDT 24 |
53592671607 ps |
| T477 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3906231056 |
|
|
Mar 31 03:10:51 PM PDT 24 |
Mar 31 03:26:52 PM PDT 24 |
56427649712 ps |
| T478 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3559257627 |
|
|
Mar 31 03:00:25 PM PDT 24 |
Mar 31 03:00:52 PM PDT 24 |
6391113560 ps |
| T479 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3444866183 |
|
|
Mar 31 03:07:23 PM PDT 24 |
Mar 31 03:09:53 PM PDT 24 |
19575722231 ps |
| T480 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3973460421 |
|
|
Mar 31 03:03:18 PM PDT 24 |
Mar 31 03:11:04 PM PDT 24 |
39380103138 ps |
| T481 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3014815252 |
|
|
Mar 31 03:04:25 PM PDT 24 |
Mar 31 03:06:44 PM PDT 24 |
807470030 ps |
| T482 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3420247043 |
|
|
Mar 31 03:01:21 PM PDT 24 |
Mar 31 03:04:47 PM PDT 24 |
4130117879 ps |
| T483 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.971076936 |
|
|
Mar 31 03:04:47 PM PDT 24 |
Mar 31 03:05:45 PM PDT 24 |
4293927630 ps |
| T107 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3793170004 |
|
|
Mar 31 03:04:54 PM PDT 24 |
Mar 31 03:05:07 PM PDT 24 |
1189376403 ps |
| T484 |
/workspace/coverage/default/9.sram_ctrl_executable.2000939756 |
|
|
Mar 31 03:01:51 PM PDT 24 |
Mar 31 03:07:00 PM PDT 24 |
6478313978 ps |
| T485 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1973889734 |
|
|
Mar 31 03:13:07 PM PDT 24 |
Mar 31 03:13:32 PM PDT 24 |
2179652760 ps |
| T486 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.176424889 |
|
|
Mar 31 03:01:33 PM PDT 24 |
Mar 31 03:04:19 PM PDT 24 |
89222163563 ps |
| T487 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1947806196 |
|
|
Mar 31 03:08:47 PM PDT 24 |
Mar 31 03:10:09 PM PDT 24 |
38738241769 ps |
| T488 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2910531859 |
|
|
Mar 31 03:11:54 PM PDT 24 |
Mar 31 03:12:13 PM PDT 24 |
740536489 ps |
| T489 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3989438200 |
|
|
Mar 31 03:05:58 PM PDT 24 |
Mar 31 03:14:08 PM PDT 24 |
22772896095 ps |
| T490 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1123949736 |
|
|
Mar 31 03:08:07 PM PDT 24 |
Mar 31 03:08:19 PM PDT 24 |
7851445694 ps |
| T491 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1572842998 |
|
|
Mar 31 03:12:47 PM PDT 24 |
Mar 31 03:20:55 PM PDT 24 |
42257243407 ps |
| T492 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.333697637 |
|
|
Mar 31 03:09:10 PM PDT 24 |
Mar 31 03:09:33 PM PDT 24 |
689245578 ps |
| T493 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.2682059668 |
|
|
Mar 31 03:06:00 PM PDT 24 |
Mar 31 03:07:37 PM PDT 24 |
17757735238 ps |
| T494 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1651333249 |
|
|
Mar 31 03:09:17 PM PDT 24 |
Mar 31 03:15:37 PM PDT 24 |
6809474801 ps |
| T495 |
/workspace/coverage/default/16.sram_ctrl_bijection.420345231 |
|
|
Mar 31 03:03:09 PM PDT 24 |
Mar 31 03:43:44 PM PDT 24 |
110746859180 ps |
| T496 |
/workspace/coverage/default/1.sram_ctrl_stress_all.982485689 |
|
|
Mar 31 03:00:29 PM PDT 24 |
Mar 31 03:11:25 PM PDT 24 |
48664775939 ps |
| T497 |
/workspace/coverage/default/34.sram_ctrl_stress_all.3672481472 |
|
|
Mar 31 03:08:34 PM PDT 24 |
Mar 31 04:03:17 PM PDT 24 |
56065603646 ps |
| T498 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.379719615 |
|
|
Mar 31 03:05:24 PM PDT 24 |
Mar 31 03:06:36 PM PDT 24 |
2347197084 ps |
| T499 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1138425482 |
|
|
Mar 31 03:13:16 PM PDT 24 |
Mar 31 03:17:00 PM PDT 24 |
9016244318 ps |
| T500 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1558927476 |
|
|
Mar 31 03:05:40 PM PDT 24 |
Mar 31 03:10:23 PM PDT 24 |
14194270906 ps |
| T501 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1585444817 |
|
|
Mar 31 03:03:09 PM PDT 24 |
Mar 31 03:07:20 PM PDT 24 |
10924062744 ps |
| T502 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.2922543429 |
|
|
Mar 31 03:04:48 PM PDT 24 |
Mar 31 03:22:29 PM PDT 24 |
80346298476 ps |
| T503 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.2912754418 |
|
|
Mar 31 03:05:09 PM PDT 24 |
Mar 31 03:09:43 PM PDT 24 |
4571930735 ps |
| T504 |
/workspace/coverage/default/2.sram_ctrl_bijection.1810556484 |
|
|
Mar 31 03:00:30 PM PDT 24 |
Mar 31 03:36:58 PM PDT 24 |
113754420490 ps |
| T505 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3449282992 |
|
|
Mar 31 03:01:35 PM PDT 24 |
Mar 31 03:36:08 PM PDT 24 |
19834050372 ps |
| T506 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4133565738 |
|
|
Mar 31 03:09:58 PM PDT 24 |
Mar 31 03:10:12 PM PDT 24 |
738090705 ps |
| T507 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.223005176 |
|
|
Mar 31 03:09:24 PM PDT 24 |
Mar 31 03:21:39 PM PDT 24 |
169515699170 ps |
| T508 |
/workspace/coverage/default/16.sram_ctrl_executable.2163246415 |
|
|
Mar 31 03:03:13 PM PDT 24 |
Mar 31 03:09:01 PM PDT 24 |
14028734237 ps |
| T509 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.274858892 |
|
|
Mar 31 03:11:42 PM PDT 24 |
Mar 31 03:12:04 PM PDT 24 |
3433625225 ps |
| T510 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3503635687 |
|
|
Mar 31 03:06:16 PM PDT 24 |
Mar 31 03:06:23 PM PDT 24 |
2790646147 ps |
| T511 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.3079289955 |
|
|
Mar 31 03:10:40 PM PDT 24 |
Mar 31 03:14:34 PM PDT 24 |
4113341940 ps |
| T512 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1934947581 |
|
|
Mar 31 03:08:46 PM PDT 24 |
Mar 31 03:09:22 PM PDT 24 |
5226367042 ps |
| T513 |
/workspace/coverage/default/32.sram_ctrl_alert_test.3904309541 |
|
|
Mar 31 03:08:00 PM PDT 24 |
Mar 31 03:08:01 PM PDT 24 |
25173023 ps |
| T514 |
/workspace/coverage/default/43.sram_ctrl_regwen.2493697319 |
|
|
Mar 31 03:11:30 PM PDT 24 |
Mar 31 03:34:56 PM PDT 24 |
2819131710 ps |
| T515 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3507189878 |
|
|
Mar 31 03:11:44 PM PDT 24 |
Mar 31 03:11:45 PM PDT 24 |
34014184 ps |
| T516 |
/workspace/coverage/default/26.sram_ctrl_smoke.2401498834 |
|
|
Mar 31 03:05:44 PM PDT 24 |
Mar 31 03:06:04 PM PDT 24 |
10392996607 ps |
| T517 |
/workspace/coverage/default/20.sram_ctrl_partial_access.768951498 |
|
|
Mar 31 03:04:08 PM PDT 24 |
Mar 31 03:04:27 PM PDT 24 |
3150599650 ps |
| T518 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1712343854 |
|
|
Mar 31 03:10:45 PM PDT 24 |
Mar 31 03:17:12 PM PDT 24 |
6244466853 ps |
| T519 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.872415980 |
|
|
Mar 31 03:12:15 PM PDT 24 |
Mar 31 03:13:29 PM PDT 24 |
10603158443 ps |
| T520 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2945346682 |
|
|
Mar 31 03:09:18 PM PDT 24 |
Mar 31 03:10:44 PM PDT 24 |
1144855411 ps |
| T521 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.520242444 |
|
|
Mar 31 03:02:22 PM PDT 24 |
Mar 31 03:03:17 PM PDT 24 |
1513568687 ps |
| T522 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1276790161 |
|
|
Mar 31 03:06:23 PM PDT 24 |
Mar 31 03:29:08 PM PDT 24 |
55361253545 ps |
| T523 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.4272294124 |
|
|
Mar 31 03:02:38 PM PDT 24 |
Mar 31 03:13:29 PM PDT 24 |
12119455135 ps |
| T524 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.699923018 |
|
|
Mar 31 03:01:29 PM PDT 24 |
Mar 31 03:02:09 PM PDT 24 |
1404046218 ps |
| T525 |
/workspace/coverage/default/40.sram_ctrl_partial_access.558257945 |
|
|
Mar 31 03:10:23 PM PDT 24 |
Mar 31 03:10:50 PM PDT 24 |
1058886164 ps |
| T526 |
/workspace/coverage/default/38.sram_ctrl_smoke.2565373236 |
|
|
Mar 31 03:09:39 PM PDT 24 |
Mar 31 03:09:53 PM PDT 24 |
1038966910 ps |
| T527 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1302871683 |
|
|
Mar 31 03:03:19 PM PDT 24 |
Mar 31 03:44:08 PM PDT 24 |
24750561801 ps |
| T528 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.412114718 |
|
|
Mar 31 03:07:41 PM PDT 24 |
Mar 31 03:12:13 PM PDT 24 |
20364301772 ps |
| T529 |
/workspace/coverage/default/17.sram_ctrl_smoke.1652605291 |
|
|
Mar 31 03:03:19 PM PDT 24 |
Mar 31 03:03:35 PM PDT 24 |
860886701 ps |
| T530 |
/workspace/coverage/default/48.sram_ctrl_bijection.2406681892 |
|
|
Mar 31 03:13:10 PM PDT 24 |
Mar 31 03:31:57 PM PDT 24 |
239801756786 ps |
| T531 |
/workspace/coverage/default/21.sram_ctrl_bijection.2297355256 |
|
|
Mar 31 03:04:15 PM PDT 24 |
Mar 31 03:46:00 PM PDT 24 |
225366933619 ps |
| T532 |
/workspace/coverage/default/31.sram_ctrl_stress_all.2618280350 |
|
|
Mar 31 03:07:46 PM PDT 24 |
Mar 31 05:21:55 PM PDT 24 |
1314701756030 ps |
| T533 |
/workspace/coverage/default/49.sram_ctrl_smoke.2624487393 |
|
|
Mar 31 03:13:33 PM PDT 24 |
Mar 31 03:13:50 PM PDT 24 |
7339533661 ps |
| T534 |
/workspace/coverage/default/35.sram_ctrl_smoke.1877957969 |
|
|
Mar 31 03:08:34 PM PDT 24 |
Mar 31 03:08:41 PM PDT 24 |
2924533101 ps |
| T535 |
/workspace/coverage/default/8.sram_ctrl_bijection.1595487521 |
|
|
Mar 31 03:01:28 PM PDT 24 |
Mar 31 03:09:03 PM PDT 24 |
7262109201 ps |
| T536 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1723411594 |
|
|
Mar 31 03:13:51 PM PDT 24 |
Mar 31 03:15:52 PM PDT 24 |
2062304575 ps |
| T537 |
/workspace/coverage/default/4.sram_ctrl_stress_all.3283063795 |
|
|
Mar 31 03:00:55 PM PDT 24 |
Mar 31 03:40:12 PM PDT 24 |
43815933686 ps |
| T538 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.1576735418 |
|
|
Mar 31 03:04:01 PM PDT 24 |
Mar 31 03:13:47 PM PDT 24 |
48261286418 ps |
| T539 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1387785518 |
|
|
Mar 31 03:01:13 PM PDT 24 |
Mar 31 03:02:26 PM PDT 24 |
9434146191 ps |
| T540 |
/workspace/coverage/default/25.sram_ctrl_regwen.2905950926 |
|
|
Mar 31 03:05:45 PM PDT 24 |
Mar 31 03:18:54 PM PDT 24 |
16804541495 ps |
| T541 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.2479493891 |
|
|
Mar 31 03:04:49 PM PDT 24 |
Mar 31 03:04:53 PM PDT 24 |
1345301958 ps |
| T542 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2866334733 |
|
|
Mar 31 03:08:27 PM PDT 24 |
Mar 31 03:08:50 PM PDT 24 |
4207217092 ps |
| T543 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.1209414708 |
|
|
Mar 31 03:07:16 PM PDT 24 |
Mar 31 03:07:23 PM PDT 24 |
703478488 ps |
| T544 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2944305239 |
|
|
Mar 31 03:08:16 PM PDT 24 |
Mar 31 03:08:19 PM PDT 24 |
678716534 ps |
| T545 |
/workspace/coverage/default/20.sram_ctrl_executable.723396332 |
|
|
Mar 31 03:04:13 PM PDT 24 |
Mar 31 03:14:09 PM PDT 24 |
26221108785 ps |
| T546 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3876476008 |
|
|
Mar 31 03:12:59 PM PDT 24 |
Mar 31 03:22:01 PM PDT 24 |
145835978766 ps |
| T547 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2692104300 |
|
|
Mar 31 03:12:41 PM PDT 24 |
Mar 31 04:33:43 PM PDT 24 |
175803063273 ps |
| T548 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.3400716467 |
|
|
Mar 31 03:03:54 PM PDT 24 |
Mar 31 03:03:57 PM PDT 24 |
1174609821 ps |
| T549 |
/workspace/coverage/default/2.sram_ctrl_stress_all.1878362412 |
|
|
Mar 31 03:00:41 PM PDT 24 |
Mar 31 04:36:24 PM PDT 24 |
75478326792 ps |
| T550 |
/workspace/coverage/default/42.sram_ctrl_stress_all.2162968204 |
|
|
Mar 31 03:11:20 PM PDT 24 |
Mar 31 03:40:18 PM PDT 24 |
150627547456 ps |
| T551 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.3292225909 |
|
|
Mar 31 03:00:05 PM PDT 24 |
Mar 31 03:00:34 PM PDT 24 |
3090174333 ps |