| T797 |
/workspace/coverage/default/28.sram_ctrl_bijection.2002376197 |
|
|
Mar 31 03:06:28 PM PDT 24 |
Mar 31 03:15:36 PM PDT 24 |
10388989888 ps |
| T798 |
/workspace/coverage/default/27.sram_ctrl_executable.2323332260 |
|
|
Mar 31 03:06:22 PM PDT 24 |
Mar 31 03:20:00 PM PDT 24 |
17147074011 ps |
| T799 |
/workspace/coverage/default/31.sram_ctrl_alert_test.782785372 |
|
|
Mar 31 03:07:47 PM PDT 24 |
Mar 31 03:07:48 PM PDT 24 |
23292150 ps |
| T800 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.4133239675 |
|
|
Mar 31 03:03:26 PM PDT 24 |
Mar 31 03:05:22 PM PDT 24 |
4205119955 ps |
| T801 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3987652539 |
|
|
Mar 31 03:00:42 PM PDT 24 |
Mar 31 03:12:29 PM PDT 24 |
35611701947 ps |
| T802 |
/workspace/coverage/default/18.sram_ctrl_bijection.1648297740 |
|
|
Mar 31 03:03:40 PM PDT 24 |
Mar 31 03:23:53 PM PDT 24 |
64362526418 ps |
| T803 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1046812208 |
|
|
Mar 31 03:10:41 PM PDT 24 |
Mar 31 03:13:18 PM PDT 24 |
24905242766 ps |
| T804 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.3807736221 |
|
|
Mar 31 03:03:11 PM PDT 24 |
Mar 31 03:03:38 PM PDT 24 |
5192945787 ps |
| T805 |
/workspace/coverage/default/29.sram_ctrl_stress_all.2031485524 |
|
|
Mar 31 03:07:03 PM PDT 24 |
Mar 31 04:37:08 PM PDT 24 |
123282294920 ps |
| T806 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.4056717942 |
|
|
Mar 31 03:12:00 PM PDT 24 |
Mar 31 03:18:36 PM PDT 24 |
22438503458 ps |
| T807 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.2844680351 |
|
|
Mar 31 03:03:50 PM PDT 24 |
Mar 31 03:05:51 PM PDT 24 |
8226175201 ps |
| T808 |
/workspace/coverage/default/15.sram_ctrl_smoke.2130369665 |
|
|
Mar 31 03:02:47 PM PDT 24 |
Mar 31 03:03:04 PM PDT 24 |
1166073040 ps |
| T809 |
/workspace/coverage/default/8.sram_ctrl_regwen.1632496461 |
|
|
Mar 31 03:01:36 PM PDT 24 |
Mar 31 03:15:39 PM PDT 24 |
4064133348 ps |
| T810 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2187730646 |
|
|
Mar 31 03:02:13 PM PDT 24 |
Mar 31 03:02:16 PM PDT 24 |
346990930 ps |
| T811 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2570523280 |
|
|
Mar 31 03:01:00 PM PDT 24 |
Mar 31 03:05:59 PM PDT 24 |
4492818088 ps |
| T812 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2803587593 |
|
|
Mar 31 03:02:00 PM PDT 24 |
Mar 31 03:06:00 PM PDT 24 |
4617444589 ps |
| T813 |
/workspace/coverage/default/41.sram_ctrl_regwen.834644919 |
|
|
Mar 31 03:10:53 PM PDT 24 |
Mar 31 03:28:53 PM PDT 24 |
17664722795 ps |
| T814 |
/workspace/coverage/default/5.sram_ctrl_bijection.3838713186 |
|
|
Mar 31 03:00:59 PM PDT 24 |
Mar 31 03:08:34 PM PDT 24 |
28726206982 ps |
| T815 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2845096582 |
|
|
Mar 31 03:13:12 PM PDT 24 |
Mar 31 03:13:50 PM PDT 24 |
1539555760 ps |
| T816 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3831704644 |
|
|
Mar 31 03:08:33 PM PDT 24 |
Mar 31 03:10:57 PM PDT 24 |
29176680414 ps |
| T817 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.4104619568 |
|
|
Mar 31 03:08:47 PM PDT 24 |
Mar 31 03:08:51 PM PDT 24 |
1349494398 ps |
| T818 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.4117269644 |
|
|
Mar 31 03:00:17 PM PDT 24 |
Mar 31 03:04:35 PM PDT 24 |
7531230095 ps |
| T819 |
/workspace/coverage/default/46.sram_ctrl_executable.4222606495 |
|
|
Mar 31 03:12:34 PM PDT 24 |
Mar 31 03:18:08 PM PDT 24 |
52533687895 ps |
| T80 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.212682822 |
|
|
Mar 31 03:11:59 PM PDT 24 |
Mar 31 03:13:16 PM PDT 24 |
10424906906 ps |
| T820 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.855762000 |
|
|
Mar 31 03:00:34 PM PDT 24 |
Mar 31 03:12:43 PM PDT 24 |
39587804096 ps |
| T821 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.873570107 |
|
|
Mar 31 03:01:11 PM PDT 24 |
Mar 31 03:01:47 PM PDT 24 |
10121436554 ps |
| T822 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.52820848 |
|
|
Mar 31 03:00:10 PM PDT 24 |
Mar 31 03:04:22 PM PDT 24 |
23863355380 ps |
| T823 |
/workspace/coverage/default/21.sram_ctrl_partial_access.2402257549 |
|
|
Mar 31 03:04:23 PM PDT 24 |
Mar 31 03:04:47 PM PDT 24 |
1583890921 ps |
| T824 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1491589898 |
|
|
Mar 31 03:01:00 PM PDT 24 |
Mar 31 03:02:15 PM PDT 24 |
35511219629 ps |
| T825 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.839153645 |
|
|
Mar 31 03:09:29 PM PDT 24 |
Mar 31 03:09:33 PM PDT 24 |
1166624884 ps |
| T826 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2741948609 |
|
|
Mar 31 03:03:20 PM PDT 24 |
Mar 31 03:05:48 PM PDT 24 |
27496558924 ps |
| T827 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.1682082037 |
|
|
Mar 31 03:12:59 PM PDT 24 |
Mar 31 03:18:30 PM PDT 24 |
103229609269 ps |
| T828 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3040829165 |
|
|
Mar 31 03:00:28 PM PDT 24 |
Mar 31 03:01:56 PM PDT 24 |
3479114755 ps |
| T829 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.185482077 |
|
|
Mar 31 03:13:53 PM PDT 24 |
Mar 31 03:14:54 PM PDT 24 |
959513435 ps |
| T830 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.4150577364 |
|
|
Mar 31 03:01:38 PM PDT 24 |
Mar 31 03:01:41 PM PDT 24 |
706836100 ps |
| T831 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1489205179 |
|
|
Mar 31 03:10:57 PM PDT 24 |
Mar 31 04:06:26 PM PDT 24 |
92978975156 ps |
| T832 |
/workspace/coverage/default/46.sram_ctrl_smoke.3107043399 |
|
|
Mar 31 03:12:25 PM PDT 24 |
Mar 31 03:12:42 PM PDT 24 |
544782557 ps |
| T833 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2806203580 |
|
|
Mar 31 03:09:58 PM PDT 24 |
Mar 31 03:16:27 PM PDT 24 |
69415193883 ps |
| T834 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.1335121787 |
|
|
Mar 31 03:07:03 PM PDT 24 |
Mar 31 03:09:23 PM PDT 24 |
7113385970 ps |
| T835 |
/workspace/coverage/default/49.sram_ctrl_bijection.162687668 |
|
|
Mar 31 03:13:32 PM PDT 24 |
Mar 31 03:33:13 PM PDT 24 |
59957982145 ps |
| T836 |
/workspace/coverage/default/43.sram_ctrl_smoke.3290581009 |
|
|
Mar 31 03:11:19 PM PDT 24 |
Mar 31 03:13:07 PM PDT 24 |
7354487727 ps |
| T837 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1988166215 |
|
|
Mar 31 03:00:23 PM PDT 24 |
Mar 31 03:07:56 PM PDT 24 |
18061389806 ps |
| T838 |
/workspace/coverage/default/45.sram_ctrl_bijection.3117487219 |
|
|
Mar 31 03:12:00 PM PDT 24 |
Mar 31 03:39:21 PM PDT 24 |
25840239611 ps |
| T839 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2297520592 |
|
|
Mar 31 03:11:43 PM PDT 24 |
Mar 31 03:12:58 PM PDT 24 |
9814788969 ps |
| T840 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.2821907636 |
|
|
Mar 31 03:05:10 PM PDT 24 |
Mar 31 03:10:02 PM PDT 24 |
18669126268 ps |
| T841 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.214506255 |
|
|
Mar 31 03:03:24 PM PDT 24 |
Mar 31 03:03:33 PM PDT 24 |
716266899 ps |
| T842 |
/workspace/coverage/default/6.sram_ctrl_regwen.1671759731 |
|
|
Mar 31 03:01:13 PM PDT 24 |
Mar 31 03:03:53 PM PDT 24 |
7932668827 ps |
| T843 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4051538105 |
|
|
Mar 31 03:13:26 PM PDT 24 |
Mar 31 03:13:53 PM PDT 24 |
4190791721 ps |
| T844 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3151805872 |
|
|
Mar 31 03:10:31 PM PDT 24 |
Mar 31 03:28:51 PM PDT 24 |
10931466457 ps |
| T845 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3859912484 |
|
|
Mar 31 03:09:00 PM PDT 24 |
Mar 31 03:17:56 PM PDT 24 |
83164530545 ps |
| T846 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.2885983286 |
|
|
Mar 31 03:06:44 PM PDT 24 |
Mar 31 03:11:43 PM PDT 24 |
39677187815 ps |
| T847 |
/workspace/coverage/default/4.sram_ctrl_regwen.2297896281 |
|
|
Mar 31 03:00:52 PM PDT 24 |
Mar 31 03:01:22 PM PDT 24 |
1530596730 ps |
| T848 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.529799897 |
|
|
Mar 31 03:09:45 PM PDT 24 |
Mar 31 03:09:49 PM PDT 24 |
350053891 ps |
| T849 |
/workspace/coverage/default/47.sram_ctrl_smoke.2344465267 |
|
|
Mar 31 03:12:48 PM PDT 24 |
Mar 31 03:13:04 PM PDT 24 |
10075712206 ps |
| T850 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.750685386 |
|
|
Mar 31 03:02:24 PM PDT 24 |
Mar 31 03:03:18 PM PDT 24 |
740906314 ps |
| T851 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.4106744020 |
|
|
Mar 31 03:05:27 PM PDT 24 |
Mar 31 03:07:28 PM PDT 24 |
1978537013 ps |
| T852 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3465011045 |
|
|
Mar 31 03:00:52 PM PDT 24 |
Mar 31 03:04:54 PM PDT 24 |
3945172836 ps |
| T853 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1710336491 |
|
|
Mar 31 03:02:06 PM PDT 24 |
Mar 31 03:03:19 PM PDT 24 |
4718409809 ps |
| T854 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.761336982 |
|
|
Mar 31 03:09:56 PM PDT 24 |
Mar 31 03:10:11 PM PDT 24 |
1679998441 ps |
| T855 |
/workspace/coverage/default/13.sram_ctrl_regwen.1026836612 |
|
|
Mar 31 03:02:36 PM PDT 24 |
Mar 31 03:21:06 PM PDT 24 |
76658082892 ps |
| T856 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3503215900 |
|
|
Mar 31 03:13:18 PM PDT 24 |
Mar 31 03:13:24 PM PDT 24 |
3058197950 ps |
| T857 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2990577478 |
|
|
Mar 31 03:02:00 PM PDT 24 |
Mar 31 03:02:15 PM PDT 24 |
493233785 ps |
| T858 |
/workspace/coverage/default/41.sram_ctrl_smoke.865471226 |
|
|
Mar 31 03:10:41 PM PDT 24 |
Mar 31 03:11:13 PM PDT 24 |
825740453 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1213015055 |
|
|
Mar 31 03:11:06 PM PDT 24 |
Mar 31 03:13:33 PM PDT 24 |
1144279602 ps |
| T860 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3152301459 |
|
|
Mar 31 03:01:27 PM PDT 24 |
Mar 31 03:01:58 PM PDT 24 |
5155206485 ps |
| T861 |
/workspace/coverage/default/29.sram_ctrl_executable.2861150183 |
|
|
Mar 31 03:07:03 PM PDT 24 |
Mar 31 03:12:57 PM PDT 24 |
16269098082 ps |
| T862 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1825759081 |
|
|
Mar 31 03:02:12 PM PDT 24 |
Mar 31 03:05:42 PM PDT 24 |
20156502262 ps |
| T863 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3333837051 |
|
|
Mar 31 03:00:27 PM PDT 24 |
Mar 31 03:06:14 PM PDT 24 |
17699974930 ps |
| T864 |
/workspace/coverage/default/36.sram_ctrl_executable.3536864905 |
|
|
Mar 31 03:09:05 PM PDT 24 |
Mar 31 03:14:15 PM PDT 24 |
51839272857 ps |
| T865 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2254966942 |
|
|
Mar 31 03:12:05 PM PDT 24 |
Mar 31 03:15:12 PM PDT 24 |
3449310507 ps |
| T866 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.584494648 |
|
|
Mar 31 03:11:49 PM PDT 24 |
Mar 31 03:20:53 PM PDT 24 |
212496297959 ps |
| T867 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1528206990 |
|
|
Mar 31 03:04:48 PM PDT 24 |
Mar 31 03:05:26 PM PDT 24 |
1483463166 ps |
| T868 |
/workspace/coverage/default/7.sram_ctrl_regwen.4247198733 |
|
|
Mar 31 03:01:28 PM PDT 24 |
Mar 31 03:14:50 PM PDT 24 |
3349254841 ps |
| T869 |
/workspace/coverage/default/14.sram_ctrl_stress_all.1448555056 |
|
|
Mar 31 03:02:50 PM PDT 24 |
Mar 31 04:05:42 PM PDT 24 |
168700321522 ps |
| T870 |
/workspace/coverage/default/21.sram_ctrl_executable.3014113594 |
|
|
Mar 31 03:04:28 PM PDT 24 |
Mar 31 03:14:56 PM PDT 24 |
71609228215 ps |
| T871 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.1146707101 |
|
|
Mar 31 03:06:40 PM PDT 24 |
Mar 31 03:07:43 PM PDT 24 |
19437320846 ps |
| T872 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1837469701 |
|
|
Mar 31 03:01:15 PM PDT 24 |
Mar 31 03:02:05 PM PDT 24 |
1725841731 ps |
| T873 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2312314127 |
|
|
Mar 31 03:12:41 PM PDT 24 |
Mar 31 03:15:02 PM PDT 24 |
4972927507 ps |
| T874 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3863249601 |
|
|
Mar 31 03:02:30 PM PDT 24 |
Mar 31 03:02:31 PM PDT 24 |
11713156 ps |
| T875 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1536269816 |
|
|
Mar 31 03:00:59 PM PDT 24 |
Mar 31 03:07:09 PM PDT 24 |
68006870234 ps |
| T876 |
/workspace/coverage/default/28.sram_ctrl_smoke.1448328627 |
|
|
Mar 31 03:06:29 PM PDT 24 |
Mar 31 03:06:41 PM PDT 24 |
483969102 ps |
| T877 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3420292217 |
|
|
Mar 31 03:11:30 PM PDT 24 |
Mar 31 03:30:28 PM PDT 24 |
214450583801 ps |
| T878 |
/workspace/coverage/default/9.sram_ctrl_bijection.2817976597 |
|
|
Mar 31 03:01:42 PM PDT 24 |
Mar 31 03:15:02 PM PDT 24 |
147706681714 ps |
| T879 |
/workspace/coverage/default/24.sram_ctrl_stress_all.2113057500 |
|
|
Mar 31 03:05:34 PM PDT 24 |
Mar 31 03:25:34 PM PDT 24 |
62154555933 ps |
| T880 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.937435370 |
|
|
Mar 31 03:00:49 PM PDT 24 |
Mar 31 03:02:43 PM PDT 24 |
6490374800 ps |
| T881 |
/workspace/coverage/default/22.sram_ctrl_smoke.1718898764 |
|
|
Mar 31 03:04:36 PM PDT 24 |
Mar 31 03:06:23 PM PDT 24 |
2503520851 ps |
| T882 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2921887246 |
|
|
Mar 31 03:08:47 PM PDT 24 |
Mar 31 03:11:15 PM PDT 24 |
14332908079 ps |
| T883 |
/workspace/coverage/default/19.sram_ctrl_smoke.601848565 |
|
|
Mar 31 03:03:55 PM PDT 24 |
Mar 31 03:04:14 PM PDT 24 |
15194091788 ps |
| T884 |
/workspace/coverage/default/46.sram_ctrl_bijection.2007828300 |
|
|
Mar 31 03:12:22 PM PDT 24 |
Mar 31 03:28:39 PM PDT 24 |
61486570910 ps |
| T885 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1840782862 |
|
|
Mar 31 03:01:14 PM PDT 24 |
Mar 31 03:01:29 PM PDT 24 |
488017327 ps |
| T886 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.4068491668 |
|
|
Mar 31 03:09:24 PM PDT 24 |
Mar 31 03:11:07 PM PDT 24 |
22272893529 ps |
| T887 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2035535897 |
|
|
Mar 31 03:00:35 PM PDT 24 |
Mar 31 03:02:38 PM PDT 24 |
6440245184 ps |
| T36 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.971878538 |
|
|
Mar 31 03:00:17 PM PDT 24 |
Mar 31 03:00:22 PM PDT 24 |
939205541 ps |
| T888 |
/workspace/coverage/default/42.sram_ctrl_regwen.3461789986 |
|
|
Mar 31 03:11:14 PM PDT 24 |
Mar 31 03:15:37 PM PDT 24 |
20547541351 ps |
| T889 |
/workspace/coverage/default/39.sram_ctrl_alert_test.3249289755 |
|
|
Mar 31 03:10:17 PM PDT 24 |
Mar 31 03:10:18 PM PDT 24 |
35780941 ps |
| T890 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2141206993 |
|
|
Mar 31 03:11:42 PM PDT 24 |
Mar 31 03:23:49 PM PDT 24 |
18549128393 ps |
| T891 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.3727942578 |
|
|
Mar 31 03:06:21 PM PDT 24 |
Mar 31 03:06:25 PM PDT 24 |
1396568536 ps |
| T892 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1933810475 |
|
|
Mar 31 03:13:33 PM PDT 24 |
Mar 31 03:13:33 PM PDT 24 |
18663643 ps |
| T893 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1950173375 |
|
|
Mar 31 03:11:08 PM PDT 24 |
Mar 31 03:12:04 PM PDT 24 |
36939277636 ps |
| T894 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3311343821 |
|
|
Mar 31 03:12:15 PM PDT 24 |
Mar 31 03:14:19 PM PDT 24 |
1976503557 ps |
| T895 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.1335152784 |
|
|
Mar 31 03:09:01 PM PDT 24 |
Mar 31 03:10:25 PM PDT 24 |
761388139 ps |
| T896 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.234940162 |
|
|
Mar 31 03:01:50 PM PDT 24 |
Mar 31 03:01:53 PM PDT 24 |
727036853 ps |
| T897 |
/workspace/coverage/default/16.sram_ctrl_regwen.1429576737 |
|
|
Mar 31 03:03:18 PM PDT 24 |
Mar 31 03:23:05 PM PDT 24 |
3023353006 ps |
| T898 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.578380081 |
|
|
Mar 31 03:06:05 PM PDT 24 |
Mar 31 03:10:51 PM PDT 24 |
55063302154 ps |
| T899 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.3353414459 |
|
|
Mar 31 03:08:07 PM PDT 24 |
Mar 31 03:08:59 PM PDT 24 |
10424655900 ps |
| T900 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.499969526 |
|
|
Mar 31 03:06:33 PM PDT 24 |
Mar 31 03:07:17 PM PDT 24 |
4120790965 ps |
| T37 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2081904601 |
|
|
Mar 31 03:00:47 PM PDT 24 |
Mar 31 03:00:50 PM PDT 24 |
229210370 ps |
| T901 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.3185379592 |
|
|
Mar 31 03:00:12 PM PDT 24 |
Mar 31 03:04:20 PM PDT 24 |
14591887211 ps |
| T902 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.702215454 |
|
|
Mar 31 03:08:27 PM PDT 24 |
Mar 31 03:15:50 PM PDT 24 |
39655031030 ps |
| T903 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4211946632 |
|
|
Mar 31 03:10:09 PM PDT 24 |
Mar 31 03:10:54 PM PDT 24 |
1594642622 ps |
| T904 |
/workspace/coverage/default/15.sram_ctrl_executable.1600590498 |
|
|
Mar 31 03:02:53 PM PDT 24 |
Mar 31 03:26:34 PM PDT 24 |
35416296772 ps |
| T905 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3266571975 |
|
|
Mar 31 03:00:41 PM PDT 24 |
Mar 31 03:01:30 PM PDT 24 |
23878240097 ps |
| T906 |
/workspace/coverage/default/37.sram_ctrl_smoke.1354369590 |
|
|
Mar 31 03:09:17 PM PDT 24 |
Mar 31 03:09:41 PM PDT 24 |
1410111512 ps |
| T907 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2712535691 |
|
|
Mar 31 03:04:48 PM PDT 24 |
Mar 31 03:06:36 PM PDT 24 |
182302269598 ps |
| T908 |
/workspace/coverage/default/27.sram_ctrl_bijection.3691346829 |
|
|
Mar 31 03:06:11 PM PDT 24 |
Mar 31 03:58:24 PM PDT 24 |
782938769457 ps |
| T909 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.293176037 |
|
|
Mar 31 03:01:22 PM PDT 24 |
Mar 31 03:07:22 PM PDT 24 |
55356613165 ps |
| T910 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1641526434 |
|
|
Mar 31 03:11:07 PM PDT 24 |
Mar 31 03:16:46 PM PDT 24 |
5378047080 ps |
| T911 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1436841047 |
|
|
Mar 31 03:03:23 PM PDT 24 |
Mar 31 03:06:48 PM PDT 24 |
4402845898 ps |
| T912 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.2368910917 |
|
|
Mar 31 03:09:52 PM PDT 24 |
Mar 31 03:25:52 PM PDT 24 |
20008579432 ps |
| T913 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3492875159 |
|
|
Mar 31 03:11:30 PM PDT 24 |
Mar 31 03:18:53 PM PDT 24 |
37430370509 ps |
| T914 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3567581692 |
|
|
Mar 31 03:13:00 PM PDT 24 |
Mar 31 03:13:46 PM PDT 24 |
32630173048 ps |
| T915 |
/workspace/coverage/default/5.sram_ctrl_regwen.4014701388 |
|
|
Mar 31 03:01:00 PM PDT 24 |
Mar 31 03:05:11 PM PDT 24 |
30526360738 ps |
| T916 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.123205279 |
|
|
Mar 31 03:02:46 PM PDT 24 |
Mar 31 03:10:13 PM PDT 24 |
7835891250 ps |
| T917 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3424987454 |
|
|
Mar 31 03:07:22 PM PDT 24 |
Mar 31 03:07:25 PM PDT 24 |
1199510245 ps |
| T918 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1115068693 |
|
|
Mar 31 03:01:37 PM PDT 24 |
Mar 31 03:01:55 PM PDT 24 |
1496423598 ps |
| T919 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2188462796 |
|
|
Mar 31 03:00:54 PM PDT 24 |
Mar 31 03:01:49 PM PDT 24 |
815711953 ps |
| T920 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.747717097 |
|
|
Mar 31 03:12:29 PM PDT 24 |
Mar 31 03:12:59 PM PDT 24 |
1475123243 ps |
| T921 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1353115119 |
|
|
Mar 31 03:05:59 PM PDT 24 |
Mar 31 03:06:02 PM PDT 24 |
708064859 ps |
| T922 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.3048399063 |
|
|
Mar 31 03:07:04 PM PDT 24 |
Mar 31 03:09:34 PM PDT 24 |
4713945898 ps |
| T923 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.4040934704 |
|
|
Mar 31 03:05:18 PM PDT 24 |
Mar 31 03:06:55 PM PDT 24 |
2832495306 ps |
| T924 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.323341535 |
|
|
Mar 31 03:12:25 PM PDT 24 |
Mar 31 03:16:50 PM PDT 24 |
4970743988 ps |
| T925 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1058254218 |
|
|
Mar 31 03:07:49 PM PDT 24 |
Mar 31 03:09:04 PM PDT 24 |
2635637096 ps |
| T926 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1831697338 |
|
|
Mar 31 03:03:40 PM PDT 24 |
Mar 31 03:04:00 PM PDT 24 |
748350743 ps |
| T927 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.1343107340 |
|
|
Mar 31 03:03:54 PM PDT 24 |
Mar 31 03:21:19 PM PDT 24 |
78185875600 ps |
| T928 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1446847343 |
|
|
Mar 31 03:10:09 PM PDT 24 |
Mar 31 03:15:08 PM PDT 24 |
121616040090 ps |
| T929 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1259738722 |
|
|
Mar 31 03:08:26 PM PDT 24 |
Mar 31 03:09:41 PM PDT 24 |
27379569060 ps |
| T930 |
/workspace/coverage/default/32.sram_ctrl_executable.3216079156 |
|
|
Mar 31 03:08:01 PM PDT 24 |
Mar 31 03:10:21 PM PDT 24 |
4425236063 ps |
| T931 |
/workspace/coverage/default/11.sram_ctrl_executable.3762926554 |
|
|
Mar 31 03:02:13 PM PDT 24 |
Mar 31 03:24:27 PM PDT 24 |
84806134421 ps |
| T932 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3783736259 |
|
|
Mar 31 03:06:33 PM PDT 24 |
Mar 31 03:06:50 PM PDT 24 |
2268106274 ps |
| T933 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.3672513509 |
|
|
Mar 31 03:00:29 PM PDT 24 |
Mar 31 03:02:48 PM PDT 24 |
28737472576 ps |
| T934 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2784162555 |
|
|
Mar 31 03:03:55 PM PDT 24 |
Mar 31 03:04:32 PM PDT 24 |
3805326689 ps |
| T935 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3655821510 |
|
|
Mar 31 03:03:41 PM PDT 24 |
Mar 31 03:07:28 PM PDT 24 |
6350601958 ps |
| T936 |
/workspace/coverage/default/20.sram_ctrl_smoke.1708099796 |
|
|
Mar 31 03:04:02 PM PDT 24 |
Mar 31 03:05:47 PM PDT 24 |
461487856 ps |
| T937 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1668675400 |
|
|
Mar 31 03:07:05 PM PDT 24 |
Mar 31 03:07:08 PM PDT 24 |
364741624 ps |
| T938 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.726401869 |
|
|
Mar 31 03:01:12 PM PDT 24 |
Mar 31 03:04:08 PM PDT 24 |
3748415527 ps |
| T939 |
/workspace/coverage/default/5.sram_ctrl_executable.554511819 |
|
|
Mar 31 03:00:58 PM PDT 24 |
Mar 31 03:23:14 PM PDT 24 |
38041340029 ps |
| T940 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1846448383 |
|
|
Mar 31 03:02:15 PM PDT 24 |
Mar 31 03:07:39 PM PDT 24 |
32635160461 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2593456314 |
|
|
Mar 31 03:48:25 PM PDT 24 |
Mar 31 03:48:26 PM PDT 24 |
23595015 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3423210185 |
|
|
Mar 31 03:48:36 PM PDT 24 |
Mar 31 03:48:40 PM PDT 24 |
1950047062 ps |
| T99 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3501900213 |
|
|
Mar 31 03:48:26 PM PDT 24 |
Mar 31 03:48:27 PM PDT 24 |
14004913 ps |
| T62 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2891816321 |
|
|
Mar 31 03:48:14 PM PDT 24 |
Mar 31 03:48:59 PM PDT 24 |
10902846084 ps |
| T127 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.721630483 |
|
|
Mar 31 03:48:39 PM PDT 24 |
Mar 31 03:48:40 PM PDT 24 |
31398768 ps |
| T92 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.483743167 |
|
|
Mar 31 03:48:19 PM PDT 24 |
Mar 31 03:48:20 PM PDT 24 |
15274226 ps |
| T101 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.913856799 |
|
|
Mar 31 03:48:23 PM PDT 24 |
Mar 31 03:48:25 PM PDT 24 |
252832077 ps |
| T942 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2576713327 |
|
|
Mar 31 03:48:04 PM PDT 24 |
Mar 31 03:48:05 PM PDT 24 |
27238209 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2967035866 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:13 PM PDT 24 |
107471892 ps |
| T63 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.629631855 |
|
|
Mar 31 03:48:14 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
23218216 ps |
| T64 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3150626686 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:54 PM PDT 24 |
7418657499 ps |
| T102 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3283435764 |
|
|
Mar 31 03:48:13 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
256020378 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2130417867 |
|
|
Mar 31 03:48:05 PM PDT 24 |
Mar 31 03:48:06 PM PDT 24 |
89856163 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.392547790 |
|
|
Mar 31 03:48:15 PM PDT 24 |
Mar 31 03:48:17 PM PDT 24 |
84018316 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4192096582 |
|
|
Mar 31 03:48:13 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
136693856 ps |
| T65 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1446199852 |
|
|
Mar 31 03:48:16 PM PDT 24 |
Mar 31 03:48:45 PM PDT 24 |
10594784442 ps |
| T66 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3065956085 |
|
|
Mar 31 03:48:29 PM PDT 24 |
Mar 31 03:48:29 PM PDT 24 |
41646172 ps |
| T946 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.61140369 |
|
|
Mar 31 03:48:17 PM PDT 24 |
Mar 31 03:48:21 PM PDT 24 |
365308145 ps |
| T67 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3490010716 |
|
|
Mar 31 03:48:29 PM PDT 24 |
Mar 31 03:48:57 PM PDT 24 |
14182473840 ps |
| T100 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3120628427 |
|
|
Mar 31 03:48:04 PM PDT 24 |
Mar 31 03:48:06 PM PDT 24 |
85086037 ps |
| T114 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1842758401 |
|
|
Mar 31 03:48:31 PM PDT 24 |
Mar 31 03:48:33 PM PDT 24 |
346465165 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.730143021 |
|
|
Mar 31 03:48:02 PM PDT 24 |
Mar 31 03:48:03 PM PDT 24 |
51243070 ps |
| T948 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2181118126 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:16 PM PDT 24 |
130764116 ps |
| T949 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2809163532 |
|
|
Mar 31 03:48:40 PM PDT 24 |
Mar 31 03:48:43 PM PDT 24 |
363443874 ps |
| T68 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2584207592 |
|
|
Mar 31 03:48:16 PM PDT 24 |
Mar 31 03:48:16 PM PDT 24 |
24807471 ps |
| T950 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1980278698 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:13 PM PDT 24 |
94456415 ps |
| T951 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.209305812 |
|
|
Mar 31 03:48:34 PM PDT 24 |
Mar 31 03:48:38 PM PDT 24 |
351940533 ps |
| T69 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2545344216 |
|
|
Mar 31 03:48:35 PM PDT 24 |
Mar 31 03:48:35 PM PDT 24 |
49756802 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2482032618 |
|
|
Mar 31 03:48:07 PM PDT 24 |
Mar 31 03:48:12 PM PDT 24 |
132574121 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3320725545 |
|
|
Mar 31 03:48:10 PM PDT 24 |
Mar 31 03:48:11 PM PDT 24 |
29284532 ps |
| T112 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1409598116 |
|
|
Mar 31 03:48:22 PM PDT 24 |
Mar 31 03:48:24 PM PDT 24 |
112731231 ps |
| T113 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2047788861 |
|
|
Mar 31 03:48:38 PM PDT 24 |
Mar 31 03:48:40 PM PDT 24 |
459344053 ps |
| T953 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3068961945 |
|
|
Mar 31 03:48:28 PM PDT 24 |
Mar 31 03:48:30 PM PDT 24 |
216807256 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3398299528 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
352991132 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.758294595 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:12 PM PDT 24 |
13281650 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1039211649 |
|
|
Mar 31 03:48:06 PM PDT 24 |
Mar 31 03:48:11 PM PDT 24 |
177398154 ps |
| T956 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1502703539 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:16 PM PDT 24 |
161354431 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3085303378 |
|
|
Mar 31 03:48:10 PM PDT 24 |
Mar 31 03:48:11 PM PDT 24 |
27650380 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3716884535 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
70318142 ps |
| T959 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3369310003 |
|
|
Mar 31 03:48:06 PM PDT 24 |
Mar 31 03:48:10 PM PDT 24 |
1500316807 ps |
| T960 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1547292698 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:12 PM PDT 24 |
13319384 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1226387530 |
|
|
Mar 31 03:48:07 PM PDT 24 |
Mar 31 03:48:08 PM PDT 24 |
21014491 ps |
| T962 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3443578041 |
|
|
Mar 31 03:48:17 PM PDT 24 |
Mar 31 03:48:22 PM PDT 24 |
367530079 ps |
| T71 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2227061480 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:13 PM PDT 24 |
31173592 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.683357262 |
|
|
Mar 31 03:48:09 PM PDT 24 |
Mar 31 03:48:10 PM PDT 24 |
48500403 ps |
| T964 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.754518288 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
347979489 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1574032700 |
|
|
Mar 31 03:48:33 PM PDT 24 |
Mar 31 03:48:36 PM PDT 24 |
362234352 ps |
| T966 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1032660657 |
|
|
Mar 31 03:48:29 PM PDT 24 |
Mar 31 03:48:34 PM PDT 24 |
1611109089 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2447700199 |
|
|
Mar 31 03:48:09 PM PDT 24 |
Mar 31 03:48:10 PM PDT 24 |
34965788 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4084316521 |
|
|
Mar 31 03:48:06 PM PDT 24 |
Mar 31 03:48:12 PM PDT 24 |
17263788 ps |
| T968 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4064132876 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:13 PM PDT 24 |
16324558 ps |
| T969 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3912962922 |
|
|
Mar 31 03:48:34 PM PDT 24 |
Mar 31 03:48:36 PM PDT 24 |
102112582 ps |
| T970 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1549344094 |
|
|
Mar 31 03:48:13 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
141828943 ps |
| T74 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1499122651 |
|
|
Mar 31 03:48:29 PM PDT 24 |
Mar 31 03:48:30 PM PDT 24 |
123076571 ps |
| T115 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2237949567 |
|
|
Mar 31 03:48:28 PM PDT 24 |
Mar 31 03:48:30 PM PDT 24 |
261747644 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2728591023 |
|
|
Mar 31 03:48:03 PM PDT 24 |
Mar 31 03:48:04 PM PDT 24 |
39326458 ps |
| T116 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2871912576 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
974735561 ps |
| T75 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3146769915 |
|
|
Mar 31 03:48:15 PM PDT 24 |
Mar 31 03:49:14 PM PDT 24 |
78113383846 ps |
| T972 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1204729351 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:16 PM PDT 24 |
699317939 ps |
| T87 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.59158562 |
|
|
Mar 31 03:48:10 PM PDT 24 |
Mar 31 03:48:59 PM PDT 24 |
14086727049 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3193937948 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:12 PM PDT 24 |
43646525 ps |
| T81 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4097419827 |
|
|
Mar 31 03:48:33 PM PDT 24 |
Mar 31 03:49:21 PM PDT 24 |
14660891586 ps |
| T974 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.546641364 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:14 PM PDT 24 |
254490653 ps |
| T82 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3392467555 |
|
|
Mar 31 03:48:07 PM PDT 24 |
Mar 31 03:48:55 PM PDT 24 |
7744537544 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4105947088 |
|
|
Mar 31 03:48:25 PM PDT 24 |
Mar 31 03:48:29 PM PDT 24 |
682993233 ps |
| T121 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4060347178 |
|
|
Mar 31 03:48:09 PM PDT 24 |
Mar 31 03:48:11 PM PDT 24 |
277673542 ps |
| T83 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3606217690 |
|
|
Mar 31 03:48:15 PM PDT 24 |
Mar 31 03:49:08 PM PDT 24 |
29533986667 ps |
| T123 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1984537450 |
|
|
Mar 31 03:48:23 PM PDT 24 |
Mar 31 03:48:25 PM PDT 24 |
378886454 ps |
| T120 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1072997071 |
|
|
Mar 31 03:48:37 PM PDT 24 |
Mar 31 03:48:40 PM PDT 24 |
193791171 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.770950173 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:16 PM PDT 24 |
37980840 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2825592418 |
|
|
Mar 31 03:48:05 PM PDT 24 |
Mar 31 03:48:05 PM PDT 24 |
16099716 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2831038844 |
|
|
Mar 31 03:48:20 PM PDT 24 |
Mar 31 03:48:23 PM PDT 24 |
1359125337 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2938396808 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:48:12 PM PDT 24 |
16249297 ps |
| T84 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.26513819 |
|
|
Mar 31 03:48:09 PM PDT 24 |
Mar 31 03:48:58 PM PDT 24 |
37331660728 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3120841348 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:20 PM PDT 24 |
568550416 ps |
| T980 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.416421389 |
|
|
Mar 31 03:48:01 PM PDT 24 |
Mar 31 03:48:04 PM PDT 24 |
1900397477 ps |
| T981 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2243964938 |
|
|
Mar 31 03:48:07 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
166493262 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.142186953 |
|
|
Mar 31 03:48:04 PM PDT 24 |
Mar 31 03:48:08 PM PDT 24 |
355969032 ps |
| T983 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1656398061 |
|
|
Mar 31 03:48:43 PM PDT 24 |
Mar 31 03:48:46 PM PDT 24 |
30401176 ps |
| T984 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2589574609 |
|
|
Mar 31 03:48:14 PM PDT 24 |
Mar 31 03:48:43 PM PDT 24 |
13650729784 ps |
| T985 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3934522122 |
|
|
Mar 31 03:48:16 PM PDT 24 |
Mar 31 03:48:17 PM PDT 24 |
54825121 ps |
| T986 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2115890984 |
|
|
Mar 31 03:48:13 PM PDT 24 |
Mar 31 03:48:17 PM PDT 24 |
751205841 ps |
| T85 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2279536830 |
|
|
Mar 31 03:48:07 PM PDT 24 |
Mar 31 03:49:04 PM PDT 24 |
25163502104 ps |
| T987 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.321175874 |
|
|
Mar 31 03:48:27 PM PDT 24 |
Mar 31 03:48:32 PM PDT 24 |
1404738927 ps |
| T988 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3408695501 |
|
|
Mar 31 03:48:29 PM PDT 24 |
Mar 31 03:48:29 PM PDT 24 |
13613535 ps |
| T86 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2724993479 |
|
|
Mar 31 03:48:11 PM PDT 24 |
Mar 31 03:49:00 PM PDT 24 |
13813393061 ps |
| T989 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.72349571 |
|
|
Mar 31 03:48:13 PM PDT 24 |
Mar 31 03:48:14 PM PDT 24 |
11392975 ps |
| T990 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3101772580 |
|
|
Mar 31 03:48:13 PM PDT 24 |
Mar 31 03:48:15 PM PDT 24 |
133015103 ps |
| T991 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4075295921 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:13 PM PDT 24 |
20091199 ps |
| T992 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1560948681 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:13 PM PDT 24 |
22847422 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4116121850 |
|
|
Mar 31 03:48:21 PM PDT 24 |
Mar 31 03:48:21 PM PDT 24 |
25954265 ps |
| T117 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3927165545 |
|
|
Mar 31 03:48:16 PM PDT 24 |
Mar 31 03:48:19 PM PDT 24 |
583822035 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2449837225 |
|
|
Mar 31 03:48:12 PM PDT 24 |
Mar 31 03:48:17 PM PDT 24 |
371112226 ps |
| T995 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1995887732 |
|
|
Mar 31 03:48:28 PM PDT 24 |
Mar 31 03:48:29 PM PDT 24 |
27655552 ps |
| T996 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.965692173 |
|
|
Mar 31 03:48:13 PM PDT 24 |
Mar 31 03:48:58 PM PDT 24 |
7470218440 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3137568497 |
|
|
Mar 31 03:48:13 PM PDT 24 |
Mar 31 03:48:14 PM PDT 24 |
17031226 ps |
| T998 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1164919650 |
|
|
Mar 31 03:48:36 PM PDT 24 |
Mar 31 03:48:39 PM PDT 24 |
133685008 ps |
| T999 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.189218792 |
|
|
Mar 31 03:48:36 PM PDT 24 |
Mar 31 03:48:39 PM PDT 24 |
706754964 ps |
| T1000 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3009580278 |
|
|
Mar 31 03:48:27 PM PDT 24 |
Mar 31 03:48:28 PM PDT 24 |
13310557 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1065871941 |
|
|
Mar 31 03:48:13 PM PDT 24 |
Mar 31 03:48:14 PM PDT 24 |
44587807 ps |
| T1002 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3050747917 |
|
|
Mar 31 03:48:10 PM PDT 24 |
Mar 31 03:48:56 PM PDT 24 |
7107357329 ps |
| T1003 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.892645955 |
|
|
Mar 31 03:48:16 PM PDT 24 |
Mar 31 03:48:18 PM PDT 24 |
85912361 ps |
| T124 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3543090904 |
|
|
Mar 31 03:48:14 PM PDT 24 |
Mar 31 03:48:17 PM PDT 24 |
167221911 ps |