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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total test records in report: 1035
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T791 /workspace/coverage/default/23.sram_ctrl_executable.1346244439 May 05 12:50:33 PM PDT 24 May 05 01:09:41 PM PDT 24 34551828334 ps
T792 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.443793906 May 05 12:50:21 PM PDT 24 May 05 12:51:38 PM PDT 24 10629420819 ps
T793 /workspace/coverage/default/5.sram_ctrl_stress_all.2638218607 May 05 12:48:15 PM PDT 24 May 05 01:55:35 PM PDT 24 49293359825 ps
T794 /workspace/coverage/default/23.sram_ctrl_multiple_keys.1137046369 May 05 12:50:22 PM PDT 24 May 05 01:03:03 PM PDT 24 27405059250 ps
T795 /workspace/coverage/default/48.sram_ctrl_lc_escalation.1567641328 May 05 12:56:26 PM PDT 24 May 05 12:57:15 PM PDT 24 28560468423 ps
T796 /workspace/coverage/default/16.sram_ctrl_partial_access.705089537 May 05 12:49:11 PM PDT 24 May 05 12:49:25 PM PDT 24 3398535539 ps
T797 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3287577626 May 05 12:48:02 PM PDT 24 May 05 12:50:39 PM PDT 24 4966404373 ps
T798 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.4063796846 May 05 12:55:17 PM PDT 24 May 05 01:00:49 PM PDT 24 17561151226 ps
T799 /workspace/coverage/default/35.sram_ctrl_ram_cfg.1493040310 May 05 12:53:26 PM PDT 24 May 05 12:53:29 PM PDT 24 353573633 ps
T800 /workspace/coverage/default/37.sram_ctrl_alert_test.3860823356 May 05 12:53:58 PM PDT 24 May 05 12:53:59 PM PDT 24 13232598 ps
T801 /workspace/coverage/default/9.sram_ctrl_lc_escalation.2260933335 May 05 12:48:22 PM PDT 24 May 05 12:49:32 PM PDT 24 11129548195 ps
T802 /workspace/coverage/default/31.sram_ctrl_ram_cfg.2062584229 May 05 12:52:12 PM PDT 24 May 05 12:52:16 PM PDT 24 460121301 ps
T803 /workspace/coverage/default/44.sram_ctrl_partial_access.3224164044 May 05 12:55:30 PM PDT 24 May 05 12:55:38 PM PDT 24 2426771890 ps
T804 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1689116657 May 05 12:48:44 PM PDT 24 May 05 12:49:03 PM PDT 24 734948929 ps
T805 /workspace/coverage/default/1.sram_ctrl_executable.942901583 May 05 12:47:59 PM PDT 24 May 05 01:06:03 PM PDT 24 8450379950 ps
T806 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2754302161 May 05 12:55:29 PM PDT 24 May 05 12:58:16 PM PDT 24 40790953992 ps
T807 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.996675107 May 05 12:50:43 PM PDT 24 May 05 01:07:54 PM PDT 24 34958086800 ps
T808 /workspace/coverage/default/20.sram_ctrl_max_throughput.296109101 May 05 12:49:48 PM PDT 24 May 05 12:50:18 PM PDT 24 736451664 ps
T809 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1792060574 May 05 12:52:58 PM PDT 24 May 05 12:59:56 PM PDT 24 18255919107 ps
T810 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3222964682 May 05 12:49:44 PM PDT 24 May 05 12:50:14 PM PDT 24 4522849032 ps
T811 /workspace/coverage/default/23.sram_ctrl_stress_all.583530965 May 05 12:50:34 PM PDT 24 May 05 01:59:27 PM PDT 24 495115870808 ps
T812 /workspace/coverage/default/7.sram_ctrl_mem_walk.1236840863 May 05 12:48:19 PM PDT 24 May 05 12:50:21 PM PDT 24 8234551049 ps
T813 /workspace/coverage/default/47.sram_ctrl_stress_all.1408075022 May 05 12:56:20 PM PDT 24 May 05 01:44:49 PM PDT 24 14716188287 ps
T814 /workspace/coverage/default/10.sram_ctrl_executable.1902045305 May 05 12:48:30 PM PDT 24 May 05 01:08:42 PM PDT 24 7258786967 ps
T815 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.550969986 May 05 12:51:13 PM PDT 24 May 05 12:52:25 PM PDT 24 4802254491 ps
T816 /workspace/coverage/default/20.sram_ctrl_alert_test.3680761577 May 05 12:50:01 PM PDT 24 May 05 12:50:02 PM PDT 24 24733561 ps
T817 /workspace/coverage/default/49.sram_ctrl_ram_cfg.928117148 May 05 12:56:51 PM PDT 24 May 05 12:56:55 PM PDT 24 354913539 ps
T818 /workspace/coverage/default/18.sram_ctrl_stress_all.1923289770 May 05 12:49:39 PM PDT 24 May 05 02:03:42 PM PDT 24 134240960226 ps
T819 /workspace/coverage/default/28.sram_ctrl_lc_escalation.2600473738 May 05 12:51:32 PM PDT 24 May 05 12:52:20 PM PDT 24 32402844496 ps
T820 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1157988328 May 05 12:53:47 PM PDT 24 May 05 12:57:53 PM PDT 24 3409731348 ps
T821 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2015453335 May 05 12:54:01 PM PDT 24 May 05 12:59:02 PM PDT 24 19137956826 ps
T822 /workspace/coverage/default/20.sram_ctrl_stress_all.1883883993 May 05 12:50:00 PM PDT 24 May 05 02:50:46 PM PDT 24 481162939516 ps
T823 /workspace/coverage/default/46.sram_ctrl_bijection.3369578433 May 05 12:55:56 PM PDT 24 May 05 01:05:22 PM PDT 24 138798555039 ps
T824 /workspace/coverage/default/34.sram_ctrl_executable.103787618 May 05 12:53:04 PM PDT 24 May 05 01:06:52 PM PDT 24 4427246228 ps
T825 /workspace/coverage/default/36.sram_ctrl_stress_all.287129812 May 05 12:53:41 PM PDT 24 May 05 02:18:17 PM PDT 24 238394800904 ps
T826 /workspace/coverage/default/8.sram_ctrl_mem_walk.2288093943 May 05 12:48:19 PM PDT 24 May 05 12:52:30 PM PDT 24 16422862262 ps
T827 /workspace/coverage/default/13.sram_ctrl_ram_cfg.1293197076 May 05 12:48:48 PM PDT 24 May 05 12:48:51 PM PDT 24 1412409723 ps
T828 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1002411302 May 05 12:52:08 PM PDT 24 May 05 12:58:32 PM PDT 24 16026428588 ps
T829 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2189663751 May 05 12:50:38 PM PDT 24 May 05 12:56:33 PM PDT 24 5588631519 ps
T830 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2678785700 May 05 12:53:21 PM PDT 24 May 05 12:56:40 PM PDT 24 8190211223 ps
T831 /workspace/coverage/default/21.sram_ctrl_executable.610044602 May 05 12:50:13 PM PDT 24 May 05 01:04:01 PM PDT 24 69817859877 ps
T832 /workspace/coverage/default/22.sram_ctrl_multiple_keys.398220655 May 05 12:50:13 PM PDT 24 May 05 01:09:57 PM PDT 24 14747934003 ps
T833 /workspace/coverage/default/29.sram_ctrl_smoke.3768232439 May 05 12:51:36 PM PDT 24 May 05 12:53:14 PM PDT 24 2533836871 ps
T834 /workspace/coverage/default/38.sram_ctrl_max_throughput.411028046 May 05 12:54:01 PM PDT 24 May 05 12:56:09 PM PDT 24 806353138 ps
T835 /workspace/coverage/default/31.sram_ctrl_mem_walk.4202432938 May 05 12:52:19 PM PDT 24 May 05 12:54:41 PM PDT 24 6899363675 ps
T836 /workspace/coverage/default/35.sram_ctrl_smoke.1539105131 May 05 12:53:19 PM PDT 24 May 05 12:54:44 PM PDT 24 972672835 ps
T837 /workspace/coverage/default/39.sram_ctrl_smoke.1424109986 May 05 12:54:12 PM PDT 24 May 05 12:54:30 PM PDT 24 1068242020 ps
T838 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3434674241 May 05 12:48:45 PM PDT 24 May 05 12:53:21 PM PDT 24 9185541080 ps
T839 /workspace/coverage/default/27.sram_ctrl_regwen.3084235229 May 05 12:51:20 PM PDT 24 May 05 01:05:58 PM PDT 24 15478063755 ps
T840 /workspace/coverage/default/45.sram_ctrl_multiple_keys.2718768596 May 05 12:55:38 PM PDT 24 May 05 01:15:55 PM PDT 24 135537187305 ps
T841 /workspace/coverage/default/36.sram_ctrl_ram_cfg.296275275 May 05 12:53:43 PM PDT 24 May 05 12:53:47 PM PDT 24 347967581 ps
T842 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.807466832 May 05 12:55:02 PM PDT 24 May 05 12:55:28 PM PDT 24 6498722878 ps
T843 /workspace/coverage/default/49.sram_ctrl_bijection.1667846853 May 05 12:56:38 PM PDT 24 May 05 01:12:24 PM PDT 24 29256386162 ps
T844 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3001719021 May 05 12:48:34 PM PDT 24 May 05 12:50:37 PM PDT 24 5993775176 ps
T845 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2123762221 May 05 12:54:29 PM PDT 24 May 05 12:59:37 PM PDT 24 66175355244 ps
T846 /workspace/coverage/default/38.sram_ctrl_mem_walk.467329144 May 05 12:54:04 PM PDT 24 May 05 12:56:34 PM PDT 24 28752447805 ps
T847 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.647137144 May 05 12:53:41 PM PDT 24 May 05 12:54:32 PM PDT 24 20303348590 ps
T848 /workspace/coverage/default/12.sram_ctrl_mem_walk.3049530039 May 05 12:48:48 PM PDT 24 May 05 12:52:54 PM PDT 24 16424358615 ps
T849 /workspace/coverage/default/45.sram_ctrl_alert_test.2225504305 May 05 12:55:51 PM PDT 24 May 05 12:55:52 PM PDT 24 37306603 ps
T850 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1647174918 May 05 12:51:55 PM PDT 24 May 05 12:55:07 PM PDT 24 12273854277 ps
T851 /workspace/coverage/default/19.sram_ctrl_max_throughput.1109621376 May 05 12:49:42 PM PDT 24 May 05 12:49:50 PM PDT 24 2679502204 ps
T852 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4214339163 May 05 12:47:54 PM PDT 24 May 05 12:53:50 PM PDT 24 69811411362 ps
T853 /workspace/coverage/default/23.sram_ctrl_regwen.3712149454 May 05 12:50:34 PM PDT 24 May 05 01:03:42 PM PDT 24 5535211185 ps
T854 /workspace/coverage/default/23.sram_ctrl_smoke.1987074738 May 05 12:50:21 PM PDT 24 May 05 12:51:23 PM PDT 24 952366924 ps
T855 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2203915655 May 05 12:54:01 PM PDT 24 May 05 12:58:40 PM PDT 24 27368153859 ps
T856 /workspace/coverage/default/47.sram_ctrl_mem_walk.2500998170 May 05 12:56:11 PM PDT 24 May 05 01:01:30 PM PDT 24 86107308490 ps
T857 /workspace/coverage/default/12.sram_ctrl_alert_test.3529343307 May 05 12:48:43 PM PDT 24 May 05 12:48:45 PM PDT 24 42272146 ps
T858 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2398165019 May 05 12:51:21 PM PDT 24 May 05 12:51:25 PM PDT 24 4181279201 ps
T859 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2986631174 May 05 12:48:08 PM PDT 24 May 05 12:53:29 PM PDT 24 16017903652 ps
T860 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.184316147 May 05 12:49:16 PM PDT 24 May 05 12:54:18 PM PDT 24 44164289339 ps
T31 /workspace/coverage/default/4.sram_ctrl_sec_cm.3922108789 May 05 12:48:04 PM PDT 24 May 05 12:48:08 PM PDT 24 474984009 ps
T861 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.877903111 May 05 12:52:27 PM PDT 24 May 05 12:57:45 PM PDT 24 9367551722 ps
T862 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.4228754637 May 05 12:48:33 PM PDT 24 May 05 01:05:50 PM PDT 24 13372981362 ps
T863 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2056989104 May 05 12:56:12 PM PDT 24 May 05 01:07:13 PM PDT 24 8756079934 ps
T864 /workspace/coverage/default/15.sram_ctrl_multiple_keys.935837036 May 05 12:49:01 PM PDT 24 May 05 01:21:11 PM PDT 24 56549689235 ps
T865 /workspace/coverage/default/27.sram_ctrl_smoke.1666992050 May 05 12:51:10 PM PDT 24 May 05 12:51:24 PM PDT 24 2727629273 ps
T866 /workspace/coverage/default/14.sram_ctrl_alert_test.3485522441 May 05 12:48:59 PM PDT 24 May 05 12:49:00 PM PDT 24 19395022 ps
T867 /workspace/coverage/default/26.sram_ctrl_partial_access.106237334 May 05 12:51:01 PM PDT 24 May 05 12:53:04 PM PDT 24 1343192494 ps
T868 /workspace/coverage/default/4.sram_ctrl_alert_test.3865225526 May 05 12:48:09 PM PDT 24 May 05 12:48:11 PM PDT 24 40013093 ps
T869 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2749902595 May 05 12:52:00 PM PDT 24 May 05 12:59:15 PM PDT 24 81011279924 ps
T870 /workspace/coverage/default/27.sram_ctrl_alert_test.698612014 May 05 12:51:21 PM PDT 24 May 05 12:51:23 PM PDT 24 12091769 ps
T871 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.297038240 May 05 12:53:10 PM PDT 24 May 05 12:53:21 PM PDT 24 691465035 ps
T88 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4127257322 May 05 12:55:02 PM PDT 24 May 05 12:56:16 PM PDT 24 24152605967 ps
T872 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.962132923 May 05 12:48:12 PM PDT 24 May 05 12:48:19 PM PDT 24 2927520742 ps
T873 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2080654119 May 05 12:50:46 PM PDT 24 May 05 12:50:55 PM PDT 24 292391031 ps
T874 /workspace/coverage/default/1.sram_ctrl_partial_access.3194416915 May 05 12:48:02 PM PDT 24 May 05 12:48:22 PM PDT 24 3995217894 ps
T875 /workspace/coverage/default/4.sram_ctrl_partial_access.1431865473 May 05 12:48:00 PM PDT 24 May 05 12:48:20 PM PDT 24 1373940342 ps
T876 /workspace/coverage/default/15.sram_ctrl_regwen.490555336 May 05 12:49:09 PM PDT 24 May 05 01:03:23 PM PDT 24 61921723536 ps
T877 /workspace/coverage/default/3.sram_ctrl_smoke.515256921 May 05 12:48:08 PM PDT 24 May 05 12:48:16 PM PDT 24 699840818 ps
T878 /workspace/coverage/default/42.sram_ctrl_ram_cfg.3250120899 May 05 12:55:05 PM PDT 24 May 05 12:55:09 PM PDT 24 1398168514 ps
T879 /workspace/coverage/default/29.sram_ctrl_partial_access.4249997180 May 05 12:51:42 PM PDT 24 May 05 12:51:50 PM PDT 24 2865901375 ps
T880 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.555687826 May 05 12:55:18 PM PDT 24 May 05 12:57:22 PM PDT 24 1578710096 ps
T881 /workspace/coverage/default/37.sram_ctrl_mem_walk.2147236426 May 05 12:53:56 PM PDT 24 May 05 12:56:16 PM PDT 24 25518104399 ps
T882 /workspace/coverage/default/13.sram_ctrl_partial_access.3489828304 May 05 12:48:46 PM PDT 24 May 05 12:48:53 PM PDT 24 8397483858 ps
T883 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3512396691 May 05 12:56:22 PM PDT 24 May 05 01:00:45 PM PDT 24 4629590890 ps
T884 /workspace/coverage/default/0.sram_ctrl_executable.1112664702 May 05 12:47:59 PM PDT 24 May 05 01:14:42 PM PDT 24 63373057376 ps
T885 /workspace/coverage/default/5.sram_ctrl_ram_cfg.36576178 May 05 12:48:07 PM PDT 24 May 05 12:48:11 PM PDT 24 699286758 ps
T886 /workspace/coverage/default/46.sram_ctrl_partial_access.917179409 May 05 12:55:56 PM PDT 24 May 05 12:56:20 PM PDT 24 6103697821 ps
T887 /workspace/coverage/default/48.sram_ctrl_multiple_keys.2265989634 May 05 12:56:19 PM PDT 24 May 05 01:15:31 PM PDT 24 9113354152 ps
T888 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.723231946 May 05 12:48:44 PM PDT 24 May 05 01:07:03 PM PDT 24 97222754044 ps
T889 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3074971408 May 05 12:48:02 PM PDT 24 May 05 12:48:25 PM PDT 24 1254006404 ps
T890 /workspace/coverage/default/17.sram_ctrl_partial_access.3808155269 May 05 12:49:15 PM PDT 24 May 05 12:49:40 PM PDT 24 763174186 ps
T891 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1375020701 May 05 12:55:03 PM PDT 24 May 05 01:10:29 PM PDT 24 21524733055 ps
T892 /workspace/coverage/default/8.sram_ctrl_multiple_keys.2066297652 May 05 12:48:19 PM PDT 24 May 05 12:57:17 PM PDT 24 16864643785 ps
T893 /workspace/coverage/default/49.sram_ctrl_stress_all.4184474773 May 05 12:56:50 PM PDT 24 May 05 01:46:02 PM PDT 24 75465344053 ps
T894 /workspace/coverage/default/3.sram_ctrl_multiple_keys.3135858888 May 05 12:47:59 PM PDT 24 May 05 12:55:56 PM PDT 24 8329819050 ps
T895 /workspace/coverage/default/24.sram_ctrl_ram_cfg.1138161082 May 05 12:50:44 PM PDT 24 May 05 12:50:48 PM PDT 24 412092785 ps
T896 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1752275553 May 05 12:48:01 PM PDT 24 May 05 01:09:06 PM PDT 24 24257090874 ps
T897 /workspace/coverage/default/45.sram_ctrl_mem_walk.393494488 May 05 12:55:50 PM PDT 24 May 05 12:58:10 PM PDT 24 9320652558 ps
T898 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.133393790 May 05 12:53:51 PM PDT 24 May 05 12:58:40 PM PDT 24 46692298928 ps
T899 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2962465931 May 05 12:55:51 PM PDT 24 May 05 12:56:07 PM PDT 24 1706557809 ps
T900 /workspace/coverage/default/0.sram_ctrl_smoke.1061426957 May 05 12:47:54 PM PDT 24 May 05 12:48:05 PM PDT 24 3056773736 ps
T901 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3346901465 May 05 12:47:59 PM PDT 24 May 05 12:50:17 PM PDT 24 8955289801 ps
T902 /workspace/coverage/default/46.sram_ctrl_ram_cfg.4071451117 May 05 12:56:00 PM PDT 24 May 05 12:56:04 PM PDT 24 346537957 ps
T903 /workspace/coverage/default/38.sram_ctrl_lc_escalation.2665194557 May 05 12:54:02 PM PDT 24 May 05 12:54:16 PM PDT 24 2297921692 ps
T904 /workspace/coverage/default/34.sram_ctrl_regwen.3573526734 May 05 12:53:03 PM PDT 24 May 05 12:57:43 PM PDT 24 3159194309 ps
T905 /workspace/coverage/default/13.sram_ctrl_executable.1458706599 May 05 12:48:48 PM PDT 24 May 05 12:56:38 PM PDT 24 23792426129 ps
T906 /workspace/coverage/default/26.sram_ctrl_multiple_keys.259555447 May 05 12:50:58 PM PDT 24 May 05 12:54:08 PM PDT 24 7083113846 ps
T907 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2794522636 May 05 12:51:59 PM PDT 24 May 05 12:56:09 PM PDT 24 21021972307 ps
T908 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4203088066 May 05 12:50:55 PM PDT 24 May 05 12:51:03 PM PDT 24 530433986 ps
T909 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1996971341 May 05 12:56:01 PM PDT 24 May 05 12:57:19 PM PDT 24 5027895203 ps
T910 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.644000189 May 05 12:50:54 PM PDT 24 May 05 12:52:24 PM PDT 24 2232586522 ps
T911 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.704763297 May 05 12:48:04 PM PDT 24 May 05 12:51:57 PM PDT 24 4833928272 ps
T912 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2912731742 May 05 12:49:18 PM PDT 24 May 05 12:58:43 PM PDT 24 91169913695 ps
T913 /workspace/coverage/default/40.sram_ctrl_ram_cfg.2933118700 May 05 12:54:34 PM PDT 24 May 05 12:54:38 PM PDT 24 709127129 ps
T914 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3400355135 May 05 12:50:13 PM PDT 24 May 05 12:50:26 PM PDT 24 1142955120 ps
T915 /workspace/coverage/default/20.sram_ctrl_multiple_keys.417907517 May 05 12:49:53 PM PDT 24 May 05 01:08:14 PM PDT 24 16135763448 ps
T916 /workspace/coverage/default/41.sram_ctrl_smoke.1771422069 May 05 12:54:39 PM PDT 24 May 05 12:54:57 PM PDT 24 5300335240 ps
T917 /workspace/coverage/default/33.sram_ctrl_smoke.2797446911 May 05 12:52:48 PM PDT 24 May 05 12:53:04 PM PDT 24 546523667 ps
T918 /workspace/coverage/default/22.sram_ctrl_regwen.2816781040 May 05 12:50:19 PM PDT 24 May 05 12:50:52 PM PDT 24 8661862498 ps
T919 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.792044455 May 05 12:50:04 PM PDT 24 May 05 12:50:32 PM PDT 24 15744073991 ps
T920 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2364116280 May 05 12:54:52 PM PDT 24 May 05 12:57:14 PM PDT 24 8697091568 ps
T921 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3972179335 May 05 12:54:01 PM PDT 24 May 05 01:11:26 PM PDT 24 27932625217 ps
T922 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2343066202 May 05 12:48:03 PM PDT 24 May 05 12:55:00 PM PDT 24 16213636290 ps
T923 /workspace/coverage/default/29.sram_ctrl_lc_escalation.817506978 May 05 12:51:48 PM PDT 24 May 05 12:52:25 PM PDT 24 33029611439 ps
T924 /workspace/coverage/default/33.sram_ctrl_ram_cfg.1457240986 May 05 12:53:00 PM PDT 24 May 05 12:53:03 PM PDT 24 361967994 ps
T925 /workspace/coverage/default/24.sram_ctrl_executable.151326586 May 05 12:50:44 PM PDT 24 May 05 12:58:42 PM PDT 24 4895021867 ps
T926 /workspace/coverage/default/16.sram_ctrl_lc_escalation.3554773207 May 05 12:49:09 PM PDT 24 May 05 12:50:42 PM PDT 24 76933797643 ps
T927 /workspace/coverage/default/37.sram_ctrl_ram_cfg.593322098 May 05 12:53:58 PM PDT 24 May 05 12:54:01 PM PDT 24 699841145 ps
T928 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3187862904 May 05 12:54:18 PM PDT 24 May 05 12:58:22 PM PDT 24 18036952871 ps
T929 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.2123686175 May 05 12:48:05 PM PDT 24 May 05 01:06:47 PM PDT 24 56540752413 ps
T930 /workspace/coverage/default/46.sram_ctrl_stress_all.1276405764 May 05 12:56:08 PM PDT 24 May 05 02:42:33 PM PDT 24 197767994968 ps
T931 /workspace/coverage/default/18.sram_ctrl_smoke.3872858928 May 05 12:49:26 PM PDT 24 May 05 12:49:33 PM PDT 24 674301280 ps
T932 /workspace/coverage/default/0.sram_ctrl_regwen.3232365675 May 05 12:47:55 PM PDT 24 May 05 12:51:13 PM PDT 24 6768139678 ps
T933 /workspace/coverage/default/12.sram_ctrl_smoke.4001057836 May 05 12:48:41 PM PDT 24 May 05 12:48:55 PM PDT 24 1454495602 ps
T934 /workspace/coverage/default/36.sram_ctrl_bijection.2489789297 May 05 12:53:29 PM PDT 24 May 05 01:30:24 PM PDT 24 127186438671 ps
T935 /workspace/coverage/default/13.sram_ctrl_smoke.1817028662 May 05 12:48:49 PM PDT 24 May 05 12:49:03 PM PDT 24 847725004 ps
T936 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.975757569 May 05 12:54:34 PM PDT 24 May 05 12:56:16 PM PDT 24 5585292052 ps
T937 /workspace/coverage/default/39.sram_ctrl_max_throughput.3409327356 May 05 12:54:16 PM PDT 24 May 05 12:54:30 PM PDT 24 1282124864 ps
T938 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3565627154 May 05 12:48:46 PM PDT 24 May 05 12:56:00 PM PDT 24 13925338543 ps
T59 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1778145276 May 05 12:47:22 PM PDT 24 May 05 12:47:58 PM PDT 24 61511586318 ps
T103 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3958779996 May 05 12:47:35 PM PDT 24 May 05 12:47:38 PM PDT 24 1049013089 ps
T939 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2765528087 May 05 12:47:32 PM PDT 24 May 05 12:47:36 PM PDT 24 726631335 ps
T60 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3709284418 May 05 12:47:48 PM PDT 24 May 05 12:48:43 PM PDT 24 29486529911 ps
T96 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3926660643 May 05 12:47:43 PM PDT 24 May 05 12:47:44 PM PDT 24 39966520 ps
T940 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1777859588 May 05 12:47:31 PM PDT 24 May 05 12:47:34 PM PDT 24 834582910 ps
T104 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1623301423 May 05 12:47:48 PM PDT 24 May 05 12:47:50 PM PDT 24 153251309 ps
T105 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3681269781 May 05 12:47:21 PM PDT 24 May 05 12:47:23 PM PDT 24 120410441 ps
T941 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1444313070 May 05 12:47:39 PM PDT 24 May 05 12:47:43 PM PDT 24 38656380 ps
T101 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.643304145 May 05 12:47:23 PM PDT 24 May 05 12:47:25 PM PDT 24 120925819 ps
T61 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2009667540 May 05 12:47:35 PM PDT 24 May 05 12:49:01 PM PDT 24 141099597319 ps
T112 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.332280587 May 05 12:47:33 PM PDT 24 May 05 12:47:36 PM PDT 24 199445414 ps
T942 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2152100292 May 05 12:47:34 PM PDT 24 May 05 12:47:38 PM PDT 24 1781889769 ps
T943 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2580556070 May 05 12:47:27 PM PDT 24 May 05 12:47:30 PM PDT 24 92150911 ps
T944 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2814000734 May 05 12:47:52 PM PDT 24 May 05 12:47:57 PM PDT 24 549556988 ps
T97 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3619577881 May 05 12:47:14 PM PDT 24 May 05 12:47:15 PM PDT 24 24814419 ps
T945 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3121359458 May 05 12:47:36 PM PDT 24 May 05 12:47:40 PM PDT 24 105302118 ps
T62 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2261338084 May 05 12:47:28 PM PDT 24 May 05 12:47:29 PM PDT 24 36542118 ps
T946 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1886777697 May 05 12:47:42 PM PDT 24 May 05 12:47:45 PM PDT 24 202270576 ps
T63 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3431520177 May 05 12:47:26 PM PDT 24 May 05 12:47:27 PM PDT 24 36814500 ps
T98 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.526183958 May 05 12:47:31 PM PDT 24 May 05 12:47:32 PM PDT 24 16994846 ps
T102 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2747080682 May 05 12:47:26 PM PDT 24 May 05 12:47:29 PM PDT 24 141647560 ps
T64 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.607329829 May 05 12:47:33 PM PDT 24 May 05 12:47:34 PM PDT 24 41249810 ps
T947 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2169239598 May 05 12:47:16 PM PDT 24 May 05 12:47:21 PM PDT 24 476529464 ps
T948 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1658050607 May 05 12:47:38 PM PDT 24 May 05 12:47:41 PM PDT 24 383562248 ps
T65 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.712771331 May 05 12:47:44 PM PDT 24 May 05 12:47:45 PM PDT 24 20787471 ps
T66 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1771344509 May 05 12:47:21 PM PDT 24 May 05 12:47:23 PM PDT 24 14858549 ps
T67 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3996334136 May 05 12:47:35 PM PDT 24 May 05 12:47:36 PM PDT 24 28824855 ps
T68 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3824736057 May 05 12:47:53 PM PDT 24 May 05 12:47:55 PM PDT 24 69337089 ps
T113 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1948816766 May 05 12:47:28 PM PDT 24 May 05 12:47:30 PM PDT 24 582109430 ps
T949 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2194077866 May 05 12:47:21 PM PDT 24 May 05 12:47:22 PM PDT 24 14307888 ps
T950 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3686561483 May 05 12:47:21 PM PDT 24 May 05 12:47:25 PM PDT 24 706747142 ps
T951 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3803908623 May 05 12:47:32 PM PDT 24 May 05 12:47:33 PM PDT 24 16042447 ps
T952 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2090901420 May 05 12:47:31 PM PDT 24 May 05 12:47:35 PM PDT 24 351890630 ps
T953 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2198953368 May 05 12:47:50 PM PDT 24 May 05 12:47:54 PM PDT 24 927207907 ps
T77 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1241966652 May 05 12:47:20 PM PDT 24 May 05 12:47:23 PM PDT 24 351850138 ps
T89 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1324875510 May 05 12:47:21 PM PDT 24 May 05 12:47:24 PM PDT 24 343352714 ps
T954 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2169502570 May 05 12:47:20 PM PDT 24 May 05 12:47:23 PM PDT 24 37585688 ps
T78 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.792768797 May 05 12:47:33 PM PDT 24 May 05 12:47:34 PM PDT 24 20331563 ps
T955 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3358664179 May 05 12:47:37 PM PDT 24 May 05 12:47:39 PM PDT 24 17258154 ps
T956 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.860147435 May 05 12:47:55 PM PDT 24 May 05 12:47:57 PM PDT 24 28532765 ps
T957 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.859841397 May 05 12:47:20 PM PDT 24 May 05 12:47:22 PM PDT 24 19261583 ps
T116 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1774484609 May 05 12:47:36 PM PDT 24 May 05 12:47:38 PM PDT 24 100952317 ps
T958 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.660123596 May 05 12:47:33 PM PDT 24 May 05 12:47:34 PM PDT 24 22337094 ps
T959 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1115614406 May 05 12:47:26 PM PDT 24 May 05 12:47:27 PM PDT 24 23571320 ps
T90 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2022374508 May 05 12:47:20 PM PDT 24 May 05 12:47:22 PM PDT 24 19659841 ps
T91 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3641304312 May 05 12:47:25 PM PDT 24 May 05 12:47:26 PM PDT 24 10938072 ps
T960 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3179973422 May 05 12:47:28 PM PDT 24 May 05 12:47:29 PM PDT 24 40754592 ps
T961 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2019864883 May 05 12:47:31 PM PDT 24 May 05 12:47:33 PM PDT 24 27233582 ps
T962 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.214225398 May 05 12:47:37 PM PDT 24 May 05 12:47:41 PM PDT 24 3385589037 ps
T963 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1740335739 May 05 12:47:26 PM PDT 24 May 05 12:47:27 PM PDT 24 69109084 ps
T964 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3960973567 May 05 12:47:20 PM PDT 24 May 05 12:47:21 PM PDT 24 104896245 ps
T965 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.727624502 May 05 12:47:49 PM PDT 24 May 05 12:48:47 PM PDT 24 14699756168 ps
T966 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3686191855 May 05 12:47:30 PM PDT 24 May 05 12:48:27 PM PDT 24 7791232457 ps
T967 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.139223090 May 05 12:47:35 PM PDT 24 May 05 12:47:36 PM PDT 24 15800088 ps
T119 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4140918622 May 05 12:47:34 PM PDT 24 May 05 12:47:37 PM PDT 24 173389156 ps
T968 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4254998230 May 05 12:47:48 PM PDT 24 May 05 12:47:49 PM PDT 24 14551208 ps
T969 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3582432464 May 05 12:47:54 PM PDT 24 May 05 12:48:26 PM PDT 24 15328809775 ps
T970 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4187495066 May 05 12:47:37 PM PDT 24 May 05 12:47:39 PM PDT 24 14135044 ps
T971 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.537657937 May 05 12:47:40 PM PDT 24 May 05 12:47:43 PM PDT 24 353293195 ps
T972 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2731591213 May 05 12:47:43 PM PDT 24 May 05 12:48:40 PM PDT 24 14108240805 ps
T973 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3531302963 May 05 12:47:41 PM PDT 24 May 05 12:47:46 PM PDT 24 331791274 ps
T974 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3673047145 May 05 12:47:14 PM PDT 24 May 05 12:47:15 PM PDT 24 73520819 ps
T975 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4091519393 May 05 12:47:53 PM PDT 24 May 05 12:47:55 PM PDT 24 15546072 ps
T976 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.881745575 May 05 12:47:48 PM PDT 24 May 05 12:47:53 PM PDT 24 1574990173 ps
T977 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2405044681 May 05 12:47:35 PM PDT 24 May 05 12:47:39 PM PDT 24 185864129 ps
T978 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1828611248 May 05 12:47:29 PM PDT 24 May 05 12:47:31 PM PDT 24 43851602 ps
T979 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2171768954 May 05 12:47:47 PM PDT 24 May 05 12:47:51 PM PDT 24 360207205 ps
T980 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1311358047 May 05 12:47:32 PM PDT 24 May 05 12:47:36 PM PDT 24 813583817 ps
T92 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.179162999 May 05 12:47:31 PM PDT 24 May 05 12:48:02 PM PDT 24 14739516500 ps
T981 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2151726916 May 05 12:47:32 PM PDT 24 May 05 12:47:36 PM PDT 24 39154508 ps
T123 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.93758846 May 05 12:47:38 PM PDT 24 May 05 12:47:40 PM PDT 24 282152686 ps
T982 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2337614940 May 05 12:47:37 PM PDT 24 May 05 12:47:39 PM PDT 24 127756493 ps
T983 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1092951775 May 05 12:47:50 PM PDT 24 May 05 12:47:51 PM PDT 24 50060826 ps
T984 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3289601612 May 05 12:47:52 PM PDT 24 May 05 12:47:55 PM PDT 24 28269946 ps
T985 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.317713941 May 05 12:47:15 PM PDT 24 May 05 12:47:45 PM PDT 24 7387297580 ps
T117 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3022969072 May 05 12:47:47 PM PDT 24 May 05 12:47:50 PM PDT 24 180085870 ps
T93 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1409893646 May 05 12:47:38 PM PDT 24 May 05 12:48:36 PM PDT 24 50334170030 ps
T986 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3851993844 May 05 12:47:42 PM PDT 24 May 05 12:47:44 PM PDT 24 47327429 ps
T987 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2829534700 May 05 12:47:23 PM PDT 24 May 05 12:47:25 PM PDT 24 37097124 ps
T988 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1561560637 May 05 12:47:32 PM PDT 24 May 05 12:48:28 PM PDT 24 28229179999 ps
T114 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1052961890 May 05 12:47:49 PM PDT 24 May 05 12:47:53 PM PDT 24 452131249 ps
T989 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2415791868 May 05 12:47:22 PM PDT 24 May 05 12:47:27 PM PDT 24 146850989 ps
T990 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1291901662 May 05 12:47:16 PM PDT 24 May 05 12:47:19 PM PDT 24 90227532 ps
T991 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1728813317 May 05 12:47:42 PM PDT 24 May 05 12:47:44 PM PDT 24 48037109 ps
T992 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2118092731 May 05 12:47:43 PM PDT 24 May 05 12:47:48 PM PDT 24 419653131 ps
T993 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1958025138 May 05 12:47:26 PM PDT 24 May 05 12:47:29 PM PDT 24 66943663 ps
T994 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3980733197 May 05 12:47:48 PM PDT 24 May 05 12:48:17 PM PDT 24 3894099735 ps
T995 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4149547504 May 05 12:47:18 PM PDT 24 May 05 12:47:19 PM PDT 24 94980195 ps
T996 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1266663179 May 05 12:47:52 PM PDT 24 May 05 12:47:53 PM PDT 24 134892097 ps
T997 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.752667112 May 05 12:47:48 PM PDT 24 May 05 12:47:52 PM PDT 24 1470136109 ps
T998 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2938614370 May 05 12:47:19 PM PDT 24 May 05 12:47:20 PM PDT 24 27034117 ps
T999 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3632329226 May 05 12:47:26 PM PDT 24 May 05 12:47:28 PM PDT 24 113437911 ps
T1000 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.399259882 May 05 12:47:51 PM PDT 24 May 05 12:48:40 PM PDT 24 7179586906 ps
T1001 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1953876175 May 05 12:47:36 PM PDT 24 May 05 12:48:32 PM PDT 24 26057269078 ps
T1002 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.212329949 May 05 12:47:36 PM PDT 24 May 05 12:47:37 PM PDT 24 13840250 ps
T1003 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.785076929 May 05 12:47:29 PM PDT 24 May 05 12:47:30 PM PDT 24 47503897 ps
T1004 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3776543887 May 05 12:47:33 PM PDT 24 May 05 12:48:06 PM PDT 24 16073817751 ps
T1005 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1482957870 May 05 12:47:33 PM PDT 24 May 05 12:47:38 PM PDT 24 368848196 ps
T1006 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2563562184 May 05 12:47:20 PM PDT 24 May 05 12:47:22 PM PDT 24 56469662 ps
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