Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13927727	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

96964864

1

T1

303

T2

109646

T3

3658

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54159116	1			T1	871		T2	60251		T3	2033
values[0x0]	26981514	1			T1	296		T2	29363		T3	959
values[0x1]	29751961	1			T1	573		T2	31166		T3	1029

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7110699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

103781892

1

T1

1031

T2

115150

T3

3848

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	378236	1			T1	3		T2	431		T3	5
valid_sources[0x01]	374445	1			T1	1		T2	489		T3	10
valid_sources[0x02]	386733	1			T1	2		T2	464		T3	7
valid_sources[0x03]	441846	1			T1	8		T2	452		T3	18
valid_sources[0x04]	377266	1			T1	6		T2	415		T3	10
valid_sources[0x05]	380416	1			T1	8		T2	524		T3	38
valid_sources[0x06]	375193	1			T1	9		T2	472		T3	18
valid_sources[0x07]	389887	1			T1	8		T2	431		T3	17
valid_sources[0x08]	376232	1			T1	2		T2	452		T3	20
valid_sources[0x09]	380116	1			T1	9		T2	464		T3	7
valid_sources[0x0a]	377960	1			T1	4		T2	496		T3	7
valid_sources[0x0b]	375750	1			T1	4		T2	478		T3	25
valid_sources[0x0c]	402397	1			T1	5		T2	466		T3	23
valid_sources[0x0d]	384137	1			T1	7		T2	462		T3	11
valid_sources[0x0e]	383601	1			T1	3		T2	432		T3	8
valid_sources[0x0f]	593378	1			T1	6		T2	473		T3	7
valid_sources[0x10]	374760	1			T1	3		T2	476		T3	16
valid_sources[0x11]	378241	1			T1	3		T2	518		T3	8
valid_sources[0x12]	390489	1			T1	3		T2	455		T3	15
valid_sources[0x13]	379399	1			T1	14		T2	449		T3	21
valid_sources[0x14]	577196	1			T1	6		T2	427		T3	18
valid_sources[0x15]	396968	1			T1	8		T2	457		T3	8
valid_sources[0x16]	387344	1			T1	7		T2	498		T3	12
valid_sources[0x17]	392051	1			T1	13		T2	451		T3	20
valid_sources[0x18]	404661	1			T1	11		T2	465		T3	20
valid_sources[0x19]	387788	1			T1	3		T2	468		T3	7
valid_sources[0x1a]	381071	1			T1	6		T2	455		T3	11
valid_sources[0x1b]	382146	1			T1	12		T2	428		T3	23
valid_sources[0x1c]	418321	1			T1	7		T2	427		T3	14
valid_sources[0x1d]	409584	1			T1	4		T2	484		T3	23
valid_sources[0x1e]	383122	1			T1	7		T2	496		T3	18
valid_sources[0x1f]	387046	1			T1	4		T2	455		T3	15
valid_sources[0x20]	387498	1			T1	9		T2	524		T3	10
valid_sources[0x21]	425039	1			T1	4		T2	473		T3	23
valid_sources[0x22]	389349	1			T1	9		T2	540		T3	12
valid_sources[0x23]	387518	1			T1	4		T2	533		T3	10
valid_sources[0x24]	574092	1			T1	2		T2	453		T3	7
valid_sources[0x25]	396189	1			T1	1		T2	511		T3	22
valid_sources[0x26]	412644	1			T1	1		T2	484		T3	21
valid_sources[0x27]	382118	1			T1	3		T2	513		T3	16
valid_sources[0x28]	376987	1			T1	11		T2	438		T3	30
valid_sources[0x29]	391316	1			T1	6		T2	447		T3	2
valid_sources[0x2a]	400037	1			T1	11		T2	423		T3	11
valid_sources[0x2b]	413614	1			T1	8		T2	420		T3	12
valid_sources[0x2c]	380020	1			T1	17		T2	460		T3	11
valid_sources[0x2d]	387937	1			T1	5		T2	501		T3	14
valid_sources[0x2e]	395644	1			T1	10		T2	464		T3	4
valid_sources[0x2f]	387526	1			T1	2		T2	490		T3	16
valid_sources[0x30]	392077	1			T1	4		T2	446		T3	24
valid_sources[0x31]	410267	1			T1	8		T2	520		T3	8
valid_sources[0x32]	383354	1			T1	2		T2	502		T3	26
valid_sources[0x33]	485440	1			T1	7		T2	452		T3	13
valid_sources[0x34]	400510	1			T1	7		T2	481		T3	18
valid_sources[0x35]	452681	1			T1	6		T2	448		T3	14
valid_sources[0x36]	390457	1			T1	8		T2	469		T3	20
valid_sources[0x37]	1688539	1			T1	3		T2	507		T3	7
valid_sources[0x38]	525193	1			T1	13		T2	500		T3	15
valid_sources[0x39]	377715	1			T1	8		T2	460		T3	8
valid_sources[0x3a]	375210	1			T1	7		T2	446		T3	11
valid_sources[0x3b]	391775	1			T1	3		T2	511		T3	34
valid_sources[0x3c]	409543	1			T1	7		T2	459		T3	10
valid_sources[0x3d]	423946	1			T1	18		T2	517		T3	22
valid_sources[0x3e]	432446	1			T1	10		T2	425		T3	29
valid_sources[0x3f]	379402	1			T1	6		T2	391		T3	30
valid_sources[0x40]	398335	1			T1	6		T2	396		T3	12
valid_sources[0x41]	388744	1			T1	11		T2	404		T3	21
valid_sources[0x42]	375886	1			T1	17		T2	511		T3	28
valid_sources[0x43]	405301	1			T1	4		T2	510		T3	24
valid_sources[0x44]	421370	1			T1	10		T2	436		T3	8
valid_sources[0x45]	379802	1			T1	1		T2	501		T3	23
valid_sources[0x46]	387150	1			T1	8		T2	443		T3	13
valid_sources[0x47]	378702	1			T1	3		T2	403		T3	19
valid_sources[0x48]	379862	1			T1	5		T2	520		T3	32
valid_sources[0x49]	377373	1			T1	7		T2	478		T3	2
valid_sources[0x4a]	402823	1			T1	5		T2	422		T3	30
valid_sources[0x4b]	394977	1			T1	1		T2	450		T3	10
valid_sources[0x4c]	397131	1			T1	9		T2	488		T3	20
valid_sources[0x4d]	374720	1			T1	5		T2	500		T3	20
valid_sources[0x4e]	382068	1			T1	6		T2	566		T3	11
valid_sources[0x4f]	414049	1			T1	8		T2	486		T3	13
valid_sources[0x50]	386932	1			T1	14		T2	513		T3	19
valid_sources[0x51]	490272	1			T1	7		T2	490		T3	10
valid_sources[0x52]	570532	1			T2	512		T3	20		T4	685
valid_sources[0x53]	628811	1			T1	4		T2	453		T3	26
valid_sources[0x54]	397395	1			T1	12		T2	482		T3	16
valid_sources[0x55]	419419	1			T1	7		T2	487		T3	21
valid_sources[0x56]	1883879	1			T1	8		T2	458		T3	29
valid_sources[0x57]	445232	1			T1	5		T2	466		T3	5
valid_sources[0x58]	381428	1			T1	9		T2	495		T3	11
valid_sources[0x59]	379762	1			T1	9		T2	440		T3	10
valid_sources[0x5a]	373609	1			T1	7		T2	444		T3	4
valid_sources[0x5b]	400589	1			T1	5		T2	495		T3	26
valid_sources[0x5c]	433843	1			T1	2		T2	521		T3	9
valid_sources[0x5d]	374373	1			T1	6		T2	410		T3	7
valid_sources[0x5e]	436604	1			T1	13		T2	383		T3	31
valid_sources[0x5f]	373226	1			T1	11		T2	472		T3	6
valid_sources[0x60]	391433	1			T1	6		T2	432		T3	7
valid_sources[0x61]	392802	1			T1	7		T2	426		T3	7
valid_sources[0x62]	378283	1			T1	6		T2	493		T3	15
valid_sources[0x63]	406130	1			T1	6		T2	514		T3	16
valid_sources[0x64]	378159	1			T1	4		T2	454		T3	7
valid_sources[0x65]	385128	1			T1	3		T2	493		T3	22
valid_sources[0x66]	381939	1			T1	3		T2	486		T3	4
valid_sources[0x67]	375743	1			T1	3		T2	481		T3	21
valid_sources[0x68]	393551	1			T1	6		T2	531		T3	13
valid_sources[0x69]	381247	1			T1	5		T2	499		T3	7
valid_sources[0x6a]	393787	1			T1	6		T2	388		T3	21
valid_sources[0x6b]	386012	1			T1	2		T2	437		T3	6
valid_sources[0x6c]	390418	1			T1	10		T2	485		T3	10
valid_sources[0x6d]	380193	1			T1	1		T2	436		T3	30
valid_sources[0x6e]	374554	1			T1	4		T2	453		T3	8
valid_sources[0x6f]	573469	1			T1	6		T2	432		T3	15
valid_sources[0x70]	419049	1			T1	8		T2	460		T3	8
valid_sources[0x71]	374224	1			T1	1		T2	478		T3	10
valid_sources[0x72]	382478	1			T1	2		T2	434		T3	20
valid_sources[0x73]	396196	1			T1	1		T2	490		T3	29
valid_sources[0x74]	373791	1			T1	15		T2	485		T3	13
valid_sources[0x75]	378280	1			T1	15		T2	468		T3	18
valid_sources[0x76]	375899	1			T1	1		T2	465		T3	18
valid_sources[0x77]	385129	1			T1	15		T2	503		T3	7
valid_sources[0x78]	384080	1			T1	23		T2	508		T3	11
valid_sources[0x79]	384114	1			T1	10		T2	515		T3	5
valid_sources[0x7a]	374056	1			T1	7		T2	461		T3	14
valid_sources[0x7b]	1881069	1			T1	8		T2	478		T3	7
valid_sources[0x7c]	381147	1			T1	8		T2	434		T3	25
valid_sources[0x7d]	383512	1			T1	12		T2	498		T3	12
valid_sources[0x7e]	398439	1			T1	7		T2	445		T3	9
valid_sources[0x7f]	386881	1			T1	4		T2	469		T3	24
valid_sources[0x80]	378813	1			T1	2		T2	461		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47153130

1

T1

161

T2

54755

T3

1850

values[0x0]

all_enables

biggest_size

24903065

1

T1

73

T2

27657

T3

903

values[0x1]

all_enables

biggest_size

24908669

1

T1

69

T2

27234

T3

905

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151707	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

129707

1

T2

37

T3

2

T4

95

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33848	1			T14	16		T23	21		T24	9
values[0x0]	122774	1			T1	1		T2	75		T3	1
values[0x1]	124792	1			T1	2		T2	62		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	131923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149491

1

T2

48

T3

2

T4

128

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	995	1			T23	3		T76	1		T85	2
valid_sources[0x01]	958	1			T13	1		T22	2		T76	1
valid_sources[0x02]	1243	1			T13	3		T22	2		T77	25
valid_sources[0x03]	1062	1			T2	1		T12	3		T13	2
valid_sources[0x04]	934	1			T9	1		T12	3		T13	1
valid_sources[0x05]	779	1			T2	1		T13	4		T44	1
valid_sources[0x06]	1147	1			T13	6		T85	1		T87	1
valid_sources[0x07]	1151	1			T13	1		T23	8		T76	1
valid_sources[0x08]	1237	1			T12	7		T13	5		T76	1
valid_sources[0x09]	963	1			T5	2		T13	5		T23	1
valid_sources[0x0a]	1039	1			T4	36		T10	5		T13	4
valid_sources[0x0b]	1102	1			T2	2		T13	1		T22	3
valid_sources[0x0c]	1206	1			T2	2		T12	7		T13	3
valid_sources[0x0d]	816	1			T12	1		T13	2		T76	1
valid_sources[0x0e]	1039	1			T10	11		T12	1		T13	3
valid_sources[0x0f]	1224	1			T2	1		T13	2		T22	4
valid_sources[0x10]	933	1			T2	1		T5	3		T13	3
valid_sources[0x11]	1085	1			T2	1		T9	1		T13	1
valid_sources[0x12]	955	1			T13	2		T22	1		T76	2
valid_sources[0x13]	1170	1			T13	4		T23	2		T76	1
valid_sources[0x14]	1295	1			T2	1		T13	2		T22	2
valid_sources[0x15]	964	1			T12	4		T87	2		T89	6
valid_sources[0x16]	1126	1			T50	116		T85	1		T87	1
valid_sources[0x17]	988	1			T12	1		T13	2		T22	1
valid_sources[0x18]	846	1			T2	1		T13	3		T22	1
valid_sources[0x19]	1235	1			T13	4		T22	1		T44	6
valid_sources[0x1a]	763	1			T2	1		T12	1		T13	3
valid_sources[0x1b]	1208	1			T13	2		T22	7		T23	1
valid_sources[0x1c]	1025	1			T12	7		T13	2		T22	1
valid_sources[0x1d]	906	1			T13	1		T22	7		T76	2
valid_sources[0x1e]	823	1			T2	1		T13	2		T23	1
valid_sources[0x1f]	1429	1			T13	3		T76	1		T86	1
valid_sources[0x20]	1060	1			T12	6		T13	3		T15	48
valid_sources[0x21]	1286	1			T13	4		T23	7		T24	74
valid_sources[0x22]	1391	1			T10	2		T13	2		T22	2
valid_sources[0x23]	1088	1			T1	1		T2	2		T13	1
valid_sources[0x24]	941	1			T9	1		T12	8		T13	3
valid_sources[0x25]	979	1			T13	1		T76	1		T85	3
valid_sources[0x26]	993	1			T2	1		T12	7		T13	1
valid_sources[0x27]	885	1			T2	1		T12	1		T13	2
valid_sources[0x28]	858	1			T12	1		T13	8		T44	1
valid_sources[0x29]	826	1			T2	2		T44	1		T76	2
valid_sources[0x2a]	942	1			T12	2		T13	5		T22	2
valid_sources[0x2b]	3142	1			T10	1		T12	2		T22	2
valid_sources[0x2c]	928	1			T12	4		T13	2		T23	2
valid_sources[0x2d]	1006	1			T2	1		T13	1		T84	3
valid_sources[0x2e]	1052	1			T13	2		T22	1		T89	3
valid_sources[0x2f]	915	1			T4	9		T13	2		T49	3
valid_sources[0x30]	1637	1			T12	5		T13	1		T43	10
valid_sources[0x31]	1133	1			T4	21		T13	4		T22	1
valid_sources[0x32]	899	1			T13	1		T22	5		T15	11
valid_sources[0x33]	965	1			T9	1		T12	7		T13	1
valid_sources[0x34]	913	1			T2	2		T13	2		T23	1
valid_sources[0x35]	982	1			T2	2		T12	2		T13	5
valid_sources[0x36]	1448	1			T13	1		T22	6		T76	1
valid_sources[0x37]	955	1			T2	3		T12	4		T13	3
valid_sources[0x38]	996	1			T2	2		T13	3		T44	8
valid_sources[0x39]	1083	1			T12	6		T23	5		T84	1
valid_sources[0x3a]	1164	1			T12	1		T44	2		T55	38
valid_sources[0x3b]	1324	1			T12	8		T13	5		T22	1
valid_sources[0x3c]	937	1			T13	3		T22	2		T15	9
valid_sources[0x3d]	1144	1			T2	1		T13	6		T23	1
valid_sources[0x3e]	1277	1			T2	2		T13	1		T76	1
valid_sources[0x3f]	925	1			T10	3		T11	1		T13	1
valid_sources[0x40]	882	1			T2	1		T13	2		T23	2
valid_sources[0x41]	1002	1			T10	11		T13	4		T14	83
valid_sources[0x42]	1042	1			T13	5		T44	3		T87	1
valid_sources[0x43]	1090	1			T13	4		T22	1		T87	2
valid_sources[0x44]	1221	1			T12	4		T13	2		T22	5
valid_sources[0x45]	1338	1			T12	2		T13	2		T22	2
valid_sources[0x46]	1004	1			T13	2		T76	1		T86	3
valid_sources[0x47]	1093	1			T2	1		T13	2		T23	1
valid_sources[0x48]	1068	1			T12	6		T13	3		T76	2
valid_sources[0x49]	1013	1			T2	2		T13	1		T23	4
valid_sources[0x4a]	867	1			T12	12		T13	2		T22	1
valid_sources[0x4b]	1295	1			T13	4		T43	3		T23	3
valid_sources[0x4c]	1049	1			T2	2		T9	1		T13	2
valid_sources[0x4d]	875	1			T12	6		T13	5		T22	2
valid_sources[0x4e]	876	1			T13	4		T22	3		T84	3
valid_sources[0x4f]	954	1			T13	2		T23	1		T76	1
valid_sources[0x50]	935	1			T2	1		T22	2		T76	2
valid_sources[0x51]	1322	1			T13	4		T23	4		T76	1
valid_sources[0x52]	953	1			T12	8		T13	4		T76	1
valid_sources[0x53]	1073	1			T2	1		T10	4		T13	4
valid_sources[0x54]	1014	1			T13	1		T44	1		T76	1
valid_sources[0x55]	866	1			T13	2		T22	10		T49	2
valid_sources[0x56]	1213	1			T12	3		T13	3		T86	2
valid_sources[0x57]	1183	1			T12	11		T13	2		T22	4
valid_sources[0x58]	1561	1			T13	5		T76	2		T160	597
valid_sources[0x59]	1077	1			T2	1		T13	2		T22	1
valid_sources[0x5a]	1156	1			T2	2		T13	8		T23	1
valid_sources[0x5b]	1294	1			T2	1		T12	8		T13	3
valid_sources[0x5c]	1435	1			T2	1		T13	4		T76	1
valid_sources[0x5d]	875	1			T12	3		T13	1		T23	7
valid_sources[0x5e]	1154	1			T12	2		T13	1		T76	1
valid_sources[0x5f]	1181	1			T22	1		T50	29		T86	1
valid_sources[0x60]	963	1			T12	2		T22	1		T23	6
valid_sources[0x61]	1037	1			T4	46		T12	2		T13	1
valid_sources[0x62]	871	1			T2	2		T13	1		T22	5
valid_sources[0x63]	959	1			T12	1		T13	2		T76	2
valid_sources[0x64]	1113	1			T12	9		T13	4		T14	79
valid_sources[0x65]	916	1			T2	1		T85	1		T86	4
valid_sources[0x66]	883	1			T13	3		T22	4		T23	2
valid_sources[0x67]	1209	1			T13	6		T86	2		T87	2
valid_sources[0x68]	866	1			T13	3		T22	1		T86	1
valid_sources[0x69]	928	1			T4	19		T13	3		T22	2
valid_sources[0x6a]	972	1			T2	3		T12	8		T13	3
valid_sources[0x6b]	927	1			T10	2		T12	7		T13	6
valid_sources[0x6c]	1093	1			T13	5		T76	1		T87	2
valid_sources[0x6d]	3025	1			T9	1		T13	1		T23	1
valid_sources[0x6e]	908	1			T2	1		T13	5		T85	1
valid_sources[0x6f]	1030	1			T13	5		T22	1		T15	10
valid_sources[0x70]	849	1			T2	6		T13	5		T23	3
valid_sources[0x71]	1143	1			T2	1		T10	1		T12	1
valid_sources[0x72]	931	1			T13	2		T22	2		T76	1
valid_sources[0x73]	816	1			T12	18		T13	4		T76	2
valid_sources[0x74]	1084	1			T12	3		T13	3		T22	1
valid_sources[0x75]	1060	1			T13	2		T29	2		T86	1
valid_sources[0x76]	958	1			T13	2		T23	3		T76	1
valid_sources[0x77]	835	1			T2	4		T12	4		T13	1
valid_sources[0x78]	1107	1			T2	1		T13	3		T161	1
valid_sources[0x79]	1188	1			T2	1		T12	7		T13	1
valid_sources[0x7a]	962	1			T44	3		T76	1		T86	1
valid_sources[0x7b]	967	1			T13	1		T22	1		T44	1
valid_sources[0x7c]	1030	1			T10	3		T12	1		T13	2
valid_sources[0x7d]	1131	1			T13	2		T87	2		T89	6
valid_sources[0x7e]	940	1			T2	2		T12	2		T13	2
valid_sources[0x7f]	1155	1			T12	4		T13	1		T22	1
valid_sources[0x80]	1125	1			T13	2		T49	2		T76	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24645

1

T14

8

T23

8

T24

6

values[0x0]

all_enables

biggest_size

60436

1

T2

23

T3

1

T4

67

values[0x1]

all_enables

biggest_size

44626

1

T2

14

T3

1

T4

28