Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.67	91.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	91.67	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13886791

1

T1

1437

T2

9425

T3

363

full_word

95367837

1

T1

303

T2

91910

T3

3658

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	109254438	1			T1	1740		T2	101335		T3	4021
auto[TlIntgErrCmd]	76	1			T46	6		T47	1		T48	8
auto[TlIntgErrData]	43	1			T46	5		T47	3		T48	3
auto[TlIntgErrBoth]	71	1			T46	9		T47	6		T48	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52484637

1

T1

871

T2

40806

T3

2033

auto[1]

56769991

1

T1

869

T2

60529

T3

1988

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	*	--	--	2

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6875975	1			T1	710		T2	3787		T3	183
auto[TlIntgErrNone]	partial	auto[1]	7010636	1			T1	727		T2	5638		T3	180
auto[TlIntgErrNone]	full_word	auto[0]	45608583	1			T1	161		T2	37019		T3	1850
auto[TlIntgErrNone]	full_word	auto[1]	49759244	1			T1	142		T2	54891		T3	1808
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T46	2		T48	2		T141	3
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T46	4		T47	1		T48	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T142	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T143	1		T144	1		-	-
auto[TlIntgErrData]	partial	auto[0]	16	1			T48	2		T141	1		T145	1
auto[TlIntgErrData]	partial	auto[1]	27	1			T46	5		T47	3		T48	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T46	2		T47	4		T48	2
auto[TlIntgErrBoth]	partial	auto[1]	34	1			T46	5		T47	2		T48	7
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T46	1		T145	1		T146	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T46	1		T144	1		T147	2