Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	310541	1			T5	3		T14	186		T15	1606
auto[1]	4332477	1			T2	3213		T4	178		T5	2
auto[2]	242760	1			T5	2		T14	164		T15	630
auto[3]	4249897	1			T2	2097		T4	142		T5	2

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5029716	1			T2	4454		T4	233		T9	36
auto[1]	862304	1			T2	387		T4	49		T5	2
auto[2]	887501	1			T2	436		T4	32		T10	6269
auto[3]	2356154	1			T2	33		T4	6		T5	7

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2401582

1

T2

5310

T4

320

T5

9

auto[1]

6734093

1

T10

79439

T44

189276

T45

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	107865	1			T14	153		T15	1312		T24	454
auto[0]	auto[0]	auto[1]	11560	1			T5	1		T14	18		T15	130
auto[0]	auto[0]	auto[2]	11550	1			T14	13		T15	152		T24	34
auto[0]	auto[0]	auto[3]	32809	1			T5	2		T14	2		T15	12
auto[0]	auto[1]	auto[0]	597314	1			T2	2682		T4	125		T9	21
auto[0]	auto[1]	auto[1]	67763	1			T2	236		T4	38		T12	273
auto[0]	auto[1]	auto[2]	87560	1			T2	276		T4	13		T12	81
auto[0]	auto[1]	auto[3]	334341	1			T2	19		T4	2		T5	2
auto[0]	auto[2]	auto[0]	78749	1			T14	132		T15	476		T24	418
auto[0]	auto[2]	auto[1]	10751	1			T5	1		T14	16		T15	48
auto[0]	auto[2]	auto[2]	7853	1			T14	14		T15	97		T24	27
auto[0]	auto[2]	auto[3]	22861	1			T5	1		T14	2		T15	9
auto[0]	auto[3]	auto[0]	555511	1			T2	1772		T4	108		T9	15
auto[0]	auto[3]	auto[1]	80850	1			T2	151		T4	11		T12	89
auto[0]	auto[3]	auto[2]	88821	1			T2	160		T4	19		T12	244
auto[0]	auto[3]	auto[3]	305424	1			T2	14		T4	4		T5	2
auto[1]	auto[0]	auto[0]	4785	1			T123	377		T157	1		T155	152
auto[1]	auto[0]	auto[1]	21885	1			T123	1808		T155	769		T156	1472
auto[1]	auto[0]	auto[2]	21760	1			T123	1754		T155	768		T156	1494
auto[1]	auto[0]	auto[3]	98327	1			T123	8089		T106	1		T155	3177
auto[1]	auto[1]	auto[0]	1841972	1			T10	32851		T44	78024		T45	1
auto[1]	auto[1]	auto[1]	334850	1			T10	3089		T44	7954		T76	3934
auto[1]	auto[1]	auto[2]	320040	1			T10	3229		T44	7798		T76	4417
auto[1]	auto[1]	auto[3]	748637	1			T10	302		T44	768		T76	395
auto[1]	auto[2]	auto[0]	4157	1			T123	358		T155	100		T156	303
auto[1]	auto[2]	auto[1]	18590	1			T123	1576		T155	410		T156	1307
auto[1]	auto[2]	auto[2]	18170	1			T123	1565		T155	783		T156	1224
auto[1]	auto[2]	auto[3]	81629	1			T123	6684		T155	3275		T156	5555
auto[1]	auto[3]	auto[0]	1839363	1			T10	33209		T44	78287		T76	42849
auto[1]	auto[3]	auto[1]	316055	1			T10	3398		T44	7849		T76	4394
auto[1]	auto[3]	auto[2]	331747	1			T10	3040		T44	7843		T76	3929
auto[1]	auto[3]	auto[3]	732126	1			T10	321		T44	753		T76	372