Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14222324	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

82986574

1

T1

3153

T2

137625

T3

2046

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47362812	1			T1	1711		T2	688128		T3	535
values[0x0]	23506744	1			T1	848		T2	343995		T3	753
values[0x1]	26339342	1			T1	911		T2	344133		T3	758

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7247980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

89960918

1

T1

3302

T2

137625

T3

2046

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	353154	1			T2	5278		T3	4		T6	113
valid_sources[0x01]	343096	1			T2	5422		T3	10		T6	279
valid_sources[0x02]	332430	1			T2	5363		T3	8		T6	157
valid_sources[0x03]	374100	1			T1	108		T2	5368		T3	17
valid_sources[0x04]	354814	1			T2	5230		T3	9		T9	42
valid_sources[0x05]	354862	1			T2	5363		T3	7		T9	40
valid_sources[0x06]	331433	1			T2	5432		T3	5		T9	32
valid_sources[0x07]	336282	1			T2	5457		T3	14		T6	118
valid_sources[0x08]	350463	1			T2	5251		T3	8		T9	34
valid_sources[0x09]	337927	1			T2	5405		T3	9		T6	99
valid_sources[0x0a]	339129	1			T2	5399		T3	6		T6	239
valid_sources[0x0b]	335926	1			T1	26		T2	5280		T3	10
valid_sources[0x0c]	366574	1			T2	5321		T3	8		T9	47
valid_sources[0x0d]	329896	1			T1	26		T2	5555		T3	9
valid_sources[0x0e]	328289	1			T2	5503		T3	7		T9	39
valid_sources[0x0f]	388439	1			T1	27		T2	5355		T3	14
valid_sources[0x10]	330296	1			T2	5289		T3	12		T9	40
valid_sources[0x11]	1613091	1			T2	5440		T3	6		T6	89
valid_sources[0x12]	368366	1			T1	74		T2	5272		T3	19
valid_sources[0x13]	338922	1			T2	5343		T3	7		T9	31
valid_sources[0x14]	328122	1			T1	98		T2	5375		T3	3
valid_sources[0x15]	339883	1			T2	5458		T3	5		T9	44
valid_sources[0x16]	336599	1			T1	8		T2	5337		T3	12
valid_sources[0x17]	330974	1			T2	5501		T3	11		T9	34
valid_sources[0x18]	357002	1			T2	5258		T3	12		T9	47
valid_sources[0x19]	330933	1			T1	24		T2	5422		T3	8
valid_sources[0x1a]	348197	1			T2	5411		T3	6		T6	65
valid_sources[0x1b]	345997	1			T2	5329		T9	35		T4	893
valid_sources[0x1c]	332214	1			T2	5473		T3	8		T9	33
valid_sources[0x1d]	337564	1			T2	5413		T3	2		T9	41
valid_sources[0x1e]	335634	1			T2	5398		T3	5		T9	29
valid_sources[0x1f]	336101	1			T2	5510		T3	8		T9	44
valid_sources[0x20]	333542	1			T1	35		T2	5512		T3	10
valid_sources[0x21]	361416	1			T2	5302		T3	6		T9	38
valid_sources[0x22]	337371	1			T1	50		T2	5319		T3	3
valid_sources[0x23]	356479	1			T2	5286		T3	3		T9	32
valid_sources[0x24]	342506	1			T2	5474		T3	7		T9	33
valid_sources[0x25]	335350	1			T2	5411		T3	11		T6	408
valid_sources[0x26]	344230	1			T1	34		T2	5305		T3	9
valid_sources[0x27]	330435	1			T2	5253		T3	8		T9	40
valid_sources[0x28]	341059	1			T2	5355		T3	10		T9	41
valid_sources[0x29]	336713	1			T1	115		T2	5463		T3	5
valid_sources[0x2a]	335083	1			T2	5303		T3	8		T9	46
valid_sources[0x2b]	335139	1			T2	5128		T3	11		T9	25
valid_sources[0x2c]	334869	1			T2	5455		T3	5		T9	46
valid_sources[0x2d]	343348	1			T2	5316		T3	13		T9	33
valid_sources[0x2e]	331317	1			T2	5501		T3	4		T9	31
valid_sources[0x2f]	337366	1			T2	5346		T3	5		T9	44
valid_sources[0x30]	355889	1			T1	5		T2	5366		T3	9
valid_sources[0x31]	359905	1			T2	5337		T3	11		T9	28
valid_sources[0x32]	364735	1			T2	5415		T3	10		T6	61
valid_sources[0x33]	347999	1			T2	5489		T3	4		T6	25
valid_sources[0x34]	327990	1			T2	5374		T3	7		T9	37
valid_sources[0x35]	330066	1			T2	5233		T3	7		T9	28
valid_sources[0x36]	351421	1			T1	57		T2	5529		T3	2
valid_sources[0x37]	332177	1			T2	5524		T3	3		T6	35
valid_sources[0x38]	365090	1			T2	5287		T3	9		T9	48
valid_sources[0x39]	330155	1			T2	5252		T3	9		T9	38
valid_sources[0x3a]	337022	1			T2	5356		T3	13		T9	43
valid_sources[0x3b]	1143459	1			T2	5420		T3	5		T9	49
valid_sources[0x3c]	375738	1			T1	85		T2	5467		T3	11
valid_sources[0x3d]	355733	1			T1	89		T2	5261		T3	8
valid_sources[0x3e]	427617	1			T2	5204		T3	5		T9	43
valid_sources[0x3f]	332481	1			T1	39		T2	5376		T3	10
valid_sources[0x40]	359675	1			T1	49		T2	5374		T3	2
valid_sources[0x41]	348043	1			T1	20		T2	5359		T3	5
valid_sources[0x42]	346228	1			T2	5498		T3	2		T9	42
valid_sources[0x43]	345834	1			T2	5309		T3	10		T9	38
valid_sources[0x44]	344112	1			T1	206		T2	5295		T3	9
valid_sources[0x45]	351760	1			T2	5341		T3	6		T9	42
valid_sources[0x46]	329869	1			T1	61		T2	5282		T3	2
valid_sources[0x47]	667654	1			T2	5424		T3	8		T9	40
valid_sources[0x48]	334580	1			T2	5327		T3	7		T9	36
valid_sources[0x49]	361004	1			T2	5277		T3	5		T9	47
valid_sources[0x4a]	329371	1			T2	5311		T3	9		T9	35
valid_sources[0x4b]	528191	1			T2	5428		T3	3		T9	38
valid_sources[0x4c]	339030	1			T2	5275		T3	3		T9	42
valid_sources[0x4d]	340427	1			T2	5299		T3	12		T9	27
valid_sources[0x4e]	343109	1			T2	5431		T3	8		T9	49
valid_sources[0x4f]	381682	1			T1	6		T2	5410		T3	5
valid_sources[0x50]	331844	1			T1	26		T2	5344		T3	3
valid_sources[0x51]	1464435	1			T2	5369		T3	10		T9	40
valid_sources[0x52]	333242	1			T2	5276		T3	9		T9	36
valid_sources[0x53]	333319	1			T2	5439		T3	4		T9	42
valid_sources[0x54]	338257	1			T2	5453		T3	3		T9	37
valid_sources[0x55]	348737	1			T2	5395		T3	2		T6	97
valid_sources[0x56]	366401	1			T2	5287		T3	6		T6	21
valid_sources[0x57]	336704	1			T1	32		T2	5452		T3	9
valid_sources[0x58]	337289	1			T2	5286		T3	11		T6	139
valid_sources[0x59]	334585	1			T2	5281		T3	7		T9	39
valid_sources[0x5a]	334019	1			T2	5437		T3	7		T9	34
valid_sources[0x5b]	339917	1			T1	98		T2	5339		T3	6
valid_sources[0x5c]	330006	1			T2	5479		T3	12		T9	39
valid_sources[0x5d]	358483	1			T2	5338		T3	3		T9	53
valid_sources[0x5e]	339811	1			T2	5381		T3	10		T9	50
valid_sources[0x5f]	379339	1			T2	5410		T3	6		T6	80
valid_sources[0x60]	337277	1			T2	5443		T3	12		T9	43
valid_sources[0x61]	349516	1			T2	5255		T3	9		T9	38
valid_sources[0x62]	374762	1			T2	5221		T3	10		T9	41
valid_sources[0x63]	338624	1			T2	5361		T3	19		T6	344
valid_sources[0x64]	341033	1			T2	5457		T3	5		T9	37
valid_sources[0x65]	338285	1			T2	5513		T3	11		T6	12
valid_sources[0x66]	333272	1			T2	5359		T3	9		T6	73
valid_sources[0x67]	330990	1			T2	5401		T3	4		T6	142
valid_sources[0x68]	1119539	1			T2	5440		T3	12		T9	31
valid_sources[0x69]	377923	1			T2	5474		T3	4		T6	11
valid_sources[0x6a]	355870	1			T1	29		T2	5267		T3	2
valid_sources[0x6b]	335410	1			T2	5346		T3	8		T9	38
valid_sources[0x6c]	338433	1			T2	5248		T3	1		T9	32
valid_sources[0x6d]	352363	1			T2	5320		T3	12		T6	67
valid_sources[0x6e]	336203	1			T1	27		T2	5469		T3	7
valid_sources[0x6f]	331044	1			T2	5429		T3	10		T9	31
valid_sources[0x70]	329386	1			T2	5378		T3	5		T9	36
valid_sources[0x71]	339534	1			T2	5383		T3	5		T9	28
valid_sources[0x72]	356708	1			T2	5411		T3	4		T9	28
valid_sources[0x73]	333016	1			T2	5286		T3	3		T9	33
valid_sources[0x74]	337135	1			T1	131		T2	5347		T3	16
valid_sources[0x75]	329957	1			T1	99		T2	5424		T3	11
valid_sources[0x76]	359955	1			T2	5201		T3	9		T9	37
valid_sources[0x77]	433568	1			T2	5352		T3	4		T9	43
valid_sources[0x78]	350508	1			T2	5497		T3	6		T9	44
valid_sources[0x79]	329352	1			T2	5291		T3	16		T9	36
valid_sources[0x7a]	355119	1			T2	5502		T3	9		T9	44
valid_sources[0x7b]	331209	1			T2	5365		T3	6		T9	36
valid_sources[0x7c]	356409	1			T2	5376		T3	13		T9	41
valid_sources[0x7d]	333917	1			T1	11		T2	5409		T3	11
valid_sources[0x7e]	1052591	1			T2	5347		T3	10		T9	47
valid_sources[0x7f]	427711	1			T2	5389		T3	4		T6	121
valid_sources[0x80]	336171	1			T2	5338		T3	7		T9	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40209096

1

T1

1560

T2

688128

T3

535

values[0x0]

all_enables

biggest_size

21386562

1

T1

797

T2

343995

T3

753

values[0x1]

all_enables

biggest_size

21390916

1

T1

796

T2

344133

T3

758

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	136859	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

111634

1

T1

75

T2

177

T3

1186

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29406	1			T1	31		T3	325		T7	22
values[0x0]	108030	1			T1	146		T2	335		T3	448
values[0x1]	111057	1			T1	134		T2	284		T3	491

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	118805	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

129688

1

T1

96

T2

236

T3

1228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	854	1			T2	4		T3	2		T18	2
valid_sources[0x01]	1564	1			T22	3		T157	2		T117	1
valid_sources[0x02]	751	1			T5	4		T7	3		T123	9
valid_sources[0x03]	847	1			T15	65		T22	1		T157	1
valid_sources[0x04]	849	1			T158	1		T157	2		T24	12
valid_sources[0x05]	735	1			T2	1		T4	1		T15	3
valid_sources[0x06]	946	1			T3	3		T4	1		T157	4
valid_sources[0x07]	926	1			T157	6		T42	7		T159	11
valid_sources[0x08]	668	1			T2	4		T7	2		T22	1
valid_sources[0x09]	777	1			T157	2		T24	4		T14	33
valid_sources[0x0a]	807	1			T8	3		T42	3		T49	1
valid_sources[0x0b]	837	1			T157	3		T24	2		T83	6
valid_sources[0x0c]	2087	1			T2	29		T4	2		T22	1
valid_sources[0x0d]	812	1			T3	2		T4	5		T22	1
valid_sources[0x0e]	810	1			T157	6		T24	1		T43	1
valid_sources[0x0f]	616	1			T22	1		T157	1		T81	2
valid_sources[0x10]	847	1			T10	9		T157	2		T42	4
valid_sources[0x11]	842	1			T157	1		T42	7		T159	10
valid_sources[0x12]	704	1			T81	5		T84	1		T42	6
valid_sources[0x13]	1653	1			T3	1		T4	2		T5	1
valid_sources[0x14]	1007	1			T3	3		T7	3		T22	2
valid_sources[0x15]	810	1			T9	2		T4	3		T22	1
valid_sources[0x16]	752	1			T3	1		T157	1		T42	4
valid_sources[0x17]	727	1			T42	5		T49	1		T159	12
valid_sources[0x18]	796	1			T22	3		T157	4		T42	6
valid_sources[0x19]	809	1			T2	2		T3	1		T22	3
valid_sources[0x1a]	711	1			T4	2		T157	2		T117	1
valid_sources[0x1b]	745	1			T15	3		T157	3		T117	1
valid_sources[0x1c]	684	1			T2	10		T22	2		T84	2
valid_sources[0x1d]	725	1			T4	2		T157	2		T24	2
valid_sources[0x1e]	995	1			T2	1		T22	2		T157	4
valid_sources[0x1f]	1494	1			T3	188		T22	1		T157	3
valid_sources[0x20]	686	1			T22	1		T157	3		T24	4
valid_sources[0x21]	824	1			T22	2		T157	3		T24	11
valid_sources[0x22]	1033	1			T7	12		T22	1		T157	3
valid_sources[0x23]	913	1			T2	3		T4	11		T22	1
valid_sources[0x24]	1868	1			T80	6		T42	1		T49	1
valid_sources[0x25]	1238	1			T2	3		T22	1		T160	1
valid_sources[0x26]	840	1			T157	3		T24	1		T117	2
valid_sources[0x27]	712	1			T22	1		T157	3		T117	1
valid_sources[0x28]	656	1			T22	1		T157	2		T42	5
valid_sources[0x29]	2847	1			T8	5		T22	2		T157	3
valid_sources[0x2a]	927	1			T3	119		T4	3		T7	2
valid_sources[0x2b]	938	1			T3	129		T157	5		T24	1
valid_sources[0x2c]	670	1			T2	6		T157	2		T84	2
valid_sources[0x2d]	3998	1			T22	2		T42	9		T49	2
valid_sources[0x2e]	831	1			T3	1		T5	1		T157	2
valid_sources[0x2f]	756	1			T157	2		T42	5		T159	4
valid_sources[0x30]	821	1			T22	1		T157	1		T117	1
valid_sources[0x31]	929	1			T22	1		T157	1		T14	4
valid_sources[0x32]	815	1			T7	17		T15	3		T22	1
valid_sources[0x33]	719	1			T3	1		T157	2		T117	1
valid_sources[0x34]	2968	1			T5	1		T22	1		T157	1
valid_sources[0x35]	715	1			T7	10		T81	3		T42	7
valid_sources[0x36]	874	1			T22	2		T157	2		T43	1
valid_sources[0x37]	842	1			T5	2		T157	3		T83	3
valid_sources[0x38]	707	1			T22	2		T157	1		T42	6
valid_sources[0x39]	2171	1			T4	1		T7	14		T157	4
valid_sources[0x3a]	760	1			T2	2		T157	1		T24	1
valid_sources[0x3b]	1178	1			T5	1		T157	2		T14	1
valid_sources[0x3c]	907	1			T157	2		T117	2		T81	2
valid_sources[0x3d]	1561	1			T4	4		T157	3		T117	1
valid_sources[0x3e]	740	1			T5	2		T157	1		T24	1
valid_sources[0x3f]	829	1			T2	4		T3	1		T7	25
valid_sources[0x40]	651	1			T3	2		T15	3		T157	3
valid_sources[0x41]	1038	1			T22	3		T157	4		T24	5
valid_sources[0x42]	1056	1			T2	16		T3	35		T84	3
valid_sources[0x43]	636	1			T22	1		T157	4		T117	2
valid_sources[0x44]	703	1			T2	1		T157	3		T14	1
valid_sources[0x45]	1189	1			T2	5		T3	1		T15	100
valid_sources[0x46]	719	1			T2	2		T4	2		T22	1
valid_sources[0x47]	737	1			T5	1		T22	1		T157	2
valid_sources[0x48]	784	1			T4	2		T157	5		T80	11
valid_sources[0x49]	845	1			T3	3		T4	2		T22	1
valid_sources[0x4a]	971	1			T14	6		T84	2		T42	6
valid_sources[0x4b]	1245	1			T157	1		T117	1		T42	9
valid_sources[0x4c]	1053	1			T5	1		T22	2		T157	1
valid_sources[0x4d]	961	1			T2	4		T157	4		T117	1
valid_sources[0x4e]	884	1			T2	8		T5	2		T157	3
valid_sources[0x4f]	971	1			T22	1		T157	3		T83	1
valid_sources[0x50]	702	1			T5	1		T157	4		T80	2
valid_sources[0x51]	767	1			T157	1		T42	5		T49	3
valid_sources[0x52]	1086	1			T5	2		T22	2		T157	1
valid_sources[0x53]	1133	1			T22	2		T157	3		T24	6
valid_sources[0x54]	792	1			T2	6		T15	3		T22	1
valid_sources[0x55]	792	1			T4	1		T22	1		T157	2
valid_sources[0x56]	1211	1			T2	2		T15	76		T22	2
valid_sources[0x57]	787	1			T2	12		T4	2		T157	3
valid_sources[0x58]	1089	1			T4	6		T15	49		T22	1
valid_sources[0x59]	916	1			T22	1		T157	1		T42	11
valid_sources[0x5a]	1068	1			T2	16		T22	2		T157	1
valid_sources[0x5b]	1175	1			T2	7		T15	3		T22	1
valid_sources[0x5c]	746	1			T10	19		T22	1		T157	1
valid_sources[0x5d]	714	1			T157	3		T42	10		T49	1
valid_sources[0x5e]	656	1			T42	4		T159	10		T50	2
valid_sources[0x5f]	1258	1			T3	1		T157	1		T117	1
valid_sources[0x60]	1012	1			T5	4		T7	2		T157	2
valid_sources[0x61]	1043	1			T2	1		T3	139		T157	2
valid_sources[0x62]	749	1			T4	3		T5	5		T157	2
valid_sources[0x63]	1195	1			T5	1		T42	8		T159	12
valid_sources[0x64]	849	1			T157	3		T84	3		T42	5
valid_sources[0x65]	1050	1			T3	113		T157	4		T14	10
valid_sources[0x66]	858	1			T5	5		T157	2		T24	15
valid_sources[0x67]	1012	1			T2	11		T22	1		T117	1
valid_sources[0x68]	678	1			T157	1		T79	2		T80	5
valid_sources[0x69]	685	1			T22	3		T157	1		T83	1
valid_sources[0x6a]	1457	1			T3	4		T158	1		T157	4
valid_sources[0x6b]	2585	1			T5	3		T22	1		T157	1
valid_sources[0x6c]	898	1			T22	2		T157	4		T42	5
valid_sources[0x6d]	836	1			T5	1		T10	6		T22	2
valid_sources[0x6e]	830	1			T3	1		T42	3		T49	5
valid_sources[0x6f]	892	1			T157	1		T42	7		T161	1
valid_sources[0x70]	990	1			T4	4		T15	134		T157	1
valid_sources[0x71]	912	1			T3	2		T42	9		T159	11
valid_sources[0x72]	748	1			T3	3		T4	1		T22	4
valid_sources[0x73]	1257	1			T8	2		T157	3		T79	1
valid_sources[0x74]	800	1			T2	2		T3	1		T157	2
valid_sources[0x75]	672	1			T3	1		T22	8		T117	1
valid_sources[0x76]	757	1			T8	1		T157	2		T81	1
valid_sources[0x77]	963	1			T3	3		T4	1		T157	5
valid_sources[0x78]	925	1			T22	5		T79	2		T84	3
valid_sources[0x79]	991	1			T3	134		T22	1		T157	3
valid_sources[0x7a]	848	1			T2	23		T22	1		T157	1
valid_sources[0x7b]	825	1			T5	1		T7	4		T157	2
valid_sources[0x7c]	1045	1			T4	4		T157	3		T14	8
valid_sources[0x7d]	892	1			T5	2		T22	1		T157	2
valid_sources[0x7e]	762	1			T42	3		T49	1		T159	9
valid_sources[0x7f]	824	1			T22	1		T157	3		T24	15
valid_sources[0x80]	882	1			T2	15		T4	1		T157	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20936

1

T1

10

T3

304

T7

12

values[0x0]

all_enables

biggest_size

52068

1

T1

47

T2

126

T3

444

values[0x1]

all_enables

biggest_size

38630

1

T1

18

T2

51

T3

438