Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14161186

1

T1

97

T3

1216

T9

1855

full_word

81432839

1

T1

1027

T2

137625

T3

2183

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	95593885	1			T1	1124		T2	137625		T3	3399
auto[TlIntgErrCmd]	43	1			T44	3		T45	3		T46	1
auto[TlIntgErrData]	48	1			T44	2		T45	3		T46	4
auto[TlIntgErrBoth]	49	1			T44	5		T45	4		T46	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45712202

1

T1

518

T2

688128

T3

817

auto[1]

49881823

1

T1

606

T2

688128

T3

2582

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7020523	1			T1	52		T3	250		T9	940
auto[TlIntgErrNone]	partial	auto[1]	7140543	1			T1	45		T3	966		T9	915
auto[TlIntgErrNone]	full_word	auto[0]	38691622	1			T1	466		T2	688128		T3	567
auto[TlIntgErrNone]	full_word	auto[1]	42741197	1			T1	561		T2	688128		T3	1616
auto[TlIntgErrCmd]	partial	auto[0]	13	1			T44	2		T45	2		T46	1
auto[TlIntgErrCmd]	partial	auto[1]	26	1			T44	1		T142	8		T143	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T45	1		T147	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T148	1		T147	1		-	-
auto[TlIntgErrData]	partial	auto[0]	18	1			T44	2		T45	2		T46	2
auto[TlIntgErrData]	partial	auto[1]	22	1			T45	1		T46	1		T142	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T142	2		T143	1		T148	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T46	1		T143	1		T146	1
auto[TlIntgErrBoth]	partial	auto[0]	16	1			T44	3		T45	2		T46	1
auto[TlIntgErrBoth]	partial	auto[1]	25	1			T44	2		T45	2		T46	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T46	1		T143	1		T147	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T146	1		T145	1		T144	1