Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	310687	1			T12	1737		T13	4313		T14	334
auto[1]	4425262	1			T1	376		T6	2948		T9	5006
auto[2]	247651	1			T1	1		T12	1164		T13	3427
auto[3]	4351358	1			T1	452		T6	3070		T9	4993

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4767847	1			T1	717		T6	6018		T9	6594
auto[1]	914359	1			T1	45		T9	1550		T4	18181
auto[2]	932948	1			T1	59		T9	1512		T4	18320
auto[3]	2719804	1			T1	8		T9	343		T4	81921

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2452724

1

T1

829

T6

6018

T9

9999

auto[1]

6882234

1

T4

122394

T5

11488

T11

16237

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	92032	1			T12	1423		T14	272		T49	15
auto[0]	auto[0]	auto[1]	10138	1			T12	141		T13	31		T14	29
auto[0]	auto[0]	auto[2]	10230	1			T12	154		T13	25		T14	26
auto[0]	auto[0]	auto[3]	74513	1			T12	19		T13	4255		T14	7
auto[0]	auto[1]	auto[0]	603051	1			T1	319		T6	2948		T9	3275
auto[0]	auto[1]	auto[1]	69865	1			T1	18		T9	791		T10	26
auto[0]	auto[1]	auto[2]	85228	1			T1	34		T9	753		T10	13
auto[0]	auto[1]	auto[3]	330163	1			T1	5		T9	187		T10	5
auto[0]	auto[2]	auto[0]	71967	1			T1	1		T12	920		T13	4
auto[0]	auto[2]	auto[1]	13181	1			T12	98		T13	371		T14	27
auto[0]	auto[2]	auto[2]	7481	1			T12	125		T13	23		T14	19
auto[0]	auto[2]	auto[3]	54184	1			T12	21		T13	3028		T14	1
auto[0]	auto[3]	auto[0]	567449	1			T1	397		T6	3070		T9	3319
auto[0]	auto[3]	auto[1]	78526	1			T1	27		T9	759		T10	6
auto[0]	auto[3]	auto[2]	89730	1			T1	25		T9	759		T10	20
auto[0]	auto[3]	auto[3]	294986	1			T1	3		T9	156		T12	20
auto[1]	auto[0]	auto[0]	4099	1			T152	249		T153	628		T154	531
auto[1]	auto[0]	auto[1]	18369	1			T155	1		T152	1004		T153	2731
auto[1]	auto[0]	auto[2]	18366	1			T152	992		T153	2669		T154	2396
auto[1]	auto[0]	auto[3]	82940	1			T13	2		T96	1		T97	1
auto[1]	auto[1]	auto[0]	1711558	1			T4	1988		T5	4734		T11	97
auto[1]	auto[1]	auto[1]	359631	1			T4	8958		T5	485		T11	1397
auto[1]	auto[1]	auto[2]	350803	1			T4	9135		T5	470		T11	447
auto[1]	auto[1]	auto[3]	914963	1			T4	41083		T5	48		T11	6111
auto[1]	auto[2]	auto[0]	3408	1			T152	131		T153	520		T154	474
auto[1]	auto[2]	auto[1]	15596	1			T152	606		T153	2423		T154	2101
auto[1]	auto[2]	auto[2]	14928	1			T152	1029		T153	1938		T154	1969
auto[1]	auto[2]	auto[3]	66906	1			T13	1		T152	4603		T153	8515
auto[1]	auto[3]	auto[0]	1714283	1			T4	1984		T5	4765		T11	112
auto[1]	auto[3]	auto[1]	349053	1			T4	9223		T5	466		T11	491
auto[1]	auto[3]	auto[2]	356182	1			T4	9185		T5	465		T11	1362
auto[1]	auto[3]	auto[3]	901149	1			T4	40838		T5	55		T11	6220