Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.12	100.00	89.90	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	689101434	102191	0	0
ctrl_regwen_rd_A	689101434	2394	0	0
exec_rd_A	689101434	2169	0	0
exec_regwen_rd_A	689101434	2441	0	0
readback_rd_A	689101434	1337	0	0
readback_regwen_rd_A	689101434	1040	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689101434	102191	0	0
T3	20961	2179	0	0
T4	791206	0	0	0
T5	611172	0	0	0
T6	72933	0	0	0
T7	685563	0	0	0
T9	79169	0	0	0
T10	376784	0	0	0
T11	194787	0	0	0
T15	0	1236	0	0
T16	1342	0	0	0
T17	817	0	0	0
T25	0	1875	0	0
T51	0	2371	0	0
T52	0	1891	0	0
T53	0	2788	0	0
T54	0	3023	0	0
T55	0	1607	0	0
T56	0	3142	0	0
T57	0	1694	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689101434	2394	0	0
T45	0	20	0	0
T53	57718	278	0	0
T72	991455	0	0	0
T87	0	38	0	0
T109	0	14	0	0
T111	0	19	0	0
T125	0	72	0	0
T126	0	119	0	0
T127	0	243	0	0
T128	0	213	0	0
T129	0	226	0	0
T130	394156	0	0	0
T131	71361	0	0	0
T132	896508	0	0	0
T133	574787	0	0	0
T134	1813	0	0	0
T135	109604	0	0	0
T136	40976	0	0	0
T137	114659	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689101434	2169	0	0
T45	0	18	0	0
T53	57718	200	0	0
T72	991455	0	0	0
T87	0	26	0	0
T109	0	16	0	0
T111	0	5	0	0
T125	0	52	0	0
T126	0	139	0	0
T127	0	188	0	0
T128	0	174	0	0
T129	0	180	0	0
T130	394156	0	0	0
T131	71361	0	0	0
T132	896508	0	0	0
T133	574787	0	0	0
T134	1813	0	0	0
T135	109604	0	0	0
T136	40976	0	0	0
T137	114659	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689101434	2441	0	0
T45	0	20	0	0
T53	57718	260	0	0
T72	991455	0	0	0
T87	0	34	0	0
T109	0	28	0	0
T111	0	7	0	0
T125	0	55	0	0
T126	0	178	0	0
T127	0	184	0	0
T128	0	166	0	0
T129	0	236	0	0
T130	394156	0	0	0
T131	71361	0	0	0
T132	896508	0	0	0
T133	574787	0	0	0
T134	1813	0	0	0
T135	109604	0	0	0
T136	40976	0	0	0
T137	114659	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689101434	1337	0	0
T53	57718	245	0	0
T72	991455	0	0	0
T125	0	29	0	0
T126	0	167	0	0
T127	0	170	0	0
T128	0	157	0	0
T129	0	286	0	0
T130	394156	0	0	0
T131	71361	0	0	0
T132	896508	0	0	0
T133	574787	0	0	0
T134	1813	0	0	0
T135	109604	0	0	0
T136	40976	0	0	0
T137	114659	0	0	0
T138	0	91	0	0
T139	0	20	0	0
T140	0	12	0	0
T141	0	56	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689101434	1040	0	0
T53	57718	213	0	0
T72	991455	0	0	0
T125	0	13	0	0
T126	0	126	0	0
T127	0	206	0	0
T128	0	150	0	0
T129	0	156	0	0
T130	394156	0	0	0
T131	71361	0	0	0
T132	896508	0	0	0
T133	574787	0	0	0
T134	1813	0	0	0
T135	109604	0	0	0
T136	40976	0	0	0
T137	114659	0	0	0
T138	0	58	0	0
T139	0	5	0	0
T140	0	6	0	0
T141	0	36	0	0