Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14091684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

86761468

1

T1

196606

T2

1237

T4

93431

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49150845	1			T1	65536		T2	682		T4	51349
values[0x0]	24444383	1			T1	65738		T2	307		T4	24964
values[0x1]	27257924	1			T1	65332		T2	352		T4	26453

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7188788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

93664364

1

T1

196606

T2

1287

T4

98086

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	305269	1			T1	758		T4	453		T5	374
valid_sources[0x01]	321453	1			T1	794		T4	423		T5	376
valid_sources[0x02]	305886	1			T1	784		T4	407		T5	384
valid_sources[0x03]	303388	1			T1	787		T4	347		T5	385
valid_sources[0x04]	300204	1			T1	761		T4	388		T5	411
valid_sources[0x05]	887895	1			T1	774		T4	420		T5	338
valid_sources[0x06]	296629	1			T1	747		T4	408		T5	376
valid_sources[0x07]	302325	1			T1	731		T4	431		T5	358
valid_sources[0x08]	296590	1			T1	720		T4	400		T5	395
valid_sources[0x09]	330918	1			T1	741		T4	470		T5	376
valid_sources[0x0a]	299351	1			T1	804		T4	450		T5	377
valid_sources[0x0b]	341734	1			T1	801		T4	385		T5	403
valid_sources[0x0c]	331509	1			T1	760		T4	449		T5	400
valid_sources[0x0d]	318461	1			T1	722		T4	429		T5	369
valid_sources[0x0e]	313665	1			T1	745		T2	101		T4	375
valid_sources[0x0f]	305162	1			T1	770		T4	449		T5	384
valid_sources[0x10]	1289578	1			T1	745		T4	364		T5	352
valid_sources[0x11]	424467	1			T1	775		T4	380		T5	382
valid_sources[0x12]	502224	1			T1	798		T4	424		T5	364
valid_sources[0x13]	303948	1			T1	706		T4	445		T5	396
valid_sources[0x14]	515108	1			T1	777		T4	355		T5	351
valid_sources[0x15]	355475	1			T1	717		T4	426		T5	416
valid_sources[0x16]	297462	1			T1	805		T4	446		T5	387
valid_sources[0x17]	316791	1			T1	686		T4	477		T5	360
valid_sources[0x18]	297518	1			T1	857		T4	453		T5	346
valid_sources[0x19]	320160	1			T1	808		T2	18		T4	423
valid_sources[0x1a]	300536	1			T1	784		T4	420		T5	441
valid_sources[0x1b]	346186	1			T1	772		T2	71		T4	364
valid_sources[0x1c]	413951	1			T1	832		T4	459		T5	389
valid_sources[0x1d]	299655	1			T1	753		T4	392		T5	380
valid_sources[0x1e]	296826	1			T1	732		T2	19		T4	360
valid_sources[0x1f]	310513	1			T1	776		T2	40		T4	397
valid_sources[0x20]	319479	1			T1	720		T4	375		T5	408
valid_sources[0x21]	299111	1			T1	779		T4	377		T5	389
valid_sources[0x22]	314450	1			T1	760		T4	460		T5	406
valid_sources[0x23]	512041	1			T1	788		T4	362		T5	334
valid_sources[0x24]	297586	1			T1	818		T4	412		T5	401
valid_sources[0x25]	374338	1			T1	715		T4	401		T5	372
valid_sources[0x26]	314318	1			T1	724		T2	37		T4	415
valid_sources[0x27]	357346	1			T1	777		T4	374		T5	349
valid_sources[0x28]	302869	1			T1	771		T4	457		T5	390
valid_sources[0x29]	303554	1			T1	750		T2	5		T4	342
valid_sources[0x2a]	318366	1			T1	758		T4	414		T5	395
valid_sources[0x2b]	324406	1			T1	731		T4	448		T5	385
valid_sources[0x2c]	328292	1			T1	761		T4	323		T5	367
valid_sources[0x2d]	348348	1			T1	858		T2	26		T4	425
valid_sources[0x2e]	888372	1			T1	808		T4	371		T5	407
valid_sources[0x2f]	309496	1			T1	708		T4	315		T5	380
valid_sources[0x30]	301218	1			T1	787		T4	402		T5	374
valid_sources[0x31]	346991	1			T1	774		T4	338		T5	363
valid_sources[0x32]	335952	1			T1	774		T4	322		T5	384
valid_sources[0x33]	335845	1			T1	783		T4	341		T5	408
valid_sources[0x34]	491047	1			T1	847		T4	375		T5	388
valid_sources[0x35]	328295	1			T1	775		T4	415		T5	376
valid_sources[0x36]	331731	1			T1	782		T4	416		T5	364
valid_sources[0x37]	304605	1			T1	769		T4	414		T5	411
valid_sources[0x38]	326782	1			T1	723		T4	483		T5	389
valid_sources[0x39]	313241	1			T1	740		T4	440		T5	406
valid_sources[0x3a]	345167	1			T1	715		T4	414		T5	387
valid_sources[0x3b]	318398	1			T1	764		T4	504		T5	417
valid_sources[0x3c]	311194	1			T1	735		T4	389		T5	351
valid_sources[0x3d]	303977	1			T1	779		T4	363		T5	407
valid_sources[0x3e]	313776	1			T1	827		T4	402		T5	415
valid_sources[0x3f]	315202	1			T1	809		T4	463		T5	403
valid_sources[0x40]	394691	1			T1	751		T4	435		T5	403
valid_sources[0x41]	299395	1			T1	716		T4	362		T5	400
valid_sources[0x42]	319216	1			T1	835		T4	388		T5	386
valid_sources[0x43]	527134	1			T1	803		T4	458		T5	364
valid_sources[0x44]	305047	1			T1	738		T4	399		T5	339
valid_sources[0x45]	304285	1			T1	800		T4	418		T5	385
valid_sources[0x46]	330001	1			T1	747		T4	395		T5	411
valid_sources[0x47]	299974	1			T1	736		T4	377		T5	413
valid_sources[0x48]	307302	1			T1	792		T4	386		T5	313
valid_sources[0x49]	312923	1			T1	739		T4	409		T5	365
valid_sources[0x4a]	356290	1			T1	816		T4	370		T5	374
valid_sources[0x4b]	318186	1			T1	757		T4	366		T5	370
valid_sources[0x4c]	316837	1			T1	698		T4	385		T5	377
valid_sources[0x4d]	319996	1			T1	781		T4	402		T5	425
valid_sources[0x4e]	300667	1			T1	772		T4	382		T5	374
valid_sources[0x4f]	393256	1			T1	792		T4	385		T5	393
valid_sources[0x50]	909998	1			T1	744		T4	400		T5	375
valid_sources[0x51]	297819	1			T1	707		T4	356		T5	407
valid_sources[0x52]	316137	1			T1	815		T2	65		T4	394
valid_sources[0x53]	370783	1			T1	777		T4	397		T5	365
valid_sources[0x54]	319910	1			T1	715		T4	378		T5	376
valid_sources[0x55]	298464	1			T1	755		T4	345		T5	375
valid_sources[0x56]	349956	1			T1	833		T4	355		T5	394
valid_sources[0x57]	363399	1			T1	787		T4	387		T5	378
valid_sources[0x58]	321781	1			T1	693		T4	396		T5	393
valid_sources[0x59]	298976	1			T1	769		T4	413		T5	364
valid_sources[0x5a]	314793	1			T1	753		T4	389		T5	379
valid_sources[0x5b]	353377	1			T1	773		T4	412		T5	461
valid_sources[0x5c]	306849	1			T1	744		T4	437		T5	365
valid_sources[0x5d]	1313793	1			T1	800		T4	412		T5	377
valid_sources[0x5e]	337003	1			T1	729		T4	389		T5	375
valid_sources[0x5f]	313696	1			T1	788		T4	416		T5	362
valid_sources[0x60]	337376	1			T1	779		T4	418		T5	406
valid_sources[0x61]	315129	1			T1	800		T2	64		T4	384
valid_sources[0x62]	307189	1			T1	772		T4	383		T5	370
valid_sources[0x63]	311787	1			T1	732		T4	446		T5	414
valid_sources[0x64]	298213	1			T1	755		T4	442		T5	405
valid_sources[0x65]	300899	1			T1	775		T4	403		T5	391
valid_sources[0x66]	334239	1			T1	742		T4	332		T5	386
valid_sources[0x67]	298909	1			T1	718		T4	329		T5	330
valid_sources[0x68]	299523	1			T1	734		T4	381		T5	387
valid_sources[0x69]	346573	1			T1	686		T4	403		T5	335
valid_sources[0x6a]	310402	1			T1	797		T4	397		T5	364
valid_sources[0x6b]	331458	1			T1	747		T4	387		T5	358
valid_sources[0x6c]	298088	1			T1	813		T4	426		T5	383
valid_sources[0x6d]	303488	1			T1	786		T4	354		T5	419
valid_sources[0x6e]	309588	1			T1	789		T4	407		T5	381
valid_sources[0x6f]	308527	1			T1	762		T4	411		T5	419
valid_sources[0x70]	326098	1			T1	736		T2	146		T4	403
valid_sources[0x71]	307023	1			T1	785		T4	336		T5	382
valid_sources[0x72]	368375	1			T1	748		T4	434		T5	354
valid_sources[0x73]	367140	1			T1	759		T4	372		T5	377
valid_sources[0x74]	404641	1			T1	790		T4	428		T5	379
valid_sources[0x75]	312540	1			T1	757		T2	25		T4	436
valid_sources[0x76]	325426	1			T1	718		T4	408		T5	378
valid_sources[0x77]	302781	1			T1	776		T4	339		T5	383
valid_sources[0x78]	386514	1			T1	779		T4	392		T5	353
valid_sources[0x79]	403539	1			T1	772		T2	40		T4	417
valid_sources[0x7a]	303065	1			T1	822		T4	349		T5	424
valid_sources[0x7b]	301333	1			T1	761		T4	406		T5	359
valid_sources[0x7c]	301038	1			T1	803		T4	392		T5	372
valid_sources[0x7d]	561199	1			T1	708		T4	431		T5	366
valid_sources[0x7e]	323463	1			T1	807		T4	424		T5	359
valid_sources[0x7f]	367499	1			T1	745		T4	420		T5	369
valid_sources[0x80]	310408	1			T1	778		T4	402		T5	383

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42058901

1

T1

65536

T2

635

T4

46707

values[0x0]

all_enables

biggest_size

22344466

1

T1

65738

T2

286

T4

23566

values[0x1]

all_enables

biggest_size

22358101

1

T1

65332

T2

316

T4

23158

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121611

1

T1

69

T2

27

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30913	1			T2	12		T4	11		T22	14
values[0x0]	119415	1			T1	138		T2	44		T3	4
values[0x1]	122812	1			T1	151		T2	43		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	131701	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141439

1

T1

94

T2

34

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	842	1			T1	1		T44	1		T26	7
valid_sources[0x01]	838	1			T1	5		T26	10		T66	1
valid_sources[0x02]	2517	1			T2	1		T44	1		T16	1
valid_sources[0x03]	974	1			T1	2		T14	1		T26	10
valid_sources[0x04]	747	1			T1	1		T6	3		T44	1
valid_sources[0x05]	3388	1			T18	1		T113	7		T26	8
valid_sources[0x06]	770	1			T6	1		T44	1		T113	1
valid_sources[0x07]	752	1			T1	4		T2	1		T26	6
valid_sources[0x08]	861	1			T2	1		T4	6		T44	3
valid_sources[0x09]	4245	1			T1	1		T4	3		T18	2
valid_sources[0x0a]	1329	1			T44	10		T113	3		T16	2
valid_sources[0x0b]	832	1			T113	4		T26	8		T7	1
valid_sources[0x0c]	979	1			T1	1		T18	1		T44	2
valid_sources[0x0d]	762	1			T11	1		T18	1		T44	2
valid_sources[0x0e]	831	1			T6	1		T44	3		T113	2
valid_sources[0x0f]	901	1			T6	1		T26	22		T7	10
valid_sources[0x10]	858	1			T1	5		T44	1		T113	2
valid_sources[0x11]	1003	1			T6	1		T14	1		T18	2
valid_sources[0x12]	724	1			T1	3		T14	1		T18	1
valid_sources[0x13]	884	1			T1	1		T2	1		T6	1
valid_sources[0x14]	654	1			T6	2		T44	1		T26	1
valid_sources[0x15]	789	1			T1	2		T14	1		T18	1
valid_sources[0x16]	791	1			T1	1		T2	3		T4	3
valid_sources[0x17]	1017	1			T18	1		T113	5		T26	9
valid_sources[0x18]	795	1			T44	2		T113	1		T26	18
valid_sources[0x19]	815	1			T1	1		T18	1		T44	2
valid_sources[0x1a]	1349	1			T1	1		T2	1		T6	4
valid_sources[0x1b]	983	1			T1	1		T6	1		T44	2
valid_sources[0x1c]	688	1			T1	1		T26	6		T66	1
valid_sources[0x1d]	767	1			T2	1		T16	2		T26	6
valid_sources[0x1e]	859	1			T1	2		T44	1		T26	13
valid_sources[0x1f]	924	1			T6	4		T44	1		T113	8
valid_sources[0x20]	887	1			T1	3		T6	4		T18	2
valid_sources[0x21]	1059	1			T1	1		T18	2		T113	3
valid_sources[0x22]	756	1			T6	1		T26	12		T66	2
valid_sources[0x23]	939	1			T2	1		T113	1		T26	11
valid_sources[0x24]	859	1			T2	1		T6	3		T18	1
valid_sources[0x25]	935	1			T2	1		T44	2		T113	5
valid_sources[0x26]	967	1			T2	1		T30	1		T44	9
valid_sources[0x27]	719	1			T2	2		T6	1		T26	12
valid_sources[0x28]	743	1			T113	6		T26	8		T7	1
valid_sources[0x29]	771	1			T1	2		T4	5		T18	1
valid_sources[0x2a]	721	1			T2	1		T6	1		T44	1
valid_sources[0x2b]	707	1			T1	4		T6	2		T18	1
valid_sources[0x2c]	672	1			T26	12		T7	4		T39	8
valid_sources[0x2d]	908	1			T18	1		T44	1		T26	13
valid_sources[0x2e]	982	1			T1	3		T18	1		T16	3
valid_sources[0x2f]	993	1			T1	4		T44	1		T26	8
valid_sources[0x30]	1026	1			T1	2		T6	1		T44	2
valid_sources[0x31]	840	1			T1	5		T4	12		T44	2
valid_sources[0x32]	729	1			T1	1		T2	1		T4	1
valid_sources[0x33]	933	1			T44	2		T16	2		T26	4
valid_sources[0x34]	773	1			T14	1		T26	17		T63	1
valid_sources[0x35]	856	1			T1	2		T6	2		T18	1
valid_sources[0x36]	896	1			T1	5		T18	1		T113	4
valid_sources[0x37]	851	1			T1	2		T6	1		T18	1
valid_sources[0x38]	795	1			T44	2		T113	1		T26	22
valid_sources[0x39]	973	1			T6	1		T18	1		T44	3
valid_sources[0x3a]	729	1			T2	1		T26	4		T7	4
valid_sources[0x3b]	915	1			T1	1		T2	1		T6	1
valid_sources[0x3c]	845	1			T1	2		T2	1		T6	1
valid_sources[0x3d]	727	1			T1	1		T2	1		T4	2
valid_sources[0x3e]	879	1			T10	1		T26	7		T66	1
valid_sources[0x3f]	754	1			T1	2		T22	32		T26	10
valid_sources[0x40]	886	1			T1	4		T6	1		T18	1
valid_sources[0x41]	689	1			T14	1		T44	1		T113	1
valid_sources[0x42]	745	1			T2	1		T18	1		T16	4
valid_sources[0x43]	877	1			T1	1		T26	16		T66	2
valid_sources[0x44]	818	1			T1	1		T6	1		T44	2
valid_sources[0x45]	1179	1			T4	10		T18	2		T113	1
valid_sources[0x46]	976	1			T2	1		T44	3		T26	4
valid_sources[0x47]	967	1			T30	1		T26	14		T64	9
valid_sources[0x48]	860	1			T44	3		T16	5		T26	10
valid_sources[0x49]	909	1			T1	2		T6	1		T18	2
valid_sources[0x4a]	1838	1			T2	1		T18	1		T44	1
valid_sources[0x4b]	968	1			T1	6		T44	3		T26	26
valid_sources[0x4c]	907	1			T2	1		T6	1		T113	3
valid_sources[0x4d]	1037	1			T1	2		T18	1		T44	5
valid_sources[0x4e]	767	1			T1	2		T16	8		T26	19
valid_sources[0x4f]	638	1			T44	2		T26	11		T66	2
valid_sources[0x50]	939	1			T1	3		T5	130		T18	1
valid_sources[0x51]	809	1			T6	1		T44	4		T26	10
valid_sources[0x52]	708	1			T6	1		T113	11		T26	13
valid_sources[0x53]	1000	1			T1	1		T4	2		T44	1
valid_sources[0x54]	820	1			T1	2		T16	2		T26	7
valid_sources[0x55]	2910	1			T1	2		T26	6		T66	1
valid_sources[0x56]	715	1			T6	1		T44	1		T26	26
valid_sources[0x57]	1066	1			T1	1		T44	1		T113	1
valid_sources[0x58]	740	1			T1	2		T2	1		T18	1
valid_sources[0x59]	714	1			T2	1		T18	2		T44	2
valid_sources[0x5a]	996	1			T6	1		T18	1		T44	1
valid_sources[0x5b]	834	1			T6	1		T44	1		T26	22
valid_sources[0x5c]	941	1			T1	2		T2	1		T6	2
valid_sources[0x5d]	676	1			T18	2		T44	1		T26	13
valid_sources[0x5e]	788	1			T26	10		T7	2		T66	1
valid_sources[0x5f]	840	1			T6	1		T22	28		T26	14
valid_sources[0x60]	1198	1			T1	5		T113	3		T26	8
valid_sources[0x61]	731	1			T26	11		T66	1		T39	7
valid_sources[0x62]	1685	1			T1	4		T6	1		T18	2
valid_sources[0x63]	1021	1			T1	7		T2	1		T6	1
valid_sources[0x64]	859	1			T1	1		T44	1		T113	2
valid_sources[0x65]	754	1			T2	1		T6	1		T44	3
valid_sources[0x66]	889	1			T2	1		T18	1		T26	10
valid_sources[0x67]	1687	1			T1	3		T2	1		T6	1
valid_sources[0x68]	646	1			T44	1		T113	1		T16	2
valid_sources[0x69]	785	1			T6	1		T44	7		T113	9
valid_sources[0x6a]	1265	1			T12	12		T44	2		T113	10
valid_sources[0x6b]	823	1			T2	1		T43	1		T26	17
valid_sources[0x6c]	904	1			T1	1		T6	1		T44	2
valid_sources[0x6d]	1097	1			T1	1		T2	1		T4	5
valid_sources[0x6e]	726	1			T14	1		T26	10		T66	4
valid_sources[0x6f]	778	1			T2	1		T113	4		T26	7
valid_sources[0x70]	792	1			T1	4		T26	16		T39	3
valid_sources[0x71]	838	1			T16	3		T26	12		T66	2
valid_sources[0x72]	803	1			T113	3		T26	3		T114	11
valid_sources[0x73]	944	1			T113	2		T26	18		T64	4
valid_sources[0x74]	1048	1			T2	1		T4	2		T44	3
valid_sources[0x75]	1042	1			T6	2		T44	2		T26	16
valid_sources[0x76]	757	1			T1	2		T10	2		T6	1
valid_sources[0x77]	900	1			T1	1		T4	4		T44	12
valid_sources[0x78]	965	1			T2	2		T44	1		T26	16
valid_sources[0x79]	826	1			T1	3		T2	1		T44	5
valid_sources[0x7a]	776	1			T2	1		T44	14		T26	7
valid_sources[0x7b]	940	1			T2	1		T18	1		T44	2
valid_sources[0x7c]	831	1			T6	2		T113	2		T26	16
valid_sources[0x7d]	753	1			T4	7		T6	1		T44	5
valid_sources[0x7e]	756	1			T1	3		T44	1		T26	8
valid_sources[0x7f]	730	1			T1	6		T6	1		T14	1
valid_sources[0x80]	1050	1			T1	3		T2	1		T16	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22132

1

T2

5

T4

3

T22

12

values[0x0]

all_enables

biggest_size

57404

1

T1

44

T2

15

T3

1

values[0x1]

all_enables

biggest_size

42075

1

T1

25

T2

7

T3

1