Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14028206

1

T2

21

T4

8117

T6

6531

full_word

85071942

1

T1

196606

T2

252

T4

80751

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	99099968	1			T1	196606		T2	273		T4	88868
auto[TlIntgErrCmd]	62	1			T46	4		T47	4		T48	3
auto[TlIntgErrData]	51	1			T46	1		T47	1		T48	2
auto[TlIntgErrBoth]	67	1			T46	5		T47	5		T48	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47354419

1

T1

65536

T2

144

T4

37451

auto[1]

51745729

1

T1

131070

T2

129

T4

51417

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6947860	1			T2	12		T4	3424		T6	3275
auto[TlIntgErrNone]	partial	auto[1]	7080186	1			T2	9		T4	4693		T6	3256
auto[TlIntgErrNone]	full_word	auto[0]	40406484	1			T1	65536		T2	132		T4	34027
auto[TlIntgErrNone]	full_word	auto[1]	44665438	1			T1	131070		T2	120		T4	46724
auto[TlIntgErrCmd]	partial	auto[0]	19	1			T46	2		T47	4		T125	3
auto[TlIntgErrCmd]	partial	auto[1]	34	1			T46	2		T48	3		T125	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T125	1		T126	1		T127	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T125	2		T127	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	21	1			T46	1		T48	1		T125	1
auto[TlIntgErrData]	partial	auto[1]	25	1			T47	1		T48	1		T125	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T125	1		T129	1		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	22	1			T46	3		T48	2		T125	3
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T46	2		T47	3		T48	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T130	1		T131	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T47	2		T133	1		-	-