Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	378298	1			T6	2650		T15	258		T16	478
auto[1]	4249156	1			T2	99		T4	262		T6	631
auto[2]	298002	1			T6	2538		T15	229		T16	273
auto[3]	4145772	1			T2	102		T4	184		T6	398

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5430167	1			T2	180		T4	316		T6	4763
auto[1]	814277	1			T2	7		T4	66		T6	698
auto[2]	829133	1			T2	13		T4	52		T6	667
auto[3]	1997651	1			T2	1		T4	12		T6	89

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2583227

1

T2

201

T4

446

T6

6217

auto[1]

6488001

1

T13

107033

T22

2

T45

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	70930	1			T6	2154		T15	218		T16	404
auto[0]	auto[0]	auto[1]	8251	1			T6	244		T15	19		T16	37
auto[0]	auto[0]	auto[2]	8281	1			T6	226		T15	21		T16	33
auto[0]	auto[0]	auto[3]	61641	1			T6	26		T16	4		T144	627
auto[0]	auto[1]	auto[0]	728747	1			T2	90		T4	180		T6	337
auto[0]	auto[1]	auto[1]	79020	1			T2	1		T4	57		T6	240
auto[0]	auto[1]	auto[2]	95132	1			T2	8		T4	20		T6	29
auto[0]	auto[1]	auto[3]	292316	1			T4	5		T6	25		T12	17
auto[0]	auto[2]	auto[0]	49021	1			T6	2106		T15	194		T16	211
auto[0]	auto[2]	auto[1]	9993	1			T6	200		T15	23		T16	21
auto[0]	auto[2]	auto[2]	5484	1			T6	211		T15	11		T16	40
auto[0]	auto[2]	auto[3]	45210	1			T6	21		T15	1		T16	1
auto[0]	auto[3]	auto[0]	684619	1			T2	90		T4	136		T6	166
auto[0]	auto[3]	auto[1]	88042	1			T2	6		T4	9		T6	14
auto[0]	auto[3]	auto[2]	95460	1			T2	5		T4	32		T6	201
auto[0]	auto[3]	auto[3]	261080	1			T2	1		T4	7		T6	17
auto[1]	auto[0]	auto[0]	7525	1			T112	705		T142	292		T143	284
auto[1]	auto[0]	auto[1]	33906	1			T112	3236		T142	1295		T143	1309
auto[1]	auto[0]	auto[2]	33914	1			T112	3260		T142	1279		T143	1251
auto[1]	auto[0]	auto[3]	153850	1			T112	15035		T142	5838		T145	3
auto[1]	auto[1]	auto[0]	1940462	1			T13	44067		T22	1		T64	5887
auto[1]	auto[1]	auto[1]	298378	1			T13	4463		T45	1		T64	473
auto[1]	auto[1]	auto[2]	271325	1			T13	4464		T64	603		T50	6516
auto[1]	auto[1]	auto[3]	543776	1			T13	465		T64	46		T50	602
auto[1]	auto[2]	auto[0]	6618	1			T112	690		T142	274		T137	1
auto[1]	auto[2]	auto[1]	29526	1			T112	3056		T142	1224		T143	1120
auto[1]	auto[2]	auto[2]	27757	1			T112	2335		T142	960		T143	1080
auto[1]	auto[2]	auto[3]	124393	1			T112	10598		T142	4142		T143	4851
auto[1]	auto[3]	auto[0]	1942245	1			T13	44204		T64	5932		T50	64469
auto[1]	auto[3]	auto[1]	267161	1			T13	4525		T22	1		T64	582
auto[1]	auto[3]	auto[2]	291780	1			T13	4437		T64	519		T50	5861
auto[1]	auto[3]	auto[3]	515385	1			T13	408		T64	56		T50	588