Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.12	100.00	89.90	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	729279559	112517	0	0
ctrl_regwen_rd_A	729279559	2664	0	0
exec_rd_A	729279559	2397	0	0
exec_regwen_rd_A	729279559	2852	0	0
readback_rd_A	729279559	1957	0	0
readback_regwen_rd_A	729279559	1632	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729279559	112517	0	0
T7	118714	0	0	0
T26	99795	3794	0	0
T28	0	3890	0	0
T29	0	3993	0	0
T49	234114	0	0	0
T51	59577	0	0	0
T56	0	1695	0	0
T57	0	1835	0	0
T58	0	2711	0	0
T59	0	1859	0	0
T60	0	4317	0	0
T61	0	5848	0	0
T62	0	1734	0	0
T63	44581	0	0	0
T64	397284	0	0	0
T65	541653	0	0	0
T66	179867	0	0	0
T67	77286	0	0	0
T68	75374	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729279559	2664	0	0
T7	118714	0	0	0
T26	99795	337	0	0
T49	234114	0	0	0
T51	59577	0	0	0
T52	0	3	0	0
T56	0	75	0	0
T63	44581	0	0	0
T64	397284	0	0	0
T65	541653	0	0	0
T66	179867	0	0	0
T67	77286	0	0	0
T68	75374	0	0	0
T108	0	45	0	0
T117	0	270	0	0
T118	0	216	0	0
T119	0	237	0	0
T120	0	333	0	0
T121	0	213	0	0
T122	0	61	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729279559	2397	0	0
T7	118714	0	0	0
T26	99795	280	0	0
T49	234114	0	0	0
T51	59577	0	0	0
T52	0	5	0	0
T56	0	48	0	0
T63	44581	0	0	0
T64	397284	0	0	0
T65	541653	0	0	0
T66	179867	0	0	0
T67	77286	0	0	0
T68	75374	0	0	0
T108	0	40	0	0
T117	0	220	0	0
T118	0	178	0	0
T119	0	179	0	0
T120	0	279	0	0
T121	0	217	0	0
T122	0	94	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729279559	2852	0	0
T7	118714	0	0	0
T26	99795	354	0	0
T49	234114	0	0	0
T51	59577	0	0	0
T52	0	26	0	0
T56	0	53	0	0
T63	44581	0	0	0
T64	397284	0	0	0
T65	541653	0	0	0
T66	179867	0	0	0
T67	77286	0	0	0
T68	75374	0	0	0
T108	0	26	0	0
T117	0	283	0	0
T118	0	173	0	0
T119	0	256	0	0
T120	0	380	0	0
T121	0	283	0	0
T122	0	155	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729279559	1957	0	0
T7	118714	0	0	0
T26	99795	250	0	0
T49	234114	0	0	0
T51	59577	0	0	0
T56	0	92	0	0
T63	44581	0	0	0
T64	397284	0	0	0
T65	541653	0	0	0
T66	179867	0	0	0
T67	77286	0	0	0
T68	75374	0	0	0
T117	0	212	0	0
T118	0	146	0	0
T119	0	214	0	0
T120	0	412	0	0
T121	0	182	0	0
T122	0	163	0	0
T123	0	77	0	0
T124	0	5	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729279559	1632	0	0
T7	118714	0	0	0
T26	99795	238	0	0
T49	234114	0	0	0
T51	59577	0	0	0
T56	0	56	0	0
T63	44581	0	0	0
T64	397284	0	0	0
T65	541653	0	0	0
T66	179867	0	0	0
T67	77286	0	0	0
T68	75374	0	0	0
T117	0	209	0	0
T118	0	116	0	0
T119	0	197	0	0
T120	0	291	0	0
T121	0	175	0	0
T122	0	82	0	0
T123	0	47	0	0
T124	0	17	0	0