Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15771755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

166480538

1

T1

209735

T2

1109

T3

721

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89739134	1			T1	115931		T2	633		T3	1992
values[0x0]	44695890	1			T1	55472		T2	325		T3	699
values[0x1]	47817269	1			T1	59578		T2	364		T3	1388

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8047098	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

174205195

1

T1

220398

T2

1207

T3

2395

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	595717	1			T1	905		T2	1		T3	7
valid_sources[0x01]	665896	1			T1	771		T2	13		T3	35
valid_sources[0x02]	640147	1			T1	1068		T2	7		T3	22
valid_sources[0x03]	649150	1			T1	1337		T2	7		T3	5
valid_sources[0x04]	660590	1			T1	987		T2	13		T3	6
valid_sources[0x05]	607639	1			T1	921		T2	5		T3	6
valid_sources[0x06]	594231	1			T1	997		T2	13		T8	40
valid_sources[0x07]	632378	1			T1	1201		T2	8		T3	39
valid_sources[0x08]	658863	1			T1	831		T2	7		T3	17
valid_sources[0x09]	598687	1			T1	1122		T2	4		T8	45
valid_sources[0x0a]	2775673	1			T1	741		T2	1		T3	4
valid_sources[0x0b]	629955	1			T1	645		T2	1		T3	32
valid_sources[0x0c]	624075	1			T1	970		T2	5		T3	24
valid_sources[0x0d]	629373	1			T1	784		T2	10		T3	29
valid_sources[0x0e]	619926	1			T1	856		T2	4		T3	8
valid_sources[0x0f]	637195	1			T1	802		T2	3		T3	7
valid_sources[0x10]	621329	1			T1	996		T2	1		T3	26
valid_sources[0x11]	588495	1			T1	866		T2	3		T3	37
valid_sources[0x12]	2051829	1			T1	1171		T2	10		T3	4
valid_sources[0x13]	655539	1			T1	815		T2	1		T3	19
valid_sources[0x14]	2142430	1			T1	893		T2	3		T8	30
valid_sources[0x15]	591569	1			T1	947		T2	4		T3	23
valid_sources[0x16]	608651	1			T1	860		T2	3		T3	23
valid_sources[0x17]	641922	1			T1	1103		T2	2		T3	24
valid_sources[0x18]	707731	1			T1	882		T2	1		T3	66
valid_sources[0x19]	1456580	1			T1	1173		T2	2		T3	15
valid_sources[0x1a]	601178	1			T1	970		T2	11		T3	11
valid_sources[0x1b]	600376	1			T1	860		T2	16		T3	21
valid_sources[0x1c]	612163	1			T1	1126		T2	3		T3	16
valid_sources[0x1d]	652799	1			T1	1031		T2	11		T3	25
valid_sources[0x1e]	593033	1			T1	778		T2	2		T3	15
valid_sources[0x1f]	656889	1			T1	950		T3	7		T8	41
valid_sources[0x20]	632557	1			T1	941		T2	9		T3	14
valid_sources[0x21]	772285	1			T1	911		T2	4		T3	8
valid_sources[0x22]	658342	1			T1	768		T2	4		T8	39
valid_sources[0x23]	589661	1			T1	938		T2	2		T3	10
valid_sources[0x24]	614600	1			T1	1184		T2	8		T3	27
valid_sources[0x25]	607861	1			T1	1004		T2	10		T3	7
valid_sources[0x26]	643678	1			T1	818		T2	1		T8	25
valid_sources[0x27]	597332	1			T1	855		T3	12		T8	37
valid_sources[0x28]	588978	1			T1	912		T3	8		T8	16
valid_sources[0x29]	628381	1			T1	806		T2	1		T3	25
valid_sources[0x2a]	599026	1			T1	932		T2	3		T3	28
valid_sources[0x2b]	623984	1			T1	771		T2	4		T3	19
valid_sources[0x2c]	602246	1			T1	796		T3	5		T8	26
valid_sources[0x2d]	598249	1			T1	802		T3	14		T8	21
valid_sources[0x2e]	603417	1			T1	776		T2	13		T3	8
valid_sources[0x2f]	621585	1			T1	862		T2	3		T3	4
valid_sources[0x30]	639965	1			T1	1113		T2	2		T3	4
valid_sources[0x31]	616682	1			T1	886		T2	6		T3	45
valid_sources[0x32]	608022	1			T1	899		T2	2		T3	10
valid_sources[0x33]	597572	1			T1	1071		T2	9		T3	4
valid_sources[0x34]	609103	1			T1	897		T2	3		T3	7
valid_sources[0x35]	602015	1			T1	871		T3	44		T8	31
valid_sources[0x36]	617507	1			T1	996		T2	12		T8	24
valid_sources[0x37]	628399	1			T1	683		T2	8		T3	55
valid_sources[0x38]	614733	1			T1	687		T2	7		T8	30
valid_sources[0x39]	638288	1			T1	856		T2	8		T3	14
valid_sources[0x3a]	596677	1			T1	950		T2	6		T3	23
valid_sources[0x3b]	671355	1			T1	688		T2	2		T3	14
valid_sources[0x3c]	625885	1			T1	841		T2	7		T3	12
valid_sources[0x3d]	1936796	1			T1	712		T2	3		T3	44
valid_sources[0x3e]	803047	1			T1	807		T3	40		T8	18
valid_sources[0x3f]	610790	1			T1	690		T2	11		T3	35
valid_sources[0x40]	588399	1			T1	899		T2	4		T3	17
valid_sources[0x41]	607761	1			T1	735		T2	6		T3	11
valid_sources[0x42]	625198	1			T1	971		T2	14		T3	9
valid_sources[0x43]	805227	1			T1	1043		T2	15		T3	1
valid_sources[0x44]	612954	1			T1	640		T2	1		T3	11
valid_sources[0x45]	598135	1			T1	913		T2	11		T3	3
valid_sources[0x46]	651546	1			T1	938		T2	4		T3	59
valid_sources[0x47]	639197	1			T1	898		T2	6		T3	14
valid_sources[0x48]	1835746	1			T1	1006		T2	7		T3	48
valid_sources[0x49]	590903	1			T1	835		T2	4		T3	2
valid_sources[0x4a]	594839	1			T1	816		T2	3		T3	10
valid_sources[0x4b]	590665	1			T1	781		T2	6		T3	9
valid_sources[0x4c]	625154	1			T1	764		T2	2		T3	12
valid_sources[0x4d]	613142	1			T1	1042		T2	6		T3	5
valid_sources[0x4e]	603655	1			T1	955		T2	1		T3	23
valid_sources[0x4f]	602229	1			T1	686		T2	1		T3	11
valid_sources[0x50]	630034	1			T1	791		T2	1		T3	25
valid_sources[0x51]	692369	1			T1	839		T2	9		T3	19
valid_sources[0x52]	593021	1			T1	902		T3	5		T8	22
valid_sources[0x53]	624751	1			T1	990		T2	7		T3	3
valid_sources[0x54]	819656	1			T1	786		T2	7		T3	7
valid_sources[0x55]	599437	1			T1	1035		T2	4		T8	38
valid_sources[0x56]	646651	1			T1	897		T2	5		T3	9
valid_sources[0x57]	663262	1			T1	726		T3	12		T8	35
valid_sources[0x58]	586526	1			T1	843		T2	3		T3	32
valid_sources[0x59]	591853	1			T1	895		T3	19		T8	33
valid_sources[0x5a]	680360	1			T1	934		T2	2		T3	11
valid_sources[0x5b]	652529	1			T1	1007		T2	15		T3	2
valid_sources[0x5c]	687151	1			T1	1072		T2	6		T3	3
valid_sources[0x5d]	1452160	1			T1	703		T2	13		T3	36
valid_sources[0x5e]	597110	1			T1	802		T2	9		T3	25
valid_sources[0x5f]	604613	1			T1	881		T2	5		T3	1
valid_sources[0x60]	655436	1			T1	715		T2	10		T3	24
valid_sources[0x61]	632503	1			T1	792		T2	14		T3	3
valid_sources[0x62]	591256	1			T1	799		T3	4		T8	40
valid_sources[0x63]	608424	1			T1	952		T2	18		T3	7
valid_sources[0x64]	620537	1			T1	963		T3	12		T8	26
valid_sources[0x65]	666509	1			T1	838		T2	6		T3	4
valid_sources[0x66]	612848	1			T1	1008		T2	3		T3	9
valid_sources[0x67]	666967	1			T1	907		T2	7		T3	21
valid_sources[0x68]	612415	1			T1	688		T2	6		T3	19
valid_sources[0x69]	587077	1			T1	821		T2	5		T3	38
valid_sources[0x6a]	615166	1			T1	1223		T2	6		T3	23
valid_sources[0x6b]	596513	1			T1	968		T2	1		T3	8
valid_sources[0x6c]	629531	1			T1	979		T2	14		T3	3
valid_sources[0x6d]	613155	1			T1	686		T2	10		T3	1
valid_sources[0x6e]	619576	1			T1	847		T2	2		T3	14
valid_sources[0x6f]	603011	1			T1	1018		T2	4		T3	18
valid_sources[0x70]	592454	1			T1	1039		T2	3		T3	16
valid_sources[0x71]	827669	1			T1	1024		T2	1		T3	39
valid_sources[0x72]	584521	1			T1	810		T2	10		T3	7
valid_sources[0x73]	609199	1			T1	682		T2	7		T3	28
valid_sources[0x74]	596705	1			T1	835		T2	13		T3	11
valid_sources[0x75]	618058	1			T1	932		T2	8		T3	5
valid_sources[0x76]	686758	1			T1	1114		T2	2		T3	37
valid_sources[0x77]	624943	1			T1	840		T3	2		T8	25
valid_sources[0x78]	649483	1			T1	945		T2	4		T3	34
valid_sources[0x79]	623099	1			T1	856		T2	5		T3	10
valid_sources[0x7a]	625917	1			T1	1146		T2	9		T3	28
valid_sources[0x7b]	600862	1			T1	1176		T3	26		T8	41
valid_sources[0x7c]	605413	1			T1	981		T2	1		T3	2
valid_sources[0x7d]	618509	1			T1	838		T2	6		T3	5
valid_sources[0x7e]	643873	1			T1	796		T3	1		T8	17
valid_sources[0x7f]	588358	1			T1	894		T2	7		T3	23
valid_sources[0x80]	649806	1			T1	947		T2	5		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81806428

1

T1

105325

T2

550

T3

372

values[0x0]

all_enables

biggest_size

42344256

1

T1

52339

T2

287

T3

169

values[0x1]

all_enables

biggest_size

42329854

1

T1

52071

T2

272

T3

180

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148842

1

T1

1

T4

6

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53456	1			T5	25		T6	27		T15	8
values[0x0]	68066	1			T1	3		T3	1		T8	2
values[0x1]	73091	1			T1	1		T2	2		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158827

1

T1

1

T4

6

T9

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	619	1			T13	2		T16	18		T20	5
valid_sources[0x01]	969	1			T6	1		T7	11		T16	31
valid_sources[0x02]	862	1			T13	1		T39	4		T16	22
valid_sources[0x03]	546	1			T13	2		T5	1		T6	1
valid_sources[0x04]	626	1			T6	1		T16	29		T20	7
valid_sources[0x05]	1022	1			T6	1		T7	1		T39	6
valid_sources[0x06]	1377	1			T13	2		T5	1		T39	5
valid_sources[0x07]	736	1			T19	1		T5	2		T7	4
valid_sources[0x08]	592	1			T13	5		T16	17		T17	1
valid_sources[0x09]	589	1			T28	1		T6	2		T15	1
valid_sources[0x0a]	656	1			T6	3		T30	1		T130	12
valid_sources[0x0b]	541	1			T15	1		T39	5		T16	20
valid_sources[0x0c]	975	1			T8	2		T13	1		T16	23
valid_sources[0x0d]	694	1			T1	4		T6	1		T141	1
valid_sources[0x0e]	681	1			T13	4		T5	1		T7	1
valid_sources[0x0f]	995	1			T13	1		T15	1		T7	10
valid_sources[0x10]	850	1			T13	5		T51	1		T7	3
valid_sources[0x11]	1095	1			T6	1		T30	1		T39	10
valid_sources[0x12]	658	1			T28	1		T6	1		T16	27
valid_sources[0x13]	682	1			T13	4		T5	1		T6	2
valid_sources[0x14]	909	1			T13	3		T5	2		T16	22
valid_sources[0x15]	769	1			T16	25		T20	2		T17	1
valid_sources[0x16]	617	1			T4	1		T12	22		T13	2
valid_sources[0x17]	680	1			T28	2		T16	27		T20	11
valid_sources[0x18]	522	1			T13	4		T7	3		T16	26
valid_sources[0x19]	821	1			T5	1		T28	1		T6	1
valid_sources[0x1a]	599	1			T13	3		T27	2		T7	1
valid_sources[0x1b]	895	1			T19	6		T6	2		T16	17
valid_sources[0x1c]	559	1			T48	6		T6	2		T16	24
valid_sources[0x1d]	731	1			T6	2		T49	1		T16	19
valid_sources[0x1e]	652	1			T13	4		T5	1		T15	1
valid_sources[0x1f]	988	1			T13	1		T16	20		T68	1
valid_sources[0x20]	658	1			T5	1		T51	1		T39	4
valid_sources[0x21]	453	1			T7	1		T16	11		T20	5
valid_sources[0x22]	796	1			T30	2		T16	40		T20	5
valid_sources[0x23]	827	1			T13	3		T51	1		T16	26
valid_sources[0x24]	885	1			T19	1		T51	1		T16	18
valid_sources[0x25]	509	1			T13	1		T16	24		T20	9
valid_sources[0x26]	597	1			T13	5		T141	1		T16	20
valid_sources[0x27]	748	1			T16	18		T20	4		T57	2
valid_sources[0x28]	812	1			T6	2		T16	24		T20	1
valid_sources[0x29]	767	1			T13	1		T6	1		T16	23
valid_sources[0x2a]	698	1			T13	5		T49	2		T7	2
valid_sources[0x2b]	695	1			T16	10		T98	1		T44	7
valid_sources[0x2c]	796	1			T16	24		T64	1		T20	5
valid_sources[0x2d]	846	1			T5	1		T6	1		T7	1
valid_sources[0x2e]	664	1			T13	2		T28	1		T16	19
valid_sources[0x2f]	600	1			T13	1		T6	1		T16	21
valid_sources[0x30]	564	1			T13	1		T19	1		T16	29
valid_sources[0x31]	590	1			T15	1		T7	2		T16	20
valid_sources[0x32]	720	1			T30	2		T16	24		T67	1
valid_sources[0x33]	554	1			T13	3		T49	1		T16	25
valid_sources[0x34]	913	1			T13	3		T5	1		T6	1
valid_sources[0x35]	474	1			T4	1		T6	2		T39	8
valid_sources[0x36]	974	1			T13	2		T6	1		T52	25
valid_sources[0x37]	747	1			T39	6		T16	20		T20	1
valid_sources[0x38]	713	1			T13	1		T142	1		T7	3
valid_sources[0x39]	600	1			T13	2		T16	22		T20	23
valid_sources[0x3a]	781	1			T13	2		T29	13		T16	29
valid_sources[0x3b]	949	1			T16	24		T20	12		T35	1
valid_sources[0x3c]	913	1			T13	7		T28	1		T6	3
valid_sources[0x3d]	679	1			T13	3		T15	1		T49	1
valid_sources[0x3e]	766	1			T22	26		T6	1		T16	33
valid_sources[0x3f]	751	1			T16	23		T65	18		T35	2
valid_sources[0x40]	675	1			T13	1		T6	1		T16	31
valid_sources[0x41]	467	1			T13	1		T16	21		T20	1
valid_sources[0x42]	718	1			T5	1		T15	1		T7	5
valid_sources[0x43]	580	1			T13	1		T5	1		T6	1
valid_sources[0x44]	632	1			T6	1		T49	1		T16	28
valid_sources[0x45]	951	1			T28	1		T51	1		T143	1
valid_sources[0x46]	748	1			T13	1		T51	1		T7	1
valid_sources[0x47]	851	1			T29	9		T16	19		T20	11
valid_sources[0x48]	898	1			T5	1		T7	10		T16	29
valid_sources[0x49]	929	1			T13	2		T15	2		T16	18
valid_sources[0x4a]	768	1			T6	1		T15	1		T16	29
valid_sources[0x4b]	1034	1			T13	1		T19	4		T15	1
valid_sources[0x4c]	1008	1			T16	22		T20	19		T144	1
valid_sources[0x4d]	1049	1			T4	1		T6	1		T16	16
valid_sources[0x4e]	715	1			T5	1		T6	1		T16	29
valid_sources[0x4f]	664	1			T16	26		T20	10		T17	2
valid_sources[0x50]	611	1			T2	1		T15	1		T16	21
valid_sources[0x51]	593	1			T16	16		T20	10		T44	3
valid_sources[0x52]	1036	1			T3	1		T13	2		T6	1
valid_sources[0x53]	785	1			T7	5		T16	20		T20	6
valid_sources[0x54]	839	1			T13	1		T28	5		T6	1
valid_sources[0x55]	514	1			T13	2		T6	1		T49	1
valid_sources[0x56]	605	1			T16	27		T20	9		T35	8
valid_sources[0x57]	773	1			T130	1		T16	11		T20	1
valid_sources[0x58]	771	1			T6	1		T7	4		T16	21
valid_sources[0x59]	562	1			T5	1		T23	1		T51	1
valid_sources[0x5a]	908	1			T16	27		T20	4		T17	1
valid_sources[0x5b]	664	1			T13	5		T16	24		T20	43
valid_sources[0x5c]	487	1			T16	15		T20	3		T112	1
valid_sources[0x5d]	1281	1			T13	2		T58	6		T6	2
valid_sources[0x5e]	742	1			T26	1		T16	34		T44	9
valid_sources[0x5f]	918	1			T13	3		T6	1		T49	1
valid_sources[0x60]	1126	1			T6	1		T39	3		T16	20
valid_sources[0x61]	931	1			T15	1		T39	8		T16	27
valid_sources[0x62]	818	1			T16	23		T20	6		T44	9
valid_sources[0x63]	952	1			T15	1		T130	1		T7	5
valid_sources[0x64]	1261	1			T39	1		T16	29		T20	8
valid_sources[0x65]	937	1			T13	1		T16	28		T20	6
valid_sources[0x66]	571	1			T13	1		T16	14		T17	1
valid_sources[0x67]	846	1			T13	8		T30	2		T7	2
valid_sources[0x68]	1172	1			T13	1		T6	1		T16	25
valid_sources[0x69]	1146	1			T4	1		T6	1		T16	16
valid_sources[0x6a]	798	1			T13	1		T5	1		T28	3
valid_sources[0x6b]	560	1			T13	1		T19	2		T5	1
valid_sources[0x6c]	772	1			T24	1		T15	1		T16	24
valid_sources[0x6d]	693	1			T4	3		T95	1		T49	1
valid_sources[0x6e]	652	1			T5	2		T16	30		T20	14
valid_sources[0x6f]	714	1			T6	1		T16	30		T18	2
valid_sources[0x70]	883	1			T4	1		T16	24		T20	4
valid_sources[0x71]	800	1			T13	7		T6	1		T15	1
valid_sources[0x72]	709	1			T9	1		T13	7		T15	1
valid_sources[0x73]	957	1			T13	4		T39	16		T16	25
valid_sources[0x74]	583	1			T19	8		T7	1		T16	9
valid_sources[0x75]	673	1			T16	23		T20	1		T17	2
valid_sources[0x76]	756	1			T15	1		T7	7		T16	26
valid_sources[0x77]	780	1			T16	19		T20	5		T35	14
valid_sources[0x78]	676	1			T6	1		T16	31		T67	1
valid_sources[0x79]	776	1			T15	1		T16	20		T20	6
valid_sources[0x7a]	703	1			T16	16		T20	1		T144	2
valid_sources[0x7b]	634	1			T5	2		T6	1		T16	18
valid_sources[0x7c]	548	1			T16	29		T17	2		T44	10
valid_sources[0x7d]	738	1			T13	3		T19	3		T16	29
valid_sources[0x7e]	675	1			T13	2		T6	1		T7	7
valid_sources[0x7f]	806	1			T16	29		T17	1		T21	101
valid_sources[0x80]	560	1			T13	1		T5	1		T16	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40067

1

T5

12

T6

16

T15

4

values[0x0]

all_enables

biggest_size

55583

1

T1

1

T4

4

T12

5

values[0x1]

all_enables

biggest_size

53192

1

T4

2

T10

1

T12

1