Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15659931

1

T1

21246

T2

213

T3

3358

full_word

163370198

1

T1

209735

T2

1109

T3

721

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	179029819	1			T1	230981		T2	1322		T3	4079
auto[TlIntgErrCmd]	116	1			T45	4		T46	6		T47	4
auto[TlIntgErrData]	82	1			T46	1		T47	1		T115	7
auto[TlIntgErrBoth]	112	1			T45	6		T46	3		T47	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86454907

1

T1

115931

T2

633

T3

1992

auto[1]

92575222

1

T1

115050

T2

689

T3

2087

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7671067	1			T1	10606		T2	83		T3	1620
auto[TlIntgErrNone]	partial	auto[1]	7988578	1			T1	10640		T2	130		T3	1738
auto[TlIntgErrNone]	full_word	auto[0]	78783719	1			T1	105325		T2	550		T3	372
auto[TlIntgErrNone]	full_word	auto[1]	84586455	1			T1	104410		T2	559		T3	349
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T45	2		T46	3		T47	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T45	2		T46	3		T47	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T47	1		T115	1		T121	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T115	1		T121	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	31	1			T115	5		T121	3		T118	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T46	1		T47	1		T115	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T121	1		T125	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T118	1		T124	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T45	2		T46	1		T47	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T45	3		T46	2		T47	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T126	1		T125	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T45	1		T127	1		T122	1