Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	692193	1			T3	510		T22	558		T27	9
auto[1]	10202437	1			T1	97272		T2	633		T3	469
auto[2]	553495	1			T3	400		T5	1		T22	320
auto[3]	9991618	1			T1	96692		T2	688		T3	289

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13215493	1			T1	159748		T2	907		T3	49
auto[1]	2051544	1			T1	16488		T2	201		T3	232
auto[2]	2066305	1			T1	16086		T2	170		T3	176
auto[3]	4106401	1			T1	1642		T2	43		T3	1211

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8048670

1

T1

25

T2

1321

T3

1668

auto[1]

13391073

1

T1

193939

T11

1

T28

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	369306	1			T3	20		T22	460		T27	6
auto[0]	auto[0]	auto[1]	37932	1			T3	81		T22	48		T27	2
auto[0]	auto[0]	auto[2]	38020	1			T3	62		T22	45		T27	1
auto[0]	auto[0]	auto[3]	41916	1			T3	347		T22	5		T15	46
auto[0]	auto[1]	auto[0]	2754057	1			T1	12		T2	451		T3	4
auto[0]	auto[1]	auto[1]	299123	1			T2	99		T3	76		T4	44
auto[0]	auto[1]	auto[2]	298256	1			T1	1		T2	68		T3	7
auto[0]	auto[1]	auto[3]	333157	1			T2	15		T3	382		T4	5
auto[0]	auto[2]	auto[0]	284439	1			T3	24		T5	1		T22	255
auto[0]	auto[2]	auto[1]	31568	1			T3	68		T22	29		T27	1
auto[0]	auto[2]	auto[2]	26968	1			T3	59		T22	33		T27	1
auto[0]	auto[2]	auto[3]	33948	1			T3	249		T22	3		T15	34
auto[0]	auto[3]	auto[0]	2608044	1			T1	12		T2	456		T3	1
auto[0]	auto[3]	auto[1]	280946	1			T2	102		T3	7		T4	11
auto[0]	auto[3]	auto[2]	303913	1			T2	102		T3	48		T4	25
auto[0]	auto[3]	auto[3]	307077	1			T2	28		T3	233		T4	2
auto[1]	auto[0]	auto[0]	6801	1			T133	483		T136	1		T135	948
auto[1]	auto[0]	auto[1]	30615	1			T133	2329		T135	4066		T137	4057
auto[1]	auto[0]	auto[2]	30563	1			T133	2263		T138	1		T134	1
auto[1]	auto[0]	auto[3]	137040	1			T139	2		T133	10277		T134	2
auto[1]	auto[1]	auto[0]	3593772	1			T1	80146		T48	4218		T95	1980
auto[1]	auto[1]	auto[1]	680423	1			T1	8311		T48	16740		T95	7904
auto[1]	auto[1]	auto[2]	666863	1			T1	7961		T11	1		T48	18682
auto[1]	auto[1]	auto[3]	1576786	1			T1	841		T48	75623		T95	35620
auto[1]	auto[2]	auto[0]	6097	1			T72	2		T133	307		T140	1
auto[1]	auto[2]	auto[1]	27419	1			T133	1377		T135	3760		T137	3710
auto[1]	auto[2]	auto[2]	26084	1			T133	2231		T135	3499		T137	3492
auto[1]	auto[2]	auto[3]	116972	1			T133	9804		T135	15227		T137	15746
auto[1]	auto[3]	auto[0]	3592977	1			T1	79578		T28	2		T48	4169
auto[1]	auto[3]	auto[1]	663518	1			T1	8177		T48	18741		T30	1
auto[1]	auto[3]	auto[2]	675638	1			T1	8124		T48	16961		T95	7916
auto[1]	auto[3]	auto[3]	1559505	1			T1	801		T48	75491		T95	35250