Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.25	100.00	81.82	100.00		100.00	44.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1258616184	202977	0	0
ctrl_regwen_rd_A	1258616184	6532	0	0
exec_rd_A	1258616184	6111	0	0
exec_regwen_rd_A	1258616184	6571	0	0
readback_rd_A	1258616184	4036	0	0
readback_regwen_rd_A	1258616184	3714	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258616184	202977	0	0
T16	192202	9423	0	0
T18	620595	0	0	0
T20	0	3499	0	0
T21	0	1394	0	0
T42	0	8963	0	0
T44	0	2671	0	0
T59	0	1669	0	0
T60	0	3772	0	0
T61	0	1664	0	0
T62	0	2848	0	0
T63	0	1835	0	0
T64	81099	0	0	0
T65	798409	0	0	0
T66	68661	0	0	0
T67	291910	0	0	0
T68	353203	0	0	0
T69	159375	0	0	0
T70	74183	0	0	0
T71	76620	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258616184	6532	0	0
T21	24825	84	0	0
T31	0	492	0	0
T36	206994	0	0	0
T37	243941	0	0	0
T42	0	598	0	0
T44	0	267	0	0
T98	326461	0	0	0
T99	120990	0	0	0
T103	0	152	0	0
T104	0	298	0	0
T105	0	104	0	0
T106	0	191	0	0
T107	0	216	0	0
T108	0	280	0	0
T109	33864	0	0	0
T110	34929	0	0	0
T111	128720	0	0	0
T112	263239	0	0	0
T113	69073	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258616184	6111	0	0
T21	24825	54	0	0
T31	0	427	0	0
T36	206994	0	0	0
T37	243941	0	0	0
T42	0	480	0	0
T44	0	214	0	0
T98	326461	0	0	0
T99	120990	0	0	0
T103	0	140	0	0
T104	0	262	0	0
T105	0	110	0	0
T106	0	178	0	0
T107	0	161	0	0
T108	0	231	0	0
T109	33864	0	0	0
T110	34929	0	0	0
T111	128720	0	0	0
T112	263239	0	0	0
T113	69073	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258616184	6571	0	0
T21	24825	51	0	0
T31	0	462	0	0
T36	206994	0	0	0
T37	243941	0	0	0
T42	0	661	0	0
T44	0	243	0	0
T98	326461	0	0	0
T99	120990	0	0	0
T103	0	122	0	0
T104	0	274	0	0
T105	0	119	0	0
T106	0	150	0	0
T107	0	172	0	0
T108	0	297	0	0
T109	33864	0	0	0
T110	34929	0	0	0
T111	128720	0	0	0
T112	263239	0	0	0
T113	69073	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258616184	4036	0	0
T21	24825	53	0	0
T31	0	337	0	0
T36	206994	0	0	0
T37	243941	0	0	0
T42	0	623	0	0
T44	0	156	0	0
T98	326461	0	0	0
T99	120990	0	0	0
T103	0	84	0	0
T104	0	280	0	0
T105	0	136	0	0
T106	0	125	0	0
T107	0	152	0	0
T108	0	264	0	0
T109	33864	0	0	0
T110	34929	0	0	0
T111	128720	0	0	0
T112	263239	0	0	0
T113	69073	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258616184	3714	0	0
T21	24825	78	0	0
T31	0	304	0	0
T36	206994	0	0	0
T37	243941	0	0	0
T42	0	520	0	0
T44	0	212	0	0
T98	326461	0	0	0
T99	120990	0	0	0
T103	0	99	0	0
T104	0	233	0	0
T105	0	163	0	0
T106	0	126	0	0
T107	0	101	0	0
T108	0	214	0	0
T109	33864	0	0	0
T110	34929	0	0	0
T111	128720	0	0	0
T112	263239	0	0	0
T113	69073	0	0	0