Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16703180	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

164368587

1

T1

17201

T2

149583

T3

176914

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89196952	1			T1	7875		T2	81991		T3	97279
values[0x0]	44276603	1			T1	5185		T2	39760		T3	46685
values[0x1]	47598212	1			T1	5387		T2	42628		T3	50755

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8493955	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172577812

1

T1

17837

T2

156973

T3

185897

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2090217	1			T1	56		T2	629		T8	1
valid_sources[0x01]	564094	1			T1	103		T2	569		T8	2
valid_sources[0x02]	568538	1			T1	84		T2	705		T8	18
valid_sources[0x03]	574418	1			T1	57		T2	592		T8	11
valid_sources[0x04]	586730	1			T1	81		T2	634		T8	8
valid_sources[0x05]	579795	1			T1	67		T2	661		T8	9
valid_sources[0x06]	587806	1			T1	47		T2	576		T8	5
valid_sources[0x07]	566566	1			T1	113		T2	617		T8	10
valid_sources[0x08]	579858	1			T1	82		T2	646		T8	5
valid_sources[0x09]	625396	1			T1	103		T2	739		T8	5
valid_sources[0x0a]	594068	1			T1	63		T2	611		T8	10
valid_sources[0x0b]	616812	1			T1	102		T2	685		T8	2
valid_sources[0x0c]	609006	1			T1	112		T2	537		T8	8
valid_sources[0x0d]	592733	1			T1	77		T2	676		T8	2
valid_sources[0x0e]	643300	1			T1	96		T2	599		T8	5
valid_sources[0x0f]	567092	1			T1	114		T2	658		T8	2
valid_sources[0x10]	577131	1			T1	133		T2	640		T8	6
valid_sources[0x11]	591494	1			T1	77		T2	682		T8	7
valid_sources[0x12]	605995	1			T1	62		T2	661		T8	3
valid_sources[0x13]	574299	1			T1	93		T2	595		T8	8
valid_sources[0x14]	592577	1			T1	71		T2	636		T8	4
valid_sources[0x15]	584428	1			T1	131		T2	571		T8	4
valid_sources[0x16]	571000	1			T1	95		T2	648		T8	7
valid_sources[0x17]	585003	1			T1	52		T2	715		T8	7
valid_sources[0x18]	1885014	1			T1	54		T2	670		T8	7
valid_sources[0x19]	594556	1			T1	52		T2	658		T8	2
valid_sources[0x1a]	590723	1			T1	40		T2	707		T8	5
valid_sources[0x1b]	599161	1			T1	102		T2	599		T8	8
valid_sources[0x1c]	566664	1			T1	88		T2	562		T8	6
valid_sources[0x1d]	673219	1			T1	55		T2	622		T8	10
valid_sources[0x1e]	564802	1			T1	103		T2	565		T8	13
valid_sources[0x1f]	620329	1			T1	76		T2	646		T8	12
valid_sources[0x20]	584451	1			T1	103		T2	594		T8	4
valid_sources[0x21]	1727844	1			T1	56		T2	604		T8	11
valid_sources[0x22]	581886	1			T1	81		T2	669		T8	9
valid_sources[0x23]	574074	1			T1	95		T2	718		T8	6
valid_sources[0x24]	580122	1			T1	62		T2	643		T8	7
valid_sources[0x25]	639703	1			T1	53		T2	625		T8	4
valid_sources[0x26]	605240	1			T1	87		T2	657		T8	3
valid_sources[0x27]	606104	1			T1	37		T2	726		T8	3
valid_sources[0x28]	599970	1			T1	57		T2	645		T8	5
valid_sources[0x29]	579244	1			T1	63		T2	724		T3	4403
valid_sources[0x2a]	582805	1			T1	71		T2	684		T8	5
valid_sources[0x2b]	638685	1			T1	113		T2	717		T8	9
valid_sources[0x2c]	594226	1			T1	96		T2	625		T8	5
valid_sources[0x2d]	569927	1			T1	101		T2	716		T8	5
valid_sources[0x2e]	627538	1			T1	58		T2	618		T8	5
valid_sources[0x2f]	578554	1			T1	52		T2	611		T8	4
valid_sources[0x30]	563440	1			T1	93		T2	655		T8	11
valid_sources[0x31]	639992	1			T1	60		T2	633		T8	12
valid_sources[0x32]	581979	1			T1	60		T2	613		T8	9
valid_sources[0x33]	650728	1			T1	60		T2	594		T8	7
valid_sources[0x34]	580772	1			T1	35		T2	576		T8	6
valid_sources[0x35]	613288	1			T1	106		T2	639		T8	7
valid_sources[0x36]	565640	1			T1	54		T2	656		T8	3
valid_sources[0x37]	578398	1			T1	108		T2	594		T8	8
valid_sources[0x38]	587620	1			T1	72		T2	675		T8	4
valid_sources[0x39]	659356	1			T1	47		T2	747		T8	6
valid_sources[0x3a]	611693	1			T1	53		T2	738		T8	8
valid_sources[0x3b]	565291	1			T1	85		T2	544		T8	2
valid_sources[0x3c]	608476	1			T1	98		T2	705		T8	8
valid_sources[0x3d]	620756	1			T1	66		T2	607		T8	7
valid_sources[0x3e]	619366	1			T1	109		T2	695		T8	6
valid_sources[0x3f]	598663	1			T1	52		T2	611		T8	10
valid_sources[0x40]	591885	1			T1	105		T2	567		T8	13
valid_sources[0x41]	606364	1			T1	65		T2	704		T8	3
valid_sources[0x42]	667168	1			T1	79		T2	663		T3	17909
valid_sources[0x43]	585120	1			T1	118		T2	686		T8	9
valid_sources[0x44]	597013	1			T1	56		T2	646		T8	2
valid_sources[0x45]	628610	1			T1	32		T2	683		T8	1
valid_sources[0x46]	603258	1			T1	46		T2	684		T8	4
valid_sources[0x47]	598589	1			T1	114		T2	626		T8	4
valid_sources[0x48]	574786	1			T1	82		T2	638		T8	12
valid_sources[0x49]	1764748	1			T1	58		T2	608		T8	8
valid_sources[0x4a]	646752	1			T1	81		T2	499		T8	11
valid_sources[0x4b]	2048412	1			T1	43		T2	580		T8	2
valid_sources[0x4c]	625994	1			T1	33		T2	628		T8	8
valid_sources[0x4d]	570486	1			T1	86		T2	596		T8	4
valid_sources[0x4e]	821712	1			T1	77		T2	654		T8	8
valid_sources[0x4f]	588477	1			T1	53		T2	728		T8	4
valid_sources[0x50]	622205	1			T1	108		T2	635		T8	4
valid_sources[0x51]	699683	1			T1	41		T2	712		T3	761
valid_sources[0x52]	574206	1			T1	86		T2	708		T8	8
valid_sources[0x53]	653380	1			T1	62		T2	611		T8	6
valid_sources[0x54]	632685	1			T1	32		T2	671		T8	3
valid_sources[0x55]	1779656	1			T1	77		T2	647		T8	4
valid_sources[0x56]	582848	1			T1	39		T2	664		T8	7
valid_sources[0x57]	633612	1			T1	69		T2	570		T3	241
valid_sources[0x58]	575146	1			T1	73		T2	836		T8	4
valid_sources[0x59]	585732	1			T1	67		T2	529		T8	7
valid_sources[0x5a]	571427	1			T1	104		T2	643		T8	6
valid_sources[0x5b]	584310	1			T1	66		T2	591		T8	5
valid_sources[0x5c]	1620892	1			T1	61		T2	626		T8	4
valid_sources[0x5d]	3018475	1			T1	71		T2	593		T8	6
valid_sources[0x5e]	600685	1			T1	140		T2	640		T8	9
valid_sources[0x5f]	571446	1			T1	54		T2	703		T8	8
valid_sources[0x60]	658583	1			T1	74		T2	628		T3	44613
valid_sources[0x61]	584767	1			T1	52		T2	645		T3	10183
valid_sources[0x62]	653588	1			T1	39		T2	734		T8	7
valid_sources[0x63]	605634	1			T1	52		T2	560		T8	3
valid_sources[0x64]	598783	1			T1	65		T2	608		T8	7
valid_sources[0x65]	1949257	1			T1	95		T2	649		T8	7
valid_sources[0x66]	632261	1			T1	66		T2	611		T8	7
valid_sources[0x67]	664651	1			T1	103		T2	639		T8	7
valid_sources[0x68]	675699	1			T1	61		T2	584		T8	8
valid_sources[0x69]	614485	1			T1	60		T2	619		T8	7
valid_sources[0x6a]	606425	1			T1	65		T2	628		T8	7
valid_sources[0x6b]	602391	1			T1	70		T2	708		T8	6
valid_sources[0x6c]	563709	1			T1	51		T2	589		T8	6
valid_sources[0x6d]	666234	1			T1	53		T2	706		T8	1
valid_sources[0x6e]	582858	1			T1	53		T2	614		T8	6
valid_sources[0x6f]	581858	1			T1	52		T2	649		T8	10
valid_sources[0x70]	564910	1			T1	52		T2	566		T8	7
valid_sources[0x71]	1487006	1			T1	52		T2	562		T8	2
valid_sources[0x72]	632788	1			T1	67		T2	575		T8	7
valid_sources[0x73]	1394921	1			T1	41		T2	646		T8	4
valid_sources[0x74]	571123	1			T1	63		T2	653		T8	8
valid_sources[0x75]	619509	1			T1	49		T2	635		T3	30103
valid_sources[0x76]	570762	1			T1	73		T2	564		T8	1
valid_sources[0x77]	644417	1			T1	90		T2	675		T8	6
valid_sources[0x78]	603607	1			T1	79		T2	651		T3	736
valid_sources[0x79]	639421	1			T1	66		T2	720		T8	12
valid_sources[0x7a]	827023	1			T1	67		T2	744		T8	10
valid_sources[0x7b]	609777	1			T1	36		T2	730		T8	9
valid_sources[0x7c]	584268	1			T1	34		T2	594		T8	4
valid_sources[0x7d]	2738130	1			T1	94		T2	686		T8	7
valid_sources[0x7e]	613149	1			T1	56		T2	617		T8	11
valid_sources[0x7f]	569869	1			T1	81		T2	647		T8	6
valid_sources[0x80]	654935	1			T1	49		T2	680		T8	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80804319

1

T1

7242

T2

74735

T3

88289

values[0x0]

all_enables

biggest_size

41782253

1

T1

5018

T2

37490

T3

44073

values[0x1]

all_enables

biggest_size

41782015

1

T1

4941

T2

37358

T3

44552

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44196	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

151911

1

T1

3143

T2

20

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53508	1			T1	815		T2	11		T10	18
values[0x0]	68968	1			T1	1197		T2	17		T3	20
values[0x1]	73631	1			T1	1282		T2	27		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34322	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161785

1

T1

3226

T2

22

T3

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	839	1			T1	26		T10	3		T59	1
valid_sources[0x01]	664	1			T1	23		T3	1		T21	17
valid_sources[0x02]	729	1			T1	25		T10	1		T12	1
valid_sources[0x03]	1256	1			T1	8		T12	1		T37	1
valid_sources[0x04]	781	1			T1	18		T10	2		T59	1
valid_sources[0x05]	753	1			T1	20		T5	4		T38	1
valid_sources[0x06]	730	1			T1	19		T38	1		T21	26
valid_sources[0x07]	615	1			T1	25		T10	2		T21	18
valid_sources[0x08]	720	1			T1	15		T12	1		T38	1
valid_sources[0x09]	656	1			T1	6		T12	1		T18	2
valid_sources[0x0a]	781	1			T1	27		T38	5		T21	24
valid_sources[0x0b]	833	1			T1	3		T38	2		T102	1
valid_sources[0x0c]	589	1			T1	16		T59	1		T38	1
valid_sources[0x0d]	889	1			T1	12		T21	18		T52	1
valid_sources[0x0e]	748	1			T10	2		T38	1		T21	19
valid_sources[0x0f]	611	1			T1	29		T38	1		T21	14
valid_sources[0x10]	735	1			T41	4		T59	1		T38	1
valid_sources[0x11]	877	1			T1	24		T10	2		T38	3
valid_sources[0x12]	543	1			T3	1		T10	1		T38	3
valid_sources[0x13]	858	1			T1	5		T2	2		T38	2
valid_sources[0x14]	673	1			T1	18		T2	1		T21	26
valid_sources[0x15]	771	1			T1	21		T10	1		T59	1
valid_sources[0x16]	720	1			T1	16		T10	1		T38	1
valid_sources[0x17]	831	1			T1	14		T21	22		T52	1
valid_sources[0x18]	672	1			T1	35		T10	1		T59	2
valid_sources[0x19]	720	1			T3	1		T9	3		T10	1
valid_sources[0x1a]	549	1			T1	8		T59	1		T38	1
valid_sources[0x1b]	738	1			T3	1		T10	1		T12	1
valid_sources[0x1c]	819	1			T1	33		T3	1		T10	2
valid_sources[0x1d]	636	1			T1	4		T59	1		T5	1
valid_sources[0x1e]	882	1			T1	8		T38	2		T21	17
valid_sources[0x1f]	679	1			T1	66		T59	1		T38	3
valid_sources[0x20]	703	1			T1	6		T5	11		T38	4
valid_sources[0x21]	662	1			T1	24		T59	2		T38	3
valid_sources[0x22]	599	1			T1	1		T21	21		T52	1
valid_sources[0x23]	919	1			T1	7		T21	27		T72	1
valid_sources[0x24]	660	1			T1	2		T3	1		T13	2
valid_sources[0x25]	956	1			T1	3		T10	2		T38	3
valid_sources[0x26]	738	1			T1	1		T59	1		T21	27
valid_sources[0x27]	1156	1			T1	36		T59	4		T46	3
valid_sources[0x28]	662	1			T1	39		T37	1		T59	1
valid_sources[0x29]	762	1			T1	6		T2	1		T11	18
valid_sources[0x2a]	816	1			T1	32		T59	1		T43	140
valid_sources[0x2b]	509	1			T38	3		T21	21		T52	1
valid_sources[0x2c]	806	1			T1	5		T10	4		T21	36
valid_sources[0x2d]	770	1			T2	4		T21	20		T22	5
valid_sources[0x2e]	581	1			T1	55		T3	1		T10	1
valid_sources[0x2f]	775	1			T1	5		T59	2		T38	1
valid_sources[0x30]	585	1			T2	1		T38	2		T21	7
valid_sources[0x31]	1106	1			T38	1		T63	22		T21	26
valid_sources[0x32]	752	1			T1	8		T38	2		T21	8
valid_sources[0x33]	651	1			T38	3		T21	18		T73	1
valid_sources[0x34]	848	1			T1	1		T12	1		T59	1
valid_sources[0x35]	661	1			T1	3		T12	1		T38	3
valid_sources[0x36]	918	1			T1	11		T3	1		T38	2
valid_sources[0x37]	1165	1			T1	19		T12	1		T21	15
valid_sources[0x38]	724	1			T1	2		T3	2		T5	2
valid_sources[0x39]	910	1			T1	16		T2	4		T38	1
valid_sources[0x3a]	920	1			T1	35		T21	10		T52	1
valid_sources[0x3b]	755	1			T1	17		T10	1		T38	1
valid_sources[0x3c]	1150	1			T1	17		T2	1		T38	1
valid_sources[0x3d]	1029	1			T1	2		T38	1		T20	1
valid_sources[0x3e]	791	1			T1	26		T10	1		T38	2
valid_sources[0x3f]	764	1			T1	25		T10	1		T5	8
valid_sources[0x40]	739	1			T38	1		T20	1		T21	27
valid_sources[0x41]	1025	1			T1	14		T38	3		T21	26
valid_sources[0x42]	876	1			T1	9		T10	2		T37	1
valid_sources[0x43]	768	1			T1	35		T38	2		T21	23
valid_sources[0x44]	711	1			T1	8		T10	3		T38	2
valid_sources[0x45]	659	1			T1	65		T10	1		T38	2
valid_sources[0x46]	584	1			T10	1		T38	1		T21	4
valid_sources[0x47]	862	1			T1	1		T59	1		T38	1
valid_sources[0x48]	698	1			T1	29		T12	1		T38	2
valid_sources[0x49]	709	1			T1	9		T2	2		T3	1
valid_sources[0x4a]	1004	1			T1	1		T50	2		T38	1
valid_sources[0x4b]	831	1			T1	4		T10	1		T21	24
valid_sources[0x4c]	680	1			T1	9		T38	3		T21	30
valid_sources[0x4d]	618	1			T1	15		T38	3		T20	2
valid_sources[0x4e]	635	1			T1	2		T2	1		T3	1
valid_sources[0x4f]	1018	1			T1	22		T10	1		T38	2
valid_sources[0x50]	768	1			T1	13		T21	22		T140	6
valid_sources[0x51]	980	1			T1	4		T38	2		T20	2
valid_sources[0x52]	644	1			T1	25		T59	1		T102	1
valid_sources[0x53]	750	1			T1	10		T3	1		T59	1
valid_sources[0x54]	578	1			T1	2		T59	1		T82	1
valid_sources[0x55]	698	1			T1	29		T38	2		T63	23
valid_sources[0x56]	719	1			T1	37		T21	19		T109	1
valid_sources[0x57]	869	1			T1	13		T38	1		T21	31
valid_sources[0x58]	731	1			T1	12		T10	1		T59	1
valid_sources[0x59]	826	1			T1	27		T10	2		T59	1
valid_sources[0x5a]	734	1			T1	28		T5	1		T21	18
valid_sources[0x5b]	694	1			T1	1		T3	1		T38	1
valid_sources[0x5c]	689	1			T38	1		T147	1		T21	17
valid_sources[0x5d]	836	1			T1	35		T2	2		T12	1
valid_sources[0x5e]	686	1			T1	22		T21	15		T22	2
valid_sources[0x5f]	845	1			T1	8		T3	1		T38	3
valid_sources[0x60]	598	1			T1	18		T3	1		T37	1
valid_sources[0x61]	655	1			T1	35		T9	2		T20	3
valid_sources[0x62]	633	1			T1	9		T10	5		T59	1
valid_sources[0x63]	767	1			T1	24		T12	1		T21	27
valid_sources[0x64]	613	1			T1	3		T59	1		T38	1
valid_sources[0x65]	578	1			T38	3		T21	19		T22	5
valid_sources[0x66]	725	1			T1	45		T10	1		T38	2
valid_sources[0x67]	711	1			T1	7		T38	3		T20	1
valid_sources[0x68]	697	1			T21	38		T52	1		T148	1
valid_sources[0x69]	631	1			T1	8		T38	1		T20	2
valid_sources[0x6a]	755	1			T1	4		T2	4		T10	1
valid_sources[0x6b]	644	1			T2	4		T38	2		T21	24
valid_sources[0x6c]	651	1			T1	32		T38	1		T21	2
valid_sources[0x6d]	540	1			T1	3		T10	2		T38	4
valid_sources[0x6e]	854	1			T1	8		T38	2		T147	1
valid_sources[0x6f]	893	1			T1	25		T10	1		T38	1
valid_sources[0x70]	613	1			T1	9		T10	1		T108	1
valid_sources[0x71]	780	1			T1	3		T10	2		T38	1
valid_sources[0x72]	681	1			T1	9		T38	2		T21	26
valid_sources[0x73]	587	1			T1	14		T12	1		T38	1
valid_sources[0x74]	935	1			T1	12		T38	2		T102	1
valid_sources[0x75]	1001	1			T1	24		T59	1		T38	2
valid_sources[0x76]	613	1			T1	15		T10	1		T12	1
valid_sources[0x77]	674	1			T12	1		T59	1		T5	3
valid_sources[0x78]	627	1			T1	19		T10	1		T21	6
valid_sources[0x79]	1034	1			T38	2		T21	24		T22	8
valid_sources[0x7a]	625	1			T1	27		T3	1		T10	4
valid_sources[0x7b]	815	1			T1	1		T10	1		T38	1
valid_sources[0x7c]	583	1			T1	2		T8	2		T21	19
valid_sources[0x7d]	754	1			T1	38		T10	1		T38	4
valid_sources[0x7e]	627	1			T1	16		T59	1		T38	2
valid_sources[0x7f]	559	1			T21	7		T22	5		T149	4
valid_sources[0x80]	604	1			T1	4		T59	1		T38	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40711

1

T1

775

T2

7

T10

7

values[0x0]

all_enables

biggest_size

57139

1

T1

1185

T2

8

T3

11

values[0x1]

all_enables

biggest_size

54061

1

T1

1183

T2

5

T3

5