Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16618792

1

T1

5108

T2

14627

T3

17805

full_word

161440721

1

T1

16742

T2

147840

T3

176914

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	178059233	1			T1	21850		T2	162467		T3	194719
auto[TlIntgErrCmd]	101	1			T56	7		T57	3		T58	10
auto[TlIntgErrData]	89	1			T56	8		T57	4		T58	4
auto[TlIntgErrBoth]	90	1			T56	5		T57	3		T58	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86095815

1

T1

7743

T2

80079

T3

97279

auto[1]

91963698

1

T1

14107

T2

82388

T3

97440

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8149466	1			T1	1351		T2	7087		T3	8990
auto[TlIntgErrNone]	partial	auto[1]	8469069	1			T1	3757		T2	7540		T3	8815
auto[TlIntgErrNone]	full_word	auto[0]	77946228	1			T1	6392		T2	72992		T3	88289
auto[TlIntgErrNone]	full_word	auto[1]	83494470	1			T1	10350		T2	74848		T3	88625
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T56	5		T57	3		T58	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T56	2		T58	7		T131	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T134	1		T135	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T127	1		T131	1		T134	2
auto[TlIntgErrData]	partial	auto[0]	37	1			T56	3		T57	1		T58	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T56	5		T57	3		T58	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T131	1		T136	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T129	1		T137	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T56	2		T57	1		T58	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T56	2		T57	2		T58	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T132	1		T126	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T56	1		T133	1		T138	1