Module Definition
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Module : prim_mubi8_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch 100.00 100.00 100.00



Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[7].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_mubi8_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Module : prim_mubi8_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 902 902 0 0
OutputsKnown_A 1256170026 1256055547 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 1256170026 1256043256 0 2706


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 902 902 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256170026 1256055547 0 0
T1 104901 104586 0 0
T2 299328 299242 0 0
T3 142081 142076 0 0
T4 35830 35764 0 0
T8 68972 68921 0 0
T9 1484 1428 0 0
T10 656112 656101 0 0
T11 869 808 0 0
T12 149220 149215 0 0
T13 72262 72189 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256170026 1256043256 0 2706
T1 104901 104568 0 3
T2 299328 299239 0 3
T3 142081 142076 0 3
T4 35830 35761 0 3
T8 68972 68918 0 3
T9 1484 1425 0 3
T10 656112 656100 0 3
T11 869 805 0 3
T12 149220 149214 0 3
T13 72262 72186 0 3

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