Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1268193180	221793	0	0
ctrl_regwen_rd_A	1268193180	3858	0	0
exec_rd_A	1268193180	3479	0	0
exec_regwen_rd_A	1268193180	3382	0	0
readback_rd_A	1268193180	2268	0	0
readback_regwen_rd_A	1268193180	2004	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1268193180	221793	0	0
T1	104901	3600	0	0
T2	299328	0	0	0
T3	142081	0	0	0
T4	35830	0	0	0
T8	68972	0	0	0
T9	1484	0	0	0
T10	656112	0	0	0
T11	869	0	0	0
T12	149220	0	0	0
T13	72262	0	0	0
T21	0	8627	0	0
T22	0	720	0	0
T65	0	2839	0	0
T66	0	4442	0	0
T67	0	2132	0	0
T68	0	2417	0	0
T69	0	1639	0	0
T70	0	1440	0	0
T71	0	6175	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1268193180	3858	0	0
T15	14420	0	0	0
T22	17558	20	0	0
T44	0	153	0	0
T48	267119	0	0	0
T67	0	162	0	0
T68	0	195	0	0
T69	0	144	0	0
T112	0	434	0	0
T113	0	215	0	0
T114	0	46	0	0
T115	0	238	0	0
T116	0	142	0	0
T117	267923	0	0	0
T118	160942	0	0	0
T119	963505	0	0	0
T120	1015	0	0	0
T121	131548	0	0	0
T122	268992	0	0	0
T123	158515	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1268193180	3479	0	0
T15	14420	0	0	0
T22	17558	48	0	0
T44	0	199	0	0
T48	267119	0	0	0
T67	0	115	0	0
T68	0	193	0	0
T69	0	140	0	0
T112	0	253	0	0
T113	0	213	0	0
T114	0	49	0	0
T115	0	162	0	0
T116	0	94	0	0
T117	267923	0	0	0
T118	160942	0	0	0
T119	963505	0	0	0
T120	1015	0	0	0
T121	131548	0	0	0
T122	268992	0	0	0
T123	158515	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1268193180	3382	0	0
T15	14420	0	0	0
T22	17558	40	0	0
T44	0	147	0	0
T48	267119	0	0	0
T67	0	178	0	0
T68	0	187	0	0
T69	0	158	0	0
T112	0	230	0	0
T113	0	158	0	0
T114	0	73	0	0
T115	0	166	0	0
T116	0	155	0	0
T117	267923	0	0	0
T118	160942	0	0	0
T119	963505	0	0	0
T120	1015	0	0	0
T121	131548	0	0	0
T122	268992	0	0	0
T123	158515	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1268193180	2268	0	0
T15	14420	0	0	0
T22	17558	26	0	0
T44	0	104	0	0
T48	267119	0	0	0
T67	0	165	0	0
T68	0	154	0	0
T69	0	89	0	0
T112	0	320	0	0
T113	0	167	0	0
T114	0	33	0	0
T115	0	179	0	0
T116	0	178	0	0
T117	267923	0	0	0
T118	160942	0	0	0
T119	963505	0	0	0
T120	1015	0	0	0
T121	131548	0	0	0
T122	268992	0	0	0
T123	158515	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1268193180	2004	0	0
T15	14420	0	0	0
T22	17558	68	0	0
T44	0	77	0	0
T48	267119	0	0	0
T67	0	117	0	0
T68	0	114	0	0
T69	0	91	0	0
T112	0	246	0	0
T113	0	128	0	0
T114	0	43	0	0
T115	0	127	0	0
T116	0	170	0	0
T117	267923	0	0	0
T118	160942	0	0	0
T119	963505	0	0	0
T120	1015	0	0	0
T121	131548	0	0	0
T122	268992	0	0	0
T123	158515	0	0	0