| T798 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2712537734 |
|
|
Jul 12 06:05:05 PM PDT 24 |
Jul 12 06:10:38 PM PDT 24 |
20501784275 ps |
| T799 |
/workspace/coverage/default/22.sram_ctrl_executable.108277498 |
|
|
Jul 12 06:01:48 PM PDT 24 |
Jul 12 06:06:23 PM PDT 24 |
27618860980 ps |
| T800 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1638697017 |
|
|
Jul 12 06:01:00 PM PDT 24 |
Jul 12 06:01:20 PM PDT 24 |
2858137855 ps |
| T801 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2134664567 |
|
|
Jul 12 06:00:36 PM PDT 24 |
Jul 12 06:02:10 PM PDT 24 |
11928805231 ps |
| T802 |
/workspace/coverage/default/47.sram_ctrl_regwen.161679364 |
|
|
Jul 12 06:05:29 PM PDT 24 |
Jul 12 06:13:05 PM PDT 24 |
5432254228 ps |
| T803 |
/workspace/coverage/default/44.sram_ctrl_smoke.1931442809 |
|
|
Jul 12 06:04:45 PM PDT 24 |
Jul 12 06:05:16 PM PDT 24 |
5927297448 ps |
| T804 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.341766118 |
|
|
Jul 12 06:03:53 PM PDT 24 |
Jul 12 06:14:05 PM PDT 24 |
23555636680 ps |
| T805 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1494907982 |
|
|
Jul 12 06:04:49 PM PDT 24 |
Jul 12 06:11:04 PM PDT 24 |
106774766596 ps |
| T806 |
/workspace/coverage/default/8.sram_ctrl_alert_test.646318212 |
|
|
Jul 12 06:00:51 PM PDT 24 |
Jul 12 06:00:53 PM PDT 24 |
11256704 ps |
| T26 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2287594613 |
|
|
Jul 12 06:00:26 PM PDT 24 |
Jul 12 06:00:31 PM PDT 24 |
249071986 ps |
| T807 |
/workspace/coverage/default/40.sram_ctrl_smoke.2882387828 |
|
|
Jul 12 06:04:12 PM PDT 24 |
Jul 12 06:05:37 PM PDT 24 |
1059558321 ps |
| T808 |
/workspace/coverage/default/40.sram_ctrl_stress_all.166937828 |
|
|
Jul 12 06:04:17 PM PDT 24 |
Jul 12 07:52:00 PM PDT 24 |
47956535592 ps |
| T809 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2099848473 |
|
|
Jul 12 06:00:50 PM PDT 24 |
Jul 12 06:12:38 PM PDT 24 |
87285453107 ps |
| T810 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1126843903 |
|
|
Jul 12 06:03:07 PM PDT 24 |
Jul 12 06:08:29 PM PDT 24 |
5183848595 ps |
| T811 |
/workspace/coverage/default/6.sram_ctrl_executable.2512054684 |
|
|
Jul 12 06:00:56 PM PDT 24 |
Jul 12 06:09:31 PM PDT 24 |
4303243271 ps |
| T812 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.4256109373 |
|
|
Jul 12 06:00:30 PM PDT 24 |
Jul 12 06:01:11 PM PDT 24 |
6788128726 ps |
| T813 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1725455038 |
|
|
Jul 12 06:02:45 PM PDT 24 |
Jul 12 06:05:19 PM PDT 24 |
9286180692 ps |
| T814 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.3497068036 |
|
|
Jul 12 06:04:59 PM PDT 24 |
Jul 12 06:05:24 PM PDT 24 |
1421517267 ps |
| T815 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3747282438 |
|
|
Jul 12 06:03:55 PM PDT 24 |
Jul 12 06:05:19 PM PDT 24 |
8663451558 ps |
| T816 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2516287741 |
|
|
Jul 12 06:02:43 PM PDT 24 |
Jul 12 06:03:16 PM PDT 24 |
23886357055 ps |
| T817 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3795151633 |
|
|
Jul 12 06:00:54 PM PDT 24 |
Jul 12 06:19:59 PM PDT 24 |
20897885932 ps |
| T818 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1195681821 |
|
|
Jul 12 06:00:42 PM PDT 24 |
Jul 12 06:00:57 PM PDT 24 |
2664007896 ps |
| T819 |
/workspace/coverage/default/39.sram_ctrl_stress_all.1917573532 |
|
|
Jul 12 06:04:10 PM PDT 24 |
Jul 12 06:28:51 PM PDT 24 |
18246988160 ps |
| T820 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1975047017 |
|
|
Jul 12 06:01:09 PM PDT 24 |
Jul 12 06:02:15 PM PDT 24 |
1861676183 ps |
| T821 |
/workspace/coverage/default/5.sram_ctrl_stress_all.3076043189 |
|
|
Jul 12 06:00:50 PM PDT 24 |
Jul 12 07:43:54 PM PDT 24 |
474026192689 ps |
| T822 |
/workspace/coverage/default/9.sram_ctrl_stress_all.776008395 |
|
|
Jul 12 06:00:48 PM PDT 24 |
Jul 12 07:16:15 PM PDT 24 |
116272798147 ps |
| T823 |
/workspace/coverage/default/2.sram_ctrl_stress_all.2703105458 |
|
|
Jul 12 06:00:38 PM PDT 24 |
Jul 12 06:35:27 PM PDT 24 |
50330611316 ps |
| T824 |
/workspace/coverage/default/29.sram_ctrl_regwen.3085615127 |
|
|
Jul 12 06:02:37 PM PDT 24 |
Jul 12 06:14:12 PM PDT 24 |
6767051413 ps |
| T825 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1291773644 |
|
|
Jul 12 06:05:07 PM PDT 24 |
Jul 12 06:07:04 PM PDT 24 |
2735866284 ps |
| T826 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2048348723 |
|
|
Jul 12 06:00:30 PM PDT 24 |
Jul 12 06:00:38 PM PDT 24 |
2817021262 ps |
| T827 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.397761868 |
|
|
Jul 12 06:00:37 PM PDT 24 |
Jul 12 06:01:12 PM PDT 24 |
8926332412 ps |
| T828 |
/workspace/coverage/default/30.sram_ctrl_stress_all.849988796 |
|
|
Jul 12 06:02:44 PM PDT 24 |
Jul 12 07:08:28 PM PDT 24 |
176282687436 ps |
| T829 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.3233541305 |
|
|
Jul 12 06:04:52 PM PDT 24 |
Jul 12 06:05:58 PM PDT 24 |
1519219044 ps |
| T830 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3034611890 |
|
|
Jul 12 06:04:51 PM PDT 24 |
Jul 12 06:05:01 PM PDT 24 |
512427092 ps |
| T831 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.983058980 |
|
|
Jul 12 06:01:23 PM PDT 24 |
Jul 12 06:02:30 PM PDT 24 |
21244934811 ps |
| T832 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.178944151 |
|
|
Jul 12 06:05:06 PM PDT 24 |
Jul 12 06:40:10 PM PDT 24 |
104791819382 ps |
| T833 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2572216636 |
|
|
Jul 12 06:03:18 PM PDT 24 |
Jul 12 06:05:25 PM PDT 24 |
6558356582 ps |
| T834 |
/workspace/coverage/default/18.sram_ctrl_stress_all.3643787703 |
|
|
Jul 12 06:01:25 PM PDT 24 |
Jul 12 06:36:05 PM PDT 24 |
140933218707 ps |
| T835 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.2698626419 |
|
|
Jul 12 06:02:12 PM PDT 24 |
Jul 12 06:02:17 PM PDT 24 |
693100122 ps |
| T836 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1163242100 |
|
|
Jul 12 06:04:42 PM PDT 24 |
Jul 12 06:07:13 PM PDT 24 |
3264836916 ps |
| T837 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.267375252 |
|
|
Jul 12 06:00:46 PM PDT 24 |
Jul 12 06:16:03 PM PDT 24 |
300405351575 ps |
| T838 |
/workspace/coverage/default/7.sram_ctrl_smoke.2125383488 |
|
|
Jul 12 06:00:40 PM PDT 24 |
Jul 12 06:00:48 PM PDT 24 |
1758370247 ps |
| T839 |
/workspace/coverage/default/36.sram_ctrl_stress_all.3158046579 |
|
|
Jul 12 06:03:39 PM PDT 24 |
Jul 12 06:34:12 PM PDT 24 |
43584919066 ps |
| T840 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2037276963 |
|
|
Jul 12 06:01:49 PM PDT 24 |
Jul 12 06:02:52 PM PDT 24 |
775948879 ps |
| T841 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.2283182516 |
|
|
Jul 12 06:01:40 PM PDT 24 |
Jul 12 06:01:45 PM PDT 24 |
345130683 ps |
| T842 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.4293919871 |
|
|
Jul 12 06:03:41 PM PDT 24 |
Jul 12 06:11:11 PM PDT 24 |
153987765609 ps |
| T843 |
/workspace/coverage/default/11.sram_ctrl_smoke.3411110858 |
|
|
Jul 12 06:00:56 PM PDT 24 |
Jul 12 06:01:16 PM PDT 24 |
2483671928 ps |
| T844 |
/workspace/coverage/default/2.sram_ctrl_partial_access.2602095920 |
|
|
Jul 12 06:00:35 PM PDT 24 |
Jul 12 06:00:46 PM PDT 24 |
654540772 ps |
| T845 |
/workspace/coverage/default/45.sram_ctrl_bijection.4256730367 |
|
|
Jul 12 06:04:52 PM PDT 24 |
Jul 12 06:46:04 PM PDT 24 |
498273797147 ps |
| T846 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1647753088 |
|
|
Jul 12 06:03:25 PM PDT 24 |
Jul 12 06:06:15 PM PDT 24 |
5233253602 ps |
| T847 |
/workspace/coverage/default/43.sram_ctrl_bijection.3118015534 |
|
|
Jul 12 06:04:36 PM PDT 24 |
Jul 12 06:26:34 PM PDT 24 |
317024671476 ps |
| T848 |
/workspace/coverage/default/48.sram_ctrl_smoke.2171951996 |
|
|
Jul 12 06:05:30 PM PDT 24 |
Jul 12 06:05:39 PM PDT 24 |
2539859250 ps |
| T849 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2253917121 |
|
|
Jul 12 06:01:56 PM PDT 24 |
Jul 12 06:09:17 PM PDT 24 |
30607522321 ps |
| T850 |
/workspace/coverage/default/34.sram_ctrl_alert_test.2361290661 |
|
|
Jul 12 06:03:25 PM PDT 24 |
Jul 12 06:03:27 PM PDT 24 |
22368648 ps |
| T851 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.2993554138 |
|
|
Jul 12 06:01:19 PM PDT 24 |
Jul 12 06:28:21 PM PDT 24 |
231737259789 ps |
| T852 |
/workspace/coverage/default/35.sram_ctrl_bijection.1053715257 |
|
|
Jul 12 06:03:31 PM PDT 24 |
Jul 12 06:30:14 PM PDT 24 |
23607799363 ps |
| T853 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.10231119 |
|
|
Jul 12 06:03:27 PM PDT 24 |
Jul 12 06:06:13 PM PDT 24 |
14720082530 ps |
| T854 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2606619739 |
|
|
Jul 12 06:01:55 PM PDT 24 |
Jul 12 06:02:02 PM PDT 24 |
427436606 ps |
| T855 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3898089688 |
|
|
Jul 12 06:05:24 PM PDT 24 |
Jul 12 06:07:43 PM PDT 24 |
7635769547 ps |
| T856 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1423382835 |
|
|
Jul 12 06:00:59 PM PDT 24 |
Jul 12 06:01:07 PM PDT 24 |
2784945437 ps |
| T857 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.3901701668 |
|
|
Jul 12 06:04:17 PM PDT 24 |
Jul 12 06:05:41 PM PDT 24 |
14998286093 ps |
| T27 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.579821330 |
|
|
Jul 12 06:00:49 PM PDT 24 |
Jul 12 06:00:53 PM PDT 24 |
439512575 ps |
| T858 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.379490598 |
|
|
Jul 12 06:05:28 PM PDT 24 |
Jul 12 06:05:32 PM PDT 24 |
2590471880 ps |
| T859 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.996165423 |
|
|
Jul 12 06:05:22 PM PDT 24 |
Jul 12 06:06:00 PM PDT 24 |
17947821560 ps |
| T860 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.23341426 |
|
|
Jul 12 06:02:14 PM PDT 24 |
Jul 12 06:06:13 PM PDT 24 |
14459576428 ps |
| T861 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1027515707 |
|
|
Jul 12 06:00:41 PM PDT 24 |
Jul 12 06:01:57 PM PDT 24 |
12590760911 ps |
| T862 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2809777503 |
|
|
Jul 12 06:01:38 PM PDT 24 |
Jul 12 06:03:29 PM PDT 24 |
4245828444 ps |
| T863 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3411569309 |
|
|
Jul 12 06:00:37 PM PDT 24 |
Jul 12 06:02:44 PM PDT 24 |
1600217558 ps |
| T864 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1429073600 |
|
|
Jul 12 06:00:41 PM PDT 24 |
Jul 12 06:01:44 PM PDT 24 |
1290821700 ps |
| T865 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2139439571 |
|
|
Jul 12 06:01:51 PM PDT 24 |
Jul 12 06:07:30 PM PDT 24 |
62800663685 ps |
| T866 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2937320020 |
|
|
Jul 12 06:01:09 PM PDT 24 |
Jul 12 06:01:16 PM PDT 24 |
787778962 ps |
| T867 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2857904050 |
|
|
Jul 12 06:01:21 PM PDT 24 |
Jul 12 06:07:25 PM PDT 24 |
21087778248 ps |
| T868 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3120420993 |
|
|
Jul 12 06:01:31 PM PDT 24 |
Jul 12 06:01:58 PM PDT 24 |
1774734377 ps |
| T869 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3988428363 |
|
|
Jul 12 06:03:22 PM PDT 24 |
Jul 12 06:12:28 PM PDT 24 |
88621788653 ps |
| T870 |
/workspace/coverage/default/18.sram_ctrl_executable.3627638646 |
|
|
Jul 12 06:01:21 PM PDT 24 |
Jul 12 06:11:17 PM PDT 24 |
24291267489 ps |
| T871 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1587472495 |
|
|
Jul 12 06:04:25 PM PDT 24 |
Jul 12 06:04:27 PM PDT 24 |
110965907 ps |
| T872 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1686205848 |
|
|
Jul 12 06:05:13 PM PDT 24 |
Jul 12 07:48:51 PM PDT 24 |
118199735668 ps |
| T873 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.2768845516 |
|
|
Jul 12 06:00:28 PM PDT 24 |
Jul 12 06:05:12 PM PDT 24 |
16403315840 ps |
| T874 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2819662011 |
|
|
Jul 12 06:00:30 PM PDT 24 |
Jul 12 06:00:38 PM PDT 24 |
707711765 ps |
| T875 |
/workspace/coverage/default/37.sram_ctrl_stress_all.2880150508 |
|
|
Jul 12 06:03:55 PM PDT 24 |
Jul 12 06:14:24 PM PDT 24 |
63059800495 ps |
| T876 |
/workspace/coverage/default/24.sram_ctrl_smoke.1064759234 |
|
|
Jul 12 06:01:56 PM PDT 24 |
Jul 12 06:02:12 PM PDT 24 |
4706956761 ps |
| T877 |
/workspace/coverage/default/33.sram_ctrl_smoke.883710617 |
|
|
Jul 12 06:03:07 PM PDT 24 |
Jul 12 06:04:17 PM PDT 24 |
1684351863 ps |
| T878 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2747366100 |
|
|
Jul 12 06:04:30 PM PDT 24 |
Jul 12 06:04:53 PM PDT 24 |
3874937314 ps |
| T879 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1795567233 |
|
|
Jul 12 06:00:51 PM PDT 24 |
Jul 12 06:04:30 PM PDT 24 |
3902436256 ps |
| T880 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.4016736952 |
|
|
Jul 12 06:01:12 PM PDT 24 |
Jul 12 06:01:51 PM PDT 24 |
24888424156 ps |
| T881 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3514855240 |
|
|
Jul 12 06:00:32 PM PDT 24 |
Jul 12 06:01:53 PM PDT 24 |
3067636883 ps |
| T882 |
/workspace/coverage/default/28.sram_ctrl_bijection.734488453 |
|
|
Jul 12 06:02:24 PM PDT 24 |
Jul 12 06:19:12 PM PDT 24 |
320172489703 ps |
| T883 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1231721677 |
|
|
Jul 12 06:00:39 PM PDT 24 |
Jul 12 06:06:15 PM PDT 24 |
18790045135 ps |
| T884 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3526375938 |
|
|
Jul 12 06:02:10 PM PDT 24 |
Jul 12 06:05:14 PM PDT 24 |
5822518736 ps |
| T885 |
/workspace/coverage/default/3.sram_ctrl_regwen.4131899805 |
|
|
Jul 12 06:00:32 PM PDT 24 |
Jul 12 06:03:03 PM PDT 24 |
7235643503 ps |
| T886 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2710316558 |
|
|
Jul 12 06:00:42 PM PDT 24 |
Jul 12 06:02:24 PM PDT 24 |
72069505571 ps |
| T887 |
/workspace/coverage/default/43.sram_ctrl_stress_all.3088828124 |
|
|
Jul 12 06:04:46 PM PDT 24 |
Jul 12 06:59:09 PM PDT 24 |
284195193799 ps |
| T888 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.2731854172 |
|
|
Jul 12 06:01:07 PM PDT 24 |
Jul 12 06:32:32 PM PDT 24 |
47097820955 ps |
| T889 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3030344962 |
|
|
Jul 12 06:00:26 PM PDT 24 |
Jul 12 06:02:40 PM PDT 24 |
984944650 ps |
| T890 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1683777926 |
|
|
Jul 12 06:03:34 PM PDT 24 |
Jul 12 06:03:41 PM PDT 24 |
8328342091 ps |
| T891 |
/workspace/coverage/default/42.sram_ctrl_smoke.1364894124 |
|
|
Jul 12 06:04:23 PM PDT 24 |
Jul 12 06:06:40 PM PDT 24 |
878685309 ps |
| T892 |
/workspace/coverage/default/36.sram_ctrl_smoke.2665408721 |
|
|
Jul 12 06:03:43 PM PDT 24 |
Jul 12 06:04:09 PM PDT 24 |
1281267261 ps |
| T893 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2839311 |
|
|
Jul 12 06:02:16 PM PDT 24 |
Jul 12 06:07:16 PM PDT 24 |
23299792127 ps |
| T894 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.3097445537 |
|
|
Jul 12 06:03:31 PM PDT 24 |
Jul 12 06:05:37 PM PDT 24 |
2040948254 ps |
| T895 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3657289275 |
|
|
Jul 12 06:03:34 PM PDT 24 |
Jul 12 06:06:28 PM PDT 24 |
50360205773 ps |
| T896 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2749840920 |
|
|
Jul 12 06:00:49 PM PDT 24 |
Jul 12 06:02:21 PM PDT 24 |
781092585 ps |
| T897 |
/workspace/coverage/default/43.sram_ctrl_executable.502581694 |
|
|
Jul 12 06:04:47 PM PDT 24 |
Jul 12 06:10:50 PM PDT 24 |
2533805887 ps |
| T898 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2709789012 |
|
|
Jul 12 06:00:41 PM PDT 24 |
Jul 12 06:05:17 PM PDT 24 |
9844345508 ps |
| T899 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.716316787 |
|
|
Jul 12 06:02:25 PM PDT 24 |
Jul 12 06:03:51 PM PDT 24 |
57481584866 ps |
| T900 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.2531760540 |
|
|
Jul 12 06:01:55 PM PDT 24 |
Jul 12 06:07:04 PM PDT 24 |
26262716535 ps |
| T901 |
/workspace/coverage/default/20.sram_ctrl_smoke.2270019066 |
|
|
Jul 12 06:01:26 PM PDT 24 |
Jul 12 06:01:43 PM PDT 24 |
3117355402 ps |
| T902 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.280226254 |
|
|
Jul 12 06:04:30 PM PDT 24 |
Jul 12 06:04:34 PM PDT 24 |
679676334 ps |
| T903 |
/workspace/coverage/default/42.sram_ctrl_executable.1203562779 |
|
|
Jul 12 06:04:33 PM PDT 24 |
Jul 12 06:09:35 PM PDT 24 |
77201909786 ps |
| T904 |
/workspace/coverage/default/7.sram_ctrl_stress_all.457897535 |
|
|
Jul 12 06:00:55 PM PDT 24 |
Jul 12 07:17:41 PM PDT 24 |
1365786505189 ps |
| T905 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2039863273 |
|
|
Jul 12 06:02:37 PM PDT 24 |
Jul 12 06:05:16 PM PDT 24 |
10954207972 ps |
| T906 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1872388875 |
|
|
Jul 12 06:00:30 PM PDT 24 |
Jul 12 06:06:43 PM PDT 24 |
29736561395 ps |
| T907 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.879228549 |
|
|
Jul 12 06:01:13 PM PDT 24 |
Jul 12 06:01:46 PM PDT 24 |
2979300095 ps |
| T908 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.826277376 |
|
|
Jul 12 06:01:56 PM PDT 24 |
Jul 12 06:06:16 PM PDT 24 |
7894840320 ps |
| T909 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.3608491881 |
|
|
Jul 12 06:03:55 PM PDT 24 |
Jul 12 06:06:22 PM PDT 24 |
5366902471 ps |
| T910 |
/workspace/coverage/default/46.sram_ctrl_executable.3984761952 |
|
|
Jul 12 06:05:08 PM PDT 24 |
Jul 12 06:15:45 PM PDT 24 |
4674135115 ps |
| T911 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3083772250 |
|
|
Jul 12 06:01:20 PM PDT 24 |
Jul 12 06:03:27 PM PDT 24 |
2755487591 ps |
| T912 |
/workspace/coverage/default/23.sram_ctrl_smoke.4070576801 |
|
|
Jul 12 06:01:47 PM PDT 24 |
Jul 12 06:02:07 PM PDT 24 |
893681324 ps |
| T913 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.1495632990 |
|
|
Jul 12 06:03:39 PM PDT 24 |
Jul 12 06:04:29 PM PDT 24 |
10014741330 ps |
| T914 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.74873476 |
|
|
Jul 12 06:03:33 PM PDT 24 |
Jul 12 06:05:43 PM PDT 24 |
801704553 ps |
| T915 |
/workspace/coverage/default/21.sram_ctrl_bijection.2113181591 |
|
|
Jul 12 06:01:32 PM PDT 24 |
Jul 12 06:45:29 PM PDT 24 |
117423218201 ps |
| T916 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2079664335 |
|
|
Jul 12 06:02:50 PM PDT 24 |
Jul 12 06:05:35 PM PDT 24 |
9689796074 ps |
| T917 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.410623255 |
|
|
Jul 12 06:01:07 PM PDT 24 |
Jul 12 06:05:18 PM PDT 24 |
17189786075 ps |
| T918 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.870379303 |
|
|
Jul 12 06:05:30 PM PDT 24 |
Jul 12 06:11:22 PM PDT 24 |
9762648755 ps |
| T919 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2469877437 |
|
|
Jul 12 06:05:07 PM PDT 24 |
Jul 12 06:05:16 PM PDT 24 |
1410446595 ps |
| T920 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.1943238240 |
|
|
Jul 12 06:01:13 PM PDT 24 |
Jul 12 06:01:18 PM PDT 24 |
4191315071 ps |
| T921 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2648151542 |
|
|
Jul 12 06:04:52 PM PDT 24 |
Jul 12 06:05:01 PM PDT 24 |
1732333958 ps |
| T922 |
/workspace/coverage/default/5.sram_ctrl_smoke.2927875985 |
|
|
Jul 12 06:00:45 PM PDT 24 |
Jul 12 06:00:52 PM PDT 24 |
1085628194 ps |
| T923 |
/workspace/coverage/default/27.sram_ctrl_bijection.2596498547 |
|
|
Jul 12 06:02:16 PM PDT 24 |
Jul 12 06:12:22 PM PDT 24 |
70929737289 ps |
| T924 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1256082345 |
|
|
Jul 12 06:00:52 PM PDT 24 |
Jul 12 06:01:37 PM PDT 24 |
7303279560 ps |
| T925 |
/workspace/coverage/default/23.sram_ctrl_executable.115944995 |
|
|
Jul 12 06:01:56 PM PDT 24 |
Jul 12 06:18:25 PM PDT 24 |
58888340064 ps |
| T926 |
/workspace/coverage/default/8.sram_ctrl_bijection.933099592 |
|
|
Jul 12 06:00:46 PM PDT 24 |
Jul 12 06:26:14 PM PDT 24 |
21528792917 ps |
| T927 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2829082464 |
|
|
Jul 12 06:00:58 PM PDT 24 |
Jul 12 06:12:50 PM PDT 24 |
43949108584 ps |
| T928 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2754236812 |
|
|
Jul 12 06:02:09 PM PDT 24 |
Jul 12 06:04:07 PM PDT 24 |
1639605742 ps |
| T929 |
/workspace/coverage/default/37.sram_ctrl_executable.3797235726 |
|
|
Jul 12 06:03:57 PM PDT 24 |
Jul 12 06:16:58 PM PDT 24 |
14187875667 ps |
| T930 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1780057180 |
|
|
Jul 12 06:02:51 PM PDT 24 |
Jul 12 06:04:10 PM PDT 24 |
1497970469 ps |
| T931 |
/workspace/coverage/default/13.sram_ctrl_bijection.1032651270 |
|
|
Jul 12 06:00:57 PM PDT 24 |
Jul 12 06:46:09 PM PDT 24 |
239706245696 ps |
| T932 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.3722583294 |
|
|
Jul 12 06:02:03 PM PDT 24 |
Jul 12 06:02:48 PM PDT 24 |
7755818231 ps |
| T933 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1436190616 |
|
|
Jul 12 06:00:22 PM PDT 24 |
Jul 12 06:04:40 PM PDT 24 |
16424264930 ps |
| T934 |
/workspace/coverage/default/1.sram_ctrl_regwen.2934485399 |
|
|
Jul 12 06:00:21 PM PDT 24 |
Jul 12 06:03:32 PM PDT 24 |
4159471676 ps |
| T935 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1174831804 |
|
|
Jul 12 06:01:41 PM PDT 24 |
Jul 12 06:01:43 PM PDT 24 |
16435282 ps |
| T936 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.494487804 |
|
|
Jul 12 06:02:37 PM PDT 24 |
Jul 12 06:08:11 PM PDT 24 |
4745946899 ps |
| T937 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.3021958376 |
|
|
Jul 12 06:01:24 PM PDT 24 |
Jul 12 06:09:14 PM PDT 24 |
22417816200 ps |
| T938 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2088021733 |
|
|
Jul 12 06:00:45 PM PDT 24 |
Jul 12 06:01:19 PM PDT 24 |
1500362070 ps |
| T939 |
/workspace/coverage/default/44.sram_ctrl_alert_test.4245958079 |
|
|
Jul 12 06:04:53 PM PDT 24 |
Jul 12 06:04:55 PM PDT 24 |
73764842 ps |
| T940 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1581390338 |
|
|
Jul 12 06:00:56 PM PDT 24 |
Jul 12 06:01:39 PM PDT 24 |
8221061716 ps |
| T941 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.322975388 |
|
|
Jul 12 06:05:28 PM PDT 24 |
Jul 12 06:07:44 PM PDT 24 |
2468531101 ps |
| T942 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.4152148443 |
|
|
Jul 12 06:02:00 PM PDT 24 |
Jul 12 06:06:25 PM PDT 24 |
4070091995 ps |
| T943 |
/workspace/coverage/default/43.sram_ctrl_regwen.2591449523 |
|
|
Jul 12 06:04:47 PM PDT 24 |
Jul 12 06:15:12 PM PDT 24 |
9240125289 ps |
| T944 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.1038853217 |
|
|
Jul 12 06:02:31 PM PDT 24 |
Jul 12 06:05:17 PM PDT 24 |
9152795702 ps |
| T945 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1662345672 |
|
|
Jul 12 06:01:13 PM PDT 24 |
Jul 12 06:06:51 PM PDT 24 |
3491803653 ps |
| T946 |
/workspace/coverage/default/46.sram_ctrl_bijection.1389647290 |
|
|
Jul 12 06:05:10 PM PDT 24 |
Jul 12 06:48:02 PM PDT 24 |
423270282857 ps |
| T947 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2400583823 |
|
|
Jul 12 06:02:59 PM PDT 24 |
Jul 12 06:03:03 PM PDT 24 |
383692299 ps |
| T60 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2846978387 |
|
|
Jul 12 06:39:32 PM PDT 24 |
Jul 12 06:40:30 PM PDT 24 |
28633499632 ps |
| T61 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.818021873 |
|
|
Jul 12 06:39:28 PM PDT 24 |
Jul 12 06:39:35 PM PDT 24 |
75570632 ps |
| T62 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.604284294 |
|
|
Jul 12 06:39:29 PM PDT 24 |
Jul 12 06:39:35 PM PDT 24 |
18131726 ps |
| T104 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3947405120 |
|
|
Jul 12 06:39:48 PM PDT 24 |
Jul 12 06:39:50 PM PDT 24 |
19610694 ps |
| T948 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4251250505 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:44 PM PDT 24 |
364816123 ps |
| T74 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3243429422 |
|
|
Jul 12 06:39:27 PM PDT 24 |
Jul 12 06:39:34 PM PDT 24 |
27535335 ps |
| T105 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2688161463 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:39 PM PDT 24 |
46386471 ps |
| T56 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3891303208 |
|
|
Jul 12 06:39:29 PM PDT 24 |
Jul 12 06:39:37 PM PDT 24 |
348062263 ps |
| T57 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3749520387 |
|
|
Jul 12 06:39:37 PM PDT 24 |
Jul 12 06:39:43 PM PDT 24 |
533822064 ps |
| T75 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2651075030 |
|
|
Jul 12 06:39:29 PM PDT 24 |
Jul 12 06:39:35 PM PDT 24 |
24379797 ps |
| T106 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2098065569 |
|
|
Jul 12 06:39:42 PM PDT 24 |
Jul 12 06:39:46 PM PDT 24 |
17398520 ps |
| T949 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1735321532 |
|
|
Jul 12 06:39:40 PM PDT 24 |
Jul 12 06:39:48 PM PDT 24 |
351857687 ps |
| T58 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.174411014 |
|
|
Jul 12 06:39:45 PM PDT 24 |
Jul 12 06:39:50 PM PDT 24 |
1446187801 ps |
| T950 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2050526030 |
|
|
Jul 12 06:39:45 PM PDT 24 |
Jul 12 06:39:52 PM PDT 24 |
757186403 ps |
| T127 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4043823298 |
|
|
Jul 12 06:39:20 PM PDT 24 |
Jul 12 06:39:27 PM PDT 24 |
99579428 ps |
| T76 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.523334552 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:41 PM PDT 24 |
12403887 ps |
| T77 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3023609514 |
|
|
Jul 12 06:39:29 PM PDT 24 |
Jul 12 06:40:29 PM PDT 24 |
7116282240 ps |
| T78 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3493672305 |
|
|
Jul 12 06:39:41 PM PDT 24 |
Jul 12 06:39:45 PM PDT 24 |
41517289 ps |
| T951 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1817433889 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:39 PM PDT 24 |
40087661 ps |
| T952 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4086566424 |
|
|
Jul 12 06:39:35 PM PDT 24 |
Jul 12 06:39:44 PM PDT 24 |
373972144 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2931516908 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:39 PM PDT 24 |
23470081 ps |
| T107 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1611936671 |
|
|
Jul 12 06:39:27 PM PDT 24 |
Jul 12 06:39:34 PM PDT 24 |
15687146 ps |
| T80 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3919310558 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:40:36 PM PDT 24 |
22904206598 ps |
| T81 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3142274500 |
|
|
Jul 12 06:39:37 PM PDT 24 |
Jul 12 06:40:10 PM PDT 24 |
3824056833 ps |
| T953 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3578760242 |
|
|
Jul 12 06:39:43 PM PDT 24 |
Jul 12 06:39:46 PM PDT 24 |
15909753 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1129671625 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:42 PM PDT 24 |
311419933 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.288806045 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:41 PM PDT 24 |
273166038 ps |
| T956 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2448787020 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:41 PM PDT 24 |
17863591 ps |
| T83 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.688150244 |
|
|
Jul 12 06:39:42 PM PDT 24 |
Jul 12 06:40:15 PM PDT 24 |
15387632181 ps |
| T957 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2886472682 |
|
|
Jul 12 06:39:35 PM PDT 24 |
Jul 12 06:39:40 PM PDT 24 |
212448874 ps |
| T958 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.740978112 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:45 PM PDT 24 |
400268374 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1251794318 |
|
|
Jul 12 06:39:31 PM PDT 24 |
Jul 12 06:39:39 PM PDT 24 |
868334186 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3654045375 |
|
|
Jul 12 06:39:47 PM PDT 24 |
Jul 12 06:39:49 PM PDT 24 |
36856489 ps |
| T960 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.86060543 |
|
|
Jul 12 06:39:49 PM PDT 24 |
Jul 12 06:40:20 PM PDT 24 |
7524355544 ps |
| T134 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.758318209 |
|
|
Jul 12 06:39:50 PM PDT 24 |
Jul 12 06:39:53 PM PDT 24 |
580995989 ps |
| T961 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3556278443 |
|
|
Jul 12 06:39:34 PM PDT 24 |
Jul 12 06:39:40 PM PDT 24 |
49515743 ps |
| T962 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.928844255 |
|
|
Jul 12 06:39:49 PM PDT 24 |
Jul 12 06:39:51 PM PDT 24 |
12091360 ps |
| T84 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2066313296 |
|
|
Jul 12 06:39:50 PM PDT 24 |
Jul 12 06:40:40 PM PDT 24 |
14723563706 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2029762974 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:44 PM PDT 24 |
373294762 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1567035744 |
|
|
Jul 12 06:39:27 PM PDT 24 |
Jul 12 06:39:37 PM PDT 24 |
2117189234 ps |
| T85 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.241843929 |
|
|
Jul 12 06:39:29 PM PDT 24 |
Jul 12 06:39:35 PM PDT 24 |
48065050 ps |
| T965 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.637260175 |
|
|
Jul 12 06:39:32 PM PDT 24 |
Jul 12 06:39:40 PM PDT 24 |
696886388 ps |
| T966 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1676362788 |
|
|
Jul 12 06:39:42 PM PDT 24 |
Jul 12 06:39:46 PM PDT 24 |
27579858 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1088595275 |
|
|
Jul 12 06:39:27 PM PDT 24 |
Jul 12 06:39:37 PM PDT 24 |
351650712 ps |
| T128 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.769674832 |
|
|
Jul 12 06:39:29 PM PDT 24 |
Jul 12 06:39:36 PM PDT 24 |
126692929 ps |
| T968 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4142644704 |
|
|
Jul 12 06:39:42 PM PDT 24 |
Jul 12 06:39:49 PM PDT 24 |
441044103 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.940646122 |
|
|
Jul 12 06:39:27 PM PDT 24 |
Jul 12 06:39:34 PM PDT 24 |
247755138 ps |
| T970 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3295769002 |
|
|
Jul 12 06:39:29 PM PDT 24 |
Jul 12 06:39:37 PM PDT 24 |
125266379 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3875749160 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:41 PM PDT 24 |
416578144 ps |
| T129 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2304741565 |
|
|
Jul 12 06:39:43 PM PDT 24 |
Jul 12 06:39:47 PM PDT 24 |
306955835 ps |
| T972 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3423489378 |
|
|
Jul 12 06:39:27 PM PDT 24 |
Jul 12 06:39:34 PM PDT 24 |
47802551 ps |
| T973 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3355805822 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:42 PM PDT 24 |
76607766 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1151619755 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:39 PM PDT 24 |
160978732 ps |
| T136 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3975227071 |
|
|
Jul 12 06:39:37 PM PDT 24 |
Jul 12 06:39:43 PM PDT 24 |
738136433 ps |
| T975 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.247555933 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:41 PM PDT 24 |
14894121 ps |
| T976 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2366343578 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:41 PM PDT 24 |
24884498 ps |
| T977 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3784598168 |
|
|
Jul 12 06:39:43 PM PDT 24 |
Jul 12 06:40:13 PM PDT 24 |
3719046421 ps |
| T86 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2508128204 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:40:36 PM PDT 24 |
14475851799 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4054511032 |
|
|
Jul 12 06:39:27 PM PDT 24 |
Jul 12 06:39:35 PM PDT 24 |
43283755 ps |
| T87 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1352689477 |
|
|
Jul 12 06:39:26 PM PDT 24 |
Jul 12 06:39:33 PM PDT 24 |
15119372 ps |
| T979 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.667224229 |
|
|
Jul 12 06:39:28 PM PDT 24 |
Jul 12 06:39:34 PM PDT 24 |
79289334 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.221723386 |
|
|
Jul 12 06:39:51 PM PDT 24 |
Jul 12 06:39:52 PM PDT 24 |
39264491 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3197030539 |
|
|
Jul 12 06:39:31 PM PDT 24 |
Jul 12 06:39:37 PM PDT 24 |
14694797 ps |
| T130 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3635789654 |
|
|
Jul 12 06:39:38 PM PDT 24 |
Jul 12 06:39:45 PM PDT 24 |
381272605 ps |
| T982 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.828314258 |
|
|
Jul 12 06:39:31 PM PDT 24 |
Jul 12 06:39:40 PM PDT 24 |
1479059761 ps |
| T983 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2008306013 |
|
|
Jul 12 06:39:48 PM PDT 24 |
Jul 12 06:39:53 PM PDT 24 |
359148520 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.312589871 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:42 PM PDT 24 |
43335366 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4200052721 |
|
|
Jul 12 06:39:38 PM PDT 24 |
Jul 12 06:39:42 PM PDT 24 |
104022884 ps |
| T985 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2180978408 |
|
|
Jul 12 06:39:35 PM PDT 24 |
Jul 12 06:39:40 PM PDT 24 |
34693817 ps |
| T94 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.591296928 |
|
|
Jul 12 06:39:27 PM PDT 24 |
Jul 12 06:40:30 PM PDT 24 |
29424991727 ps |
| T137 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2742671906 |
|
|
Jul 12 06:39:39 PM PDT 24 |
Jul 12 06:39:44 PM PDT 24 |
152503201 ps |
| T986 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2915375792 |
|
|
Jul 12 06:39:39 PM PDT 24 |
Jul 12 06:39:47 PM PDT 24 |
354885367 ps |
| T987 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2551578528 |
|
|
Jul 12 06:39:36 PM PDT 24 |
Jul 12 06:39:41 PM PDT 24 |
48477576 ps |
| T988 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2920370942 |
|
|
Jul 12 06:39:35 PM PDT 24 |
Jul 12 06:39:44 PM PDT 24 |
376364897 ps |
| T989 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.922416547 |
|
|
Jul 12 06:39:37 PM PDT 24 |
Jul 12 06:39:44 PM PDT 24 |
36829974 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.644592678 |
|
|
Jul 12 06:39:27 PM PDT 24 |
Jul 12 06:39:34 PM PDT 24 |
14394537 ps |
| T125 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2819188421 |
|
|
Jul 12 06:39:35 PM PDT 24 |
Jul 12 06:39:42 PM PDT 24 |
352565017 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.765424813 |
|
|
Jul 12 06:39:46 PM PDT 24 |
Jul 12 06:39:49 PM PDT 24 |
21464508 ps |
| T95 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.460754177 |
|
|
Jul 12 06:39:34 PM PDT 24 |
Jul 12 06:39:40 PM PDT 24 |
33125371 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2612493166 |
|
|
Jul 12 06:39:42 PM PDT 24 |
Jul 12 06:39:49 PM PDT 24 |
125352870 ps |
| T993 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1597003112 |
|
|
Jul 12 06:39:45 PM PDT 24 |
Jul 12 06:39:49 PM PDT 24 |
326095991 ps |
| T96 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3452992485 |
|
|
Jul 12 06:39:39 PM PDT 24 |
Jul 12 06:40:39 PM PDT 24 |
29373297863 ps |
| T994 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.607926815 |
|
|
Jul 12 06:39:29 PM PDT 24 |
Jul 12 06:40:08 PM PDT 24 |
19404229188 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3139395279 |
|
|
Jul 12 06:39:28 PM PDT 24 |
Jul 12 06:40:00 PM PDT 24 |
15376373283 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3903212868 |
|
|
Jul 12 06:39:42 PM PDT 24 |
Jul 12 06:39:46 PM PDT 24 |
35954459 ps |
| T997 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.428515037 |
|
|
Jul 12 06:39:49 PM PDT 24 |
Jul 12 06:40:45 PM PDT 24 |
14679315215 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1119332869 |
|
|
Jul 12 06:39:31 PM PDT 24 |
Jul 12 06:40:08 PM PDT 24 |
12737544802 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3249861413 |
|
|
Jul 12 06:39:47 PM PDT 24 |
Jul 12 06:39:51 PM PDT 24 |
62236787 ps |
| T1000 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3467824779 |
|
|
Jul 12 06:39:46 PM PDT 24 |
Jul 12 06:39:52 PM PDT 24 |
2023639530 ps |
| T1001 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2049266054 |
|
|
Jul 12 06:39:43 PM PDT 24 |
Jul 12 06:39:49 PM PDT 24 |
1316051698 ps |
| T1002 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1405747836 |
|
|
Jul 12 06:39:50 PM PDT 24 |
Jul 12 06:39:55 PM PDT 24 |
1436881617 ps |
| T1003 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3700160311 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:42 PM PDT 24 |
350119570 ps |
| T1004 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3638629345 |
|
|
Jul 12 06:39:35 PM PDT 24 |
Jul 12 06:39:41 PM PDT 24 |
26000375 ps |
| T1005 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2039000855 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:39 PM PDT 24 |
15152745 ps |
| T1006 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4055630668 |
|
|
Jul 12 06:39:33 PM PDT 24 |
Jul 12 06:39:40 PM PDT 24 |
28874054 ps |
| T1007 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3136322180 |
|
|
Jul 12 06:39:22 PM PDT 24 |
Jul 12 06:39:32 PM PDT 24 |
88602738 ps |
| T1008 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2389329078 |
|
|
Jul 12 06:39:40 PM PDT 24 |
Jul 12 06:39:47 PM PDT 24 |
262199077 ps |
| T97 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2614369569 |
|
|
Jul 12 06:39:38 PM PDT 24 |
Jul 12 06:40:09 PM PDT 24 |
7540732272 ps |