Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1037
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T1009 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3517945971 Jul 12 06:39:46 PM PDT 24 Jul 12 06:39:52 PM PDT 24 351747286 ps
T1010 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.435617622 Jul 12 06:39:41 PM PDT 24 Jul 12 06:39:49 PM PDT 24 259856873 ps
T98 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3333749557 Jul 12 06:39:22 PM PDT 24 Jul 12 06:39:53 PM PDT 24 3790457300 ps
T1011 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.681508594 Jul 12 06:39:26 PM PDT 24 Jul 12 06:39:37 PM PDT 24 600097330 ps
T1012 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2503039863 Jul 12 06:39:36 PM PDT 24 Jul 12 06:39:45 PM PDT 24 152321634 ps
T1013 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.640516727 Jul 12 06:39:38 PM PDT 24 Jul 12 06:39:45 PM PDT 24 27802675 ps
T1014 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3209649726 Jul 12 06:39:51 PM PDT 24 Jul 12 06:39:54 PM PDT 24 1317412736 ps
T1015 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1877570869 Jul 12 06:39:41 PM PDT 24 Jul 12 06:39:48 PM PDT 24 356648917 ps
T1016 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.359498218 Jul 12 06:39:36 PM PDT 24 Jul 12 06:39:41 PM PDT 24 40354173 ps
T1017 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2482370215 Jul 12 06:39:49 PM PDT 24 Jul 12 06:39:52 PM PDT 24 13981067 ps
T1018 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1297793032 Jul 12 06:39:46 PM PDT 24 Jul 12 06:39:50 PM PDT 24 240143862 ps
T132 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1477438723 Jul 12 06:39:37 PM PDT 24 Jul 12 06:39:43 PM PDT 24 284015129 ps
T1019 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4206171592 Jul 12 06:39:27 PM PDT 24 Jul 12 06:39:34 PM PDT 24 20813269 ps
T1020 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3099138836 Jul 12 06:39:28 PM PDT 24 Jul 12 06:39:34 PM PDT 24 23090934 ps
T1021 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1901687652 Jul 12 06:39:48 PM PDT 24 Jul 12 06:39:50 PM PDT 24 82651904 ps
T1022 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3025834369 Jul 12 06:39:33 PM PDT 24 Jul 12 06:39:41 PM PDT 24 137505870 ps
T133 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3198556682 Jul 12 06:39:38 PM PDT 24 Jul 12 06:39:44 PM PDT 24 412900818 ps
T135 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4101639862 Jul 12 06:39:52 PM PDT 24 Jul 12 06:39:56 PM PDT 24 358395926 ps
T1023 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3214618414 Jul 12 06:39:46 PM PDT 24 Jul 12 06:39:51 PM PDT 24 83553529 ps
T1024 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.740075561 Jul 12 06:39:34 PM PDT 24 Jul 12 06:39:41 PM PDT 24 81091125 ps
T138 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3255934888 Jul 12 06:39:43 PM PDT 24 Jul 12 06:39:48 PM PDT 24 274206281 ps
T126 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2775751001 Jul 12 06:39:37 PM PDT 24 Jul 12 06:39:44 PM PDT 24 328461136 ps
T1025 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3979095668 Jul 12 06:39:42 PM PDT 24 Jul 12 06:39:47 PM PDT 24 712926811 ps
T99 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2609380838 Jul 12 06:39:37 PM PDT 24 Jul 12 06:40:13 PM PDT 24 7391862594 ps
T1026 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1841317962 Jul 12 06:39:27 PM PDT 24 Jul 12 06:39:37 PM PDT 24 372030049 ps
T1027 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3254246012 Jul 12 06:39:33 PM PDT 24 Jul 12 06:39:43 PM PDT 24 3196709109 ps
T100 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2223358336 Jul 12 06:39:40 PM PDT 24 Jul 12 06:40:36 PM PDT 24 7358944309 ps
T1028 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2939496243 Jul 12 06:39:52 PM PDT 24 Jul 12 06:39:54 PM PDT 24 45670797 ps
T1029 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2974110275 Jul 12 06:39:47 PM PDT 24 Jul 12 06:40:45 PM PDT 24 14694856340 ps
T1030 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2626151157 Jul 12 06:39:46 PM PDT 24 Jul 12 06:39:50 PM PDT 24 69478974 ps
T1031 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3126123733 Jul 12 06:39:36 PM PDT 24 Jul 12 06:39:42 PM PDT 24 26455315 ps
T1032 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3945349988 Jul 12 06:39:29 PM PDT 24 Jul 12 06:39:35 PM PDT 24 21037563 ps
T1033 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2950082993 Jul 12 06:39:45 PM PDT 24 Jul 12 06:39:48 PM PDT 24 52639231 ps
T1034 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.597949434 Jul 12 06:39:37 PM PDT 24 Jul 12 06:39:42 PM PDT 24 20447850 ps
T1035 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3234718903 Jul 12 06:39:41 PM PDT 24 Jul 12 06:39:45 PM PDT 24 16221721 ps
T1036 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3689436868 Jul 12 06:39:29 PM PDT 24 Jul 12 06:39:36 PM PDT 24 228443769 ps
T1037 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2225703490 Jul 12 06:39:38 PM PDT 24 Jul 12 06:39:42 PM PDT 24 17252762 ps


Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3526035190
Short name T1
Test name
Test status
Simulation time 1049035942 ps
CPU time 144.66 seconds
Started Jul 12 06:05:44 PM PDT 24
Finished Jul 12 06:08:10 PM PDT 24
Peak memory 355116 kb
Host smart-682fcd66-dc3d-4f87-bbe4-136e388967d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3526035190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3526035190
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2171336753
Short name T47
Test name
Test status
Simulation time 23155742701 ps
CPU time 165.1 seconds
Started Jul 12 06:04:53 PM PDT 24
Finished Jul 12 06:07:39 PM PDT 24
Peak memory 211012 kb
Host smart-950dac18-3301-40bb-acca-5f4d5109f39b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171336753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.2171336753
Directory /workspace/44.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/16.sram_ctrl_stress_all.2476595396
Short name T6
Test name
Test status
Simulation time 42708903694 ps
CPU time 2483.54 seconds
Started Jul 12 06:01:12 PM PDT 24
Finished Jul 12 06:42:37 PM PDT 24
Peak memory 388892 kb
Host smart-5a198a3c-215a-4692-810c-470fcfd427b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476595396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.2476595396
Directory /workspace/16.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/41.sram_ctrl_stress_all.3938142906
Short name T10
Test name
Test status
Simulation time 262444912634 ps
CPU time 3483.73 seconds
Started Jul 12 06:04:24 PM PDT 24
Finished Jul 12 07:02:29 PM PDT 24
Peak memory 379672 kb
Host smart-217efad2-ade2-415a-a4fd-94e263ea1188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938142906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.3938142906
Directory /workspace/41.sram_ctrl_stress_all/latest


Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.174411014
Short name T58
Test name
Test status
Simulation time 1446187801 ps
CPU time 2.83 seconds
Started Jul 12 06:39:45 PM PDT 24
Finished Jul 12 06:39:50 PM PDT 24
Peak memory 202928 kb
Host smart-6d3d0606-8838-4590-bef0-1011229dd288
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174411014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.sram_ctrl_tl_intg_err.174411014
Directory /workspace/16.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.1989524746
Short name T15
Test name
Test status
Simulation time 294312405 ps
CPU time 1.93 seconds
Started Jul 12 06:00:40 PM PDT 24
Finished Jul 12 06:00:43 PM PDT 24
Peak memory 222152 kb
Host smart-190cb222-c218-46d2-b533-b22a962a5d09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989524746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.1989524746
Directory /workspace/4.sram_ctrl_sec_cm/latest


Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.35847966
Short name T21
Test name
Test status
Simulation time 7425632083 ps
CPU time 136.57 seconds
Started Jul 12 06:04:38 PM PDT 24
Finished Jul 12 06:06:55 PM PDT 24
Peak memory 331064 kb
Host smart-904fac84-fcfb-416e-b0c2-b13206538c02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=35847966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.35847966
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3881837242
Short name T32
Test name
Test status
Simulation time 29866273645 ps
CPU time 370.32 seconds
Started Jul 12 06:04:08 PM PDT 24
Finished Jul 12 06:10:19 PM PDT 24
Peak memory 202692 kb
Host smart-0060ebec-1f30-45c6-bd2d-8273c2bfc9d7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881837242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.3881837242
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3970486578
Short name T44
Test name
Test status
Simulation time 3434546072 ps
CPU time 37.48 seconds
Started Jul 12 06:05:29 PM PDT 24
Finished Jul 12 06:06:08 PM PDT 24
Peak memory 262072 kb
Host smart-2ffe9734-c305-4644-afa6-c8239273fe15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3970486578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3970486578
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3919310558
Short name T80
Test name
Test status
Simulation time 22904206598 ps
CPU time 55.15 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 203076 kb
Host smart-51f8c600-aa1c-4d4a-9634-471076f23261
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919310558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3919310558
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.4210745320
Short name T108
Test name
Test status
Simulation time 9562182648 ps
CPU time 348.89 seconds
Started Jul 12 06:01:08 PM PDT 24
Finished Jul 12 06:06:58 PM PDT 24
Peak memory 202752 kb
Host smart-f0ace7aa-5107-4625-8816-b41fece3227e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210745320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.4210745320
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/8.sram_ctrl_executable.114232377
Short name T140
Test name
Test status
Simulation time 14472691122 ps
CPU time 1670.69 seconds
Started Jul 12 06:00:48 PM PDT 24
Finished Jul 12 06:28:41 PM PDT 24
Peak memory 378676 kb
Host smart-8453e948-6577-461b-8b45-8b991c9d864e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114232377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable
.114232377
Directory /workspace/8.sram_ctrl_executable/latest


Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.551003559
Short name T25
Test name
Test status
Simulation time 1398117635 ps
CPU time 3.61 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:01:02 PM PDT 24
Peak memory 202776 kb
Host smart-be5d87e8-4cf9-4ac6-b660-aed5e316337b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551003559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.551003559
Directory /workspace/10.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2775751001
Short name T126
Test name
Test status
Simulation time 328461136 ps
CPU time 2.33 seconds
Started Jul 12 06:39:37 PM PDT 24
Finished Jul 12 06:39:44 PM PDT 24
Peak memory 210632 kb
Host smart-f559ab42-59dc-437a-b0e7-7377b5a7cf77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775751001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2775751001
Directory /workspace/2.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/default/13.sram_ctrl_alert_test.2462113334
Short name T102
Test name
Test status
Simulation time 28083536 ps
CPU time 0.67 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:01:04 PM PDT 24
Peak memory 202484 kb
Host smart-a49c0431-3af8-487b-b971-0fab34cd8ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462113334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.2462113334
Directory /workspace/13.sram_ctrl_alert_test/latest


Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3198556682
Short name T133
Test name
Test status
Simulation time 412900818 ps
CPU time 2.42 seconds
Started Jul 12 06:39:38 PM PDT 24
Finished Jul 12 06:39:44 PM PDT 24
Peak memory 211088 kb
Host smart-84efd6bf-b45c-42e2-a800-b49c685bd3f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198556682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.3198556682
Directory /workspace/12.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4101639862
Short name T135
Test name
Test status
Simulation time 358395926 ps
CPU time 2.71 seconds
Started Jul 12 06:39:52 PM PDT 24
Finished Jul 12 06:39:56 PM PDT 24
Peak memory 202912 kb
Host smart-842bf862-e4f4-4368-a9b1-fc46d21bd87f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101639862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.4101639862
Directory /workspace/17.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2858180781
Short name T142
Test name
Test status
Simulation time 39236612387 ps
CPU time 499.48 seconds
Started Jul 12 06:00:23 PM PDT 24
Finished Jul 12 06:08:46 PM PDT 24
Peak memory 202820 kb
Host smart-ee3349db-2048-415b-9323-634e0b80358d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858180781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.2858180781
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2304741565
Short name T129
Test name
Test status
Simulation time 306955835 ps
CPU time 1.61 seconds
Started Jul 12 06:39:43 PM PDT 24
Finished Jul 12 06:39:47 PM PDT 24
Peak memory 202900 kb
Host smart-3f48fd2f-c28e-46ee-a4b6-2f86f6dc78e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304741565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.2304741565
Directory /workspace/15.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.1857092497
Short name T146
Test name
Test status
Simulation time 10794906187 ps
CPU time 41.89 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:01:15 PM PDT 24
Peak memory 202812 kb
Host smart-1f431b6a-1afd-48e9-90b3-60858c1e8bb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857092497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.1857092497
Directory /workspace/0.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.818021873
Short name T61
Test name
Test status
Simulation time 75570632 ps
CPU time 0.69 seconds
Started Jul 12 06:39:28 PM PDT 24
Finished Jul 12 06:39:35 PM PDT 24
Peak memory 202620 kb
Host smart-bb8aebbb-bd5f-4fd2-8391-ae1328ed80a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818021873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_hw_reset.818021873
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2039000855
Short name T1005
Test name
Test status
Simulation time 15152745 ps
CPU time 0.66 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:39 PM PDT 24
Peak memory 202564 kb
Host smart-ecc6c2ee-7b80-4005-8f52-40964f758aa2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039000855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.2039000855
Directory /workspace/0.sram_ctrl_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3295769002
Short name T970
Test name
Test status
Simulation time 125266379 ps
CPU time 2.01 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:39:37 PM PDT 24
Peak memory 202932 kb
Host smart-d17c4ddf-d905-48b2-901e-2b92e2d82691
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295769002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.3295769002
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1088595275
Short name T967
Test name
Test status
Simulation time 351650712 ps
CPU time 3.46 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:37 PM PDT 24
Peak memory 210860 kb
Host smart-0c35b02e-fc9b-496d-9d05-49d39b403791
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088595275 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1088595275
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.667224229
Short name T979
Test name
Test status
Simulation time 79289334 ps
CPU time 0.7 seconds
Started Jul 12 06:39:28 PM PDT 24
Finished Jul 12 06:39:34 PM PDT 24
Peak memory 202684 kb
Host smart-e3e8183b-5f16-49c3-9f3e-50d2cd67fb80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667224229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.sram_ctrl_csr_rw.667224229
Directory /workspace/0.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3333749557
Short name T98
Test name
Test status
Simulation time 3790457300 ps
CPU time 24.42 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:53 PM PDT 24
Peak memory 202872 kb
Host smart-4ee17f6a-0c2f-4436-8cbc-b4f8b6c922a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333749557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3333749557
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2931516908
Short name T79
Test name
Test status
Simulation time 23470081 ps
CPU time 0.68 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:39 PM PDT 24
Peak memory 202656 kb
Host smart-b958a6a0-ba7e-4019-8308-6e47463f5adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931516908 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2931516908
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3136322180
Short name T1007
Test name
Test status
Simulation time 88602738 ps
CPU time 3.76 seconds
Started Jul 12 06:39:22 PM PDT 24
Finished Jul 12 06:39:32 PM PDT 24
Peak memory 211064 kb
Host smart-617d8db5-efa2-4272-a825-f444de423201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136322180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.3136322180
Directory /workspace/0.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4043823298
Short name T127
Test name
Test status
Simulation time 99579428 ps
CPU time 1.49 seconds
Started Jul 12 06:39:20 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 211112 kb
Host smart-2fa90424-7d34-4d9a-aa8a-b19eb6a402d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043823298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.4043823298
Directory /workspace/0.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.597949434
Short name T1034
Test name
Test status
Simulation time 20447850 ps
CPU time 0.73 seconds
Started Jul 12 06:39:37 PM PDT 24
Finished Jul 12 06:39:42 PM PDT 24
Peak memory 202648 kb
Host smart-ff9ec919-40a5-4e55-8ed8-895a427adaec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597949434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_aliasing.597949434
Directory /workspace/1.sram_ctrl_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3689436868
Short name T1036
Test name
Test status
Simulation time 228443769 ps
CPU time 1.98 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:39:36 PM PDT 24
Peak memory 202884 kb
Host smart-1edacfa8-cc47-41eb-a5d4-7ab25edc5592
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689436868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.3689436868
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.604284294
Short name T62
Test name
Test status
Simulation time 18131726 ps
CPU time 0.69 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:39:35 PM PDT 24
Peak memory 202636 kb
Host smart-92088c0a-438f-432b-becf-43e6706455e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604284294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_hw_reset.604284294
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3700160311
Short name T1003
Test name
Test status
Simulation time 350119570 ps
CPU time 3.45 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:42 PM PDT 24
Peak memory 210896 kb
Host smart-14572ea9-617d-413a-a0d4-9d0533d5aaba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700160311 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3700160311
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4206171592
Short name T1019
Test name
Test status
Simulation time 20813269 ps
CPU time 0.68 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:34 PM PDT 24
Peak memory 202916 kb
Host smart-77eeeb58-5d70-4f26-b57d-b82f7caf3daa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206171592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.4206171592
Directory /workspace/1.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3139395279
Short name T995
Test name
Test status
Simulation time 15376373283 ps
CPU time 26.92 seconds
Started Jul 12 06:39:28 PM PDT 24
Finished Jul 12 06:40:00 PM PDT 24
Peak memory 202916 kb
Host smart-f0f07115-fd71-4f3f-88ca-8f33168fd00c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139395279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3139395279
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3945349988
Short name T1032
Test name
Test status
Simulation time 21037563 ps
CPU time 0.71 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:39:35 PM PDT 24
Peak memory 202612 kb
Host smart-82e16651-412b-46f1-84fb-ff179c5c320c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945349988 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3945349988
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.681508594
Short name T1011
Test name
Test status
Simulation time 600097330 ps
CPU time 4.95 seconds
Started Jul 12 06:39:26 PM PDT 24
Finished Jul 12 06:39:37 PM PDT 24
Peak memory 211080 kb
Host smart-c226c5ac-936c-4f31-9c65-07e31ba9e18b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681508594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_tl_errors.681508594
Directory /workspace/1.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2819188421
Short name T125
Test name
Test status
Simulation time 352565017 ps
CPU time 1.54 seconds
Started Jul 12 06:39:35 PM PDT 24
Finished Jul 12 06:39:42 PM PDT 24
Peak memory 202992 kb
Host smart-209fef37-19c2-47cd-8020-9e65c5a8f6c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819188421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.2819188421
Directory /workspace/1.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2915375792
Short name T986
Test name
Test status
Simulation time 354885367 ps
CPU time 3.86 seconds
Started Jul 12 06:39:39 PM PDT 24
Finished Jul 12 06:39:47 PM PDT 24
Peak memory 210936 kb
Host smart-3417e8af-7a97-4adf-8d3e-fdd1b1c2985f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915375792 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2915375792
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2180978408
Short name T985
Test name
Test status
Simulation time 34693817 ps
CPU time 0.67 seconds
Started Jul 12 06:39:35 PM PDT 24
Finished Jul 12 06:39:40 PM PDT 24
Peak memory 202628 kb
Host smart-a0dc549b-795d-43d7-a15c-0db0066a1939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180978408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.2180978408
Directory /workspace/10.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2614369569
Short name T97
Test name
Test status
Simulation time 7540732272 ps
CPU time 26.83 seconds
Started Jul 12 06:39:38 PM PDT 24
Finished Jul 12 06:40:09 PM PDT 24
Peak memory 202860 kb
Host smart-d29631ba-e00e-41e0-8562-2b957b986cfa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614369569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2614369569
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2886472682
Short name T957
Test name
Test status
Simulation time 212448874 ps
CPU time 0.83 seconds
Started Jul 12 06:39:35 PM PDT 24
Finished Jul 12 06:39:40 PM PDT 24
Peak memory 202628 kb
Host smart-1d6f3f7a-4ac4-40d0-bdf0-7786ac664343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886472682 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2886472682
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.740978112
Short name T958
Test name
Test status
Simulation time 400268374 ps
CPU time 4.21 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:45 PM PDT 24
Peak memory 211080 kb
Host smart-3ba46205-140f-4c16-a7a3-1eead55cc47e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740978112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_tl_errors.740978112
Directory /workspace/10.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3635789654
Short name T130
Test name
Test status
Simulation time 381272605 ps
CPU time 2.36 seconds
Started Jul 12 06:39:38 PM PDT 24
Finished Jul 12 06:39:45 PM PDT 24
Peak memory 211020 kb
Host smart-ccf849ee-3593-4105-bbed-4b5146744802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635789654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.3635789654
Directory /workspace/10.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4086566424
Short name T952
Test name
Test status
Simulation time 373972144 ps
CPU time 4.08 seconds
Started Jul 12 06:39:35 PM PDT 24
Finished Jul 12 06:39:44 PM PDT 24
Peak memory 211040 kb
Host smart-f69e8e3a-68d0-4d09-a1b2-8c1726297d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086566424 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.4086566424
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.359498218
Short name T1016
Test name
Test status
Simulation time 40354173 ps
CPU time 0.65 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 202612 kb
Host smart-5692ebb3-41bb-477a-b1cd-40054df231dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359498218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 11.sram_ctrl_csr_rw.359498218
Directory /workspace/11.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2609380838
Short name T99
Test name
Test status
Simulation time 7391862594 ps
CPU time 31.14 seconds
Started Jul 12 06:39:37 PM PDT 24
Finished Jul 12 06:40:13 PM PDT 24
Peak memory 202924 kb
Host smart-6131f09a-45da-49f4-9d5a-5a2b391bed02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609380838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.2609380838
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3126123733
Short name T1031
Test name
Test status
Simulation time 26455315 ps
CPU time 0.77 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:42 PM PDT 24
Peak memory 202684 kb
Host smart-00e78939-c167-4637-ac97-578fcd851538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126123733 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.3126123733
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.640516727
Short name T1013
Test name
Test status
Simulation time 27802675 ps
CPU time 2.08 seconds
Started Jul 12 06:39:38 PM PDT 24
Finished Jul 12 06:39:45 PM PDT 24
Peak memory 202868 kb
Host smart-c891ff2f-1454-49e2-adaf-ee4451d656c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640516727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.640516727
Directory /workspace/11.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3749520387
Short name T57
Test name
Test status
Simulation time 533822064 ps
CPU time 1.64 seconds
Started Jul 12 06:39:37 PM PDT 24
Finished Jul 12 06:39:43 PM PDT 24
Peak memory 211096 kb
Host smart-7d39a5af-d3a6-42e4-adfa-fb4a58d2e6a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749520387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.3749520387
Directory /workspace/11.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2050526030
Short name T950
Test name
Test status
Simulation time 757186403 ps
CPU time 4.06 seconds
Started Jul 12 06:39:45 PM PDT 24
Finished Jul 12 06:39:52 PM PDT 24
Peak memory 212532 kb
Host smart-63d36b82-830d-4d3f-a05e-132221aa1ce5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050526030 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2050526030
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.312589871
Short name T88
Test name
Test status
Simulation time 43335366 ps
CPU time 0.69 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:42 PM PDT 24
Peak memory 202628 kb
Host smart-44548f3f-76b5-4e73-8500-de129d916261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312589871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 12.sram_ctrl_csr_rw.312589871
Directory /workspace/12.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2846978387
Short name T60
Test name
Test status
Simulation time 28633499632 ps
CPU time 52.92 seconds
Started Jul 12 06:39:32 PM PDT 24
Finished Jul 12 06:40:30 PM PDT 24
Peak memory 211248 kb
Host smart-d45334fa-19a5-4303-99fe-40701f7c0639
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846978387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2846978387
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3578760242
Short name T953
Test name
Test status
Simulation time 15909753 ps
CPU time 0.75 seconds
Started Jul 12 06:39:43 PM PDT 24
Finished Jul 12 06:39:46 PM PDT 24
Peak memory 202696 kb
Host smart-81c43587-3dc3-43b2-a099-f39e493b6aac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578760242 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3578760242
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2503039863
Short name T1012
Test name
Test status
Simulation time 152321634 ps
CPU time 4.03 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:45 PM PDT 24
Peak memory 211084 kb
Host smart-449a6fd0-eaa5-4c9f-8b24-a5012b14c1b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503039863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.2503039863
Directory /workspace/12.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1877570869
Short name T1015
Test name
Test status
Simulation time 356648917 ps
CPU time 3.46 seconds
Started Jul 12 06:39:41 PM PDT 24
Finished Jul 12 06:39:48 PM PDT 24
Peak memory 210896 kb
Host smart-1f22c732-99ac-4ba1-bf9a-657767673267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877570869 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1877570869
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3903212868
Short name T996
Test name
Test status
Simulation time 35954459 ps
CPU time 0.66 seconds
Started Jul 12 06:39:42 PM PDT 24
Finished Jul 12 06:39:46 PM PDT 24
Peak memory 202660 kb
Host smart-8ad17367-d549-4ebc-a172-73be2706846d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903212868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.3903212868
Directory /workspace/13.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.688150244
Short name T83
Test name
Test status
Simulation time 15387632181 ps
CPU time 30.45 seconds
Started Jul 12 06:39:42 PM PDT 24
Finished Jul 12 06:40:15 PM PDT 24
Peak memory 202920 kb
Host smart-cf0eec57-11f1-4983-bfae-34a79c4f64c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688150244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.688150244
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3234718903
Short name T1035
Test name
Test status
Simulation time 16221721 ps
CPU time 0.73 seconds
Started Jul 12 06:39:41 PM PDT 24
Finished Jul 12 06:39:45 PM PDT 24
Peak memory 202648 kb
Host smart-3121af3f-99e0-4279-abbb-b16b5b496e76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234718903 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3234718903
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3979095668
Short name T1025
Test name
Test status
Simulation time 712926811 ps
CPU time 2.57 seconds
Started Jul 12 06:39:42 PM PDT 24
Finished Jul 12 06:39:47 PM PDT 24
Peak memory 202840 kb
Host smart-21317507-7906-4069-927c-f8fd5791fd3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979095668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.3979095668
Directory /workspace/13.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3255934888
Short name T138
Test name
Test status
Simulation time 274206281 ps
CPU time 2.66 seconds
Started Jul 12 06:39:43 PM PDT 24
Finished Jul 12 06:39:48 PM PDT 24
Peak memory 211084 kb
Host smart-b9ea2634-2ffc-41e4-bb9c-0aaac60425b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255934888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.3255934888
Directory /workspace/13.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1735321532
Short name T949
Test name
Test status
Simulation time 351857687 ps
CPU time 3.79 seconds
Started Jul 12 06:39:40 PM PDT 24
Finished Jul 12 06:39:48 PM PDT 24
Peak memory 211068 kb
Host smart-0a686935-3db7-4a6d-a5e5-8638bf1d0586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735321532 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1735321532
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3493672305
Short name T78
Test name
Test status
Simulation time 41517289 ps
CPU time 0.69 seconds
Started Jul 12 06:39:41 PM PDT 24
Finished Jul 12 06:39:45 PM PDT 24
Peak memory 202696 kb
Host smart-3bca047c-38e7-4008-a86e-a86ac41dc591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493672305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.3493672305
Directory /workspace/14.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2223358336
Short name T100
Test name
Test status
Simulation time 7358944309 ps
CPU time 52.26 seconds
Started Jul 12 06:39:40 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 203124 kb
Host smart-21392377-d2fb-47ee-889f-5af61949ecbc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223358336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2223358336
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2950082993
Short name T1033
Test name
Test status
Simulation time 52639231 ps
CPU time 0.73 seconds
Started Jul 12 06:39:45 PM PDT 24
Finished Jul 12 06:39:48 PM PDT 24
Peak memory 202860 kb
Host smart-090b4361-5aa5-43f8-992a-68f42a786434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950082993 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.2950082993
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2612493166
Short name T992
Test name
Test status
Simulation time 125352870 ps
CPU time 3.32 seconds
Started Jul 12 06:39:42 PM PDT 24
Finished Jul 12 06:39:49 PM PDT 24
Peak memory 211104 kb
Host smart-1e111973-7fe1-4eaa-bca5-d0e10ba131d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612493166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.2612493166
Directory /workspace/14.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1597003112
Short name T993
Test name
Test status
Simulation time 326095991 ps
CPU time 1.55 seconds
Started Jul 12 06:39:45 PM PDT 24
Finished Jul 12 06:39:49 PM PDT 24
Peak memory 211096 kb
Host smart-1eb1889c-62f9-4e44-ae31-1ed824398c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597003112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.1597003112
Directory /workspace/14.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2049266054
Short name T1001
Test name
Test status
Simulation time 1316051698 ps
CPU time 3.4 seconds
Started Jul 12 06:39:43 PM PDT 24
Finished Jul 12 06:39:49 PM PDT 24
Peak memory 210916 kb
Host smart-eaa07296-d4d7-4103-a3fc-3fab490e674c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049266054 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2049266054
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1676362788
Short name T966
Test name
Test status
Simulation time 27579858 ps
CPU time 0.7 seconds
Started Jul 12 06:39:42 PM PDT 24
Finished Jul 12 06:39:46 PM PDT 24
Peak memory 202588 kb
Host smart-86d2ce05-f81d-432b-972f-0e39dbf8e76e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676362788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.1676362788
Directory /workspace/15.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3784598168
Short name T977
Test name
Test status
Simulation time 3719046421 ps
CPU time 27.39 seconds
Started Jul 12 06:39:43 PM PDT 24
Finished Jul 12 06:40:13 PM PDT 24
Peak memory 202900 kb
Host smart-8460c44c-8f0e-4aad-8924-c310473e7d22
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784598168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3784598168
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2098065569
Short name T106
Test name
Test status
Simulation time 17398520 ps
CPU time 0.72 seconds
Started Jul 12 06:39:42 PM PDT 24
Finished Jul 12 06:39:46 PM PDT 24
Peak memory 202692 kb
Host smart-d05ffe62-891b-4923-bd4a-f89a5f03438e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098065569 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2098065569
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4142644704
Short name T968
Test name
Test status
Simulation time 441044103 ps
CPU time 4.1 seconds
Started Jul 12 06:39:42 PM PDT 24
Finished Jul 12 06:39:49 PM PDT 24
Peak memory 211356 kb
Host smart-55736804-8718-43f6-b16d-fbf5939c0c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142644704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.4142644704
Directory /workspace/15.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3517945971
Short name T1009
Test name
Test status
Simulation time 351747286 ps
CPU time 3.89 seconds
Started Jul 12 06:39:46 PM PDT 24
Finished Jul 12 06:39:52 PM PDT 24
Peak memory 212352 kb
Host smart-ec59d9a0-3b40-4d8f-864e-59544f8d2e7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517945971 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3517945971
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.221723386
Short name T980
Test name
Test status
Simulation time 39264491 ps
CPU time 0.67 seconds
Started Jul 12 06:39:51 PM PDT 24
Finished Jul 12 06:39:52 PM PDT 24
Peak memory 202676 kb
Host smart-3662acda-b11b-4cc7-a348-6aa24969e828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221723386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_csr_rw.221723386
Directory /workspace/16.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.428515037
Short name T997
Test name
Test status
Simulation time 14679315215 ps
CPU time 54.67 seconds
Started Jul 12 06:39:49 PM PDT 24
Finished Jul 12 06:40:45 PM PDT 24
Peak memory 203104 kb
Host smart-83f34b85-b696-4c21-be36-8294ec9e6a5f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428515037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.428515037
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.765424813
Short name T991
Test name
Test status
Simulation time 21464508 ps
CPU time 0.74 seconds
Started Jul 12 06:39:46 PM PDT 24
Finished Jul 12 06:39:49 PM PDT 24
Peak memory 202620 kb
Host smart-72becbc5-a9b8-4784-93a6-c70cb0981340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765424813 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.765424813
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3214618414
Short name T1023
Test name
Test status
Simulation time 83553529 ps
CPU time 2.71 seconds
Started Jul 12 06:39:46 PM PDT 24
Finished Jul 12 06:39:51 PM PDT 24
Peak memory 210996 kb
Host smart-deb7d55e-d351-4646-bbce-a18d34d8be47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214618414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.3214618414
Directory /workspace/16.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3467824779
Short name T1000
Test name
Test status
Simulation time 2023639530 ps
CPU time 4.49 seconds
Started Jul 12 06:39:46 PM PDT 24
Finished Jul 12 06:39:52 PM PDT 24
Peak memory 212216 kb
Host smart-021b2aa2-de2d-483d-9e15-4aa7dff2b772
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467824779 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3467824779
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.928844255
Short name T962
Test name
Test status
Simulation time 12091360 ps
CPU time 0.69 seconds
Started Jul 12 06:39:49 PM PDT 24
Finished Jul 12 06:39:51 PM PDT 24
Peak memory 202672 kb
Host smart-e6c27dde-661f-40a3-add0-1a232a098e7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928844255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 17.sram_ctrl_csr_rw.928844255
Directory /workspace/17.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2974110275
Short name T1029
Test name
Test status
Simulation time 14694856340 ps
CPU time 56.34 seconds
Started Jul 12 06:39:47 PM PDT 24
Finished Jul 12 06:40:45 PM PDT 24
Peak memory 211280 kb
Host smart-8d0507e7-2982-4e52-8eb1-09cb3ea17f7d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974110275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2974110275
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2939496243
Short name T1028
Test name
Test status
Simulation time 45670797 ps
CPU time 0.69 seconds
Started Jul 12 06:39:52 PM PDT 24
Finished Jul 12 06:39:54 PM PDT 24
Peak memory 202684 kb
Host smart-a525a8b4-65fc-4ec2-821b-ecfaeb946586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939496243 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.2939496243
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2626151157
Short name T1030
Test name
Test status
Simulation time 69478974 ps
CPU time 2.35 seconds
Started Jul 12 06:39:46 PM PDT 24
Finished Jul 12 06:39:50 PM PDT 24
Peak memory 211272 kb
Host smart-617281aa-6fba-4225-928b-4d81bab784da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626151157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.2626151157
Directory /workspace/17.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1405747836
Short name T1002
Test name
Test status
Simulation time 1436881617 ps
CPU time 3.28 seconds
Started Jul 12 06:39:50 PM PDT 24
Finished Jul 12 06:39:55 PM PDT 24
Peak memory 210900 kb
Host smart-c8664bca-a864-4b06-8ee4-5e9896e4a3f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405747836 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1405747836
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3654045375
Short name T959
Test name
Test status
Simulation time 36856489 ps
CPU time 0.72 seconds
Started Jul 12 06:39:47 PM PDT 24
Finished Jul 12 06:39:49 PM PDT 24
Peak memory 202664 kb
Host smart-f78d1dae-8017-4659-b364-f3e2d108dd17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654045375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.3654045375
Directory /workspace/18.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.86060543
Short name T960
Test name
Test status
Simulation time 7524355544 ps
CPU time 30.1 seconds
Started Jul 12 06:39:49 PM PDT 24
Finished Jul 12 06:40:20 PM PDT 24
Peak memory 202792 kb
Host smart-cce34f68-efef-443c-b4ca-84e7906301be
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86060543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base
_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.86060543
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1901687652
Short name T1021
Test name
Test status
Simulation time 82651904 ps
CPU time 0.77 seconds
Started Jul 12 06:39:48 PM PDT 24
Finished Jul 12 06:39:50 PM PDT 24
Peak memory 202672 kb
Host smart-65e36bcf-5fe5-4120-98a4-512c9725ced5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901687652 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1901687652
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1297793032
Short name T1018
Test name
Test status
Simulation time 240143862 ps
CPU time 2.2 seconds
Started Jul 12 06:39:46 PM PDT 24
Finished Jul 12 06:39:50 PM PDT 24
Peak memory 202880 kb
Host smart-444d97bf-3bf8-4249-b3ff-5d2b16664359
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297793032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.1297793032
Directory /workspace/18.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.758318209
Short name T134
Test name
Test status
Simulation time 580995989 ps
CPU time 1.62 seconds
Started Jul 12 06:39:50 PM PDT 24
Finished Jul 12 06:39:53 PM PDT 24
Peak memory 202904 kb
Host smart-43580fe6-b6fc-4fa5-8c50-a8b10d099473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758318209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.sram_ctrl_tl_intg_err.758318209
Directory /workspace/18.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2008306013
Short name T983
Test name
Test status
Simulation time 359148520 ps
CPU time 3.25 seconds
Started Jul 12 06:39:48 PM PDT 24
Finished Jul 12 06:39:53 PM PDT 24
Peak memory 210948 kb
Host smart-1bb9fbe4-7d0a-4236-92e9-f13ee620e878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008306013 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.2008306013
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2482370215
Short name T1017
Test name
Test status
Simulation time 13981067 ps
CPU time 0.66 seconds
Started Jul 12 06:39:49 PM PDT 24
Finished Jul 12 06:39:52 PM PDT 24
Peak memory 202612 kb
Host smart-51607d74-eaca-417e-a13b-65939bc398de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482370215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.2482370215
Directory /workspace/19.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2066313296
Short name T84
Test name
Test status
Simulation time 14723563706 ps
CPU time 49.02 seconds
Started Jul 12 06:39:50 PM PDT 24
Finished Jul 12 06:40:40 PM PDT 24
Peak memory 203312 kb
Host smart-f95ddfb6-6212-46a1-bd24-2d265c544fe3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066313296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2066313296
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3947405120
Short name T104
Test name
Test status
Simulation time 19610694 ps
CPU time 0.72 seconds
Started Jul 12 06:39:48 PM PDT 24
Finished Jul 12 06:39:50 PM PDT 24
Peak memory 202656 kb
Host smart-a5ffad07-99e4-4296-a4da-482696a13c9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947405120 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3947405120
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3249861413
Short name T999
Test name
Test status
Simulation time 62236787 ps
CPU time 2.36 seconds
Started Jul 12 06:39:47 PM PDT 24
Finished Jul 12 06:39:51 PM PDT 24
Peak memory 211076 kb
Host smart-4a48f3a2-9925-4f40-819f-33efc8a36e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249861413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.3249861413
Directory /workspace/19.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3209649726
Short name T1014
Test name
Test status
Simulation time 1317412736 ps
CPU time 1.4 seconds
Started Jul 12 06:39:51 PM PDT 24
Finished Jul 12 06:39:54 PM PDT 24
Peak memory 211096 kb
Host smart-fda332c7-912c-47e7-8837-6f235847c80f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209649726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.3209649726
Directory /workspace/19.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.241843929
Short name T85
Test name
Test status
Simulation time 48065050 ps
CPU time 0.67 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:39:35 PM PDT 24
Peak memory 202560 kb
Host smart-e578a770-c43a-4a2d-9fa6-3d278b9e65b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241843929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_aliasing.241843929
Directory /workspace/2.sram_ctrl_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3875749160
Short name T971
Test name
Test status
Simulation time 416578144 ps
CPU time 2.16 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 202876 kb
Host smart-3c5466f3-247d-4b71-b90e-c1bc1330841e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875749160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.3875749160
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3099138836
Short name T1020
Test name
Test status
Simulation time 23090934 ps
CPU time 0.67 seconds
Started Jul 12 06:39:28 PM PDT 24
Finished Jul 12 06:39:34 PM PDT 24
Peak memory 202396 kb
Host smart-345264d0-c14a-4d58-8dcc-570aa78a98ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099138836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.3099138836
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1841317962
Short name T1026
Test name
Test status
Simulation time 372030049 ps
CPU time 3.46 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:37 PM PDT 24
Peak memory 210960 kb
Host smart-702ee24b-919e-4e3d-83d4-7413153b1eed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841317962 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1841317962
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1817433889
Short name T951
Test name
Test status
Simulation time 40087661 ps
CPU time 0.67 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:39 PM PDT 24
Peak memory 202552 kb
Host smart-38fe7847-9555-4c8c-b8c0-80e06ac0203b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817433889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.1817433889
Directory /workspace/2.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.607926815
Short name T994
Test name
Test status
Simulation time 19404229188 ps
CPU time 33.21 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:40:08 PM PDT 24
Peak memory 202984 kb
Host smart-2e8f3286-cbba-4558-93a1-18cad716847a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607926815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.607926815
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1611936671
Short name T107
Test name
Test status
Simulation time 15687146 ps
CPU time 0.76 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:34 PM PDT 24
Peak memory 202684 kb
Host smart-0d16c155-0fd9-4d51-badb-add133a79218
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611936671 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1611936671
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3025834369
Short name T1022
Test name
Test status
Simulation time 137505870 ps
CPU time 3.59 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 202880 kb
Host smart-e279bc58-3284-449f-a1eb-5e3e5fbb25b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025834369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.3025834369
Directory /workspace/2.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2551578528
Short name T987
Test name
Test status
Simulation time 48477576 ps
CPU time 0.71 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 202656 kb
Host smart-d4eb0b33-7997-4916-917a-34f3bbd0aa2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551578528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.2551578528
Directory /workspace/3.sram_ctrl_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1129671625
Short name T954
Test name
Test status
Simulation time 311419933 ps
CPU time 1.55 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:42 PM PDT 24
Peak memory 202852 kb
Host smart-2810a000-0037-4272-9671-08b3da7a4c2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129671625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1129671625
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2651075030
Short name T75
Test name
Test status
Simulation time 24379797 ps
CPU time 0.66 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:39:35 PM PDT 24
Peak memory 202556 kb
Host smart-1e2d13b0-e91b-442c-a584-2a74f7671a0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651075030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.2651075030
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2029762974
Short name T963
Test name
Test status
Simulation time 373294762 ps
CPU time 5.08 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:44 PM PDT 24
Peak memory 211048 kb
Host smart-3cbffcce-719e-4250-8d69-038ae0206d3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029762974 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2029762974
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.523334552
Short name T76
Test name
Test status
Simulation time 12403887 ps
CPU time 0.67 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 202668 kb
Host smart-f5be6aca-9a1d-4798-a2e3-b3757d8da7b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523334552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_csr_rw.523334552
Directory /workspace/3.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3023609514
Short name T77
Test name
Test status
Simulation time 7116282240 ps
CPU time 54.41 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 203072 kb
Host smart-52722de1-a61b-4900-a4ec-19139e982375
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023609514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3023609514
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3423489378
Short name T972
Test name
Test status
Simulation time 47802551 ps
CPU time 0.77 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:34 PM PDT 24
Peak memory 202660 kb
Host smart-12fc950e-8b06-491b-8f5a-18de1f62c860
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423489378 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3423489378
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4054511032
Short name T978
Test name
Test status
Simulation time 43283755 ps
CPU time 1.81 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:35 PM PDT 24
Peak memory 211112 kb
Host smart-bb536197-12cb-422c-b8c2-b35dd28d0b49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054511032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.4054511032
Directory /workspace/3.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3891303208
Short name T56
Test name
Test status
Simulation time 348062263 ps
CPU time 2.33 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:39:37 PM PDT 24
Peak memory 202824 kb
Host smart-29518bf7-59a2-4f37-8b05-71a75bd8fe73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891303208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.3891303208
Directory /workspace/3.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1352689477
Short name T87
Test name
Test status
Simulation time 15119372 ps
CPU time 0.73 seconds
Started Jul 12 06:39:26 PM PDT 24
Finished Jul 12 06:39:33 PM PDT 24
Peak memory 202708 kb
Host smart-bce51482-a488-4ed9-944f-1a7220084d20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352689477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.1352689477
Directory /workspace/4.sram_ctrl_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.940646122
Short name T969
Test name
Test status
Simulation time 247755138 ps
CPU time 1.45 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:34 PM PDT 24
Peak memory 202828 kb
Host smart-053cf385-d39f-408b-9670-df81b12f7105
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940646122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_bit_bash.940646122
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.644592678
Short name T990
Test name
Test status
Simulation time 14394537 ps
CPU time 0.67 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:34 PM PDT 24
Peak memory 202668 kb
Host smart-8e6ec82c-212c-4e3b-a17f-d038b137fc99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644592678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_hw_reset.644592678
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1567035744
Short name T964
Test name
Test status
Simulation time 2117189234 ps
CPU time 3.81 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:37 PM PDT 24
Peak memory 202684 kb
Host smart-ae86e1a1-135f-4bc1-8bc3-838e93303326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567035744 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1567035744
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3243429422
Short name T74
Test name
Test status
Simulation time 27535335 ps
CPU time 0.66 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:39:34 PM PDT 24
Peak memory 202520 kb
Host smart-ef82225e-6af9-4a17-ae56-75e761da200c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243429422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3243429422
Directory /workspace/4.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1119332869
Short name T998
Test name
Test status
Simulation time 12737544802 ps
CPU time 31.97 seconds
Started Jul 12 06:39:31 PM PDT 24
Finished Jul 12 06:40:08 PM PDT 24
Peak memory 202908 kb
Host smart-63256f26-8863-40e1-8cb5-992904cc470a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119332869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1119332869
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1151619755
Short name T974
Test name
Test status
Simulation time 160978732 ps
CPU time 0.74 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:39 PM PDT 24
Peak memory 202656 kb
Host smart-e505ce15-3ec4-410a-a337-8db1ce5cf6a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151619755 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1151619755
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.288806045
Short name T955
Test name
Test status
Simulation time 273166038 ps
CPU time 2.49 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 211056 kb
Host smart-fda5327f-35fc-4bb7-b2d7-84211c6dabe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288806045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_tl_errors.288806045
Directory /workspace/4.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1251794318
Short name T131
Test name
Test status
Simulation time 868334186 ps
CPU time 2.73 seconds
Started Jul 12 06:39:31 PM PDT 24
Finished Jul 12 06:39:39 PM PDT 24
Peak memory 211132 kb
Host smart-5791090d-e473-48a3-856b-f4da789a04a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251794318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.1251794318
Directory /workspace/4.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.828314258
Short name T982
Test name
Test status
Simulation time 1479059761 ps
CPU time 3.75 seconds
Started Jul 12 06:39:31 PM PDT 24
Finished Jul 12 06:39:40 PM PDT 24
Peak memory 210924 kb
Host smart-b3621e07-159d-473b-b79b-d99256d318c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828314258 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.828314258
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3197030539
Short name T981
Test name
Test status
Simulation time 14694797 ps
CPU time 0.72 seconds
Started Jul 12 06:39:31 PM PDT 24
Finished Jul 12 06:39:37 PM PDT 24
Peak memory 202696 kb
Host smart-b2b46eb7-56db-4558-a951-081bb88698c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197030539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.3197030539
Directory /workspace/5.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3556278443
Short name T961
Test name
Test status
Simulation time 49515743 ps
CPU time 0.76 seconds
Started Jul 12 06:39:34 PM PDT 24
Finished Jul 12 06:39:40 PM PDT 24
Peak memory 202692 kb
Host smart-aea0c022-0d16-4e1c-aca0-39159e50818e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556278443 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3556278443
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3355805822
Short name T973
Test name
Test status
Simulation time 76607766 ps
CPU time 2.11 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:42 PM PDT 24
Peak memory 211068 kb
Host smart-4b48b3da-d391-47ac-a3db-c14e51efd71e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355805822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.3355805822
Directory /workspace/5.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.769674832
Short name T128
Test name
Test status
Simulation time 126692929 ps
CPU time 1.52 seconds
Started Jul 12 06:39:29 PM PDT 24
Finished Jul 12 06:39:36 PM PDT 24
Peak memory 211108 kb
Host smart-a64a5455-908d-400a-a6c2-8b896c9f2046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769674832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.sram_ctrl_tl_intg_err.769674832
Directory /workspace/5.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3254246012
Short name T1027
Test name
Test status
Simulation time 3196709109 ps
CPU time 5.09 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:43 PM PDT 24
Peak memory 211144 kb
Host smart-384ce8a6-d41a-477a-8994-2478a378675d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254246012 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3254246012
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.247555933
Short name T975
Test name
Test status
Simulation time 14894121 ps
CPU time 0.66 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 202656 kb
Host smart-bc25cebf-7244-4e50-ab70-6ee3b1af2c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247555933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_csr_rw.247555933
Directory /workspace/6.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.591296928
Short name T94
Test name
Test status
Simulation time 29424991727 ps
CPU time 56.87 seconds
Started Jul 12 06:39:27 PM PDT 24
Finished Jul 12 06:40:30 PM PDT 24
Peak memory 203068 kb
Host smart-3cd05887-47d9-4ef4-bc0c-f9c93d559437
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591296928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.591296928
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2225703490
Short name T1037
Test name
Test status
Simulation time 17252762 ps
CPU time 0.72 seconds
Started Jul 12 06:39:38 PM PDT 24
Finished Jul 12 06:39:42 PM PDT 24
Peak memory 202712 kb
Host smart-ec796f10-6265-4cc0-9ee2-29227aea9680
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225703490 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.2225703490
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4055630668
Short name T1006
Test name
Test status
Simulation time 28874054 ps
CPU time 2.77 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:40 PM PDT 24
Peak memory 202812 kb
Host smart-d732a45a-7094-472b-852b-8e7e18585866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055630668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.4055630668
Directory /workspace/6.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.740075561
Short name T1024
Test name
Test status
Simulation time 81091125 ps
CPU time 1.44 seconds
Started Jul 12 06:39:34 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 211140 kb
Host smart-b6c3123e-bfae-4804-a409-d1832d98c003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740075561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.sram_ctrl_tl_intg_err.740075561
Directory /workspace/6.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.637260175
Short name T965
Test name
Test status
Simulation time 696886388 ps
CPU time 3.11 seconds
Started Jul 12 06:39:32 PM PDT 24
Finished Jul 12 06:39:40 PM PDT 24
Peak memory 210832 kb
Host smart-ff8a6a48-6d9c-41b1-85fa-660de3019b3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637260175 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.637260175
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2448787020
Short name T956
Test name
Test status
Simulation time 17863591 ps
CPU time 0.67 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 202576 kb
Host smart-2f1e2f49-3db4-46e1-8217-701cc5486451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448787020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.2448787020
Directory /workspace/7.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3142274500
Short name T81
Test name
Test status
Simulation time 3824056833 ps
CPU time 28.76 seconds
Started Jul 12 06:39:37 PM PDT 24
Finished Jul 12 06:40:10 PM PDT 24
Peak memory 202844 kb
Host smart-0cd17a8b-68f3-42dd-a511-191281e56b6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142274500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3142274500
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4200052721
Short name T984
Test name
Test status
Simulation time 104022884 ps
CPU time 0.7 seconds
Started Jul 12 06:39:38 PM PDT 24
Finished Jul 12 06:39:42 PM PDT 24
Peak memory 202608 kb
Host smart-11a10111-6213-46c0-a000-0590cd0e0990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200052721 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.4200052721
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2389329078
Short name T1008
Test name
Test status
Simulation time 262199077 ps
CPU time 3.02 seconds
Started Jul 12 06:39:40 PM PDT 24
Finished Jul 12 06:39:47 PM PDT 24
Peak memory 211076 kb
Host smart-666fcfb8-c095-4411-8164-975897a8eb56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389329078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.2389329078
Directory /workspace/7.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1477438723
Short name T132
Test name
Test status
Simulation time 284015129 ps
CPU time 1.4 seconds
Started Jul 12 06:39:37 PM PDT 24
Finished Jul 12 06:39:43 PM PDT 24
Peak memory 202912 kb
Host smart-a73177d8-b49a-4244-b3a2-ea8fd326c4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477438723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.1477438723
Directory /workspace/7.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2920370942
Short name T988
Test name
Test status
Simulation time 376364897 ps
CPU time 4.05 seconds
Started Jul 12 06:39:35 PM PDT 24
Finished Jul 12 06:39:44 PM PDT 24
Peak memory 211104 kb
Host smart-4ac3f82c-1664-4ba2-811e-d81662eb2d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920370942 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2920370942
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.460754177
Short name T95
Test name
Test status
Simulation time 33125371 ps
CPU time 0.68 seconds
Started Jul 12 06:39:34 PM PDT 24
Finished Jul 12 06:39:40 PM PDT 24
Peak memory 202652 kb
Host smart-309187e6-de50-4ad5-8365-6a4d8dc17346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460754177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 8.sram_ctrl_csr_rw.460754177
Directory /workspace/8.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2508128204
Short name T86
Test name
Test status
Simulation time 14475851799 ps
CPU time 55.39 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 203064 kb
Host smart-8b1b8922-ad78-4809-bb5b-c97d38f28715
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508128204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.2508128204
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2688161463
Short name T105
Test name
Test status
Simulation time 46386471 ps
CPU time 0.73 seconds
Started Jul 12 06:39:33 PM PDT 24
Finished Jul 12 06:39:39 PM PDT 24
Peak memory 202644 kb
Host smart-6f4af765-4e0a-44e8-b1a2-72be27a11918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688161463 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2688161463
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.922416547
Short name T989
Test name
Test status
Simulation time 36829974 ps
CPU time 2.42 seconds
Started Jul 12 06:39:37 PM PDT 24
Finished Jul 12 06:39:44 PM PDT 24
Peak memory 202240 kb
Host smart-0630a075-8a4f-4b09-987f-8d084f2aeaf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922416547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_tl_errors.922416547
Directory /workspace/8.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3975227071
Short name T136
Test name
Test status
Simulation time 738136433 ps
CPU time 1.59 seconds
Started Jul 12 06:39:37 PM PDT 24
Finished Jul 12 06:39:43 PM PDT 24
Peak memory 211112 kb
Host smart-78f2cd24-4835-4b87-a8b4-4cbb18a5b56b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975227071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.3975227071
Directory /workspace/8.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4251250505
Short name T948
Test name
Test status
Simulation time 364816123 ps
CPU time 3.43 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:44 PM PDT 24
Peak memory 211996 kb
Host smart-752132b5-d277-48db-b74c-7fad8259b903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251250505 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.4251250505
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2366343578
Short name T976
Test name
Test status
Simulation time 24884498 ps
CPU time 0.62 seconds
Started Jul 12 06:39:36 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 202520 kb
Host smart-88bde13b-1bb1-42b7-9f1e-fa17f52e1e71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366343578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.2366343578
Directory /workspace/9.sram_ctrl_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3452992485
Short name T96
Test name
Test status
Simulation time 29373297863 ps
CPU time 56.58 seconds
Started Jul 12 06:39:39 PM PDT 24
Finished Jul 12 06:40:39 PM PDT 24
Peak memory 203060 kb
Host smart-dfc1b234-6a0c-4872-846b-d4aef5aed71e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452992485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3452992485
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3638629345
Short name T1004
Test name
Test status
Simulation time 26000375 ps
CPU time 0.78 seconds
Started Jul 12 06:39:35 PM PDT 24
Finished Jul 12 06:39:41 PM PDT 24
Peak memory 202628 kb
Host smart-54ada555-b19e-417f-9914-9b847ff20649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638629345 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3638629345
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.435617622
Short name T1010
Test name
Test status
Simulation time 259856873 ps
CPU time 4.58 seconds
Started Jul 12 06:39:41 PM PDT 24
Finished Jul 12 06:39:49 PM PDT 24
Peak memory 211208 kb
Host smart-cdc6748e-f740-452c-845d-6c623450dee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435617622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_tl_errors.435617622
Directory /workspace/9.sram_ctrl_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2742671906
Short name T137
Test name
Test status
Simulation time 152503201 ps
CPU time 1.65 seconds
Started Jul 12 06:39:39 PM PDT 24
Finished Jul 12 06:39:44 PM PDT 24
Peak memory 202968 kb
Host smart-0c18beb0-8729-4286-9a84-a1a470738525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742671906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.2742671906
Directory /workspace/9.sram_ctrl_tl_intg_err/latest


Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3710718544
Short name T271
Test name
Test status
Simulation time 7470325492 ps
CPU time 734.97 seconds
Started Jul 12 06:00:25 PM PDT 24
Finished Jul 12 06:12:42 PM PDT 24
Peak memory 359996 kb
Host smart-55d07cea-7dc8-4c45-b63c-ebd8de202acc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710718544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.3710718544
Directory /workspace/0.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/0.sram_ctrl_alert_test.2174238975
Short name T709
Test name
Test status
Simulation time 42100712 ps
CPU time 0.71 seconds
Started Jul 12 06:00:22 PM PDT 24
Finished Jul 12 06:00:26 PM PDT 24
Peak memory 202496 kb
Host smart-587853f8-d038-4f53-bbf3-e31b1d367efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174238975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.2174238975
Directory /workspace/0.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/0.sram_ctrl_bijection.366055948
Short name T407
Test name
Test status
Simulation time 28736568601 ps
CPU time 2064.66 seconds
Started Jul 12 06:00:21 PM PDT 24
Finished Jul 12 06:34:49 PM PDT 24
Peak memory 203528 kb
Host smart-abfbe1b0-473e-440b-9d8b-0643219ca46d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366055948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.366055948
Directory /workspace/0.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/0.sram_ctrl_executable.840824510
Short name T183
Test name
Test status
Simulation time 8572108071 ps
CPU time 247.75 seconds
Started Jul 12 06:00:20 PM PDT 24
Finished Jul 12 06:04:30 PM PDT 24
Peak memory 365956 kb
Host smart-b480419b-daf4-44f3-b0dd-dada74946ff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840824510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable
.840824510
Directory /workspace/0.sram_ctrl_executable/latest


Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.4173953611
Short name T379
Test name
Test status
Simulation time 783407551 ps
CPU time 89.93 seconds
Started Jul 12 06:00:22 PM PDT 24
Finished Jul 12 06:01:55 PM PDT 24
Peak memory 345848 kb
Host smart-93c385b4-f87b-43e5-915e-c9eea5869dbf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173953611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.4173953611
Directory /workspace/0.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2545969378
Short name T429
Test name
Test status
Simulation time 11393187590 ps
CPU time 85.36 seconds
Started Jul 12 06:00:29 PM PDT 24
Finished Jul 12 06:01:57 PM PDT 24
Peak memory 219144 kb
Host smart-ffd215ea-1bf9-47e2-b8ed-49474c977ddc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545969378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.2545969378
Directory /workspace/0.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.1436190616
Short name T933
Test name
Test status
Simulation time 16424264930 ps
CPU time 254.67 seconds
Started Jul 12 06:00:22 PM PDT 24
Finished Jul 12 06:04:40 PM PDT 24
Peak memory 202720 kb
Host smart-49adb869-2bdf-41b5-b187-e16d4ea7db32
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436190616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.1436190616
Directory /workspace/0.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.2240015082
Short name T410
Test name
Test status
Simulation time 26139126320 ps
CPU time 2165.79 seconds
Started Jul 12 06:00:26 PM PDT 24
Finished Jul 12 06:36:34 PM PDT 24
Peak memory 376600 kb
Host smart-aaceee56-b48a-4d89-88de-841674b669fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240015082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.2240015082
Directory /workspace/0.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/0.sram_ctrl_partial_access.528782022
Short name T274
Test name
Test status
Simulation time 510138541 ps
CPU time 11.38 seconds
Started Jul 12 06:00:29 PM PDT 24
Finished Jul 12 06:00:42 PM PDT 24
Peak memory 235820 kb
Host smart-4259d248-6345-400a-875d-ca92d90de239
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528782022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr
am_ctrl_partial_access.528782022
Directory /workspace/0.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.256565565
Short name T793
Test name
Test status
Simulation time 7078841988 ps
CPU time 150.18 seconds
Started Jul 12 06:00:23 PM PDT 24
Finished Jul 12 06:02:56 PM PDT 24
Peak memory 202760 kb
Host smart-fc769628-f1b6-451f-8b12-68b10aca4efe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256565565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.sram_ctrl_partial_access_b2b.256565565
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.619606863
Short name T411
Test name
Test status
Simulation time 1160754683 ps
CPU time 3.86 seconds
Started Jul 12 06:00:26 PM PDT 24
Finished Jul 12 06:00:32 PM PDT 24
Peak memory 202792 kb
Host smart-3e1c945b-e891-4065-a277-74b2fa4d8206
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619606863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.619606863
Directory /workspace/0.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/0.sram_ctrl_regwen.4245150083
Short name T203
Test name
Test status
Simulation time 15885220229 ps
CPU time 554.07 seconds
Started Jul 12 06:00:22 PM PDT 24
Finished Jul 12 06:09:39 PM PDT 24
Peak memory 379692 kb
Host smart-33e5303e-f3c0-412c-8640-0b4fe061b2b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245150083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.4245150083
Directory /workspace/0.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.2287594613
Short name T26
Test name
Test status
Simulation time 249071986 ps
CPU time 3.16 seconds
Started Jul 12 06:00:26 PM PDT 24
Finished Jul 12 06:00:31 PM PDT 24
Peak memory 222092 kb
Host smart-2154772c-c57a-42bf-9a35-a17041d319c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287594613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.2287594613
Directory /workspace/0.sram_ctrl_sec_cm/latest


Test location /workspace/coverage/default/0.sram_ctrl_smoke.3710547426
Short name T650
Test name
Test status
Simulation time 922348208 ps
CPU time 14.36 seconds
Started Jul 12 06:00:21 PM PDT 24
Finished Jul 12 06:00:39 PM PDT 24
Peak memory 202656 kb
Host smart-3bef39f3-05ff-433c-b6c6-e00c765f3155
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710547426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3710547426
Directory /workspace/0.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/0.sram_ctrl_stress_all.2084178437
Short name T264
Test name
Test status
Simulation time 50197723991 ps
CPU time 2233.26 seconds
Started Jul 12 06:00:22 PM PDT 24
Finished Jul 12 06:37:39 PM PDT 24
Peak memory 380756 kb
Host smart-e25c80cc-faab-4fcb-aade-89f12ce44091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084178437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.2084178437
Directory /workspace/0.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1294030795
Short name T185
Test name
Test status
Simulation time 13152180649 ps
CPU time 184.43 seconds
Started Jul 12 06:00:25 PM PDT 24
Finished Jul 12 06:03:32 PM PDT 24
Peak memory 202564 kb
Host smart-114b42a1-5a7e-4040-9d3c-6b9b172c62e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294030795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.1294030795
Directory /workspace/0.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3066319534
Short name T722
Test name
Test status
Simulation time 820266949 ps
CPU time 120.64 seconds
Started Jul 12 06:00:20 PM PDT 24
Finished Jul 12 06:02:24 PM PDT 24
Peak memory 370236 kb
Host smart-afe93ac8-4305-4373-973a-550ff94dfbe2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066319534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3066319534
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.719848599
Short name T174
Test name
Test status
Simulation time 6712148984 ps
CPU time 681.98 seconds
Started Jul 12 06:00:24 PM PDT 24
Finished Jul 12 06:11:49 PM PDT 24
Peak memory 374464 kb
Host smart-b66a7f2e-a696-427b-8322-d9b520740e39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719848599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_access_during_key_req.719848599
Directory /workspace/1.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/1.sram_ctrl_alert_test.3002244794
Short name T605
Test name
Test status
Simulation time 33958135 ps
CPU time 0.65 seconds
Started Jul 12 06:00:25 PM PDT 24
Finished Jul 12 06:00:28 PM PDT 24
Peak memory 202300 kb
Host smart-6986b354-2c8c-48bf-90f4-5aac31d5dc4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002244794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.3002244794
Directory /workspace/1.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/1.sram_ctrl_bijection.2617274466
Short name T532
Test name
Test status
Simulation time 50483782059 ps
CPU time 1775.28 seconds
Started Jul 12 06:00:26 PM PDT 24
Finished Jul 12 06:30:04 PM PDT 24
Peak memory 203600 kb
Host smart-a86371cb-674d-4643-bd80-24a9d061550e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617274466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
2617274466
Directory /workspace/1.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/1.sram_ctrl_executable.1027871546
Short name T437
Test name
Test status
Simulation time 6930576665 ps
CPU time 814.44 seconds
Started Jul 12 06:00:22 PM PDT 24
Finished Jul 12 06:14:00 PM PDT 24
Peak memory 371484 kb
Host smart-09f64073-8839-4b13-aa44-4d77ab9563f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027871546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.1027871546
Directory /workspace/1.sram_ctrl_executable/latest


Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.1540907635
Short name T472
Test name
Test status
Simulation time 20403752210 ps
CPU time 116.23 seconds
Started Jul 12 06:00:21 PM PDT 24
Finished Jul 12 06:02:21 PM PDT 24
Peak memory 211040 kb
Host smart-d2b1ccc7-f892-4532-ab1c-5e0546f8b6ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540907635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.1540907635
Directory /workspace/1.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.3030344962
Short name T889
Test name
Test status
Simulation time 984944650 ps
CPU time 131.91 seconds
Started Jul 12 06:00:26 PM PDT 24
Finished Jul 12 06:02:40 PM PDT 24
Peak memory 369556 kb
Host smart-cce1d461-42af-424d-b1a1-0cb7a94d9dee
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030344962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.3030344962
Directory /workspace/1.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.494816229
Short name T398
Test name
Test status
Simulation time 1915651301 ps
CPU time 69.56 seconds
Started Jul 12 06:00:23 PM PDT 24
Finished Jul 12 06:01:35 PM PDT 24
Peak memory 219116 kb
Host smart-57f807ed-42dd-4519-9bf5-53b69ccd85b9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494816229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_mem_partial_access.494816229
Directory /workspace/1.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.4249311297
Short name T40
Test name
Test status
Simulation time 28747031984 ps
CPU time 322.3 seconds
Started Jul 12 06:00:23 PM PDT 24
Finished Jul 12 06:05:49 PM PDT 24
Peak memory 202896 kb
Host smart-9c2e15e5-9530-45e1-aaef-5b9bd3a77028
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249311297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.4249311297
Directory /workspace/1.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.905095783
Short name T342
Test name
Test status
Simulation time 3310779975 ps
CPU time 45.61 seconds
Started Jul 12 06:00:21 PM PDT 24
Finished Jul 12 06:01:10 PM PDT 24
Peak memory 274680 kb
Host smart-28a6e2a6-1de4-4287-9c47-7af91a3db913
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905095783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multipl
e_keys.905095783
Directory /workspace/1.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2970194866
Short name T497
Test name
Test status
Simulation time 763275747 ps
CPU time 3.7 seconds
Started Jul 12 06:00:26 PM PDT 24
Finished Jul 12 06:00:32 PM PDT 24
Peak memory 202560 kb
Host smart-94bd382e-a633-41c4-82b3-9b31647b80e5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970194866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2970194866
Directory /workspace/1.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.1010366363
Short name T430
Test name
Test status
Simulation time 682890223 ps
CPU time 3.12 seconds
Started Jul 12 06:00:23 PM PDT 24
Finished Jul 12 06:00:29 PM PDT 24
Peak memory 202772 kb
Host smart-a5f78653-41d8-4d0e-87da-b66ea6d3067c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010366363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1010366363
Directory /workspace/1.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/1.sram_ctrl_regwen.2934485399
Short name T934
Test name
Test status
Simulation time 4159471676 ps
CPU time 187.39 seconds
Started Jul 12 06:00:21 PM PDT 24
Finished Jul 12 06:03:32 PM PDT 24
Peak memory 337376 kb
Host smart-9293f00a-c1b0-4f51-843b-1ab2d272e68d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934485399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2934485399
Directory /workspace/1.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.2041684176
Short name T16
Test name
Test status
Simulation time 581168820 ps
CPU time 1.85 seconds
Started Jul 12 06:00:23 PM PDT 24
Finished Jul 12 06:00:28 PM PDT 24
Peak memory 222664 kb
Host smart-f45c9a57-9677-4ed6-add8-9ca4b93c72f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041684176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.2041684176
Directory /workspace/1.sram_ctrl_sec_cm/latest


Test location /workspace/coverage/default/1.sram_ctrl_smoke.1555115230
Short name T504
Test name
Test status
Simulation time 1105316364 ps
CPU time 20.85 seconds
Started Jul 12 06:00:23 PM PDT 24
Finished Jul 12 06:00:47 PM PDT 24
Peak memory 202684 kb
Host smart-8f012994-0fa2-48a9-97cb-bbcf8aeb6b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555115230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1555115230
Directory /workspace/1.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/1.sram_ctrl_stress_all.1743943736
Short name T255
Test name
Test status
Simulation time 604603131350 ps
CPU time 2807.57 seconds
Started Jul 12 06:00:23 PM PDT 24
Finished Jul 12 06:47:14 PM PDT 24
Peak memory 378672 kb
Host smart-cc909b1c-8bf5-494c-b1f3-f1fe90198836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743943736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.1743943736
Directory /workspace/1.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.705937810
Short name T691
Test name
Test status
Simulation time 566149301 ps
CPU time 17.98 seconds
Started Jul 12 06:00:25 PM PDT 24
Finished Jul 12 06:00:45 PM PDT 24
Peak memory 211016 kb
Host smart-c993c782-e08d-47b8-b1e6-dca02829fbdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=705937810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.705937810
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1562552932
Short name T438
Test name
Test status
Simulation time 4862862428 ps
CPU time 272.12 seconds
Started Jul 12 06:00:26 PM PDT 24
Finished Jul 12 06:05:00 PM PDT 24
Peak memory 202792 kb
Host smart-cee6528e-61ea-4aa5-ba19-f0de124b83fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562552932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.1562552932
Directory /workspace/1.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1055969269
Short name T170
Test name
Test status
Simulation time 792347515 ps
CPU time 53.82 seconds
Started Jul 12 06:00:20 PM PDT 24
Finished Jul 12 06:01:16 PM PDT 24
Peak memory 312580 kb
Host smart-95632501-f574-4bac-a3cf-2fc0528e7144
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055969269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1055969269
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1551604049
Short name T599
Test name
Test status
Simulation time 15310756525 ps
CPU time 1322.32 seconds
Started Jul 12 06:00:54 PM PDT 24
Finished Jul 12 06:22:57 PM PDT 24
Peak memory 379716 kb
Host smart-a5c8f3a0-fd14-4274-98bd-1f552204d45b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551604049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.1551604049
Directory /workspace/10.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/10.sram_ctrl_alert_test.2284915300
Short name T702
Test name
Test status
Simulation time 148086866 ps
CPU time 0.7 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:00:58 PM PDT 24
Peak memory 202312 kb
Host smart-5a69540c-188d-411e-8900-0110c7696137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284915300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.2284915300
Directory /workspace/10.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/10.sram_ctrl_bijection.3807072085
Short name T206
Test name
Test status
Simulation time 144869615355 ps
CPU time 2486.57 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 203308 kb
Host smart-3f8897c4-4a1f-48be-afcf-34d029cd221f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807072085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.3807072085
Directory /workspace/10.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/10.sram_ctrl_executable.1834031940
Short name T457
Test name
Test status
Simulation time 8080372319 ps
CPU time 203.96 seconds
Started Jul 12 06:00:58 PM PDT 24
Finished Jul 12 06:04:23 PM PDT 24
Peak memory 326764 kb
Host smart-e72cc0eb-06f5-4898-8c4c-3e6e3489d0b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834031940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.1834031940
Directory /workspace/10.sram_ctrl_executable/latest


Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.921504277
Short name T489
Test name
Test status
Simulation time 17380821402 ps
CPU time 75.52 seconds
Started Jul 12 06:00:53 PM PDT 24
Finished Jul 12 06:02:09 PM PDT 24
Peak memory 202800 kb
Host smart-3e48d5da-dedd-42fd-b00b-30de43bf33b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921504277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esc
alation.921504277
Directory /workspace/10.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.763609461
Short name T320
Test name
Test status
Simulation time 3080849830 ps
CPU time 97.39 seconds
Started Jul 12 06:00:53 PM PDT 24
Finished Jul 12 06:02:32 PM PDT 24
Peak memory 330444 kb
Host smart-01c09cb2-a57b-4a38-a333-0715f1eeeace
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763609461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.sram_ctrl_max_throughput.763609461
Directory /workspace/10.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1970435464
Short name T752
Test name
Test status
Simulation time 6063293120 ps
CPU time 125.2 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:03:08 PM PDT 24
Peak memory 211016 kb
Host smart-71ce06af-7067-400d-9c59-4d2fd2b3dc9f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970435464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.1970435464
Directory /workspace/10.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.2163741654
Short name T59
Test name
Test status
Simulation time 15767174516 ps
CPU time 270.54 seconds
Started Jul 12 06:00:58 PM PDT 24
Finished Jul 12 06:05:30 PM PDT 24
Peak memory 210900 kb
Host smart-23575a34-9fa1-462f-b346-1c49ab78778c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163741654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.2163741654
Directory /workspace/10.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.3795151633
Short name T817
Test name
Test status
Simulation time 20897885932 ps
CPU time 1144.58 seconds
Started Jul 12 06:00:54 PM PDT 24
Finished Jul 12 06:19:59 PM PDT 24
Peak memory 380700 kb
Host smart-b91967ad-0aa1-414f-92d9-21259e0f4941
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795151633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.3795151633
Directory /workspace/10.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/10.sram_ctrl_partial_access.2121692386
Short name T153
Test name
Test status
Simulation time 1249992834 ps
CPU time 85.86 seconds
Started Jul 12 06:00:53 PM PDT 24
Finished Jul 12 06:02:19 PM PDT 24
Peak memory 343648 kb
Host smart-b6a41982-7c12-4b20-a8e0-5b54906857a7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121692386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.2121692386
Directory /workspace/10.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1197936943
Short name T778
Test name
Test status
Simulation time 17552522392 ps
CPU time 426.37 seconds
Started Jul 12 06:00:53 PM PDT 24
Finished Jul 12 06:08:01 PM PDT 24
Peak memory 202812 kb
Host smart-1d24c053-a186-43ce-95bf-0ae6eba9a6c5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197936943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.1197936943
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/10.sram_ctrl_regwen.327618903
Short name T73
Test name
Test status
Simulation time 3158171382 ps
CPU time 833.32 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:14:51 PM PDT 24
Peak memory 373604 kb
Host smart-0fc9d820-010b-4e33-add2-ea97317c10d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327618903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.327618903
Directory /workspace/10.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/10.sram_ctrl_smoke.3590471217
Short name T547
Test name
Test status
Simulation time 3796190318 ps
CPU time 18.47 seconds
Started Jul 12 06:00:50 PM PDT 24
Finished Jul 12 06:01:10 PM PDT 24
Peak memory 202812 kb
Host smart-776c36d3-6317-46ff-8c55-683668eef28e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590471217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3590471217
Directory /workspace/10.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/10.sram_ctrl_stress_all.2917107090
Short name T464
Test name
Test status
Simulation time 592557674588 ps
CPU time 5214.69 seconds
Started Jul 12 06:00:52 PM PDT 24
Finished Jul 12 07:27:48 PM PDT 24
Peak memory 378652 kb
Host smart-1465f13c-1a5d-4710-9d1a-c8629bdddb62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917107090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.2917107090
Directory /workspace/10.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3577923836
Short name T622
Test name
Test status
Simulation time 2482006106 ps
CPU time 36.67 seconds
Started Jul 12 06:00:55 PM PDT 24
Finished Jul 12 06:01:33 PM PDT 24
Peak memory 219300 kb
Host smart-4d8b102f-d8f3-4516-b9b9-8058464ac19c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3577923836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3577923836
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2665786488
Short name T729
Test name
Test status
Simulation time 3815732033 ps
CPU time 303.38 seconds
Started Jul 12 06:00:53 PM PDT 24
Finished Jul 12 06:05:57 PM PDT 24
Peak memory 202812 kb
Host smart-44df7f5f-dc70-4377-808a-f3928e754771
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665786488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.2665786488
Directory /workspace/10.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.76470335
Short name T740
Test name
Test status
Simulation time 1577883218 ps
CPU time 76.51 seconds
Started Jul 12 06:00:57 PM PDT 24
Finished Jul 12 06:02:15 PM PDT 24
Peak memory 332412 kb
Host smart-d9cfd0dd-b0a7-45d7-88ab-87394f30fc45
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76470335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.sram_ctrl_throughput_w_partial_write.76470335
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1210044604
Short name T527
Test name
Test status
Simulation time 20896129057 ps
CPU time 297.01 seconds
Started Jul 12 06:00:54 PM PDT 24
Finished Jul 12 06:05:52 PM PDT 24
Peak memory 362360 kb
Host smart-9f2c58c5-05c1-4b16-8488-78bb2761739d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210044604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.1210044604
Directory /workspace/11.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/11.sram_ctrl_alert_test.4246624446
Short name T673
Test name
Test status
Simulation time 13865255 ps
CPU time 0.67 seconds
Started Jul 12 06:00:53 PM PDT 24
Finished Jul 12 06:00:55 PM PDT 24
Peak memory 202380 kb
Host smart-0b04ca6f-2483-45ec-a780-7056deee32db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246624446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.4246624446
Directory /workspace/11.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/11.sram_ctrl_bijection.2178098220
Short name T313
Test name
Test status
Simulation time 19478690353 ps
CPU time 1366.8 seconds
Started Jul 12 06:00:53 PM PDT 24
Finished Jul 12 06:23:41 PM PDT 24
Peak memory 203656 kb
Host smart-4d22b242-0cbe-40e2-ac94-8bbaa512628e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178098220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.2178098220
Directory /workspace/11.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/11.sram_ctrl_executable.743547866
Short name T509
Test name
Test status
Simulation time 16093116197 ps
CPU time 856.09 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:15:14 PM PDT 24
Peak memory 377616 kb
Host smart-5aaa397a-e909-4fc3-b0cc-b656c5a553ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743547866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executabl
e.743547866
Directory /workspace/11.sram_ctrl_executable/latest


Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.1581390338
Short name T940
Test name
Test status
Simulation time 8221061716 ps
CPU time 41.61 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:01:39 PM PDT 24
Peak memory 210936 kb
Host smart-1550dca8-0f8c-441e-ae6e-be6df238c806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581390338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.1581390338
Directory /workspace/11.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.1423382835
Short name T856
Test name
Test status
Simulation time 2784945437 ps
CPU time 5.9 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:01:07 PM PDT 24
Peak memory 210864 kb
Host smart-19256d2d-0f27-41d6-a096-5dea946336d3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423382835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.1423382835
Directory /workspace/11.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.518906099
Short name T375
Test name
Test status
Simulation time 2689086590 ps
CPU time 71.38 seconds
Started Jul 12 06:00:53 PM PDT 24
Finished Jul 12 06:02:06 PM PDT 24
Peak memory 211032 kb
Host smart-933535d1-be70-438a-b52a-9905fea6cd22
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518906099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.sram_ctrl_mem_partial_access.518906099
Directory /workspace/11.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.851259832
Short name T428
Test name
Test status
Simulation time 65845539307 ps
CPU time 356.2 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:06:57 PM PDT 24
Peak memory 211996 kb
Host smart-39cc54d6-54b0-4528-aa65-29eaa1c4de4a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851259832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_mem_walk.851259832
Directory /workspace/11.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.958459042
Short name T466
Test name
Test status
Simulation time 9658682565 ps
CPU time 1505.72 seconds
Started Jul 12 06:00:52 PM PDT 24
Finished Jul 12 06:25:59 PM PDT 24
Peak memory 380508 kb
Host smart-f77da08f-8d7a-44ca-9083-55725577f953
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958459042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multip
le_keys.958459042
Directory /workspace/11.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/11.sram_ctrl_partial_access.3782214356
Short name T667
Test name
Test status
Simulation time 4918102900 ps
CPU time 22.64 seconds
Started Jul 12 06:00:54 PM PDT 24
Finished Jul 12 06:01:18 PM PDT 24
Peak memory 203048 kb
Host smart-c920c488-baf2-4560-9391-5e40762b19ee
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782214356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.3782214356
Directory /workspace/11.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2044787066
Short name T689
Test name
Test status
Simulation time 21180908996 ps
CPU time 530.47 seconds
Started Jul 12 06:00:54 PM PDT 24
Finished Jul 12 06:09:45 PM PDT 24
Peak memory 202744 kb
Host smart-57200473-022c-43a4-8423-19fe8b8aab12
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044787066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.2044787066
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.40439619
Short name T251
Test name
Test status
Simulation time 1343509120 ps
CPU time 3.58 seconds
Started Jul 12 06:00:54 PM PDT 24
Finished Jul 12 06:00:58 PM PDT 24
Peak memory 202836 kb
Host smart-5f50f4b7-8379-4270-8b46-84978fb2fa8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40439619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.40439619
Directory /workspace/11.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/11.sram_ctrl_regwen.2908207779
Short name T224
Test name
Test status
Simulation time 17590647830 ps
CPU time 2456.23 seconds
Started Jul 12 06:00:52 PM PDT 24
Finished Jul 12 06:41:49 PM PDT 24
Peak memory 380744 kb
Host smart-a7bfce72-701a-46d7-b60b-2a5506bf7211
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908207779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2908207779
Directory /workspace/11.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/11.sram_ctrl_smoke.3411110858
Short name T843
Test name
Test status
Simulation time 2483671928 ps
CPU time 18.45 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:01:16 PM PDT 24
Peak memory 202736 kb
Host smart-b398fe9d-ad9a-4062-a571-7f352632d8e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411110858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3411110858
Directory /workspace/11.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/11.sram_ctrl_stress_all.2531933503
Short name T479
Test name
Test status
Simulation time 222304416529 ps
CPU time 5085.78 seconds
Started Jul 12 06:02:46 PM PDT 24
Finished Jul 12 07:27:33 PM PDT 24
Peak memory 379716 kb
Host smart-b938274e-27bb-4741-8ce8-e632ec11d6fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531933503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.2531933503
Directory /workspace/11.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3264816687
Short name T448
Test name
Test status
Simulation time 1061126052 ps
CPU time 14.39 seconds
Started Jul 12 06:00:55 PM PDT 24
Finished Jul 12 06:01:11 PM PDT 24
Peak memory 211228 kb
Host smart-6947f2e9-90fc-48db-ab33-d3d2d1c86184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3264816687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3264816687
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1395729876
Short name T239
Test name
Test status
Simulation time 13700045070 ps
CPU time 190.95 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:04:09 PM PDT 24
Peak memory 202768 kb
Host smart-0233f137-36a2-4b58-aaf9-a153dfbd94cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395729876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.1395729876
Directory /workspace/11.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4125120961
Short name T240
Test name
Test status
Simulation time 768764151 ps
CPU time 30.19 seconds
Started Jul 12 06:00:54 PM PDT 24
Finished Jul 12 06:01:26 PM PDT 24
Peak memory 284620 kb
Host smart-4eb2da4f-3ef6-4161-8c02-2678ad398a2c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125120961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.4125120961
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.426609879
Short name T465
Test name
Test status
Simulation time 8729283188 ps
CPU time 93.48 seconds
Started Jul 12 06:00:58 PM PDT 24
Finished Jul 12 06:02:34 PM PDT 24
Peak memory 337616 kb
Host smart-3bb86435-b128-41c1-bdb9-dc659d8c306e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426609879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.sram_ctrl_access_during_key_req.426609879
Directory /workspace/12.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/12.sram_ctrl_alert_test.2087035754
Short name T186
Test name
Test status
Simulation time 11643521 ps
CPU time 0.72 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:01:04 PM PDT 24
Peak memory 202520 kb
Host smart-110b70f7-dbf7-40cd-b597-04ccf962aa6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087035754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.2087035754
Directory /workspace/12.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/12.sram_ctrl_bijection.2327210078
Short name T641
Test name
Test status
Simulation time 12143912091 ps
CPU time 852.87 seconds
Started Jul 12 06:00:55 PM PDT 24
Finished Jul 12 06:15:09 PM PDT 24
Peak memory 203444 kb
Host smart-fafe1a5c-3df0-4b68-9b4b-ac3a81dee7b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327210078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.2327210078
Directory /workspace/12.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/12.sram_ctrl_executable.59803468
Short name T524
Test name
Test status
Simulation time 12981775822 ps
CPU time 316.78 seconds
Started Jul 12 06:01:00 PM PDT 24
Finished Jul 12 06:06:18 PM PDT 24
Peak memory 356128 kb
Host smart-c3108e4e-f472-44b5-b736-775e67b4ad96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59803468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable
.59803468
Directory /workspace/12.sram_ctrl_executable/latest


Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.4277536756
Short name T544
Test name
Test status
Simulation time 15588758767 ps
CPU time 85.57 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:02:26 PM PDT 24
Peak memory 211016 kb
Host smart-4333b149-bd0d-4ab6-9076-d0805c2f09e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277536756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.4277536756
Directory /workspace/12.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.1917427348
Short name T343
Test name
Test status
Simulation time 3409575075 ps
CPU time 122.03 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 06:03:09 PM PDT 24
Peak memory 347920 kb
Host smart-c8cbd0f1-0576-4f5c-be08-446136a39ca2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917427348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.1917427348
Directory /workspace/12.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.323211523
Short name T424
Test name
Test status
Simulation time 13789964550 ps
CPU time 173.43 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:03:56 PM PDT 24
Peak memory 211128 kb
Host smart-bf009b06-7b26-45eb-83fe-d8ec898212ed
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323211523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.sram_ctrl_mem_partial_access.323211523
Directory /workspace/12.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.1859263217
Short name T573
Test name
Test status
Simulation time 17916005004 ps
CPU time 251.27 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:05:14 PM PDT 24
Peak memory 210960 kb
Host smart-667ac4f9-b3ac-4050-9fd0-0e809ed33e0a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859263217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.1859263217
Directory /workspace/12.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.2829082464
Short name T927
Test name
Test status
Simulation time 43949108584 ps
CPU time 711.01 seconds
Started Jul 12 06:00:58 PM PDT 24
Finished Jul 12 06:12:50 PM PDT 24
Peak memory 371420 kb
Host smart-014148b8-d78b-4a3b-ae23-a098a2e8ff2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829082464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.2829082464
Directory /workspace/12.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/12.sram_ctrl_partial_access.4208293036
Short name T401
Test name
Test status
Simulation time 5496565605 ps
CPU time 39.93 seconds
Started Jul 12 06:00:54 PM PDT 24
Finished Jul 12 06:01:36 PM PDT 24
Peak memory 292900 kb
Host smart-5185e1fe-ea05-47b6-9517-d8803ce52b05
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208293036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.4208293036
Directory /workspace/12.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1816587211
Short name T533
Test name
Test status
Simulation time 61770749120 ps
CPU time 428.63 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:08:09 PM PDT 24
Peak memory 202788 kb
Host smart-0ceed13b-bc8b-4336-a8ee-64c87375a800
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816587211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.1816587211
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.2816735094
Short name T701
Test name
Test status
Simulation time 1406453074 ps
CPU time 3.78 seconds
Started Jul 12 06:00:58 PM PDT 24
Finished Jul 12 06:01:03 PM PDT 24
Peak memory 202840 kb
Host smart-c4f67df2-5db3-48bc-aa2b-b9186ef6cb42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816735094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2816735094
Directory /workspace/12.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/12.sram_ctrl_regwen.4052196047
Short name T441
Test name
Test status
Simulation time 62435666674 ps
CPU time 611.73 seconds
Started Jul 12 06:01:05 PM PDT 24
Finished Jul 12 06:11:18 PM PDT 24
Peak memory 365336 kb
Host smart-23faff13-4eaa-4137-ab1e-4fbfa60e2685
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052196047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.4052196047
Directory /workspace/12.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/12.sram_ctrl_smoke.1312227799
Short name T331
Test name
Test status
Simulation time 4393846945 ps
CPU time 15.47 seconds
Started Jul 12 06:00:55 PM PDT 24
Finished Jul 12 06:01:12 PM PDT 24
Peak memory 202808 kb
Host smart-96d77f06-03cd-4562-b430-6cf37bab6a13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312227799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1312227799
Directory /workspace/12.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/12.sram_ctrl_stress_all.1418190527
Short name T467
Test name
Test status
Simulation time 62834579063 ps
CPU time 4728.74 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 07:19:56 PM PDT 24
Peak memory 380776 kb
Host smart-120a52a8-2a10-4fff-b490-f451ff65a45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418190527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.1418190527
Directory /workspace/12.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.170438769
Short name T539
Test name
Test status
Simulation time 1148281351 ps
CPU time 41.75 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:01:43 PM PDT 24
Peak memory 219100 kb
Host smart-a39de096-7e59-4952-a6a6-2d74de8f88ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=170438769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.170438769
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.4171644573
Short name T629
Test name
Test status
Simulation time 13047647663 ps
CPU time 249 seconds
Started Jul 12 06:00:57 PM PDT 24
Finished Jul 12 06:05:08 PM PDT 24
Peak memory 202904 kb
Host smart-162477d9-e08c-410f-b919-42973d852766
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171644573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.4171644573
Directory /workspace/12.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1049688193
Short name T724
Test name
Test status
Simulation time 866523838 ps
CPU time 99.4 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 06:02:47 PM PDT 24
Peak memory 360080 kb
Host smart-aabf2d91-7f29-44af-b766-88c32b4d6209
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049688193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1049688193
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1644516493
Short name T559
Test name
Test status
Simulation time 55349499533 ps
CPU time 1139.25 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:20:00 PM PDT 24
Peak memory 378676 kb
Host smart-b286da9e-17ce-40b1-af2f-34db1234ae29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644516493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.1644516493
Directory /workspace/13.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/13.sram_ctrl_bijection.1032651270
Short name T931
Test name
Test status
Simulation time 239706245696 ps
CPU time 2710.26 seconds
Started Jul 12 06:00:57 PM PDT 24
Finished Jul 12 06:46:09 PM PDT 24
Peak memory 203624 kb
Host smart-24f83b4c-1c45-43eb-8bcc-618cab610571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032651270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.1032651270
Directory /workspace/13.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/13.sram_ctrl_executable.770768639
Short name T620
Test name
Test status
Simulation time 37478377951 ps
CPU time 555.61 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:10:17 PM PDT 24
Peak memory 364308 kb
Host smart-19fc3d4d-d1ab-457f-9288-b52ef5f38f38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770768639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executabl
e.770768639
Directory /workspace/13.sram_ctrl_executable/latest


Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.2104964721
Short name T334
Test name
Test status
Simulation time 4556270823 ps
CPU time 26.76 seconds
Started Jul 12 06:01:05 PM PDT 24
Finished Jul 12 06:01:33 PM PDT 24
Peak memory 210940 kb
Host smart-fd265b46-a4d5-427c-97e5-a8ce5988968e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104964721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.2104964721
Directory /workspace/13.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.1009267763
Short name T578
Test name
Test status
Simulation time 707541639 ps
CPU time 9.08 seconds
Started Jul 12 06:01:00 PM PDT 24
Finished Jul 12 06:01:11 PM PDT 24
Peak memory 223652 kb
Host smart-c87f95f1-56f5-4a15-821d-68825680c010
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009267763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.1009267763
Directory /workspace/13.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.4218204612
Short name T718
Test name
Test status
Simulation time 54689521663 ps
CPU time 185.33 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:04:07 PM PDT 24
Peak memory 211608 kb
Host smart-ff2e1a69-54ac-4449-9aed-993fdfdbc79b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218204612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.4218204612
Directory /workspace/13.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.2494864847
Short name T696
Test name
Test status
Simulation time 65614451781 ps
CPU time 298.03 seconds
Started Jul 12 06:00:58 PM PDT 24
Finished Jul 12 06:05:58 PM PDT 24
Peak memory 210944 kb
Host smart-1a06de65-223f-4419-a3ef-ed663881d71e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494864847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.2494864847
Directory /workspace/13.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.858630528
Short name T515
Test name
Test status
Simulation time 7399474417 ps
CPU time 229.57 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:04:50 PM PDT 24
Peak memory 340312 kb
Host smart-fc05db0a-a087-450f-b706-78f197f43617
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858630528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip
le_keys.858630528
Directory /workspace/13.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/13.sram_ctrl_partial_access.639076546
Short name T656
Test name
Test status
Simulation time 1124840830 ps
CPU time 13.53 seconds
Started Jul 12 06:00:59 PM PDT 24
Finished Jul 12 06:01:14 PM PDT 24
Peak memory 202628 kb
Host smart-99045660-ff7c-434f-87d6-74247f7a8176
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639076546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.s
ram_ctrl_partial_access.639076546
Directory /workspace/13.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2349111026
Short name T687
Test name
Test status
Simulation time 10245706799 ps
CPU time 256.98 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:05:19 PM PDT 24
Peak memory 202792 kb
Host smart-e670a491-1ece-4385-8bf2-0272a4730f22
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349111026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.2349111026
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.3963685237
Short name T516
Test name
Test status
Simulation time 3047703742 ps
CPU time 3.58 seconds
Started Jul 12 06:01:04 PM PDT 24
Finished Jul 12 06:01:09 PM PDT 24
Peak memory 202964 kb
Host smart-f4915647-4e01-44f2-9575-f97c01bad9a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963685237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3963685237
Directory /workspace/13.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/13.sram_ctrl_regwen.996167917
Short name T310
Test name
Test status
Simulation time 808565068 ps
CPU time 11.97 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:01:15 PM PDT 24
Peak memory 240940 kb
Host smart-337cd0d7-0c40-40c5-815b-d45290fba03d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996167917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.996167917
Directory /workspace/13.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/13.sram_ctrl_smoke.1182919127
Short name T300
Test name
Test status
Simulation time 1334617774 ps
CPU time 173.71 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 06:04:01 PM PDT 24
Peak memory 370276 kb
Host smart-87a87f61-a227-4f4a-b103-ed0c79e72f53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182919127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1182919127
Directory /workspace/13.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/13.sram_ctrl_stress_all.2896580244
Short name T617
Test name
Test status
Simulation time 63238569738 ps
CPU time 4672.94 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 07:18:57 PM PDT 24
Peak memory 382784 kb
Host smart-08165e9c-4b3f-4dfc-b769-9301130e2284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896580244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.2896580244
Directory /workspace/13.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2997091798
Short name T377
Test name
Test status
Simulation time 21903438892 ps
CPU time 173.83 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:03:56 PM PDT 24
Peak memory 347852 kb
Host smart-3ad50906-d7c9-44b9-afee-6ce4ee4418c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2997091798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2997091798
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1068190381
Short name T395
Test name
Test status
Simulation time 9499163890 ps
CPU time 150.87 seconds
Started Jul 12 06:01:00 PM PDT 24
Finished Jul 12 06:03:33 PM PDT 24
Peak memory 202808 kb
Host smart-8c35276d-b7ac-4826-b26d-fd4c66c1eca5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068190381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.1068190381
Directory /workspace/13.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.656128658
Short name T404
Test name
Test status
Simulation time 10846564401 ps
CPU time 77.12 seconds
Started Jul 12 06:01:04 PM PDT 24
Finished Jul 12 06:02:22 PM PDT 24
Peak memory 343812 kb
Host smart-742294ff-b1cc-41b2-b1a4-cf22e64cdeb8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656128658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_throughput_w_partial_write.656128658
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1487134836
Short name T451
Test name
Test status
Simulation time 7670366580 ps
CPU time 634.6 seconds
Started Jul 12 06:01:03 PM PDT 24
Finished Jul 12 06:11:39 PM PDT 24
Peak memory 379752 kb
Host smart-f430fdf3-dc2d-4b4c-acf1-6298188b1e21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487134836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1487134836
Directory /workspace/14.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/14.sram_ctrl_alert_test.229079669
Short name T569
Test name
Test status
Simulation time 23516714 ps
CPU time 0.65 seconds
Started Jul 12 06:01:10 PM PDT 24
Finished Jul 12 06:01:12 PM PDT 24
Peak memory 202356 kb
Host smart-e790964c-897d-4ac8-adab-12a029011a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229079669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.229079669
Directory /workspace/14.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/14.sram_ctrl_bijection.2394620936
Short name T481
Test name
Test status
Simulation time 115681309470 ps
CPU time 2014.3 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:34:38 PM PDT 24
Peak memory 203304 kb
Host smart-d8dd2b30-28e8-4e3e-b83b-495ac3f528c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394620936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.2394620936
Directory /workspace/14.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/14.sram_ctrl_executable.2033140428
Short name T397
Test name
Test status
Simulation time 27229861858 ps
CPU time 817.81 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:14:41 PM PDT 24
Peak memory 378684 kb
Host smart-4a0cb875-a93d-4078-a0f2-0477ea38e748
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033140428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.2033140428
Directory /workspace/14.sram_ctrl_executable/latest


Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.2927700535
Short name T670
Test name
Test status
Simulation time 12720359466 ps
CPU time 75.51 seconds
Started Jul 12 06:01:05 PM PDT 24
Finished Jul 12 06:02:21 PM PDT 24
Peak memory 215580 kb
Host smart-eda204d1-5bf7-46a1-9a38-7b6cf1974809
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927700535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.2927700535
Directory /workspace/14.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.3063943141
Short name T294
Test name
Test status
Simulation time 744042004 ps
CPU time 64.24 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:02:07 PM PDT 24
Peak memory 317176 kb
Host smart-32e82d18-f498-4573-a196-9384a6b00797
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063943141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.3063943141
Directory /workspace/14.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1975047017
Short name T820
Test name
Test status
Simulation time 1861676183 ps
CPU time 64.82 seconds
Started Jul 12 06:01:09 PM PDT 24
Finished Jul 12 06:02:15 PM PDT 24
Peak memory 210896 kb
Host smart-227a2fbe-367e-47c5-86fe-b9d4f3dfe945
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975047017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.1975047017
Directory /workspace/14.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.2070600684
Short name T214
Test name
Test status
Simulation time 13164656303 ps
CPU time 127.03 seconds
Started Jul 12 06:01:04 PM PDT 24
Finished Jul 12 06:03:12 PM PDT 24
Peak memory 210940 kb
Host smart-39893767-7a8c-42b8-b5ef-14cb51a53769
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070600684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.2070600684
Directory /workspace/14.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.2882619840
Short name T392
Test name
Test status
Simulation time 107321857640 ps
CPU time 830.75 seconds
Started Jul 12 06:01:01 PM PDT 24
Finished Jul 12 06:14:54 PM PDT 24
Peak memory 375296 kb
Host smart-a4409df6-afc7-42ac-9073-adb286935aeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882619840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.2882619840
Directory /workspace/14.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/14.sram_ctrl_partial_access.1638697017
Short name T800
Test name
Test status
Simulation time 2858137855 ps
CPU time 18.4 seconds
Started Jul 12 06:01:00 PM PDT 24
Finished Jul 12 06:01:20 PM PDT 24
Peak memory 202732 kb
Host smart-034d3a35-2b24-4211-af7a-0865792d5a41
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638697017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.1638697017
Directory /workspace/14.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2082359092
Short name T723
Test name
Test status
Simulation time 7210228652 ps
CPU time 402.89 seconds
Started Jul 12 06:01:04 PM PDT 24
Finished Jul 12 06:07:48 PM PDT 24
Peak memory 203008 kb
Host smart-0efbbb08-3c47-412b-9ecb-778dc608ab34
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082359092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.2082359092
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.1206820565
Short name T285
Test name
Test status
Simulation time 1345416800 ps
CPU time 3.48 seconds
Started Jul 12 06:01:03 PM PDT 24
Finished Jul 12 06:01:07 PM PDT 24
Peak memory 203028 kb
Host smart-101f19d6-4b81-438c-bffd-ee533c0cdd53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206820565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1206820565
Directory /workspace/14.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/14.sram_ctrl_regwen.347259608
Short name T118
Test name
Test status
Simulation time 6706028331 ps
CPU time 752.69 seconds
Started Jul 12 06:01:04 PM PDT 24
Finished Jul 12 06:13:38 PM PDT 24
Peak memory 377668 kb
Host smart-87cbb50d-e38e-4c3f-81e0-61ce6697c428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347259608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.347259608
Directory /workspace/14.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/14.sram_ctrl_smoke.2231794431
Short name T538
Test name
Test status
Simulation time 1403587743 ps
CPU time 22.53 seconds
Started Jul 12 06:01:05 PM PDT 24
Finished Jul 12 06:01:28 PM PDT 24
Peak memory 202676 kb
Host smart-f3caf968-3bd8-4409-96c5-fa2c8ced4898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231794431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2231794431
Directory /workspace/14.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/14.sram_ctrl_stress_all.2817396698
Short name T455
Test name
Test status
Simulation time 505216995123 ps
CPU time 3121.36 seconds
Started Jul 12 06:01:08 PM PDT 24
Finished Jul 12 06:53:10 PM PDT 24
Peak memory 382700 kb
Host smart-63dae47f-5aef-44e7-8d04-d2d885a9a0b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817396698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.2817396698
Directory /workspace/14.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2937320020
Short name T866
Test name
Test status
Simulation time 787778962 ps
CPU time 6.29 seconds
Started Jul 12 06:01:09 PM PDT 24
Finished Jul 12 06:01:16 PM PDT 24
Peak memory 211068 kb
Host smart-2be7bfc3-6875-49ff-a939-92c72d057364
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2937320020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.2937320020
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.4076885703
Short name T445
Test name
Test status
Simulation time 3979123734 ps
CPU time 241.91 seconds
Started Jul 12 06:01:05 PM PDT 24
Finished Jul 12 06:05:08 PM PDT 24
Peak memory 202716 kb
Host smart-680ac743-cab3-4f45-bf35-238ad9e1729d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076885703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.4076885703
Directory /workspace/14.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2046412408
Short name T344
Test name
Test status
Simulation time 730960036 ps
CPU time 29.36 seconds
Started Jul 12 06:01:00 PM PDT 24
Finished Jul 12 06:01:32 PM PDT 24
Peak memory 279372 kb
Host smart-5e16fbde-99b1-422d-8eb1-8080d2846b23
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046412408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.2046412408
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.604203199
Short name T736
Test name
Test status
Simulation time 12605145070 ps
CPU time 905.83 seconds
Started Jul 12 06:01:07 PM PDT 24
Finished Jul 12 06:16:14 PM PDT 24
Peak memory 371412 kb
Host smart-63d894ba-df4a-428f-956f-a58ce4cf9e90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604203199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 15.sram_ctrl_access_during_key_req.604203199
Directory /workspace/15.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/15.sram_ctrl_alert_test.99421552
Short name T469
Test name
Test status
Simulation time 42615344 ps
CPU time 0.63 seconds
Started Jul 12 06:01:11 PM PDT 24
Finished Jul 12 06:01:13 PM PDT 24
Peak memory 202324 kb
Host smart-f17fdace-f994-4573-8617-b9bd50c6c147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99421552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_alert_test.99421552
Directory /workspace/15.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/15.sram_ctrl_bijection.2085044128
Short name T412
Test name
Test status
Simulation time 110822203593 ps
CPU time 1260.39 seconds
Started Jul 12 06:01:12 PM PDT 24
Finished Jul 12 06:22:14 PM PDT 24
Peak memory 203320 kb
Host smart-805f63f4-0c0e-4109-bb57-d842090e7df2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085044128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.2085044128
Directory /workspace/15.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/15.sram_ctrl_executable.3039432390
Short name T563
Test name
Test status
Simulation time 43471573277 ps
CPU time 1353.18 seconds
Started Jul 12 06:01:09 PM PDT 24
Finished Jul 12 06:23:43 PM PDT 24
Peak memory 378668 kb
Host smart-52a7a64d-9f02-4111-89e5-2ab60cfaad6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039432390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.3039432390
Directory /workspace/15.sram_ctrl_executable/latest


Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.817712145
Short name T241
Test name
Test status
Simulation time 93334416698 ps
CPU time 114.02 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 06:03:02 PM PDT 24
Peak memory 211016 kb
Host smart-18db9591-d8a0-4c14-b1b2-1811da7ad6aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817712145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_esc
alation.817712145
Directory /workspace/15.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.1946271610
Short name T265
Test name
Test status
Simulation time 2964837038 ps
CPU time 22.94 seconds
Started Jul 12 06:01:08 PM PDT 24
Finished Jul 12 06:01:32 PM PDT 24
Peak memory 277672 kb
Host smart-96b20e43-31d6-498e-8af7-b30d57336384
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946271610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.1946271610
Directory /workspace/15.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.4092369129
Short name T594
Test name
Test status
Simulation time 19570473452 ps
CPU time 160.78 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 06:03:48 PM PDT 24
Peak memory 210996 kb
Host smart-c848b781-d5d5-4372-8df5-fc20e4d6da18
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092369129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.4092369129
Directory /workspace/15.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.1552370491
Short name T149
Test name
Test status
Simulation time 3946223953 ps
CPU time 252.33 seconds
Started Jul 12 06:01:08 PM PDT 24
Finished Jul 12 06:05:21 PM PDT 24
Peak memory 210856 kb
Host smart-0dcf3707-2915-495a-98f9-6f277dba6b7a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552370491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.1552370491
Directory /workspace/15.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.3896731673
Short name T273
Test name
Test status
Simulation time 43422299627 ps
CPU time 1222.85 seconds
Started Jul 12 06:01:07 PM PDT 24
Finished Jul 12 06:21:31 PM PDT 24
Peak memory 379596 kb
Host smart-ef3a6491-a60b-4f70-ac09-6d62ed2f624b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896731673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.3896731673
Directory /workspace/15.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/15.sram_ctrl_partial_access.1991762153
Short name T190
Test name
Test status
Simulation time 15222262735 ps
CPU time 77.02 seconds
Started Jul 12 06:01:09 PM PDT 24
Finished Jul 12 06:02:27 PM PDT 24
Peak memory 309136 kb
Host smart-aee6ff92-31a1-4eec-af3a-918d7c98c09a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991762153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.1991762153
Directory /workspace/15.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.1427758664
Short name T324
Test name
Test status
Simulation time 1343320639 ps
CPU time 3.75 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 06:01:11 PM PDT 24
Peak memory 202804 kb
Host smart-34e87cea-0f41-4a15-a5b8-8c574544ef9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427758664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1427758664
Directory /workspace/15.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/15.sram_ctrl_regwen.955836819
Short name T545
Test name
Test status
Simulation time 22084473461 ps
CPU time 1025.96 seconds
Started Jul 12 06:01:09 PM PDT 24
Finished Jul 12 06:18:16 PM PDT 24
Peak memory 377644 kb
Host smart-ad6f0159-ece5-4dcb-98de-ba8fd7812550
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955836819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.955836819
Directory /workspace/15.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/15.sram_ctrl_smoke.344645731
Short name T162
Test name
Test status
Simulation time 696157092 ps
CPU time 33.62 seconds
Started Jul 12 06:01:04 PM PDT 24
Finished Jul 12 06:01:39 PM PDT 24
Peak memory 280208 kb
Host smart-6909d0bc-a939-4650-8609-cd96d8f9b1e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344645731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.344645731
Directory /workspace/15.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/15.sram_ctrl_stress_all.4067174677
Short name T686
Test name
Test status
Simulation time 144493225427 ps
CPU time 2576.34 seconds
Started Jul 12 06:01:11 PM PDT 24
Finished Jul 12 06:44:08 PM PDT 24
Peak memory 210980 kb
Host smart-9dfe3e7d-3d91-4485-b36d-0b70b835e458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067174677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.4067174677
Directory /workspace/15.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2178809363
Short name T388
Test name
Test status
Simulation time 1156966755 ps
CPU time 13.5 seconds
Started Jul 12 06:01:08 PM PDT 24
Finished Jul 12 06:01:22 PM PDT 24
Peak memory 210980 kb
Host smart-14c7de93-d16a-48d3-94f6-53f02cd3ea65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2178809363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2178809363
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.410623255
Short name T917
Test name
Test status
Simulation time 17189786075 ps
CPU time 250.01 seconds
Started Jul 12 06:01:07 PM PDT 24
Finished Jul 12 06:05:18 PM PDT 24
Peak memory 202720 kb
Host smart-9abfedbc-fa74-4817-af9a-aa5652b40eef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410623255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_stress_pipeline.410623255
Directory /workspace/15.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1975484711
Short name T376
Test name
Test status
Simulation time 2741236918 ps
CPU time 11.9 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 06:01:19 PM PDT 24
Peak memory 235104 kb
Host smart-f3c7ce99-3c57-4820-9339-213a76b7ae43
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975484711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.1975484711
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2096902451
Short name T478
Test name
Test status
Simulation time 31288344068 ps
CPU time 1609.45 seconds
Started Jul 12 06:01:07 PM PDT 24
Finished Jul 12 06:27:58 PM PDT 24
Peak memory 379924 kb
Host smart-22795140-7e98-4fcd-bbf5-2ba30ae7f823
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096902451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.2096902451
Directory /workspace/16.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/16.sram_ctrl_alert_test.4092154258
Short name T234
Test name
Test status
Simulation time 17803487 ps
CPU time 0.68 seconds
Started Jul 12 06:01:14 PM PDT 24
Finished Jul 12 06:01:16 PM PDT 24
Peak memory 202520 kb
Host smart-1afdf82c-6517-479b-914d-ee5a4269c860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092154258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.4092154258
Directory /workspace/16.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/16.sram_ctrl_bijection.1561071103
Short name T18
Test name
Test status
Simulation time 138347648161 ps
CPU time 1622.35 seconds
Started Jul 12 06:01:09 PM PDT 24
Finished Jul 12 06:28:13 PM PDT 24
Peak memory 203444 kb
Host smart-8d7f8188-1ba0-41ee-9471-4daa3852d28d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561071103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1561071103
Directory /workspace/16.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/16.sram_ctrl_executable.3938801577
Short name T735
Test name
Test status
Simulation time 29671839342 ps
CPU time 785.06 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 06:14:12 PM PDT 24
Peak memory 378628 kb
Host smart-a47b8caf-5676-457a-b4db-77e50379f50a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938801577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.3938801577
Directory /workspace/16.sram_ctrl_executable/latest


Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.2678350379
Short name T727
Test name
Test status
Simulation time 56756787548 ps
CPU time 75.58 seconds
Started Jul 12 06:01:07 PM PDT 24
Finished Jul 12 06:02:24 PM PDT 24
Peak memory 211020 kb
Host smart-99a21313-7c14-4d94-9e4b-3a85579ed142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678350379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.2678350379
Directory /workspace/16.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.2377187933
Short name T663
Test name
Test status
Simulation time 9545776404 ps
CPU time 137.74 seconds
Started Jul 12 06:01:11 PM PDT 24
Finished Jul 12 06:03:29 PM PDT 24
Peak memory 370380 kb
Host smart-377fd3c9-61ec-4990-8804-0e9d7aacf160
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377187933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.2377187933
Directory /workspace/16.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.677512281
Short name T48
Test name
Test status
Simulation time 5342413919 ps
CPU time 88.71 seconds
Started Jul 12 06:01:14 PM PDT 24
Finished Jul 12 06:02:44 PM PDT 24
Peak memory 211040 kb
Host smart-e67c3647-63c0-4be3-8cb7-6c16ccf251f0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677512281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.sram_ctrl_mem_partial_access.677512281
Directory /workspace/16.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.1274034300
Short name T228
Test name
Test status
Simulation time 10716570708 ps
CPU time 311.97 seconds
Started Jul 12 06:01:08 PM PDT 24
Finished Jul 12 06:06:21 PM PDT 24
Peak memory 211852 kb
Host smart-808f0053-536f-4671-9860-ae4e24022556
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274034300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.1274034300
Directory /workspace/16.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.2731854172
Short name T888
Test name
Test status
Simulation time 47097820955 ps
CPU time 1883.73 seconds
Started Jul 12 06:01:07 PM PDT 24
Finished Jul 12 06:32:32 PM PDT 24
Peak memory 377616 kb
Host smart-bf3b59f3-374e-44ac-acab-c996a85f402c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731854172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.2731854172
Directory /workspace/16.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/16.sram_ctrl_partial_access.3393201653
Short name T737
Test name
Test status
Simulation time 1143725078 ps
CPU time 17.83 seconds
Started Jul 12 06:01:10 PM PDT 24
Finished Jul 12 06:01:28 PM PDT 24
Peak memory 202692 kb
Host smart-1203c009-9c30-4d59-9c78-bed8db03c7cd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393201653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.3393201653
Directory /workspace/16.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1615588166
Short name T236
Test name
Test status
Simulation time 11033169541 ps
CPU time 197.98 seconds
Started Jul 12 06:01:05 PM PDT 24
Finished Jul 12 06:04:24 PM PDT 24
Peak memory 202824 kb
Host smart-d27d8ec6-6beb-4ba3-b27d-368bddedc967
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615588166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.1615588166
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.438465339
Short name T329
Test name
Test status
Simulation time 354967916 ps
CPU time 3.3 seconds
Started Jul 12 06:01:11 PM PDT 24
Finished Jul 12 06:01:16 PM PDT 24
Peak memory 202840 kb
Host smart-01cac718-9bbd-431c-bc34-be5bec922e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438465339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.438465339
Directory /workspace/16.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/16.sram_ctrl_regwen.411935263
Short name T757
Test name
Test status
Simulation time 17051794272 ps
CPU time 1333.77 seconds
Started Jul 12 06:01:11 PM PDT 24
Finished Jul 12 06:23:27 PM PDT 24
Peak memory 378708 kb
Host smart-9d7a8ff9-56df-40c9-9a03-9aa7480aad64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411935263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.411935263
Directory /workspace/16.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/16.sram_ctrl_smoke.1376290173
Short name T452
Test name
Test status
Simulation time 1452882822 ps
CPU time 10.17 seconds
Started Jul 12 06:01:07 PM PDT 24
Finished Jul 12 06:01:19 PM PDT 24
Peak memory 202716 kb
Host smart-369f04ce-5d73-44f0-8e77-73964d9a2ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376290173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1376290173
Directory /workspace/16.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2639020633
Short name T797
Test name
Test status
Simulation time 1172018065 ps
CPU time 20.87 seconds
Started Jul 12 06:01:11 PM PDT 24
Finished Jul 12 06:01:33 PM PDT 24
Peak memory 211020 kb
Host smart-8285405c-5e5e-4d0f-b150-64fd38f5b101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2639020633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2639020633
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2181280415
Short name T178
Test name
Test status
Simulation time 7626601507 ps
CPU time 178.63 seconds
Started Jul 12 06:01:09 PM PDT 24
Finished Jul 12 06:04:09 PM PDT 24
Peak memory 202804 kb
Host smart-541aca65-f688-4c37-abe2-51f005dfb387
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181280415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.2181280415
Directory /workspace/16.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.4258785381
Short name T513
Test name
Test status
Simulation time 1511753960 ps
CPU time 47.97 seconds
Started Jul 12 06:01:06 PM PDT 24
Finished Jul 12 06:01:55 PM PDT 24
Peak memory 300820 kb
Host smart-4c629488-9472-4052-a618-548bf00580d6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258785381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.4258785381
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.34694111
Short name T361
Test name
Test status
Simulation time 42649143119 ps
CPU time 808.21 seconds
Started Jul 12 06:01:15 PM PDT 24
Finished Jul 12 06:14:44 PM PDT 24
Peak memory 378504 kb
Host smart-a9d166e9-4cef-4414-94d1-8aef809cceb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34694111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.sram_ctrl_access_during_key_req.34694111
Directory /workspace/17.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/17.sram_ctrl_alert_test.3578552038
Short name T783
Test name
Test status
Simulation time 20832476 ps
CPU time 0.66 seconds
Started Jul 12 06:01:25 PM PDT 24
Finished Jul 12 06:01:26 PM PDT 24
Peak memory 202336 kb
Host smart-2c657b06-f809-4d74-a1d3-c11a0faecf31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578552038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.3578552038
Directory /workspace/17.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/17.sram_ctrl_bijection.1044440001
Short name T31
Test name
Test status
Simulation time 345461016033 ps
CPU time 2044.47 seconds
Started Jul 12 06:01:11 PM PDT 24
Finished Jul 12 06:35:17 PM PDT 24
Peak memory 202820 kb
Host smart-91f88f58-a51c-4126-a914-13ba38c040f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044440001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.1044440001
Directory /workspace/17.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/17.sram_ctrl_executable.4021724567
Short name T139
Test name
Test status
Simulation time 17080011244 ps
CPU time 591.55 seconds
Started Jul 12 06:01:15 PM PDT 24
Finished Jul 12 06:11:07 PM PDT 24
Peak memory 378508 kb
Host smart-d12858ac-420a-4c80-9a42-22d5dbc8df32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021724567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.4021724567
Directory /workspace/17.sram_ctrl_executable/latest


Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.4016736952
Short name T880
Test name
Test status
Simulation time 24888424156 ps
CPU time 37.48 seconds
Started Jul 12 06:01:12 PM PDT 24
Finished Jul 12 06:01:51 PM PDT 24
Peak memory 202816 kb
Host smart-a6ff2c32-6410-4baa-9d88-ff11f6ba686c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016736952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.4016736952
Directory /workspace/17.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.879228549
Short name T907
Test name
Test status
Simulation time 2979300095 ps
CPU time 31.8 seconds
Started Jul 12 06:01:13 PM PDT 24
Finished Jul 12 06:01:46 PM PDT 24
Peak memory 281596 kb
Host smart-907e3a85-f5e2-4b93-a078-2eb296e7c396
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879228549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.sram_ctrl_max_throughput.879228549
Directory /workspace/17.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1743019060
Short name T746
Test name
Test status
Simulation time 2447404968 ps
CPU time 152.24 seconds
Started Jul 12 06:01:15 PM PDT 24
Finished Jul 12 06:03:48 PM PDT 24
Peak memory 210996 kb
Host smart-252398b6-e587-442a-ab34-906824c770fb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743019060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.1743019060
Directory /workspace/17.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.610067159
Short name T418
Test name
Test status
Simulation time 103416201156 ps
CPU time 185.71 seconds
Started Jul 12 06:01:22 PM PDT 24
Finished Jul 12 06:04:29 PM PDT 24
Peak memory 210936 kb
Host smart-032dfb57-f118-4acc-8fe6-41878bc343b5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610067159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl
_mem_walk.610067159
Directory /workspace/17.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.1662345672
Short name T945
Test name
Test status
Simulation time 3491803653 ps
CPU time 336.37 seconds
Started Jul 12 06:01:13 PM PDT 24
Finished Jul 12 06:06:51 PM PDT 24
Peak memory 370424 kb
Host smart-4772543b-76e8-4a7c-bf8c-631d966740a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662345672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.1662345672
Directory /workspace/17.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/17.sram_ctrl_partial_access.1422115654
Short name T755
Test name
Test status
Simulation time 719845041 ps
CPU time 5.04 seconds
Started Jul 12 06:01:11 PM PDT 24
Finished Jul 12 06:01:18 PM PDT 24
Peak memory 202708 kb
Host smart-d9f3f5d8-805b-4088-971c-e633f4cae862
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422115654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.1422115654
Directory /workspace/17.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2448589806
Short name T557
Test name
Test status
Simulation time 25020949160 ps
CPU time 554.87 seconds
Started Jul 12 06:01:13 PM PDT 24
Finished Jul 12 06:10:29 PM PDT 24
Peak memory 202832 kb
Host smart-e5d615fc-befb-48ac-9cce-868db1652ebe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448589806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.2448589806
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.1943238240
Short name T920
Test name
Test status
Simulation time 4191315071 ps
CPU time 3.58 seconds
Started Jul 12 06:01:13 PM PDT 24
Finished Jul 12 06:01:18 PM PDT 24
Peak memory 202848 kb
Host smart-460e78ee-0132-4e82-9ba1-bea6041775bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943238240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1943238240
Directory /workspace/17.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/17.sram_ctrl_regwen.4022101101
Short name T64
Test name
Test status
Simulation time 80042766503 ps
CPU time 1429.81 seconds
Started Jul 12 06:01:12 PM PDT 24
Finished Jul 12 06:25:04 PM PDT 24
Peak memory 378708 kb
Host smart-ff73ba6f-0ead-46b6-868c-8aa9d66645e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022101101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.4022101101
Directory /workspace/17.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/17.sram_ctrl_smoke.3557369345
Short name T588
Test name
Test status
Simulation time 6295037291 ps
CPU time 101.44 seconds
Started Jul 12 06:01:12 PM PDT 24
Finished Jul 12 06:02:55 PM PDT 24
Peak memory 344924 kb
Host smart-91c75533-66d9-4423-affb-c3d44e58929a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557369345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3557369345
Directory /workspace/17.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/17.sram_ctrl_stress_all.20946805
Short name T704
Test name
Test status
Simulation time 526358170970 ps
CPU time 3280.78 seconds
Started Jul 12 06:01:19 PM PDT 24
Finished Jul 12 06:56:01 PM PDT 24
Peak memory 366996 kb
Host smart-8f691f01-e963-4808-863b-235c0f1958d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.sram_ctrl_stress_all.20946805
Directory /workspace/17.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.334059134
Short name T612
Test name
Test status
Simulation time 1149931004 ps
CPU time 26.12 seconds
Started Jul 12 06:01:21 PM PDT 24
Finished Jul 12 06:01:48 PM PDT 24
Peak memory 211016 kb
Host smart-c16be678-1504-4257-95a1-56db220f555f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=334059134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.334059134
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3841196807
Short name T280
Test name
Test status
Simulation time 54620678088 ps
CPU time 208.58 seconds
Started Jul 12 06:01:12 PM PDT 24
Finished Jul 12 06:04:43 PM PDT 24
Peak memory 202788 kb
Host smart-ff6bffc6-2c27-469f-a69d-1b940b9a2413
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841196807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.3841196807
Directory /workspace/17.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.433270437
Short name T50
Test name
Test status
Simulation time 1447101642 ps
CPU time 17.82 seconds
Started Jul 12 06:01:13 PM PDT 24
Finished Jul 12 06:01:32 PM PDT 24
Peak memory 257832 kb
Host smart-f86f1646-2f8f-477b-bc2d-b59974910ca5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433270437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_throughput_w_partial_write.433270437
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1072267979
Short name T349
Test name
Test status
Simulation time 28441485287 ps
CPU time 1597.26 seconds
Started Jul 12 06:01:23 PM PDT 24
Finished Jul 12 06:28:01 PM PDT 24
Peak memory 378712 kb
Host smart-4f7f8354-a093-409f-abe9-38ebc6de98e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072267979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.1072267979
Directory /workspace/18.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/18.sram_ctrl_alert_test.4052731704
Short name T503
Test name
Test status
Simulation time 15882932 ps
CPU time 0.68 seconds
Started Jul 12 06:01:25 PM PDT 24
Finished Jul 12 06:01:26 PM PDT 24
Peak memory 202456 kb
Host smart-c9a10002-f349-4277-ba7b-52da7c9e5dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052731704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.4052731704
Directory /workspace/18.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/18.sram_ctrl_bijection.1139091515
Short name T626
Test name
Test status
Simulation time 258445842488 ps
CPU time 1536.94 seconds
Started Jul 12 06:01:25 PM PDT 24
Finished Jul 12 06:27:03 PM PDT 24
Peak memory 203360 kb
Host smart-9919a01e-1bb8-43fa-930c-6af318ffe3ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139091515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.1139091515
Directory /workspace/18.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/18.sram_ctrl_executable.3627638646
Short name T870
Test name
Test status
Simulation time 24291267489 ps
CPU time 594.59 seconds
Started Jul 12 06:01:21 PM PDT 24
Finished Jul 12 06:11:17 PM PDT 24
Peak memory 375684 kb
Host smart-eae46b00-820b-4ada-8809-cea8326fa07d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627638646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.3627638646
Directory /workspace/18.sram_ctrl_executable/latest


Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.983058980
Short name T831
Test name
Test status
Simulation time 21244934811 ps
CPU time 66.28 seconds
Started Jul 12 06:01:23 PM PDT 24
Finished Jul 12 06:02:30 PM PDT 24
Peak memory 202776 kb
Host smart-6c3341a6-ac2e-4fa1-a3ba-c3b4c4068d31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983058980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc
alation.983058980
Directory /workspace/18.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.3398495427
Short name T604
Test name
Test status
Simulation time 820299700 ps
CPU time 149.06 seconds
Started Jul 12 06:01:22 PM PDT 24
Finished Jul 12 06:03:52 PM PDT 24
Peak memory 365436 kb
Host smart-7c695435-6186-4d0f-b1cb-78c7f533b813
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398495427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.3398495427
Directory /workspace/18.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.4205382761
Short name T609
Test name
Test status
Simulation time 6569113502 ps
CPU time 76.61 seconds
Started Jul 12 06:01:23 PM PDT 24
Finished Jul 12 06:02:40 PM PDT 24
Peak memory 210908 kb
Host smart-1d6da9dd-442c-4a2b-b2de-f3a6b45dc853
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205382761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.4205382761
Directory /workspace/18.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.2372690127
Short name T333
Test name
Test status
Simulation time 2107331797 ps
CPU time 127.93 seconds
Started Jul 12 06:01:19 PM PDT 24
Finished Jul 12 06:03:28 PM PDT 24
Peak memory 210816 kb
Host smart-3710335a-e4ed-4aa9-965c-ad4b0e2ff51c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372690127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.2372690127
Directory /workspace/18.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.3021958376
Short name T937
Test name
Test status
Simulation time 22417816200 ps
CPU time 469.19 seconds
Started Jul 12 06:01:24 PM PDT 24
Finished Jul 12 06:09:14 PM PDT 24
Peak memory 351196 kb
Host smart-1db69287-dc90-4c13-ad3b-a3f85977ee75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021958376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.3021958376
Directory /workspace/18.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/18.sram_ctrl_partial_access.2658371307
Short name T402
Test name
Test status
Simulation time 781810047 ps
CPU time 50.67 seconds
Started Jul 12 06:01:20 PM PDT 24
Finished Jul 12 06:02:11 PM PDT 24
Peak memory 300792 kb
Host smart-ab37e8b1-886d-41c8-a983-0afcabf1fcc7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658371307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.2658371307
Directory /workspace/18.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3083299228
Short name T287
Test name
Test status
Simulation time 12500261650 ps
CPU time 303.23 seconds
Started Jul 12 06:01:20 PM PDT 24
Finished Jul 12 06:06:24 PM PDT 24
Peak memory 202796 kb
Host smart-fcc14244-e39f-45b5-bb8a-33a23cf0510d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083299228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.3083299228
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.491910445
Short name T263
Test name
Test status
Simulation time 721485851 ps
CPU time 3.13 seconds
Started Jul 12 06:01:21 PM PDT 24
Finished Jul 12 06:01:25 PM PDT 24
Peak memory 202800 kb
Host smart-c78d59e5-fe53-49bd-9f55-0b4e83e38e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491910445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.491910445
Directory /workspace/18.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/18.sram_ctrl_regwen.1520138902
Short name T356
Test name
Test status
Simulation time 2558773378 ps
CPU time 670.64 seconds
Started Jul 12 06:01:19 PM PDT 24
Finished Jul 12 06:12:30 PM PDT 24
Peak memory 375592 kb
Host smart-2b35ef8e-572b-43de-a196-ba484a219214
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520138902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1520138902
Directory /workspace/18.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/18.sram_ctrl_smoke.4120027818
Short name T505
Test name
Test status
Simulation time 957908233 ps
CPU time 114.79 seconds
Started Jul 12 06:01:20 PM PDT 24
Finished Jul 12 06:03:16 PM PDT 24
Peak memory 346788 kb
Host smart-0450598b-c563-460c-befc-a8d72c3ea3fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120027818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.4120027818
Directory /workspace/18.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/18.sram_ctrl_stress_all.3643787703
Short name T834
Test name
Test status
Simulation time 140933218707 ps
CPU time 2079.52 seconds
Started Jul 12 06:01:25 PM PDT 24
Finished Jul 12 06:36:05 PM PDT 24
Peak memory 384776 kb
Host smart-dab006b6-a4c3-45c2-8e26-3ed0f17c66ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643787703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.3643787703
Directory /workspace/18.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3083772250
Short name T911
Test name
Test status
Simulation time 2755487591 ps
CPU time 127.19 seconds
Started Jul 12 06:01:20 PM PDT 24
Finished Jul 12 06:03:27 PM PDT 24
Peak memory 211064 kb
Host smart-9596ccba-ebac-49c0-922e-5932ad848247
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3083772250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.3083772250
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2857904050
Short name T867
Test name
Test status
Simulation time 21087778248 ps
CPU time 363.32 seconds
Started Jul 12 06:01:21 PM PDT 24
Finished Jul 12 06:07:25 PM PDT 24
Peak memory 202788 kb
Host smart-dbdb1e76-0339-4bdb-a203-6fd870b26f8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857904050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.2857904050
Directory /workspace/18.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1234987765
Short name T536
Test name
Test status
Simulation time 2990604692 ps
CPU time 71.02 seconds
Started Jul 12 06:01:21 PM PDT 24
Finished Jul 12 06:02:33 PM PDT 24
Peak memory 322352 kb
Host smart-688e5f5c-cf5e-4cd4-b8b8-3fa46391d0cf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234987765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1234987765
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.2722049382
Short name T12
Test name
Test status
Simulation time 62175946606 ps
CPU time 961.4 seconds
Started Jul 12 06:01:25 PM PDT 24
Finished Jul 12 06:17:27 PM PDT 24
Peak memory 374640 kb
Host smart-743fd90b-1983-4c72-a1db-ed8f9569f613
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722049382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.2722049382
Directory /workspace/19.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/19.sram_ctrl_alert_test.3485243251
Short name T427
Test name
Test status
Simulation time 14602871 ps
CPU time 0.73 seconds
Started Jul 12 06:01:28 PM PDT 24
Finished Jul 12 06:01:30 PM PDT 24
Peak memory 202364 kb
Host smart-eb823d02-9206-4f82-a107-3141a3bac453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485243251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.3485243251
Directory /workspace/19.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/19.sram_ctrl_bijection.3991606798
Short name T661
Test name
Test status
Simulation time 193241402081 ps
CPU time 1636 seconds
Started Jul 12 06:01:25 PM PDT 24
Finished Jul 12 06:28:42 PM PDT 24
Peak memory 202976 kb
Host smart-889cbb43-bbd0-42c2-a463-21d55f789d78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991606798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.3991606798
Directory /workspace/19.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/19.sram_ctrl_executable.3115320653
Short name T209
Test name
Test status
Simulation time 6127312541 ps
CPU time 160.77 seconds
Started Jul 12 06:01:24 PM PDT 24
Finished Jul 12 06:04:06 PM PDT 24
Peak memory 359264 kb
Host smart-35ce3621-1945-48e5-b517-fcd7a3a611c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115320653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.3115320653
Directory /workspace/19.sram_ctrl_executable/latest


Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.4047578170
Short name T719
Test name
Test status
Simulation time 62294991995 ps
CPU time 104 seconds
Started Jul 12 06:01:25 PM PDT 24
Finished Jul 12 06:03:10 PM PDT 24
Peak memory 211032 kb
Host smart-e5ae0528-b501-465e-9178-1812f74cf16a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047578170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.4047578170
Directory /workspace/19.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.2199505492
Short name T657
Test name
Test status
Simulation time 1548778615 ps
CPU time 96.87 seconds
Started Jul 12 06:01:25 PM PDT 24
Finished Jul 12 06:03:02 PM PDT 24
Peak memory 357064 kb
Host smart-de57df57-306c-4f5f-8733-13d74e9f58e6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199505492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.2199505492
Directory /workspace/19.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1489144699
Short name T712
Test name
Test status
Simulation time 3669336769 ps
CPU time 84.51 seconds
Started Jul 12 06:01:34 PM PDT 24
Finished Jul 12 06:03:00 PM PDT 24
Peak memory 219088 kb
Host smart-e18b3dd1-25bb-4315-b1b9-554a9e88cd8f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489144699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.1489144699
Directory /workspace/19.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.1201213656
Short name T449
Test name
Test status
Simulation time 10801086864 ps
CPU time 166.39 seconds
Started Jul 12 06:01:28 PM PDT 24
Finished Jul 12 06:04:15 PM PDT 24
Peak memory 202952 kb
Host smart-2f81161c-4e7b-4c83-9976-c136842c037f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201213656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.1201213656
Directory /workspace/19.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.2993554138
Short name T851
Test name
Test status
Simulation time 231737259789 ps
CPU time 1621.66 seconds
Started Jul 12 06:01:19 PM PDT 24
Finished Jul 12 06:28:21 PM PDT 24
Peak memory 377356 kb
Host smart-39a2337d-b7ae-4c9b-b33b-e4528dfb32f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993554138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.2993554138
Directory /workspace/19.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/19.sram_ctrl_partial_access.3290398191
Short name T29
Test name
Test status
Simulation time 696500299 ps
CPU time 5.5 seconds
Started Jul 12 06:01:34 PM PDT 24
Finished Jul 12 06:01:41 PM PDT 24
Peak memory 202500 kb
Host smart-fdfe731b-3cee-4e6b-811e-042de5efc1cb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290398191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.3290398191
Directory /workspace/19.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1599107914
Short name T408
Test name
Test status
Simulation time 5197036381 ps
CPU time 244.65 seconds
Started Jul 12 06:01:26 PM PDT 24
Finished Jul 12 06:05:31 PM PDT 24
Peak memory 202772 kb
Host smart-31106823-0649-49d3-af35-360c6e05f3cc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599107914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.1599107914
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.295927802
Short name T279
Test name
Test status
Simulation time 359151990 ps
CPU time 3.26 seconds
Started Jul 12 06:01:27 PM PDT 24
Finished Jul 12 06:01:31 PM PDT 24
Peak memory 202804 kb
Host smart-1418e9b4-9e37-46db-8fd3-953b9ce27b9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295927802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.295927802
Directory /workspace/19.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/19.sram_ctrl_regwen.39733539
Short name T665
Test name
Test status
Simulation time 24975572751 ps
CPU time 250.79 seconds
Started Jul 12 06:01:26 PM PDT 24
Finished Jul 12 06:05:38 PM PDT 24
Peak memory 339804 kb
Host smart-5f98494a-9e59-4b83-87cf-5c93851586e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39733539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.39733539
Directory /workspace/19.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/19.sram_ctrl_smoke.2608959899
Short name T703
Test name
Test status
Simulation time 5831842791 ps
CPU time 24.41 seconds
Started Jul 12 06:01:20 PM PDT 24
Finished Jul 12 06:01:46 PM PDT 24
Peak memory 202796 kb
Host smart-fc3c21d3-31db-4e3e-acd6-eb90f5c0bb17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608959899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2608959899
Directory /workspace/19.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/19.sram_ctrl_stress_all.537569384
Short name T601
Test name
Test status
Simulation time 71225570804 ps
CPU time 1641.77 seconds
Started Jul 12 06:01:30 PM PDT 24
Finished Jul 12 06:28:52 PM PDT 24
Peak memory 382692 kb
Host smart-bb5391f7-1b65-49fa-a011-c25e10e8309e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537569384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_stress_all.537569384
Directory /workspace/19.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2778492034
Short name T552
Test name
Test status
Simulation time 1707104599 ps
CPU time 29.82 seconds
Started Jul 12 06:01:26 PM PDT 24
Finished Jul 12 06:01:57 PM PDT 24
Peak memory 210996 kb
Host smart-07d767e9-b39b-471a-9de6-0ddab029aaaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2778492034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2778492034
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1991921332
Short name T745
Test name
Test status
Simulation time 4618518724 ps
CPU time 311.11 seconds
Started Jul 12 06:01:25 PM PDT 24
Finished Jul 12 06:06:38 PM PDT 24
Peak memory 202768 kb
Host smart-a458a7ec-cb6b-4bd7-9a64-463e3568acb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991921332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.1991921332
Directory /workspace/19.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.630243446
Short name T403
Test name
Test status
Simulation time 1620489081 ps
CPU time 20.39 seconds
Started Jul 12 06:01:26 PM PDT 24
Finished Jul 12 06:01:47 PM PDT 24
Peak memory 267160 kb
Host smart-7528588e-929b-47d5-9f23-acb71d8d6d72
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630243446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.630243446
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.4139380070
Short name T89
Test name
Test status
Simulation time 57019713896 ps
CPU time 894.17 seconds
Started Jul 12 06:00:27 PM PDT 24
Finished Jul 12 06:15:23 PM PDT 24
Peak memory 376880 kb
Host smart-dbbba7d9-13c1-4ef2-adfd-58c17d44aa29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139380070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.4139380070
Directory /workspace/2.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/2.sram_ctrl_alert_test.1673714546
Short name T653
Test name
Test status
Simulation time 21940892 ps
CPU time 0.68 seconds
Started Jul 12 06:00:28 PM PDT 24
Finished Jul 12 06:00:30 PM PDT 24
Peak memory 202452 kb
Host smart-dd0ee110-6467-4095-aaf2-35e4417edf30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673714546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.1673714546
Directory /workspace/2.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/2.sram_ctrl_bijection.1534516870
Short name T754
Test name
Test status
Simulation time 131087060738 ps
CPU time 2107.99 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:35:41 PM PDT 24
Peak memory 202896 kb
Host smart-a8336f6d-abdf-4959-9183-a47932f7bc0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534516870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
1534516870
Directory /workspace/2.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/2.sram_ctrl_executable.598020919
Short name T713
Test name
Test status
Simulation time 23917248551 ps
CPU time 1042.7 seconds
Started Jul 12 06:00:35 PM PDT 24
Finished Jul 12 06:17:59 PM PDT 24
Peak memory 373588 kb
Host smart-d865cb1a-c28b-48d8-a833-1e1f48ccaef9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598020919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable
.598020919
Directory /workspace/2.sram_ctrl_executable/latest


Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.2716466430
Short name T450
Test name
Test status
Simulation time 41573683799 ps
CPU time 66.58 seconds
Started Jul 12 06:00:28 PM PDT 24
Finished Jul 12 06:01:36 PM PDT 24
Peak memory 202804 kb
Host smart-081b3842-50c4-49b1-b3dd-4727dec898f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716466430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.2716466430
Directory /workspace/2.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.3514855240
Short name T881
Test name
Test status
Simulation time 3067636883 ps
CPU time 79.62 seconds
Started Jul 12 06:00:32 PM PDT 24
Finished Jul 12 06:01:53 PM PDT 24
Peak memory 320348 kb
Host smart-d9c99344-5d5b-419d-919f-88c997d6e6c2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514855240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.3514855240
Directory /workspace/2.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2134664567
Short name T801
Test name
Test status
Simulation time 11928805231 ps
CPU time 92.42 seconds
Started Jul 12 06:00:36 PM PDT 24
Finished Jul 12 06:02:10 PM PDT 24
Peak memory 211000 kb
Host smart-1a921211-2b95-4cb6-8d42-e770695851e7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134664567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.2134664567
Directory /workspace/2.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.2835670799
Short name T771
Test name
Test status
Simulation time 27689459873 ps
CPU time 334.89 seconds
Started Jul 12 06:00:31 PM PDT 24
Finished Jul 12 06:06:08 PM PDT 24
Peak memory 210932 kb
Host smart-f59834ba-7f9d-4680-a280-a8342dfa73f3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835670799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.2835670799
Directory /workspace/2.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.1200467816
Short name T772
Test name
Test status
Simulation time 91400453112 ps
CPU time 1974.6 seconds
Started Jul 12 06:00:31 PM PDT 24
Finished Jul 12 06:33:28 PM PDT 24
Peak memory 380832 kb
Host smart-45e3ae38-f47b-4634-bc05-5f2d3c63bb16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200467816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.1200467816
Directory /workspace/2.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/2.sram_ctrl_partial_access.2602095920
Short name T844
Test name
Test status
Simulation time 654540772 ps
CPU time 9.13 seconds
Started Jul 12 06:00:35 PM PDT 24
Finished Jul 12 06:00:46 PM PDT 24
Peak memory 202648 kb
Host smart-091b0260-f22f-4804-b840-468509165617
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602095920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.2602095920
Directory /workspace/2.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2654746610
Short name T321
Test name
Test status
Simulation time 7314298625 ps
CPU time 181.46 seconds
Started Jul 12 06:00:33 PM PDT 24
Finished Jul 12 06:03:36 PM PDT 24
Peak memory 202740 kb
Host smart-7b92d31d-9130-40c7-8c5f-7d5437c597a4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654746610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.2654746610
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.3814642996
Short name T422
Test name
Test status
Simulation time 4204220101 ps
CPU time 4.61 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:00:37 PM PDT 24
Peak memory 202904 kb
Host smart-539d2866-1570-40cc-834e-c7dafb6620bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814642996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3814642996
Directory /workspace/2.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/2.sram_ctrl_regwen.4060905066
Short name T145
Test name
Test status
Simulation time 23091665549 ps
CPU time 2255.24 seconds
Started Jul 12 06:00:28 PM PDT 24
Finished Jul 12 06:38:05 PM PDT 24
Peak memory 381776 kb
Host smart-120ffa78-eaa2-4782-be4f-cebdbcf795c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060905066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.4060905066
Directory /workspace/2.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.3869301506
Short name T17
Test name
Test status
Simulation time 644238086 ps
CPU time 3.42 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:00:35 PM PDT 24
Peak memory 222412 kb
Host smart-1d53e2f5-9cd8-4ce0-9a9a-c73795f12609
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869301506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.3869301506
Directory /workspace/2.sram_ctrl_sec_cm/latest


Test location /workspace/coverage/default/2.sram_ctrl_smoke.3270469457
Short name T688
Test name
Test status
Simulation time 3567089364 ps
CPU time 12.23 seconds
Started Jul 12 06:00:24 PM PDT 24
Finished Jul 12 06:00:39 PM PDT 24
Peak memory 202836 kb
Host smart-7782aaa9-cd7b-4101-9ca2-b628166693dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270469457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3270469457
Directory /workspace/2.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/2.sram_ctrl_stress_all.2703105458
Short name T823
Test name
Test status
Simulation time 50330611316 ps
CPU time 2087.97 seconds
Started Jul 12 06:00:38 PM PDT 24
Finished Jul 12 06:35:27 PM PDT 24
Peak memory 376616 kb
Host smart-af55e194-ac29-4afc-89c3-b6cdeb2b4f77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703105458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.2703105458
Directory /workspace/2.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2489719536
Short name T453
Test name
Test status
Simulation time 1077855264 ps
CPU time 10.17 seconds
Started Jul 12 06:00:29 PM PDT 24
Finished Jul 12 06:00:42 PM PDT 24
Peak memory 211080 kb
Host smart-87dc9556-65ac-4013-8a49-b80365a50cf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2489719536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2489719536
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1875973996
Short name T39
Test name
Test status
Simulation time 17336082980 ps
CPU time 269.41 seconds
Started Jul 12 06:00:28 PM PDT 24
Finished Jul 12 06:04:59 PM PDT 24
Peak memory 202832 kb
Host smart-8511452c-90cf-4525-af53-46b89c691454
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875973996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.1875973996
Directory /workspace/2.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.54160343
Short name T366
Test name
Test status
Simulation time 2291036220 ps
CPU time 143.26 seconds
Started Jul 12 06:00:29 PM PDT 24
Finished Jul 12 06:02:55 PM PDT 24
Peak memory 368332 kb
Host smart-f0bf08a3-1833-432d-968a-361f2860b6e1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54160343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.sram_ctrl_throughput_w_partial_write.54160343
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3704019106
Short name T738
Test name
Test status
Simulation time 7687311977 ps
CPU time 440.22 seconds
Started Jul 12 06:01:31 PM PDT 24
Finished Jul 12 06:08:51 PM PDT 24
Peak memory 361304 kb
Host smart-bfbf1b5a-3e81-4452-9ad1-62bde3b0e0b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704019106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.3704019106
Directory /workspace/20.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/20.sram_ctrl_alert_test.214364168
Short name T596
Test name
Test status
Simulation time 34335490 ps
CPU time 0.61 seconds
Started Jul 12 06:01:33 PM PDT 24
Finished Jul 12 06:01:35 PM PDT 24
Peak memory 202504 kb
Host smart-68549f5e-7bb3-4eb1-9d42-81b3c3a830c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214364168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.214364168
Directory /workspace/20.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/20.sram_ctrl_bijection.2160291724
Short name T646
Test name
Test status
Simulation time 287513093340 ps
CPU time 2400.24 seconds
Started Jul 12 06:01:32 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 203332 kb
Host smart-8168f4b8-1882-4303-9088-dd60313783fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160291724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.2160291724
Directory /workspace/20.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/20.sram_ctrl_executable.2635548898
Short name T406
Test name
Test status
Simulation time 16818245464 ps
CPU time 736.97 seconds
Started Jul 12 06:01:32 PM PDT 24
Finished Jul 12 06:13:50 PM PDT 24
Peak memory 375640 kb
Host smart-5adcc0f4-c140-49de-ae9c-1728ab3d0bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635548898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.2635548898
Directory /workspace/20.sram_ctrl_executable/latest


Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.411681045
Short name T202
Test name
Test status
Simulation time 16904746728 ps
CPU time 61.92 seconds
Started Jul 12 06:01:33 PM PDT 24
Finished Jul 12 06:02:36 PM PDT 24
Peak memory 202808 kb
Host smart-8c301a62-4b4e-4c02-bb51-868186fc60cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411681045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc
alation.411681045
Directory /workspace/20.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.1471768047
Short name T784
Test name
Test status
Simulation time 3119361474 ps
CPU time 119.98 seconds
Started Jul 12 06:01:34 PM PDT 24
Finished Jul 12 06:03:35 PM PDT 24
Peak memory 344828 kb
Host smart-41b7f0e0-bf50-4ac8-850a-62d29e19927d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471768047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.1471768047
Directory /workspace/20.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.893424657
Short name T454
Test name
Test status
Simulation time 3399896428 ps
CPU time 93 seconds
Started Jul 12 06:01:33 PM PDT 24
Finished Jul 12 06:03:08 PM PDT 24
Peak memory 211000 kb
Host smart-d7e4f9b0-c11f-4c76-ab93-9d1b69f9d866
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893424657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.sram_ctrl_mem_partial_access.893424657
Directory /workspace/20.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.838723453
Short name T38
Test name
Test status
Simulation time 51260384981 ps
CPU time 344.66 seconds
Started Jul 12 06:01:35 PM PDT 24
Finished Jul 12 06:07:21 PM PDT 24
Peak memory 202752 kb
Host smart-6971eed6-56aa-4391-8aec-99506130a50e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838723453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl
_mem_walk.838723453
Directory /workspace/20.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.2897810526
Short name T765
Test name
Test status
Simulation time 10014739270 ps
CPU time 490.12 seconds
Started Jul 12 06:01:26 PM PDT 24
Finished Jul 12 06:09:37 PM PDT 24
Peak memory 373488 kb
Host smart-8005b183-4905-44fb-8efb-505b3cbdd88c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897810526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.2897810526
Directory /workspace/20.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/20.sram_ctrl_partial_access.1201479916
Short name T181
Test name
Test status
Simulation time 665233803 ps
CPU time 26.02 seconds
Started Jul 12 06:01:39 PM PDT 24
Finished Jul 12 06:02:05 PM PDT 24
Peak memory 282416 kb
Host smart-3f4d37b1-fafa-46a6-a0af-de7377edd70b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201479916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.1201479916
Directory /workspace/20.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3299615355
Short name T570
Test name
Test status
Simulation time 103334143791 ps
CPU time 480.07 seconds
Started Jul 12 06:01:39 PM PDT 24
Finished Jul 12 06:09:40 PM PDT 24
Peak memory 202812 kb
Host smart-f0e1d75f-635f-4292-9aa5-aefd489a1e10
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299615355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.3299615355
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.4120047476
Short name T777
Test name
Test status
Simulation time 366840316 ps
CPU time 3.29 seconds
Started Jul 12 06:01:33 PM PDT 24
Finished Jul 12 06:01:37 PM PDT 24
Peak memory 202836 kb
Host smart-e03b47b9-257a-4f86-84c8-a21b6c915c50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120047476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.4120047476
Directory /workspace/20.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/20.sram_ctrl_regwen.2600579568
Short name T482
Test name
Test status
Simulation time 34546058529 ps
CPU time 968.75 seconds
Started Jul 12 06:01:33 PM PDT 24
Finished Jul 12 06:17:43 PM PDT 24
Peak memory 380764 kb
Host smart-44ec22cb-2c8c-49d5-a7c2-03e96a0b8224
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600579568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2600579568
Directory /workspace/20.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/20.sram_ctrl_smoke.2270019066
Short name T901
Test name
Test status
Simulation time 3117355402 ps
CPU time 16.29 seconds
Started Jul 12 06:01:26 PM PDT 24
Finished Jul 12 06:01:43 PM PDT 24
Peak memory 202800 kb
Host smart-50e10681-cff2-4146-adca-c0df6866c485
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270019066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2270019066
Directory /workspace/20.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/20.sram_ctrl_stress_all.1534792270
Short name T766
Test name
Test status
Simulation time 251737689323 ps
CPU time 4545.24 seconds
Started Jul 12 06:01:32 PM PDT 24
Finished Jul 12 07:17:18 PM PDT 24
Peak memory 370512 kb
Host smart-a735886b-a012-4099-afd9-95be8981cac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534792270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.1534792270
Directory /workspace/20.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3120420993
Short name T868
Test name
Test status
Simulation time 1774734377 ps
CPU time 26.72 seconds
Started Jul 12 06:01:31 PM PDT 24
Finished Jul 12 06:01:58 PM PDT 24
Peak memory 211004 kb
Host smart-a8385d51-96f5-4b47-bb8e-c9de90810bea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3120420993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3120420993
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1305960614
Short name T761
Test name
Test status
Simulation time 61857624093 ps
CPU time 367.25 seconds
Started Jul 12 06:01:26 PM PDT 24
Finished Jul 12 06:07:34 PM PDT 24
Peak memory 202768 kb
Host smart-65e8ab30-e9f9-4506-bf6a-60ad68943d48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305960614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1305960614
Directory /workspace/20.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.470705672
Short name T584
Test name
Test status
Simulation time 713961122 ps
CPU time 12.21 seconds
Started Jul 12 06:01:33 PM PDT 24
Finished Jul 12 06:01:47 PM PDT 24
Peak memory 235548 kb
Host smart-eac6dd6d-bcc1-49b6-a7e5-ab09983ad53f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470705672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.470705672
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2749356431
Short name T238
Test name
Test status
Simulation time 17081632495 ps
CPU time 1066.46 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:19:28 PM PDT 24
Peak memory 378672 kb
Host smart-04f257a7-79e3-4337-9a2f-67da75244363
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749356431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.2749356431
Directory /workspace/21.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/21.sram_ctrl_alert_test.1174831804
Short name T935
Test name
Test status
Simulation time 16435282 ps
CPU time 0.66 seconds
Started Jul 12 06:01:41 PM PDT 24
Finished Jul 12 06:01:43 PM PDT 24
Peak memory 202336 kb
Host smart-b44ca5d2-ed26-4c3c-9f93-cf6dabab570c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174831804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.1174831804
Directory /workspace/21.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/21.sram_ctrl_bijection.2113181591
Short name T915
Test name
Test status
Simulation time 117423218201 ps
CPU time 2635.46 seconds
Started Jul 12 06:01:32 PM PDT 24
Finished Jul 12 06:45:29 PM PDT 24
Peak memory 203388 kb
Host smart-f16a622f-4d54-4e8b-a8ac-b0c7e63b3430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113181591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.2113181591
Directory /workspace/21.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/21.sram_ctrl_executable.713877758
Short name T312
Test name
Test status
Simulation time 11784360279 ps
CPU time 810.89 seconds
Started Jul 12 06:01:41 PM PDT 24
Finished Jul 12 06:15:14 PM PDT 24
Peak memory 379688 kb
Host smart-8362e152-52ef-4337-a0d0-d68b9d57bfa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713877758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executabl
e.713877758
Directory /workspace/21.sram_ctrl_executable/latest


Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.1762639497
Short name T5
Test name
Test status
Simulation time 55355839978 ps
CPU time 99.31 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:03:20 PM PDT 24
Peak memory 210996 kb
Host smart-d7c08c10-b794-409e-ab7d-f089fc08b28c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762639497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.1762639497
Directory /workspace/21.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.5014185
Short name T177
Test name
Test status
Simulation time 1494828259 ps
CPU time 56.74 seconds
Started Jul 12 06:01:38 PM PDT 24
Finished Jul 12 06:02:35 PM PDT 24
Peak memory 326652 kb
Host smart-b53a89be-d397-4bfb-8aab-648169c446ae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5014185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base
_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.sram_ctrl_max_throughput.5014185
Directory /workspace/21.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3774005125
Short name T518
Test name
Test status
Simulation time 5654770933 ps
CPU time 176.93 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:04:38 PM PDT 24
Peak memory 219164 kb
Host smart-e4b4fdc2-a73f-4a88-9d88-a46f6e188e6d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774005125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.3774005125
Directory /workspace/21.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.1707758112
Short name T261
Test name
Test status
Simulation time 2774933680 ps
CPU time 143.47 seconds
Started Jul 12 06:01:39 PM PDT 24
Finished Jul 12 06:04:03 PM PDT 24
Peak memory 210940 kb
Host smart-7c68b40b-1a68-4cc0-88f7-fb2606c79cf0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707758112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.1707758112
Directory /workspace/21.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.2809777503
Short name T862
Test name
Test status
Simulation time 4245828444 ps
CPU time 110.52 seconds
Started Jul 12 06:01:38 PM PDT 24
Finished Jul 12 06:03:29 PM PDT 24
Peak memory 320384 kb
Host smart-ca824c24-de8f-46f4-9698-ae50750adb77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809777503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.2809777503
Directory /workspace/21.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/21.sram_ctrl_partial_access.1219170691
Short name T668
Test name
Test status
Simulation time 3501772994 ps
CPU time 10.68 seconds
Started Jul 12 06:01:38 PM PDT 24
Finished Jul 12 06:01:49 PM PDT 24
Peak memory 202804 kb
Host smart-3857ad74-aba1-4fd4-9076-ce9a56622c22
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219170691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.1219170691
Directory /workspace/21.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2979146549
Short name T447
Test name
Test status
Simulation time 12887887816 ps
CPU time 299.61 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:06:40 PM PDT 24
Peak memory 202796 kb
Host smart-6a51408c-794d-4c41-901a-d9f4a0e53254
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979146549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.2979146549
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.2283182516
Short name T841
Test name
Test status
Simulation time 345130683 ps
CPU time 3.26 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:01:45 PM PDT 24
Peak memory 202812 kb
Host smart-3ba42154-dd34-4d31-8c4a-7ac3b837098a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283182516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2283182516
Directory /workspace/21.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/21.sram_ctrl_regwen.1604828415
Short name T2
Test name
Test status
Simulation time 12472151414 ps
CPU time 678.46 seconds
Started Jul 12 06:01:41 PM PDT 24
Finished Jul 12 06:13:01 PM PDT 24
Peak memory 371336 kb
Host smart-6e00f461-4764-4e04-bb9b-2cd212ae77d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604828415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1604828415
Directory /workspace/21.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/21.sram_ctrl_smoke.717307196
Short name T350
Test name
Test status
Simulation time 4812244542 ps
CPU time 21.17 seconds
Started Jul 12 06:01:33 PM PDT 24
Finished Jul 12 06:01:55 PM PDT 24
Peak memory 202820 kb
Host smart-2d4308d7-bfe8-4bc0-b43a-d4ea48e51179
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717307196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.717307196
Directory /workspace/21.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/21.sram_ctrl_stress_all.1068818762
Short name T364
Test name
Test status
Simulation time 1182386029313 ps
CPU time 5179.7 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 07:28:02 PM PDT 24
Peak memory 380700 kb
Host smart-93fe3c82-0d45-4e5f-b718-830ce9f18ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068818762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.sram_ctrl_stress_all.1068818762
Directory /workspace/21.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1447498509
Short name T707
Test name
Test status
Simulation time 1365088122 ps
CPU time 33.1 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:02:15 PM PDT 24
Peak memory 210980 kb
Host smart-6d714414-baa4-4219-b005-6e7357739d6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1447498509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1447498509
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2329295145
Short name T582
Test name
Test status
Simulation time 36101631181 ps
CPU time 228.46 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:05:30 PM PDT 24
Peak memory 202844 kb
Host smart-fbbe38b9-252a-46f9-8257-bf9ae2ed783c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329295145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.2329295145
Directory /workspace/21.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.297472012
Short name T311
Test name
Test status
Simulation time 4471883279 ps
CPU time 112.49 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:03:33 PM PDT 24
Peak memory 341840 kb
Host smart-e9cadcfd-df3b-4bdc-ab14-192295887e45
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297472012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.297472012
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1533367805
Short name T555
Test name
Test status
Simulation time 13293800629 ps
CPU time 979.63 seconds
Started Jul 12 06:01:52 PM PDT 24
Finished Jul 12 06:18:12 PM PDT 24
Peak memory 371460 kb
Host smart-c619c915-a484-436a-935d-14e231e7782f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533367805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.1533367805
Directory /workspace/22.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/22.sram_ctrl_alert_test.1650304813
Short name T426
Test name
Test status
Simulation time 13031813 ps
CPU time 0.68 seconds
Started Jul 12 06:01:47 PM PDT 24
Finished Jul 12 06:01:49 PM PDT 24
Peak memory 202460 kb
Host smart-5f34b370-348a-4397-8162-933b0750804c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650304813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.1650304813
Directory /workspace/22.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/22.sram_ctrl_bijection.3013126987
Short name T794
Test name
Test status
Simulation time 33474743489 ps
CPU time 1134.41 seconds
Started Jul 12 06:01:41 PM PDT 24
Finished Jul 12 06:20:37 PM PDT 24
Peak memory 202880 kb
Host smart-c5dd5530-c089-4771-9c9f-c6d083daed99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013126987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.3013126987
Directory /workspace/22.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/22.sram_ctrl_executable.108277498
Short name T799
Test name
Test status
Simulation time 27618860980 ps
CPU time 274.51 seconds
Started Jul 12 06:01:48 PM PDT 24
Finished Jul 12 06:06:23 PM PDT 24
Peak memory 335708 kb
Host smart-1c6b7479-8ffd-4109-98b4-6af70a670dbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108277498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl
e.108277498
Directory /workspace/22.sram_ctrl_executable/latest


Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.2515800758
Short name T530
Test name
Test status
Simulation time 30057584453 ps
CPU time 81.78 seconds
Started Jul 12 06:01:48 PM PDT 24
Finished Jul 12 06:03:10 PM PDT 24
Peak memory 215488 kb
Host smart-88d44b10-3255-4417-9129-db6460299330
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515800758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.2515800758
Directory /workspace/22.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.2013517439
Short name T167
Test name
Test status
Simulation time 9776197186 ps
CPU time 15.18 seconds
Started Jul 12 06:01:49 PM PDT 24
Finished Jul 12 06:02:05 PM PDT 24
Peak memory 235464 kb
Host smart-d103847d-8197-4d7e-85bd-48d6f74f4e8d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013517439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.2013517439
Directory /workspace/22.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2176684957
Short name T352
Test name
Test status
Simulation time 23663027559 ps
CPU time 85.37 seconds
Started Jul 12 06:01:48 PM PDT 24
Finished Jul 12 06:03:14 PM PDT 24
Peak memory 213444 kb
Host smart-1b39f85d-8c8d-42c4-85e9-e184a6406b84
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176684957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.2176684957
Directory /workspace/22.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.2139439571
Short name T865
Test name
Test status
Simulation time 62800663685 ps
CPU time 338.6 seconds
Started Jul 12 06:01:51 PM PDT 24
Finished Jul 12 06:07:30 PM PDT 24
Peak memory 210904 kb
Host smart-ba72456f-231c-4b9a-a72d-069a9f64d310
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139439571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.2139439571
Directory /workspace/22.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.3711047018
Short name T237
Test name
Test status
Simulation time 42029468734 ps
CPU time 430.3 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:08:52 PM PDT 24
Peak memory 366848 kb
Host smart-6762d285-b726-45a5-bc41-7958a1995f1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711047018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.3711047018
Directory /workspace/22.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/22.sram_ctrl_partial_access.3259282924
Short name T541
Test name
Test status
Simulation time 2723500923 ps
CPU time 21.22 seconds
Started Jul 12 06:01:41 PM PDT 24
Finished Jul 12 06:02:04 PM PDT 24
Peak memory 202752 kb
Host smart-d68509e3-1984-47ac-b9c7-56c6a00a774f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259282924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.3259282924
Directory /workspace/22.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3292852134
Short name T307
Test name
Test status
Simulation time 26846072000 ps
CPU time 403.71 seconds
Started Jul 12 06:01:48 PM PDT 24
Finished Jul 12 06:08:32 PM PDT 24
Peak memory 202732 kb
Host smart-d085655d-1c9d-4b65-8f84-457dce8b2ed2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292852134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.3292852134
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.4077199677
Short name T244
Test name
Test status
Simulation time 357174404 ps
CPU time 3.11 seconds
Started Jul 12 06:01:49 PM PDT 24
Finished Jul 12 06:01:53 PM PDT 24
Peak memory 202796 kb
Host smart-9c665e62-2399-44ff-ae74-3b557601bf84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077199677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.4077199677
Directory /workspace/22.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/22.sram_ctrl_regwen.2267049834
Short name T354
Test name
Test status
Simulation time 53054727808 ps
CPU time 674.27 seconds
Started Jul 12 06:01:52 PM PDT 24
Finished Jul 12 06:13:07 PM PDT 24
Peak memory 374452 kb
Host smart-40a7014e-490e-4e0f-8df0-1396dd7f803f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267049834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2267049834
Directory /workspace/22.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/22.sram_ctrl_smoke.242140293
Short name T764
Test name
Test status
Simulation time 4422187365 ps
CPU time 16.56 seconds
Started Jul 12 06:01:41 PM PDT 24
Finished Jul 12 06:01:59 PM PDT 24
Peak memory 202796 kb
Host smart-dc9acace-c718-4fa4-b160-a19f1a6e1d19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242140293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.242140293
Directory /workspace/22.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/22.sram_ctrl_stress_all.1174371631
Short name T491
Test name
Test status
Simulation time 161142218760 ps
CPU time 4694.41 seconds
Started Jul 12 06:01:50 PM PDT 24
Finished Jul 12 07:20:06 PM PDT 24
Peak memory 377684 kb
Host smart-5105e6bd-174a-4368-a95c-b7e06a6773a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174371631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.1174371631
Directory /workspace/22.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1340879255
Short name T335
Test name
Test status
Simulation time 185291837 ps
CPU time 8.17 seconds
Started Jul 12 06:01:49 PM PDT 24
Finished Jul 12 06:01:57 PM PDT 24
Peak memory 211048 kb
Host smart-e4168779-0412-4cdd-8eae-8f94f3c5e190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1340879255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1340879255
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.1561760391
Short name T795
Test name
Test status
Simulation time 7828060464 ps
CPU time 269.69 seconds
Started Jul 12 06:01:40 PM PDT 24
Finished Jul 12 06:06:11 PM PDT 24
Peak memory 202828 kb
Host smart-66c9d16c-b8a4-4cc5-8f09-4f7f39b3c137
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561760391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.1561760391
Directory /workspace/22.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.744322380
Short name T624
Test name
Test status
Simulation time 6514493174 ps
CPU time 149.71 seconds
Started Jul 12 06:01:52 PM PDT 24
Finished Jul 12 06:04:23 PM PDT 24
Peak memory 371632 kb
Host smart-751114f1-5048-4944-a5fe-ac1c7bdc11e4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744322380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.744322380
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1503470056
Short name T42
Test name
Test status
Simulation time 13140003137 ps
CPU time 729.15 seconds
Started Jul 12 06:01:53 PM PDT 24
Finished Jul 12 06:14:02 PM PDT 24
Peak memory 363388 kb
Host smart-f280755f-bd35-4cde-9a35-235be96bec6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503470056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.1503470056
Directory /workspace/23.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/23.sram_ctrl_alert_test.1338950312
Short name T415
Test name
Test status
Simulation time 17527706 ps
CPU time 0.68 seconds
Started Jul 12 06:01:57 PM PDT 24
Finished Jul 12 06:01:59 PM PDT 24
Peak memory 202284 kb
Host smart-1b0402ec-6be7-4e0e-8d83-c6ade214a18b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338950312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.1338950312
Directory /workspace/23.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/23.sram_ctrl_bijection.335924403
Short name T781
Test name
Test status
Simulation time 180966321245 ps
CPU time 2742.38 seconds
Started Jul 12 06:01:48 PM PDT 24
Finished Jul 12 06:47:31 PM PDT 24
Peak memory 203644 kb
Host smart-464ef5bf-77b2-4911-ae09-bc7038f81e96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335924403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.
335924403
Directory /workspace/23.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/23.sram_ctrl_executable.115944995
Short name T925
Test name
Test status
Simulation time 58888340064 ps
CPU time 987.57 seconds
Started Jul 12 06:01:56 PM PDT 24
Finished Jul 12 06:18:25 PM PDT 24
Peak memory 376588 kb
Host smart-9b44d749-dde5-4943-b56a-06faefd642e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115944995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executabl
e.115944995
Directory /workspace/23.sram_ctrl_executable/latest


Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.3567812126
Short name T277
Test name
Test status
Simulation time 2296178301 ps
CPU time 13.66 seconds
Started Jul 12 06:36:58 PM PDT 24
Finished Jul 12 06:37:14 PM PDT 24
Peak memory 202768 kb
Host smart-3130c701-690d-4176-978f-989a2781245f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567812126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.3567812126
Directory /workspace/23.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.3108853299
Short name T554
Test name
Test status
Simulation time 3498789177 ps
CPU time 156.71 seconds
Started Jul 12 06:01:50 PM PDT 24
Finished Jul 12 06:04:27 PM PDT 24
Peak memory 371040 kb
Host smart-aa35d7ba-e788-4f61-bfad-152f94b6a045
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108853299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.3108853299
Directory /workspace/23.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2145257474
Short name T90
Test name
Test status
Simulation time 4112235265 ps
CPU time 78.05 seconds
Started Jul 12 06:01:54 PM PDT 24
Finished Jul 12 06:03:13 PM PDT 24
Peak memory 211000 kb
Host smart-5ed1d8a6-b292-4325-8bae-3cedcaa7e6ef
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145257474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.2145257474
Directory /workspace/23.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.1979021289
Short name T574
Test name
Test status
Simulation time 57631307255 ps
CPU time 350.6 seconds
Started Jul 12 06:01:54 PM PDT 24
Finished Jul 12 06:07:45 PM PDT 24
Peak memory 210920 kb
Host smart-4fb19dcc-e119-4f07-9b95-60ae1f3495f3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979021289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.1979021289
Directory /workspace/23.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.1094441056
Short name T386
Test name
Test status
Simulation time 93315422200 ps
CPU time 679.92 seconds
Started Jul 12 06:01:49 PM PDT 24
Finished Jul 12 06:13:09 PM PDT 24
Peak memory 374028 kb
Host smart-55d7c0cf-0bac-47cf-9c9b-269f333336e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094441056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.1094441056
Directory /workspace/23.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/23.sram_ctrl_partial_access.3734723772
Short name T692
Test name
Test status
Simulation time 7750715188 ps
CPU time 27.31 seconds
Started Jul 12 06:01:53 PM PDT 24
Finished Jul 12 06:02:21 PM PDT 24
Peak memory 202796 kb
Host smart-dac1cac0-0c31-4c0b-87b1-cda057417a35
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734723772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.3734723772
Directory /workspace/23.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3988428363
Short name T869
Test name
Test status
Simulation time 88621788653 ps
CPU time 544.91 seconds
Started Jul 12 06:03:22 PM PDT 24
Finished Jul 12 06:12:28 PM PDT 24
Peak memory 202812 kb
Host smart-ce6cb8df-01be-4b75-98ed-02ee9c01b6de
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988428363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.3988428363
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.3783141537
Short name T24
Test name
Test status
Simulation time 2110393524 ps
CPU time 3.33 seconds
Started Jul 12 06:01:54 PM PDT 24
Finished Jul 12 06:01:58 PM PDT 24
Peak memory 202808 kb
Host smart-74befe58-4c08-4532-a435-f83bf31237ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783141537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3783141537
Directory /workspace/23.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/23.sram_ctrl_regwen.1299660989
Short name T534
Test name
Test status
Simulation time 10007614561 ps
CPU time 1046.51 seconds
Started Jul 12 06:01:54 PM PDT 24
Finished Jul 12 06:19:22 PM PDT 24
Peak memory 378648 kb
Host smart-15b02530-5537-4925-a7cb-af232a62380c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299660989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1299660989
Directory /workspace/23.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/23.sram_ctrl_smoke.4070576801
Short name T912
Test name
Test status
Simulation time 893681324 ps
CPU time 19.78 seconds
Started Jul 12 06:01:47 PM PDT 24
Finished Jul 12 06:02:07 PM PDT 24
Peak memory 202700 kb
Host smart-ad64a9bd-a251-4781-8490-0b9d1423b698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070576801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.4070576801
Directory /workspace/23.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/23.sram_ctrl_stress_all.834316900
Short name T674
Test name
Test status
Simulation time 285578944194 ps
CPU time 1729.53 seconds
Started Jul 12 06:01:57 PM PDT 24
Finished Jul 12 06:30:48 PM PDT 24
Peak memory 380736 kb
Host smart-95bf6349-de4b-421c-9d07-b98222e55ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834316900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_stress_all.834316900
Directory /workspace/23.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2984100131
Short name T338
Test name
Test status
Simulation time 324799679 ps
CPU time 11.23 seconds
Started Jul 12 06:01:55 PM PDT 24
Finished Jul 12 06:02:07 PM PDT 24
Peak memory 212748 kb
Host smart-b020df3f-4657-46ea-8216-d23ca14b3faa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2984100131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2984100131
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1391956838
Short name T355
Test name
Test status
Simulation time 9210661239 ps
CPU time 180.49 seconds
Started Jul 12 06:01:49 PM PDT 24
Finished Jul 12 06:04:50 PM PDT 24
Peak memory 202788 kb
Host smart-c64b5c3c-4885-4686-bf62-6e686953b6f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391956838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.1391956838
Directory /workspace/23.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2037276963
Short name T840
Test name
Test status
Simulation time 775948879 ps
CPU time 61.84 seconds
Started Jul 12 06:01:49 PM PDT 24
Finished Jul 12 06:02:52 PM PDT 24
Peak memory 301804 kb
Host smart-d74749ec-105b-41a7-b4b0-e6e50c40c0b2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037276963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2037276963
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2253917121
Short name T849
Test name
Test status
Simulation time 30607522321 ps
CPU time 439.35 seconds
Started Jul 12 06:01:56 PM PDT 24
Finished Jul 12 06:09:17 PM PDT 24
Peak memory 340000 kb
Host smart-c813dab4-7346-42fa-9b3d-695d7d5b0cc0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253917121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.2253917121
Directory /workspace/24.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/24.sram_ctrl_alert_test.1416623518
Short name T652
Test name
Test status
Simulation time 44967702 ps
CPU time 0.7 seconds
Started Jul 12 06:02:02 PM PDT 24
Finished Jul 12 06:02:03 PM PDT 24
Peak memory 202500 kb
Host smart-229bc674-58eb-421d-b229-d062a28160cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416623518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.1416623518
Directory /workspace/24.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/24.sram_ctrl_bijection.1421849278
Short name T610
Test name
Test status
Simulation time 962499835323 ps
CPU time 2793.04 seconds
Started Jul 12 06:01:55 PM PDT 24
Finished Jul 12 06:48:29 PM PDT 24
Peak memory 203444 kb
Host smart-5906128a-050a-4e67-95fc-b569ed08004e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421849278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.1421849278
Directory /workspace/24.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/24.sram_ctrl_executable.714284327
Short name T493
Test name
Test status
Simulation time 48014962763 ps
CPU time 1670.12 seconds
Started Jul 12 06:01:54 PM PDT 24
Finished Jul 12 06:29:45 PM PDT 24
Peak memory 376608 kb
Host smart-e6b36ed7-b1fe-4fe8-8f7b-438980a81ccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714284327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executabl
e.714284327
Directory /workspace/24.sram_ctrl_executable/latest


Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.80291786
Short name T233
Test name
Test status
Simulation time 86649967342 ps
CPU time 97.84 seconds
Started Jul 12 06:01:58 PM PDT 24
Finished Jul 12 06:03:37 PM PDT 24
Peak memory 215532 kb
Host smart-c77417bc-803a-4ad5-8141-4d051c09e709
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80291786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esca
lation.80291786
Directory /workspace/24.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.1169578596
Short name T198
Test name
Test status
Simulation time 3068547399 ps
CPU time 51.12 seconds
Started Jul 12 06:01:55 PM PDT 24
Finished Jul 12 06:02:47 PM PDT 24
Peak memory 324372 kb
Host smart-5383fa80-ea22-4ef6-ba05-30d822f82d22
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169578596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.1169578596
Directory /workspace/24.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.45860854
Short name T756
Test name
Test status
Simulation time 9714312252 ps
CPU time 88.26 seconds
Started Jul 12 06:01:55 PM PDT 24
Finished Jul 12 06:03:24 PM PDT 24
Peak memory 210992 kb
Host smart-2f4222c3-8214-48a9-bfb7-69ff7bb2dea2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45860854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_mem_partial_access.45860854
Directory /workspace/24.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.2531760540
Short name T900
Test name
Test status
Simulation time 26262716535 ps
CPU time 307.47 seconds
Started Jul 12 06:01:55 PM PDT 24
Finished Jul 12 06:07:04 PM PDT 24
Peak memory 210964 kb
Host smart-eff69a0e-3cd7-4ea4-9a18-b9100dfb24d0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531760540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.2531760540
Directory /workspace/24.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.272108690
Short name T728
Test name
Test status
Simulation time 97045557096 ps
CPU time 1332.83 seconds
Started Jul 12 06:01:58 PM PDT 24
Finished Jul 12 06:24:12 PM PDT 24
Peak memory 379704 kb
Host smart-922c1239-9fb1-4644-a147-0ca0dad4bddc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272108690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multip
le_keys.272108690
Directory /workspace/24.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/24.sram_ctrl_partial_access.2606619739
Short name T854
Test name
Test status
Simulation time 427436606 ps
CPU time 5.91 seconds
Started Jul 12 06:01:55 PM PDT 24
Finished Jul 12 06:02:02 PM PDT 24
Peak memory 212708 kb
Host smart-27cb6774-52c7-4537-8af3-6d986456d77c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606619739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.2606619739
Directory /workspace/24.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1965359183
Short name T786
Test name
Test status
Simulation time 42312314687 ps
CPU time 243.39 seconds
Started Jul 12 06:01:54 PM PDT 24
Finished Jul 12 06:05:58 PM PDT 24
Peak memory 202792 kb
Host smart-390149d7-7f63-4757-a618-63e578ad1868
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965359183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.1965359183
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.1833966685
Short name T542
Test name
Test status
Simulation time 963492072 ps
CPU time 3.44 seconds
Started Jul 12 06:01:54 PM PDT 24
Finished Jul 12 06:01:58 PM PDT 24
Peak memory 202768 kb
Host smart-b4773d34-4244-4bf9-98d1-09eb8f866a83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833966685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1833966685
Directory /workspace/24.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/24.sram_ctrl_regwen.1288587024
Short name T330
Test name
Test status
Simulation time 12511906018 ps
CPU time 647.58 seconds
Started Jul 12 06:01:58 PM PDT 24
Finished Jul 12 06:12:47 PM PDT 24
Peak memory 377640 kb
Host smart-aa5a3aa7-cfef-4c9b-972e-27c0c669f258
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288587024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1288587024
Directory /workspace/24.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/24.sram_ctrl_smoke.1064759234
Short name T876
Test name
Test status
Simulation time 4706956761 ps
CPU time 14.29 seconds
Started Jul 12 06:01:56 PM PDT 24
Finished Jul 12 06:02:12 PM PDT 24
Peak memory 234560 kb
Host smart-07e5e1aa-e945-4777-bc3d-8f261a05094b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064759234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1064759234
Directory /workspace/24.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/24.sram_ctrl_stress_all.2141928457
Short name T211
Test name
Test status
Simulation time 791024124590 ps
CPU time 7960.96 seconds
Started Jul 12 06:01:59 PM PDT 24
Finished Jul 12 08:14:42 PM PDT 24
Peak memory 382792 kb
Host smart-c4dba185-97a6-4548-9096-a5b079c85a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141928457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.2141928457
Directory /workspace/24.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1452552800
Short name T744
Test name
Test status
Simulation time 891247480 ps
CPU time 32.35 seconds
Started Jul 12 06:01:56 PM PDT 24
Finished Jul 12 06:02:29 PM PDT 24
Peak memory 211020 kb
Host smart-d3f5114c-7f7d-49cb-85e1-cdee6b840da9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1452552800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.1452552800
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.826277376
Short name T908
Test name
Test status
Simulation time 7894840320 ps
CPU time 259.03 seconds
Started Jul 12 06:01:56 PM PDT 24
Finished Jul 12 06:06:16 PM PDT 24
Peak memory 202820 kb
Host smart-cada6611-a72d-4e49-b980-1322f752edbf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826277376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_stress_pipeline.826277376
Directory /workspace/24.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1859148058
Short name T357
Test name
Test status
Simulation time 2238191096 ps
CPU time 41.4 seconds
Started Jul 12 06:01:57 PM PDT 24
Finished Jul 12 06:02:39 PM PDT 24
Peak memory 300856 kb
Host smart-16d769b0-0d7a-4622-9ae7-b81619ca218e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859148058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1859148058
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.824465035
Short name T680
Test name
Test status
Simulation time 42491764106 ps
CPU time 817.15 seconds
Started Jul 12 06:02:02 PM PDT 24
Finished Jul 12 06:15:39 PM PDT 24
Peak memory 378652 kb
Host smart-02fe9c57-d943-4e0a-b801-6bbe21f5ae1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824465035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.sram_ctrl_access_during_key_req.824465035
Directory /workspace/25.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/25.sram_ctrl_alert_test.1607838891
Short name T508
Test name
Test status
Simulation time 26151255 ps
CPU time 0.64 seconds
Started Jul 12 06:02:10 PM PDT 24
Finished Jul 12 06:02:11 PM PDT 24
Peak memory 202236 kb
Host smart-4a72442b-bad5-4142-ad3a-7a2d645ee00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607838891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.1607838891
Directory /workspace/25.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/25.sram_ctrl_bijection.2143875312
Short name T173
Test name
Test status
Simulation time 289881492949 ps
CPU time 2540.14 seconds
Started Jul 12 06:02:01 PM PDT 24
Finished Jul 12 06:44:22 PM PDT 24
Peak memory 203384 kb
Host smart-281ea472-5b27-408a-8002-7c809b9dfe6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143875312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.2143875312
Directory /workspace/25.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/25.sram_ctrl_executable.2551320238
Short name T281
Test name
Test status
Simulation time 35447995903 ps
CPU time 1146.81 seconds
Started Jul 12 06:02:01 PM PDT 24
Finished Jul 12 06:21:08 PM PDT 24
Peak memory 369540 kb
Host smart-01f4dbe2-78f5-4452-8cb6-b6dc0b4f4908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551320238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.2551320238
Directory /workspace/25.sram_ctrl_executable/latest


Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.3722583294
Short name T932
Test name
Test status
Simulation time 7755818231 ps
CPU time 44.45 seconds
Started Jul 12 06:02:03 PM PDT 24
Finished Jul 12 06:02:48 PM PDT 24
Peak memory 202824 kb
Host smart-3a5a8194-e355-4ea8-9534-03b712c45d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722583294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.3722583294
Directory /workspace/25.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.1510692760
Short name T566
Test name
Test status
Simulation time 699385542 ps
CPU time 5.8 seconds
Started Jul 12 06:02:00 PM PDT 24
Finished Jul 12 06:02:07 PM PDT 24
Peak memory 202596 kb
Host smart-a4af8b17-557c-49b8-836c-e5aefe36b95d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510692760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.1510692760
Directory /workspace/25.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3526375938
Short name T884
Test name
Test status
Simulation time 5822518736 ps
CPU time 183.59 seconds
Started Jul 12 06:02:10 PM PDT 24
Finished Jul 12 06:05:14 PM PDT 24
Peak memory 219120 kb
Host smart-382c10c2-95b9-44d1-8bec-49228b1bf660
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526375938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.3526375938
Directory /workspace/25.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.4152148443
Short name T942
Test name
Test status
Simulation time 4070091995 ps
CPU time 265.09 seconds
Started Jul 12 06:02:00 PM PDT 24
Finished Jul 12 06:06:25 PM PDT 24
Peak memory 210928 kb
Host smart-3dd62eff-24a9-4c6f-8b3e-a2c14694bedd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152148443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.4152148443
Directory /workspace/25.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.3937574243
Short name T716
Test name
Test status
Simulation time 35880537052 ps
CPU time 2544.01 seconds
Started Jul 12 06:02:04 PM PDT 24
Finished Jul 12 06:44:29 PM PDT 24
Peak memory 380688 kb
Host smart-7d64f289-72d4-42c2-9404-549fa069df3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937574243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.3937574243
Directory /workspace/25.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/25.sram_ctrl_partial_access.2309817083
Short name T647
Test name
Test status
Simulation time 1512152364 ps
CPU time 6.72 seconds
Started Jul 12 06:02:09 PM PDT 24
Finished Jul 12 06:02:16 PM PDT 24
Peak memory 216960 kb
Host smart-799e3ccb-d4a5-4f7c-911b-f74fbba0cd67
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309817083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.2309817083
Directory /workspace/25.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2789273938
Short name T317
Test name
Test status
Simulation time 39198395629 ps
CPU time 481.96 seconds
Started Jul 12 06:02:07 PM PDT 24
Finished Jul 12 06:10:10 PM PDT 24
Peak memory 202812 kb
Host smart-cd70d672-5ca6-46ab-ad94-bdc8127109da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789273938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.2789273938
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.652577059
Short name T351
Test name
Test status
Simulation time 1404442606 ps
CPU time 3.57 seconds
Started Jul 12 06:02:01 PM PDT 24
Finished Jul 12 06:02:05 PM PDT 24
Peak memory 202792 kb
Host smart-dd7a8dc4-649c-443d-acae-91aa4b1de3d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652577059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.652577059
Directory /workspace/25.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/25.sram_ctrl_regwen.807068672
Short name T474
Test name
Test status
Simulation time 17926219351 ps
CPU time 338.61 seconds
Started Jul 12 06:02:01 PM PDT 24
Finished Jul 12 06:07:40 PM PDT 24
Peak memory 376548 kb
Host smart-4c3d541b-60ae-46b3-b4d6-45521b126810
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807068672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.807068672
Directory /workspace/25.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/25.sram_ctrl_smoke.2036742376
Short name T193
Test name
Test status
Simulation time 776806564 ps
CPU time 54.66 seconds
Started Jul 12 06:02:00 PM PDT 24
Finished Jul 12 06:02:55 PM PDT 24
Peak memory 317168 kb
Host smart-6aac150b-1577-4408-bc0c-f8ce4920b797
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036742376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2036742376
Directory /workspace/25.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/25.sram_ctrl_stress_all.3311696561
Short name T221
Test name
Test status
Simulation time 214991963111 ps
CPU time 4959.94 seconds
Started Jul 12 06:02:10 PM PDT 24
Finished Jul 12 07:24:51 PM PDT 24
Peak memory 379740 kb
Host smart-950db82a-9100-4050-8d51-53ff137d2d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311696561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.sram_ctrl_stress_all.3311696561
Directory /workspace/25.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1961675938
Short name T66
Test name
Test status
Simulation time 624434459 ps
CPU time 25.4 seconds
Started Jul 12 06:02:09 PM PDT 24
Finished Jul 12 06:02:35 PM PDT 24
Peak memory 211044 kb
Host smart-99da5b69-5111-431f-a14b-fe57caada815
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1961675938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.1961675938
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.836988454
Short name T110
Test name
Test status
Simulation time 50291872863 ps
CPU time 392.67 seconds
Started Jul 12 06:02:02 PM PDT 24
Finished Jul 12 06:08:36 PM PDT 24
Peak memory 202932 kb
Host smart-8f121d97-c287-4d0c-97b1-5a66361a7097
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836988454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.sram_ctrl_stress_pipeline.836988454
Directory /workspace/25.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1261751070
Short name T540
Test name
Test status
Simulation time 1379327115 ps
CPU time 11.04 seconds
Started Jul 12 06:02:02 PM PDT 24
Finished Jul 12 06:02:14 PM PDT 24
Peak memory 235572 kb
Host smart-6b595f54-6723-40b4-a71f-52da14420e2a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261751070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1261751070
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2794050196
Short name T421
Test name
Test status
Simulation time 70980566948 ps
CPU time 1672.22 seconds
Started Jul 12 06:02:08 PM PDT 24
Finished Jul 12 06:30:01 PM PDT 24
Peak memory 378076 kb
Host smart-9e9d0b2a-2e64-4c40-aca1-1d2ca3fd00d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794050196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.2794050196
Directory /workspace/26.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/26.sram_ctrl_alert_test.829702669
Short name T9
Test name
Test status
Simulation time 15319218 ps
CPU time 0.69 seconds
Started Jul 12 06:02:11 PM PDT 24
Finished Jul 12 06:02:13 PM PDT 24
Peak memory 202532 kb
Host smart-2be8710c-daeb-42ce-9fcb-976f31d3f934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829702669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.829702669
Directory /workspace/26.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/26.sram_ctrl_bijection.1896017940
Short name T163
Test name
Test status
Simulation time 89306050558 ps
CPU time 2087.61 seconds
Started Jul 12 06:02:12 PM PDT 24
Finished Jul 12 06:37:01 PM PDT 24
Peak memory 203320 kb
Host smart-a5218bfa-afa8-4be4-a808-06db59dca93c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896017940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.1896017940
Directory /workspace/26.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/26.sram_ctrl_executable.1530929452
Short name T625
Test name
Test status
Simulation time 27434566067 ps
CPU time 429.62 seconds
Started Jul 12 06:02:10 PM PDT 24
Finished Jul 12 06:09:21 PM PDT 24
Peak memory 326108 kb
Host smart-edaf67bf-36d6-4c26-acd8-f1eff3eef91c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530929452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.1530929452
Directory /workspace/26.sram_ctrl_executable/latest


Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.1986357894
Short name T242
Test name
Test status
Simulation time 2243231457 ps
CPU time 14.34 seconds
Started Jul 12 06:02:11 PM PDT 24
Finished Jul 12 06:02:26 PM PDT 24
Peak memory 202680 kb
Host smart-e9d04008-9e9b-41ac-8a1c-e0a54507532f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986357894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.1986357894
Directory /workspace/26.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.3650413265
Short name T337
Test name
Test status
Simulation time 710120094 ps
CPU time 5.92 seconds
Started Jul 12 06:02:12 PM PDT 24
Finished Jul 12 06:02:19 PM PDT 24
Peak memory 210748 kb
Host smart-f8eca5fe-7b8a-475e-9e25-5dd637591beb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650413265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.3650413265
Directory /workspace/26.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1224577018
Short name T53
Test name
Test status
Simulation time 1403071665 ps
CPU time 79.05 seconds
Started Jul 12 06:02:11 PM PDT 24
Finished Jul 12 06:03:32 PM PDT 24
Peak memory 219056 kb
Host smart-ca0f99ff-12fc-4a46-9482-021164dfef17
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224577018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.1224577018
Directory /workspace/26.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.2555924014
Short name T618
Test name
Test status
Simulation time 98790940249 ps
CPU time 186.86 seconds
Started Jul 12 06:02:12 PM PDT 24
Finished Jul 12 06:05:20 PM PDT 24
Peak memory 202848 kb
Host smart-82d3acd3-5354-4167-a090-5912ebc00dff
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555924014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.2555924014
Directory /workspace/26.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.60045539
Short name T394
Test name
Test status
Simulation time 3780992269 ps
CPU time 169.33 seconds
Started Jul 12 06:02:08 PM PDT 24
Finished Jul 12 06:04:58 PM PDT 24
Peak memory 348776 kb
Host smart-a1d6319c-9887-4131-a1b1-0cf41090c3a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60045539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multipl
e_keys.60045539
Directory /workspace/26.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/26.sram_ctrl_partial_access.630670801
Short name T615
Test name
Test status
Simulation time 826459056 ps
CPU time 69.38 seconds
Started Jul 12 06:02:09 PM PDT 24
Finished Jul 12 06:03:19 PM PDT 24
Peak memory 313184 kb
Host smart-8a7d3a35-e001-45e5-9080-4042d63a0958
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630670801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s
ram_ctrl_partial_access.630670801
Directory /workspace/26.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2489438818
Short name T488
Test name
Test status
Simulation time 42559229425 ps
CPU time 583.11 seconds
Started Jul 12 06:02:09 PM PDT 24
Finished Jul 12 06:11:53 PM PDT 24
Peak memory 202800 kb
Host smart-0bde74a7-7e65-44de-a711-e546cde1beec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489438818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.2489438818
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.2698626419
Short name T835
Test name
Test status
Simulation time 693100122 ps
CPU time 3.65 seconds
Started Jul 12 06:02:12 PM PDT 24
Finished Jul 12 06:02:17 PM PDT 24
Peak memory 202580 kb
Host smart-4321fbc7-bfdc-4425-bff2-91b4a52adcb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698626419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2698626419
Directory /workspace/26.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/26.sram_ctrl_regwen.2518680665
Short name T611
Test name
Test status
Simulation time 5346993120 ps
CPU time 354.49 seconds
Started Jul 12 06:02:10 PM PDT 24
Finished Jul 12 06:08:06 PM PDT 24
Peak memory 365376 kb
Host smart-5944deb1-d26b-4608-8d43-b0c881bb7855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518680665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2518680665
Directory /workspace/26.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/26.sram_ctrl_smoke.2084076764
Short name T638
Test name
Test status
Simulation time 2549684591 ps
CPU time 70.73 seconds
Started Jul 12 06:02:09 PM PDT 24
Finished Jul 12 06:03:20 PM PDT 24
Peak memory 343792 kb
Host smart-0ed2f5e6-7973-46d7-a563-a871703cef7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084076764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2084076764
Directory /workspace/26.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/26.sram_ctrl_stress_all.2448876805
Short name T245
Test name
Test status
Simulation time 479363605398 ps
CPU time 5330.21 seconds
Started Jul 12 06:02:10 PM PDT 24
Finished Jul 12 07:31:02 PM PDT 24
Peak memory 382756 kb
Host smart-79642890-ac9f-4bac-a34c-e616852bc8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448876805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.2448876805
Directory /workspace/26.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4291631020
Short name T45
Test name
Test status
Simulation time 7703035213 ps
CPU time 49.28 seconds
Started Jul 12 06:02:10 PM PDT 24
Finished Jul 12 06:03:00 PM PDT 24
Peak memory 219244 kb
Host smart-cf0019a2-d24d-45a1-b829-3edced7a26ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4291631020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.4291631020
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1676376664
Short name T111
Test name
Test status
Simulation time 17811058370 ps
CPU time 247.46 seconds
Started Jul 12 06:02:12 PM PDT 24
Finished Jul 12 06:06:21 PM PDT 24
Peak memory 202460 kb
Host smart-c08220cd-613a-44de-8362-0b038893844e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676376664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.1676376664
Directory /workspace/26.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2754236812
Short name T928
Test name
Test status
Simulation time 1639605742 ps
CPU time 117.18 seconds
Started Jul 12 06:02:09 PM PDT 24
Finished Jul 12 06:04:07 PM PDT 24
Peak memory 350512 kb
Host smart-2b275fe3-e80a-49b2-ac98-268fa0173802
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754236812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2754236812
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2939766738
Short name T519
Test name
Test status
Simulation time 10709567615 ps
CPU time 1163.23 seconds
Started Jul 12 06:02:15 PM PDT 24
Finished Jul 12 06:21:40 PM PDT 24
Peak memory 378668 kb
Host smart-256512bb-bb9f-4f70-a19d-49be89f9ff21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939766738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.2939766738
Directory /workspace/27.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/27.sram_ctrl_alert_test.841157454
Short name T347
Test name
Test status
Simulation time 17034931 ps
CPU time 0.69 seconds
Started Jul 12 06:02:23 PM PDT 24
Finished Jul 12 06:02:25 PM PDT 24
Peak memory 202348 kb
Host smart-b41c7d6a-3f0c-4d07-ac39-629a84cce3d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841157454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.841157454
Directory /workspace/27.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/27.sram_ctrl_bijection.2596498547
Short name T923
Test name
Test status
Simulation time 70929737289 ps
CPU time 604.66 seconds
Started Jul 12 06:02:16 PM PDT 24
Finished Jul 12 06:12:22 PM PDT 24
Peak memory 203528 kb
Host smart-7517b7fd-22ae-45b6-a35d-2a7d5287a1da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596498547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.2596498547
Directory /workspace/27.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/27.sram_ctrl_executable.280350539
Short name T191
Test name
Test status
Simulation time 40503447740 ps
CPU time 539.52 seconds
Started Jul 12 06:02:16 PM PDT 24
Finished Jul 12 06:11:16 PM PDT 24
Peak memory 348392 kb
Host smart-20dee9e7-9dfd-4169-8f23-5a998deac82d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280350539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executabl
e.280350539
Directory /workspace/27.sram_ctrl_executable/latest


Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.2866660496
Short name T284
Test name
Test status
Simulation time 14116792133 ps
CPU time 50.47 seconds
Started Jul 12 06:02:19 PM PDT 24
Finished Jul 12 06:03:10 PM PDT 24
Peak memory 215332 kb
Host smart-099f5029-3eeb-4101-bfcd-8b6e2d2065b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866660496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.2866660496
Directory /workspace/27.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.3764313942
Short name T341
Test name
Test status
Simulation time 3306322400 ps
CPU time 19.33 seconds
Started Jul 12 06:02:16 PM PDT 24
Finished Jul 12 06:02:37 PM PDT 24
Peak memory 251864 kb
Host smart-d686e7ef-804e-4a9f-a12a-17614062ba5e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764313942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.3764313942
Directory /workspace/27.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1264584251
Short name T654
Test name
Test status
Simulation time 9702554750 ps
CPU time 146.81 seconds
Started Jul 12 06:02:14 PM PDT 24
Finished Jul 12 06:04:42 PM PDT 24
Peak memory 211012 kb
Host smart-578bb61e-bdcd-4fdc-91cb-aabd95330c88
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264584251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.1264584251
Directory /workspace/27.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.3420977708
Short name T581
Test name
Test status
Simulation time 57663379080 ps
CPU time 343.33 seconds
Started Jul 12 06:02:15 PM PDT 24
Finished Jul 12 06:08:00 PM PDT 24
Peak memory 210940 kb
Host smart-dd7185c4-18d6-4dfe-a432-108a74b552ed
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420977708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.3420977708
Directory /workspace/27.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.2631726092
Short name T644
Test name
Test status
Simulation time 10280942871 ps
CPU time 962.6 seconds
Started Jul 12 06:02:17 PM PDT 24
Finished Jul 12 06:18:20 PM PDT 24
Peak memory 379732 kb
Host smart-8db9be10-d11e-4e85-a21d-31757df85754
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631726092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.2631726092
Directory /workspace/27.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/27.sram_ctrl_partial_access.4284172769
Short name T157
Test name
Test status
Simulation time 3231002837 ps
CPU time 66.37 seconds
Started Jul 12 06:02:16 PM PDT 24
Finished Jul 12 06:03:24 PM PDT 24
Peak memory 306544 kb
Host smart-b61faf02-a9fd-4913-9a9a-1055c9cb268d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284172769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.4284172769
Directory /workspace/27.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2839311
Short name T893
Test name
Test status
Simulation time 23299792127 ps
CPU time 298.73 seconds
Started Jul 12 06:02:16 PM PDT 24
Finished Jul 12 06:07:16 PM PDT 24
Peak memory 202800 kb
Host smart-624cd381-4f70-4b72-b523-0a9e47e8b149
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.sram_ctrl_partial_access_b2b.2839311
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.171367714
Short name T635
Test name
Test status
Simulation time 3726310428 ps
CPU time 3.45 seconds
Started Jul 12 06:02:18 PM PDT 24
Finished Jul 12 06:02:23 PM PDT 24
Peak memory 202900 kb
Host smart-c1083b1f-75b6-4d4e-8950-b83f2feee9da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171367714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.171367714
Directory /workspace/27.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/27.sram_ctrl_regwen.4214742555
Short name T20
Test name
Test status
Simulation time 71457398706 ps
CPU time 1522.04 seconds
Started Jul 12 06:02:16 PM PDT 24
Finished Jul 12 06:27:39 PM PDT 24
Peak memory 380736 kb
Host smart-8ddf3704-185a-4928-8198-535a8a1868ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214742555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.4214742555
Directory /workspace/27.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/27.sram_ctrl_smoke.1502204330
Short name T606
Test name
Test status
Simulation time 1078071127 ps
CPU time 54.95 seconds
Started Jul 12 06:02:16 PM PDT 24
Finished Jul 12 06:03:12 PM PDT 24
Peak memory 312752 kb
Host smart-700c31b5-dd53-48ad-9717-38d75b949c63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502204330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1502204330
Directory /workspace/27.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/27.sram_ctrl_stress_all.1924148342
Short name T301
Test name
Test status
Simulation time 93936396570 ps
CPU time 1435.87 seconds
Started Jul 12 06:02:22 PM PDT 24
Finished Jul 12 06:26:19 PM PDT 24
Peak memory 386900 kb
Host smart-63d2316e-44d1-47a5-92fe-400b693b9e02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924148342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.1924148342
Directory /workspace/27.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.113672368
Short name T564
Test name
Test status
Simulation time 1160289832 ps
CPU time 39.28 seconds
Started Jul 12 06:02:22 PM PDT 24
Finished Jul 12 06:03:02 PM PDT 24
Peak memory 214076 kb
Host smart-1893544e-e741-4d16-abbe-5262b4ba8277
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=113672368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.113672368
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.23341426
Short name T860
Test name
Test status
Simulation time 14459576428 ps
CPU time 237.88 seconds
Started Jul 12 06:02:14 PM PDT 24
Finished Jul 12 06:06:13 PM PDT 24
Peak memory 202788 kb
Host smart-595cfab1-8df9-40a2-b3ec-4cadf6b0cea0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23341426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_stress_pipeline.23341426
Directory /workspace/27.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2432097514
Short name T734
Test name
Test status
Simulation time 1427712295 ps
CPU time 23.97 seconds
Started Jul 12 06:02:19 PM PDT 24
Finished Jul 12 06:02:43 PM PDT 24
Peak memory 268136 kb
Host smart-d80e10dc-911c-4aea-b520-e4ebf36c3c29
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432097514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2432097514
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1618590193
Short name T370
Test name
Test status
Simulation time 31902753022 ps
CPU time 1838.3 seconds
Started Jul 12 06:02:24 PM PDT 24
Finished Jul 12 06:33:03 PM PDT 24
Peak memory 380068 kb
Host smart-e3e425db-939b-42e7-8c9b-a009e2f86ee0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618590193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.1618590193
Directory /workspace/28.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/28.sram_ctrl_alert_test.1464020697
Short name T685
Test name
Test status
Simulation time 16541815 ps
CPU time 0.68 seconds
Started Jul 12 06:02:29 PM PDT 24
Finished Jul 12 06:02:30 PM PDT 24
Peak memory 202524 kb
Host smart-4ca26e3d-e2cc-4a67-adc8-b302b68097e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464020697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.1464020697
Directory /workspace/28.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/28.sram_ctrl_bijection.734488453
Short name T882
Test name
Test status
Simulation time 320172489703 ps
CPU time 1006.49 seconds
Started Jul 12 06:02:24 PM PDT 24
Finished Jul 12 06:19:12 PM PDT 24
Peak memory 203264 kb
Host smart-757acf1b-7498-4273-b082-7f8b884a9d14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734488453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.
734488453
Directory /workspace/28.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/28.sram_ctrl_executable.2996797380
Short name T560
Test name
Test status
Simulation time 32466351196 ps
CPU time 822.46 seconds
Started Jul 12 06:02:23 PM PDT 24
Finished Jul 12 06:16:06 PM PDT 24
Peak memory 373544 kb
Host smart-8d30a347-35cb-4928-9b26-27d411514fd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996797380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.2996797380
Directory /workspace/28.sram_ctrl_executable/latest


Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.716316787
Short name T899
Test name
Test status
Simulation time 57481584866 ps
CPU time 85.39 seconds
Started Jul 12 06:02:25 PM PDT 24
Finished Jul 12 06:03:51 PM PDT 24
Peak memory 202860 kb
Host smart-cdc8a30c-c1c2-4563-86f0-faa3fb956f3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716316787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc
alation.716316787
Directory /workspace/28.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.1718197951
Short name T161
Test name
Test status
Simulation time 10874389000 ps
CPU time 160.07 seconds
Started Jul 12 06:02:24 PM PDT 24
Finished Jul 12 06:05:05 PM PDT 24
Peak memory 369304 kb
Host smart-2a86d858-e21c-42db-8fff-c5a510936d8d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718197951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.1718197951
Directory /workspace/28.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1328454613
Short name T171
Test name
Test status
Simulation time 16926864645 ps
CPU time 158.41 seconds
Started Jul 12 06:02:30 PM PDT 24
Finished Jul 12 06:05:09 PM PDT 24
Peak memory 210988 kb
Host smart-69af1c1e-01d5-4b7e-a369-40282990fe03
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328454613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.1328454613
Directory /workspace/28.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.1038853217
Short name T944
Test name
Test status
Simulation time 9152795702 ps
CPU time 165.66 seconds
Started Jul 12 06:02:31 PM PDT 24
Finished Jul 12 06:05:17 PM PDT 24
Peak memory 210896 kb
Host smart-26d9385a-0efa-4246-84b9-9b619e881f74
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038853217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.1038853217
Directory /workspace/28.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.1273365559
Short name T510
Test name
Test status
Simulation time 8892166855 ps
CPU time 151.21 seconds
Started Jul 12 06:02:24 PM PDT 24
Finished Jul 12 06:04:56 PM PDT 24
Peak memory 358140 kb
Host smart-5bc2bbff-a574-472f-8db3-6fb3b80d4685
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273365559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.1273365559
Directory /workspace/28.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/28.sram_ctrl_partial_access.2359713400
Short name T613
Test name
Test status
Simulation time 1019423949 ps
CPU time 171.53 seconds
Started Jul 12 06:02:25 PM PDT 24
Finished Jul 12 06:05:18 PM PDT 24
Peak memory 368188 kb
Host smart-6885e565-eb40-420f-9a01-30852e10b760
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359713400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.2359713400
Directory /workspace/28.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1668836113
Short name T664
Test name
Test status
Simulation time 20101901745 ps
CPU time 443.85 seconds
Started Jul 12 06:02:26 PM PDT 24
Finished Jul 12 06:09:50 PM PDT 24
Peak memory 202792 kb
Host smart-6f5bf970-c42d-4a5f-9758-d16ccff101f3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668836113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.1668836113
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.1469578337
Short name T739
Test name
Test status
Simulation time 680928493 ps
CPU time 3.2 seconds
Started Jul 12 06:02:23 PM PDT 24
Finished Jul 12 06:02:27 PM PDT 24
Peak memory 202780 kb
Host smart-ab602d38-315b-479e-94f2-5980204dc442
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469578337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1469578337
Directory /workspace/28.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/28.sram_ctrl_regwen.863445854
Short name T123
Test name
Test status
Simulation time 30484126078 ps
CPU time 1138.67 seconds
Started Jul 12 06:02:24 PM PDT 24
Finished Jul 12 06:21:24 PM PDT 24
Peak memory 372552 kb
Host smart-3eb47e4e-487e-4912-b6ba-43f3531e5a80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863445854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.863445854
Directory /workspace/28.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/28.sram_ctrl_smoke.2542917899
Short name T340
Test name
Test status
Simulation time 1744297699 ps
CPU time 16.54 seconds
Started Jul 12 06:02:23 PM PDT 24
Finished Jul 12 06:02:40 PM PDT 24
Peak memory 202692 kb
Host smart-6364f2f4-1e8b-4d64-86e6-92122fee1550
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542917899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2542917899
Directory /workspace/28.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/28.sram_ctrl_stress_all.2097637600
Short name T791
Test name
Test status
Simulation time 1566924192237 ps
CPU time 9179.03 seconds
Started Jul 12 06:02:29 PM PDT 24
Finished Jul 12 08:35:30 PM PDT 24
Peak memory 381776 kb
Host smart-3556e3c6-6168-4262-a485-a9829992a1c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097637600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.2097637600
Directory /workspace/28.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1439810522
Short name T67
Test name
Test status
Simulation time 1105477973 ps
CPU time 16.64 seconds
Started Jul 12 06:02:35 PM PDT 24
Finished Jul 12 06:02:52 PM PDT 24
Peak memory 211028 kb
Host smart-dfa76c90-c6b0-4760-ac36-c92450a23b85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1439810522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1439810522
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1541054115
Short name T37
Test name
Test status
Simulation time 6586723128 ps
CPU time 332.81 seconds
Started Jul 12 06:02:25 PM PDT 24
Finished Jul 12 06:07:59 PM PDT 24
Peak memory 202768 kb
Host smart-7d291c40-da1f-48ce-922a-5bcdb6fb3f9d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541054115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.1541054115
Directory /workspace/28.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4102525681
Short name T556
Test name
Test status
Simulation time 4052603428 ps
CPU time 11.28 seconds
Started Jul 12 06:02:23 PM PDT 24
Finished Jul 12 06:02:35 PM PDT 24
Peak memory 235408 kb
Host smart-fb924379-ce1e-4ac9-81f9-bb66714dd358
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102525681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.4102525681
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1004787237
Short name T583
Test name
Test status
Simulation time 47703042039 ps
CPU time 866.96 seconds
Started Jul 12 06:02:37 PM PDT 24
Finished Jul 12 06:17:05 PM PDT 24
Peak memory 376368 kb
Host smart-0115c84d-8eb7-4dab-8c4c-496e43c300cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004787237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.1004787237
Directory /workspace/29.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/29.sram_ctrl_alert_test.942557424
Short name T164
Test name
Test status
Simulation time 15902859 ps
CPU time 0.69 seconds
Started Jul 12 06:02:36 PM PDT 24
Finished Jul 12 06:02:38 PM PDT 24
Peak memory 202300 kb
Host smart-826c1d48-d07f-46af-99c0-452a0edc8990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942557424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.942557424
Directory /workspace/29.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/29.sram_ctrl_bijection.2431871923
Short name T216
Test name
Test status
Simulation time 524597615213 ps
CPU time 2289.12 seconds
Started Jul 12 06:02:35 PM PDT 24
Finished Jul 12 06:40:45 PM PDT 24
Peak memory 203372 kb
Host smart-d43b380e-200e-4525-ab13-b5f1f2bf4474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431871923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.2431871923
Directory /workspace/29.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/29.sram_ctrl_executable.1598887054
Short name T526
Test name
Test status
Simulation time 155227900890 ps
CPU time 973.65 seconds
Started Jul 12 06:02:36 PM PDT 24
Finished Jul 12 06:18:50 PM PDT 24
Peak memory 352112 kb
Host smart-974c6301-4ccb-475d-9663-6f6ff4fedf20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598887054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.1598887054
Directory /workspace/29.sram_ctrl_executable/latest


Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.591434242
Short name T332
Test name
Test status
Simulation time 10531146778 ps
CPU time 60.2 seconds
Started Jul 12 06:02:37 PM PDT 24
Finished Jul 12 06:03:38 PM PDT 24
Peak memory 202844 kb
Host smart-ef43ffad-b0df-4338-90a1-21917406be72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591434242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esc
alation.591434242
Directory /workspace/29.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.1401730265
Short name T293
Test name
Test status
Simulation time 746452642 ps
CPU time 71.52 seconds
Started Jul 12 06:02:37 PM PDT 24
Finished Jul 12 06:03:49 PM PDT 24
Peak memory 326504 kb
Host smart-1cb93227-0bc0-4a03-b65a-8fd64676c103
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401730265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.1401730265
Directory /workspace/29.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2747367386
Short name T396
Test name
Test status
Simulation time 4936621090 ps
CPU time 155.44 seconds
Started Jul 12 06:02:43 PM PDT 24
Finished Jul 12 06:05:19 PM PDT 24
Peak memory 211024 kb
Host smart-4411aae4-c794-4b34-a53e-36d4c9ffde3a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747367386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.2747367386
Directory /workspace/29.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.2039863273
Short name T905
Test name
Test status
Simulation time 10954207972 ps
CPU time 158.64 seconds
Started Jul 12 06:02:37 PM PDT 24
Finished Jul 12 06:05:16 PM PDT 24
Peak memory 210948 kb
Host smart-072c5c21-e316-416d-b573-7d7a756cf6c0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039863273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.2039863273
Directory /workspace/29.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.2918136906
Short name T708
Test name
Test status
Simulation time 73222814252 ps
CPU time 1730.38 seconds
Started Jul 12 06:02:29 PM PDT 24
Finished Jul 12 06:31:20 PM PDT 24
Peak memory 380712 kb
Host smart-ac042d96-87d4-4f29-a17f-0e0ab37f0113
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918136906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.2918136906
Directory /workspace/29.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/29.sram_ctrl_partial_access.3625944768
Short name T298
Test name
Test status
Simulation time 741767498 ps
CPU time 12.75 seconds
Started Jul 12 06:02:36 PM PDT 24
Finished Jul 12 06:02:49 PM PDT 24
Peak memory 242276 kb
Host smart-55fcb52e-fb83-4fdd-b8d3-c3a624729e25
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625944768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.3625944768
Directory /workspace/29.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3313923404
Short name T141
Test name
Test status
Simulation time 22316191650 ps
CPU time 483.91 seconds
Started Jul 12 06:02:43 PM PDT 24
Finished Jul 12 06:10:48 PM PDT 24
Peak memory 202812 kb
Host smart-855bf434-f94e-4197-98e1-c54b124bccb6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313923404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.3313923404
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.2810276217
Short name T243
Test name
Test status
Simulation time 344038302 ps
CPU time 3.24 seconds
Started Jul 12 06:02:37 PM PDT 24
Finished Jul 12 06:02:41 PM PDT 24
Peak memory 202776 kb
Host smart-44165b77-eea2-4826-9da3-a8430d780407
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810276217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2810276217
Directory /workspace/29.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/29.sram_ctrl_regwen.3085615127
Short name T824
Test name
Test status
Simulation time 6767051413 ps
CPU time 693.65 seconds
Started Jul 12 06:02:37 PM PDT 24
Finished Jul 12 06:14:12 PM PDT 24
Peak memory 375592 kb
Host smart-871d130d-186c-4875-81db-d6ab96666250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085615127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3085615127
Directory /workspace/29.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/29.sram_ctrl_smoke.3989788924
Short name T195
Test name
Test status
Simulation time 4577157788 ps
CPU time 73.12 seconds
Started Jul 12 06:02:29 PM PDT 24
Finished Jul 12 06:03:43 PM PDT 24
Peak memory 333572 kb
Host smart-80be6994-32ab-4ff9-9eb3-2c705da34e94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989788924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3989788924
Directory /workspace/29.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/29.sram_ctrl_stress_all.4187454938
Short name T502
Test name
Test status
Simulation time 602112123322 ps
CPU time 1507.64 seconds
Started Jul 12 06:02:43 PM PDT 24
Finished Jul 12 06:27:51 PM PDT 24
Peak memory 371744 kb
Host smart-89aa8eb3-9eb6-4301-b068-c026e6418d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187454938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.4187454938
Directory /workspace/29.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1155388015
Short name T70
Test name
Test status
Simulation time 235478433 ps
CPU time 8.43 seconds
Started Jul 12 06:02:36 PM PDT 24
Finished Jul 12 06:02:45 PM PDT 24
Peak memory 210984 kb
Host smart-197ff5b1-e5a5-488e-8e43-5f8cf8bcf344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1155388015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1155388015
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.494487804
Short name T936
Test name
Test status
Simulation time 4745946899 ps
CPU time 333.38 seconds
Started Jul 12 06:02:37 PM PDT 24
Finished Jul 12 06:08:11 PM PDT 24
Peak memory 202932 kb
Host smart-7153ac2a-295d-4fb0-9a67-547f4073a16a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494487804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_stress_pipeline.494487804
Directory /workspace/29.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3370587127
Short name T705
Test name
Test status
Simulation time 1439437386 ps
CPU time 34.06 seconds
Started Jul 12 06:02:38 PM PDT 24
Finished Jul 12 06:03:13 PM PDT 24
Peak memory 277192 kb
Host smart-15dda159-4ec3-455e-82e3-d9ca3ad89f96
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370587127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3370587127
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.313238360
Short name T598
Test name
Test status
Simulation time 10935386633 ps
CPU time 601.58 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:10:34 PM PDT 24
Peak memory 378412 kb
Host smart-7c6171a5-3d5e-482f-8243-9b2a97120ca8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313238360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_access_during_key_req.313238360
Directory /workspace/3.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/3.sram_ctrl_alert_test.1492926643
Short name T28
Test name
Test status
Simulation time 19933207 ps
CPU time 0.68 seconds
Started Jul 12 06:00:50 PM PDT 24
Finished Jul 12 06:00:52 PM PDT 24
Peak memory 202484 kb
Host smart-e28184f3-e0be-4abb-8715-71a7790888f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492926643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.1492926643
Directory /workspace/3.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/3.sram_ctrl_bijection.2819971702
Short name T666
Test name
Test status
Simulation time 32810817483 ps
CPU time 585.66 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:10:18 PM PDT 24
Peak memory 203372 kb
Host smart-c800f6d9-c960-4b1e-b790-d14e91a11ba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819971702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
2819971702
Directory /workspace/3.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/3.sram_ctrl_executable.178506253
Short name T636
Test name
Test status
Simulation time 6620382394 ps
CPU time 924.44 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:15:58 PM PDT 24
Peak memory 372568 kb
Host smart-e208d326-94ac-4ae4-880c-5c12ee4336d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178506253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable
.178506253
Directory /workspace/3.sram_ctrl_executable/latest


Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.4256109373
Short name T812
Test name
Test status
Simulation time 6788128726 ps
CPU time 38.81 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:01:11 PM PDT 24
Peak memory 211020 kb
Host smart-8cef3c92-4ded-4c30-a270-35c48cc2e714
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256109373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.4256109373
Directory /workspace/3.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.70718230
Short name T750
Test name
Test status
Simulation time 1144833340 ps
CPU time 28.2 seconds
Started Jul 12 06:00:36 PM PDT 24
Finished Jul 12 06:01:06 PM PDT 24
Peak memory 276688 kb
Host smart-6af68d9d-eac8-4a45-9d8c-f941b8139745
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70718230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_max_throughput.70718230
Directory /workspace/3.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1027515707
Short name T861
Test name
Test status
Simulation time 12590760911 ps
CPU time 74.41 seconds
Started Jul 12 06:00:41 PM PDT 24
Finished Jul 12 06:01:57 PM PDT 24
Peak memory 212748 kb
Host smart-4702533a-9f30-4a6a-95eb-2fb5d6714975
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027515707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.1027515707
Directory /workspace/3.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.949195490
Short name T553
Test name
Test status
Simulation time 13817129880 ps
CPU time 322.37 seconds
Started Jul 12 06:00:41 PM PDT 24
Finished Jul 12 06:06:04 PM PDT 24
Peak memory 211360 kb
Host smart-e44f2364-f2de-4964-8d10-fde26df9b3c6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949195490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_
mem_walk.949195490
Directory /workspace/3.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.3460932556
Short name T512
Test name
Test status
Simulation time 6863510004 ps
CPU time 1056.38 seconds
Started Jul 12 06:00:31 PM PDT 24
Finished Jul 12 06:18:09 PM PDT 24
Peak memory 375648 kb
Host smart-fe55fe1f-714e-4f24-8b38-cc619180fdc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460932556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.3460932556
Directory /workspace/3.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/3.sram_ctrl_partial_access.2048348723
Short name T826
Test name
Test status
Simulation time 2817021262 ps
CPU time 5.79 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:00:38 PM PDT 24
Peak memory 209904 kb
Host smart-098e49c3-9aa8-42c2-ba6b-9067a772c3cc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048348723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.2048348723
Directory /workspace/3.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1872388875
Short name T906
Test name
Test status
Simulation time 29736561395 ps
CPU time 370.25 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:06:43 PM PDT 24
Peak memory 202752 kb
Host smart-a3885309-cfdc-456a-94f0-8ee1b313aeb3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872388875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.1872388875
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.3830743048
Short name T511
Test name
Test status
Simulation time 655975483 ps
CPU time 3.36 seconds
Started Jul 12 06:00:38 PM PDT 24
Finished Jul 12 06:00:42 PM PDT 24
Peak memory 202756 kb
Host smart-3ac1067a-c4d9-4dd8-b2fe-c8f1e3e155cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830743048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3830743048
Directory /workspace/3.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/3.sram_ctrl_regwen.4131899805
Short name T885
Test name
Test status
Simulation time 7235643503 ps
CPU time 149.28 seconds
Started Jul 12 06:00:32 PM PDT 24
Finished Jul 12 06:03:03 PM PDT 24
Peak memory 367404 kb
Host smart-f4b8f762-f127-4fec-b6da-678c3233e833
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131899805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.4131899805
Directory /workspace/3.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.579821330
Short name T27
Test name
Test status
Simulation time 439512575 ps
CPU time 1.79 seconds
Started Jul 12 06:00:49 PM PDT 24
Finished Jul 12 06:00:53 PM PDT 24
Peak memory 222228 kb
Host smart-ab3367d0-51d0-4ed7-8453-47d7ffb38932
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579821330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_sec_cm.579821330
Directory /workspace/3.sram_ctrl_sec_cm/latest


Test location /workspace/coverage/default/3.sram_ctrl_smoke.937370881
Short name T215
Test name
Test status
Simulation time 1872052003 ps
CPU time 13.14 seconds
Started Jul 12 06:00:35 PM PDT 24
Finished Jul 12 06:00:49 PM PDT 24
Peak memory 202688 kb
Host smart-8332d46c-b9b2-49f6-8979-ec788468b48c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937370881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.937370881
Directory /workspace/3.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/3.sram_ctrl_stress_all.40614943
Short name T201
Test name
Test status
Simulation time 570486569436 ps
CPU time 6760.29 seconds
Started Jul 12 06:00:29 PM PDT 24
Finished Jul 12 07:53:12 PM PDT 24
Peak memory 303584 kb
Host smart-8cc204d4-8b67-460e-9050-741d6cec2d76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40614943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.sram_ctrl_stress_all.40614943
Directory /workspace/3.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1864456726
Short name T68
Test name
Test status
Simulation time 1970764296 ps
CPU time 19.41 seconds
Started Jul 12 06:00:39 PM PDT 24
Finished Jul 12 06:01:00 PM PDT 24
Peak memory 210940 kb
Host smart-2073cf9a-cdc4-4305-a478-cd58fc3b920b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1864456726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1864456726
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2768845516
Short name T873
Test name
Test status
Simulation time 16403315840 ps
CPU time 283.05 seconds
Started Jul 12 06:00:28 PM PDT 24
Finished Jul 12 06:05:12 PM PDT 24
Peak memory 202744 kb
Host smart-cc2d8f85-009e-405d-adb2-a782e8d62e5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768845516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.2768845516
Directory /workspace/3.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2819662011
Short name T874
Test name
Test status
Simulation time 707711765 ps
CPU time 5.47 seconds
Started Jul 12 06:00:30 PM PDT 24
Finished Jul 12 06:00:38 PM PDT 24
Peak memory 202564 kb
Host smart-c1533237-3163-4f70-acaa-a2a85075c52c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819662011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2819662011
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3428109265
Short name T462
Test name
Test status
Simulation time 50680413955 ps
CPU time 1476.1 seconds
Started Jul 12 06:02:43 PM PDT 24
Finished Jul 12 06:27:20 PM PDT 24
Peak memory 380724 kb
Host smart-f44b016c-6520-4a6a-9967-0edafbf60abb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428109265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.3428109265
Directory /workspace/30.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/30.sram_ctrl_alert_test.2609359956
Short name T367
Test name
Test status
Simulation time 14019804 ps
CPU time 0.67 seconds
Started Jul 12 06:02:45 PM PDT 24
Finished Jul 12 06:02:46 PM PDT 24
Peak memory 202504 kb
Host smart-731aa0d1-a0bf-4e57-9ac6-a4957e55e50a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609359956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.2609359956
Directory /workspace/30.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/30.sram_ctrl_bijection.930460862
Short name T587
Test name
Test status
Simulation time 33992474264 ps
CPU time 1940.94 seconds
Started Jul 12 06:02:51 PM PDT 24
Finished Jul 12 06:35:12 PM PDT 24
Peak memory 203660 kb
Host smart-0da1d6f4-b10f-4b1b-a393-e7f245720fbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930460862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.
930460862
Directory /workspace/30.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/30.sram_ctrl_executable.1535601234
Short name T420
Test name
Test status
Simulation time 70171216565 ps
CPU time 893.56 seconds
Started Jul 12 06:02:46 PM PDT 24
Finished Jul 12 06:17:40 PM PDT 24
Peak memory 379768 kb
Host smart-8ea009be-cbfb-4fe4-bb4f-56e0e9dcb62b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535601234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.1535601234
Directory /workspace/30.sram_ctrl_executable/latest


Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.2763648090
Short name T675
Test name
Test status
Simulation time 3090523770 ps
CPU time 20.6 seconds
Started Jul 12 06:02:51 PM PDT 24
Finished Jul 12 06:03:12 PM PDT 24
Peak memory 202840 kb
Host smart-e6bdcd3d-8ee4-4134-b346-b3b5a5d309a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763648090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.2763648090
Directory /workspace/30.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.2148102335
Short name T254
Test name
Test status
Simulation time 693973411 ps
CPU time 7.56 seconds
Started Jul 12 06:02:46 PM PDT 24
Finished Jul 12 06:02:54 PM PDT 24
Peak memory 218972 kb
Host smart-9634ef6f-342f-44a1-a084-440fe55038a0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148102335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.2148102335
Directory /workspace/30.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.1725455038
Short name T813
Test name
Test status
Simulation time 9286180692 ps
CPU time 153.11 seconds
Started Jul 12 06:02:45 PM PDT 24
Finished Jul 12 06:05:19 PM PDT 24
Peak memory 219176 kb
Host smart-58ea3a8a-45dc-4904-9044-dc0e2d3c156d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725455038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.1725455038
Directory /workspace/30.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.1074056852
Short name T43
Test name
Test status
Simulation time 7218058325 ps
CPU time 165.02 seconds
Started Jul 12 06:02:44 PM PDT 24
Finished Jul 12 06:05:30 PM PDT 24
Peak memory 210992 kb
Host smart-e9643010-4e0d-49a1-995a-5ce873e479b0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074056852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.1074056852
Directory /workspace/30.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.1924033748
Short name T373
Test name
Test status
Simulation time 10827593308 ps
CPU time 511.84 seconds
Started Jul 12 06:02:38 PM PDT 24
Finished Jul 12 06:11:10 PM PDT 24
Peak memory 336680 kb
Host smart-9ecf218f-0130-4b8f-a0e2-1c6ffdb4727f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924033748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.1924033748
Directory /workspace/30.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/30.sram_ctrl_partial_access.2516287741
Short name T816
Test name
Test status
Simulation time 23886357055 ps
CPU time 31.61 seconds
Started Jul 12 06:02:43 PM PDT 24
Finished Jul 12 06:03:16 PM PDT 24
Peak memory 202772 kb
Host smart-c85f90b3-9df0-4dca-ab99-b2f2b19e7d0c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516287741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.2516287741
Directory /workspace/30.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1525880018
Short name T378
Test name
Test status
Simulation time 61929666927 ps
CPU time 659.47 seconds
Started Jul 12 06:02:44 PM PDT 24
Finished Jul 12 06:13:45 PM PDT 24
Peak memory 202812 kb
Host smart-33f7e9de-659f-4064-85af-7a6e83e82564
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525880018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.1525880018
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.2288095047
Short name T590
Test name
Test status
Simulation time 1256499763 ps
CPU time 3.45 seconds
Started Jul 12 06:02:51 PM PDT 24
Finished Jul 12 06:02:56 PM PDT 24
Peak memory 202832 kb
Host smart-1f3ad823-a45b-4a42-97ab-1fa12aa5a71f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288095047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2288095047
Directory /workspace/30.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/30.sram_ctrl_regwen.1668297533
Short name T767
Test name
Test status
Simulation time 4710235878 ps
CPU time 250.53 seconds
Started Jul 12 06:02:43 PM PDT 24
Finished Jul 12 06:06:54 PM PDT 24
Peak memory 375540 kb
Host smart-5795b1ce-9a17-42e4-a9f8-298ae0e77c49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668297533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1668297533
Directory /workspace/30.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/30.sram_ctrl_smoke.3040869046
Short name T476
Test name
Test status
Simulation time 2808647290 ps
CPU time 7.41 seconds
Started Jul 12 06:02:43 PM PDT 24
Finished Jul 12 06:02:51 PM PDT 24
Peak memory 202748 kb
Host smart-980baa76-9129-4e14-8875-09c8a4ece733
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040869046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3040869046
Directory /workspace/30.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/30.sram_ctrl_stress_all.849988796
Short name T828
Test name
Test status
Simulation time 176282687436 ps
CPU time 3942.86 seconds
Started Jul 12 06:02:44 PM PDT 24
Finished Jul 12 07:08:28 PM PDT 24
Peak memory 381676 kb
Host smart-77d6a90a-11bd-4733-8caa-848af3d67a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849988796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_stress_all.849988796
Directory /workspace/30.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3432944386
Short name T116
Test name
Test status
Simulation time 5786574448 ps
CPU time 43.24 seconds
Started Jul 12 06:02:44 PM PDT 24
Finished Jul 12 06:03:28 PM PDT 24
Peak memory 212176 kb
Host smart-7c63bfeb-2b64-4176-b220-23a5f0f97dc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3432944386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3432944386
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2674520594
Short name T419
Test name
Test status
Simulation time 6641731951 ps
CPU time 390.25 seconds
Started Jul 12 06:02:44 PM PDT 24
Finished Jul 12 06:09:16 PM PDT 24
Peak memory 202668 kb
Host smart-8153dc6c-2520-4925-9b78-450e66518f7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674520594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.2674520594
Directory /workspace/30.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3286759820
Short name T192
Test name
Test status
Simulation time 3318975735 ps
CPU time 103.66 seconds
Started Jul 12 06:02:46 PM PDT 24
Finished Jul 12 06:04:31 PM PDT 24
Peak memory 338716 kb
Host smart-1d623f10-8385-41ad-ad4b-88a458497fd7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286759820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3286759820
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2724682359
Short name T259
Test name
Test status
Simulation time 12999109160 ps
CPU time 1010.85 seconds
Started Jul 12 06:02:49 PM PDT 24
Finished Jul 12 06:19:41 PM PDT 24
Peak memory 372420 kb
Host smart-d6270055-ad97-404f-9e00-14efa9e63696
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724682359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.2724682359
Directory /workspace/31.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/31.sram_ctrl_alert_test.2948759003
Short name T14
Test name
Test status
Simulation time 28767560 ps
CPU time 0.66 seconds
Started Jul 12 06:02:51 PM PDT 24
Finished Jul 12 06:02:52 PM PDT 24
Peak memory 202308 kb
Host smart-7a58d8f6-4a9e-464e-a8ce-c2c72cd9429b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948759003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.2948759003
Directory /workspace/31.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/31.sram_ctrl_bijection.3549772856
Short name T649
Test name
Test status
Simulation time 317062257004 ps
CPU time 1321.47 seconds
Started Jul 12 06:02:45 PM PDT 24
Finished Jul 12 06:24:47 PM PDT 24
Peak memory 203476 kb
Host smart-fef74831-fea2-4767-9212-81453e2b300b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549772856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.3549772856
Directory /workspace/31.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/31.sram_ctrl_executable.1458075090
Short name T681
Test name
Test status
Simulation time 5158889128 ps
CPU time 112.18 seconds
Started Jul 12 06:02:49 PM PDT 24
Finished Jul 12 06:04:42 PM PDT 24
Peak memory 316284 kb
Host smart-06728c9a-4ce1-4c18-888a-22b7c82b924a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458075090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.1458075090
Directory /workspace/31.sram_ctrl_executable/latest


Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.3724030150
Short name T671
Test name
Test status
Simulation time 17296947565 ps
CPU time 34.47 seconds
Started Jul 12 06:02:53 PM PDT 24
Finished Jul 12 06:03:28 PM PDT 24
Peak memory 202752 kb
Host smart-4f1d8813-b73c-4d5f-a992-98e4a47155b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724030150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.3724030150
Directory /workspace/31.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.3636795520
Short name T391
Test name
Test status
Simulation time 792662385 ps
CPU time 80.8 seconds
Started Jul 12 06:02:53 PM PDT 24
Finished Jul 12 06:04:15 PM PDT 24
Peak memory 336620 kb
Host smart-55f0974f-8f40-406a-959b-fe7516eae7b4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636795520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.3636795520
Directory /workspace/31.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2079664335
Short name T916
Test name
Test status
Simulation time 9689796074 ps
CPU time 163.9 seconds
Started Jul 12 06:02:50 PM PDT 24
Finished Jul 12 06:05:35 PM PDT 24
Peak memory 210972 kb
Host smart-d799923b-8e06-4940-a0e2-33a016c6d6c8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079664335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.2079664335
Directory /workspace/31.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.70155718
Short name T276
Test name
Test status
Simulation time 82738414541 ps
CPU time 339.43 seconds
Started Jul 12 06:02:51 PM PDT 24
Finished Jul 12 06:08:31 PM PDT 24
Peak memory 203676 kb
Host smart-549a7c75-f959-461a-bf72-0c18b913155c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70155718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_
mem_walk.70155718
Directory /workspace/31.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.4234236820
Short name T669
Test name
Test status
Simulation time 33602716457 ps
CPU time 1915.75 seconds
Started Jul 12 06:02:44 PM PDT 24
Finished Jul 12 06:34:41 PM PDT 24
Peak memory 378672 kb
Host smart-4c798b23-f0c4-4a3b-acd0-42fa2959f70b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234236820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.4234236820
Directory /workspace/31.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/31.sram_ctrl_partial_access.1393164008
Short name T268
Test name
Test status
Simulation time 9901338402 ps
CPU time 46.22 seconds
Started Jul 12 06:02:51 PM PDT 24
Finished Jul 12 06:03:39 PM PDT 24
Peak memory 286900 kb
Host smart-0df74557-22fd-464e-bf57-fef08faf9ee7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393164008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.1393164008
Directory /workspace/31.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.395562069
Short name T608
Test name
Test status
Simulation time 28656977066 ps
CPU time 671.39 seconds
Started Jul 12 06:02:49 PM PDT 24
Finished Jul 12 06:14:02 PM PDT 24
Peak memory 202984 kb
Host smart-19888e90-709e-4634-b68f-249bd177f3df
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395562069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.sram_ctrl_partial_access_b2b.395562069
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.3370500542
Short name T731
Test name
Test status
Simulation time 348921000 ps
CPU time 3.3 seconds
Started Jul 12 06:02:54 PM PDT 24
Finished Jul 12 06:02:58 PM PDT 24
Peak memory 202728 kb
Host smart-3baedb86-055e-4f1c-b4d5-c7466fdfef99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370500542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3370500542
Directory /workspace/31.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/31.sram_ctrl_regwen.2399491180
Short name T506
Test name
Test status
Simulation time 16270118597 ps
CPU time 1051.93 seconds
Started Jul 12 06:02:54 PM PDT 24
Finished Jul 12 06:20:27 PM PDT 24
Peak memory 376644 kb
Host smart-f10c19b6-fbb0-4562-83e9-b94cc91f81f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399491180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2399491180
Directory /workspace/31.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/31.sram_ctrl_smoke.987588383
Short name T362
Test name
Test status
Simulation time 780893418 ps
CPU time 52.91 seconds
Started Jul 12 06:02:43 PM PDT 24
Finished Jul 12 06:03:37 PM PDT 24
Peak memory 332412 kb
Host smart-85536879-f26b-4b65-94b7-d5f73f407836
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987588383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.987588383
Directory /workspace/31.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/31.sram_ctrl_stress_all.4168816137
Short name T788
Test name
Test status
Simulation time 170751874783 ps
CPU time 2906.97 seconds
Started Jul 12 06:05:38 PM PDT 24
Finished Jul 12 06:54:06 PM PDT 24
Peak memory 381040 kb
Host smart-3328538a-fcbc-43a2-ab97-6efe9e499c6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168816137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.4168816137
Directory /workspace/31.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2358378333
Short name T561
Test name
Test status
Simulation time 2514118320 ps
CPU time 25.67 seconds
Started Jul 12 06:02:50 PM PDT 24
Finished Jul 12 06:03:16 PM PDT 24
Peak memory 211140 kb
Host smart-d4f26ffe-806a-4dbb-a6fa-fae8afafc823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2358378333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2358378333
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3559229997
Short name T477
Test name
Test status
Simulation time 4487618383 ps
CPU time 312.56 seconds
Started Jul 12 06:02:43 PM PDT 24
Finished Jul 12 06:07:57 PM PDT 24
Peak memory 202820 kb
Host smart-314d89db-8b68-4097-a744-f062984e4255
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559229997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.3559229997
Directory /workspace/31.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1780057180
Short name T930
Test name
Test status
Simulation time 1497970469 ps
CPU time 77.59 seconds
Started Jul 12 06:02:51 PM PDT 24
Finished Jul 12 06:04:10 PM PDT 24
Peak memory 311288 kb
Host smart-8d782168-5837-4bac-ab14-e0491d440775
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780057180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1780057180
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2096397644
Short name T217
Test name
Test status
Simulation time 43847047405 ps
CPU time 1127.97 seconds
Started Jul 12 06:02:58 PM PDT 24
Finished Jul 12 06:21:47 PM PDT 24
Peak memory 377232 kb
Host smart-0593f62f-32f9-4e73-a0a5-ceaefe976895
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096397644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.2096397644
Directory /workspace/32.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/32.sram_ctrl_alert_test.2627844366
Short name T152
Test name
Test status
Simulation time 14824859 ps
CPU time 0.66 seconds
Started Jul 12 06:03:08 PM PDT 24
Finished Jul 12 06:03:10 PM PDT 24
Peak memory 202560 kb
Host smart-9db77b3b-aef1-4eed-bdad-008578064e67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627844366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.2627844366
Directory /workspace/32.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/32.sram_ctrl_bijection.620469471
Short name T714
Test name
Test status
Simulation time 276868057615 ps
CPU time 1007.61 seconds
Started Jul 12 06:02:53 PM PDT 24
Finished Jul 12 06:19:41 PM PDT 24
Peak memory 203548 kb
Host smart-be0d1fbf-8fe7-4994-99b5-c659edfa6b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620469471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.
620469471
Directory /workspace/32.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/32.sram_ctrl_executable.4205958393
Short name T290
Test name
Test status
Simulation time 7852874524 ps
CPU time 564.5 seconds
Started Jul 12 06:02:58 PM PDT 24
Finished Jul 12 06:12:24 PM PDT 24
Peak memory 355132 kb
Host smart-d2a5b9a6-9168-4a80-b3b3-e03512d8df1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205958393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.4205958393
Directory /workspace/32.sram_ctrl_executable/latest


Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.3013235440
Short name T275
Test name
Test status
Simulation time 8593149140 ps
CPU time 45.33 seconds
Started Jul 12 06:02:59 PM PDT 24
Finished Jul 12 06:03:45 PM PDT 24
Peak memory 202848 kb
Host smart-2c52aa03-cf5c-4f99-9011-e4b0179f2b45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013235440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.3013235440
Directory /workspace/32.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.3897553803
Short name T787
Test name
Test status
Simulation time 1366487765 ps
CPU time 9.86 seconds
Started Jul 12 06:02:58 PM PDT 24
Finished Jul 12 06:03:09 PM PDT 24
Peak memory 235012 kb
Host smart-f13f5bbd-7909-47cb-9257-7b5105d1a1f8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897553803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.3897553803
Directory /workspace/32.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2572216636
Short name T833
Test name
Test status
Simulation time 6558356582 ps
CPU time 126.09 seconds
Started Jul 12 06:03:18 PM PDT 24
Finished Jul 12 06:05:25 PM PDT 24
Peak memory 219044 kb
Host smart-34358be9-c9e1-45f2-bde6-b2b6e24ff17c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572216636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.2572216636
Directory /workspace/32.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.1895110216
Short name T220
Test name
Test status
Simulation time 14124966993 ps
CPU time 321.24 seconds
Started Jul 12 06:03:00 PM PDT 24
Finished Jul 12 06:08:22 PM PDT 24
Peak memory 210928 kb
Host smart-561f12fa-9419-456a-8b7f-96c7cfc70d05
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895110216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.1895110216
Directory /workspace/32.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.1584550231
Short name T159
Test name
Test status
Simulation time 12365550247 ps
CPU time 389.2 seconds
Started Jul 12 06:02:52 PM PDT 24
Finished Jul 12 06:09:22 PM PDT 24
Peak memory 376636 kb
Host smart-5eafd52b-d3ef-4f65-b7fe-35f6765a9f2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584550231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.1584550231
Directory /workspace/32.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/32.sram_ctrl_partial_access.3755717311
Short name T521
Test name
Test status
Simulation time 907564984 ps
CPU time 17.5 seconds
Started Jul 12 06:03:01 PM PDT 24
Finished Jul 12 06:03:19 PM PDT 24
Peak memory 202700 kb
Host smart-0e5c5daf-bb98-439a-9d2d-b77cdcb55618
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755717311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.3755717311
Directory /workspace/32.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1485783359
Short name T369
Test name
Test status
Simulation time 20406544025 ps
CPU time 496.56 seconds
Started Jul 12 06:02:58 PM PDT 24
Finished Jul 12 06:11:15 PM PDT 24
Peak memory 202736 kb
Host smart-9aa8c4d1-b337-4796-bf61-16c0f641e117
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485783359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.1485783359
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.2400583823
Short name T947
Test name
Test status
Simulation time 383692299 ps
CPU time 3.32 seconds
Started Jul 12 06:02:59 PM PDT 24
Finished Jul 12 06:03:03 PM PDT 24
Peak memory 202804 kb
Host smart-729dc3a0-1f47-4f76-86f3-7e8e6284dc00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400583823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2400583823
Directory /workspace/32.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/32.sram_ctrl_regwen.181612924
Short name T231
Test name
Test status
Simulation time 14058947880 ps
CPU time 1087.58 seconds
Started Jul 12 06:02:58 PM PDT 24
Finished Jul 12 06:21:06 PM PDT 24
Peak memory 380700 kb
Host smart-9a6f8601-ea06-45a8-aadf-f3abb88e35c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181612924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.181612924
Directory /workspace/32.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/32.sram_ctrl_smoke.1739943871
Short name T773
Test name
Test status
Simulation time 948546563 ps
CPU time 76.21 seconds
Started Jul 12 06:02:53 PM PDT 24
Finished Jul 12 06:04:10 PM PDT 24
Peak memory 330332 kb
Host smart-d558d6f5-56b2-4485-aaad-52ea3321aecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739943871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1739943871
Directory /workspace/32.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/32.sram_ctrl_stress_all.2457819887
Short name T393
Test name
Test status
Simulation time 479709336952 ps
CPU time 3764.85 seconds
Started Jul 12 06:03:08 PM PDT 24
Finished Jul 12 07:05:54 PM PDT 24
Peak memory 376680 kb
Host smart-ae5c181d-d1f9-4861-9b3a-652947b50085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457819887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.sram_ctrl_stress_all.2457819887
Directory /workspace/32.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.4134102561
Short name T748
Test name
Test status
Simulation time 742036785 ps
CPU time 7.48 seconds
Started Jul 12 06:03:08 PM PDT 24
Finished Jul 12 06:03:16 PM PDT 24
Peak memory 211012 kb
Host smart-535b02c6-4b37-4492-ba88-5b3cfccc699e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4134102561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.4134102561
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3676393425
Short name T323
Test name
Test status
Simulation time 12247280167 ps
CPU time 176.6 seconds
Started Jul 12 06:02:58 PM PDT 24
Finished Jul 12 06:05:55 PM PDT 24
Peak memory 202832 kb
Host smart-ce48541f-61fa-4f58-a293-cf8cd0bb1d4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676393425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.3676393425
Directory /workspace/32.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3620000258
Short name T257
Test name
Test status
Simulation time 13653369018 ps
CPU time 13.86 seconds
Started Jul 12 06:02:59 PM PDT 24
Finished Jul 12 06:03:13 PM PDT 24
Peak memory 225468 kb
Host smart-d84e7cfc-49f4-4fe8-9488-1270c459e5fd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620000258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3620000258
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.644346951
Short name T381
Test name
Test status
Simulation time 84882615747 ps
CPU time 1813.11 seconds
Started Jul 12 06:03:08 PM PDT 24
Finished Jul 12 06:33:22 PM PDT 24
Peak memory 379668 kb
Host smart-cc121f00-0247-4ea9-8ad7-60b920651294
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644346951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 33.sram_ctrl_access_during_key_req.644346951
Directory /workspace/33.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/33.sram_ctrl_alert_test.2682355230
Short name T120
Test name
Test status
Simulation time 46200125 ps
CPU time 0.67 seconds
Started Jul 12 06:03:17 PM PDT 24
Finished Jul 12 06:03:19 PM PDT 24
Peak memory 202488 kb
Host smart-899d25bc-a817-4629-a50c-943d9e3a887a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682355230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.2682355230
Directory /workspace/33.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/33.sram_ctrl_bijection.930057887
Short name T160
Test name
Test status
Simulation time 63135741434 ps
CPU time 1348.52 seconds
Started Jul 12 06:03:11 PM PDT 24
Finished Jul 12 06:25:40 PM PDT 24
Peak memory 203460 kb
Host smart-121e22a6-a622-431f-85ee-7903a0d64665
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930057887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.
930057887
Directory /workspace/33.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/33.sram_ctrl_executable.2789521477
Short name T660
Test name
Test status
Simulation time 21115675509 ps
CPU time 1241.98 seconds
Started Jul 12 06:03:07 PM PDT 24
Finished Jul 12 06:23:50 PM PDT 24
Peak memory 379692 kb
Host smart-034cd386-2a30-46a4-a62a-77cc83260771
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789521477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.2789521477
Directory /workspace/33.sram_ctrl_executable/latest


Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.2675724688
Short name T595
Test name
Test status
Simulation time 3696101340 ps
CPU time 24.28 seconds
Started Jul 12 06:03:08 PM PDT 24
Finished Jul 12 06:03:33 PM PDT 24
Peak memory 202784 kb
Host smart-c3278a47-55f7-440a-a325-147c067295f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675724688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.2675724688
Directory /workspace/33.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.32420659
Short name T325
Test name
Test status
Simulation time 2873118511 ps
CPU time 47.12 seconds
Started Jul 12 06:03:08 PM PDT 24
Finished Jul 12 06:03:56 PM PDT 24
Peak memory 287552 kb
Host smart-e62006b9-fc02-4435-ac16-55d9e4aa279c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32420659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.sram_ctrl_max_throughput.32420659
Directory /workspace/33.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.4243443587
Short name T492
Test name
Test status
Simulation time 1443097393 ps
CPU time 73.34 seconds
Started Jul 12 06:03:16 PM PDT 24
Finished Jul 12 06:04:30 PM PDT 24
Peak memory 210892 kb
Host smart-2e3b79b9-cfbd-4969-b47f-31efefe64ebb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243443587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.4243443587
Directory /workspace/33.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.10231119
Short name T853
Test name
Test status
Simulation time 14720082530 ps
CPU time 165.67 seconds
Started Jul 12 06:03:27 PM PDT 24
Finished Jul 12 06:06:13 PM PDT 24
Peak memory 210908 kb
Host smart-f40e2244-6a9b-4e1a-b5f3-269d2093065a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10231119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_
mem_walk.10231119
Directory /workspace/33.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1940416330
Short name T507
Test name
Test status
Simulation time 35839500592 ps
CPU time 1251.48 seconds
Started Jul 12 06:03:07 PM PDT 24
Finished Jul 12 06:23:59 PM PDT 24
Peak memory 379700 kb
Host smart-c2e9e858-a003-47c7-9c66-a15384856380
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940416330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1940416330
Directory /workspace/33.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/33.sram_ctrl_partial_access.3395125176
Short name T168
Test name
Test status
Simulation time 1601015582 ps
CPU time 8.78 seconds
Started Jul 12 06:03:08 PM PDT 24
Finished Jul 12 06:03:18 PM PDT 24
Peak memory 220092 kb
Host smart-9f681e2b-06d1-4452-9642-aa06ce8d5790
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395125176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.3395125176
Directory /workspace/33.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1741368868
Short name T498
Test name
Test status
Simulation time 5176967257 ps
CPU time 332.93 seconds
Started Jul 12 06:03:08 PM PDT 24
Finished Jul 12 06:08:42 PM PDT 24
Peak memory 202740 kb
Host smart-74b3980d-fa73-40ba-a77b-366c184e2f13
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741368868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.1741368868
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.1047895375
Short name T633
Test name
Test status
Simulation time 356653502 ps
CPU time 3.4 seconds
Started Jul 12 06:03:06 PM PDT 24
Finished Jul 12 06:03:11 PM PDT 24
Peak memory 202764 kb
Host smart-2afe22bb-cf38-469c-998c-3f65d2de5cf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047895375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1047895375
Directory /workspace/33.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/33.sram_ctrl_regwen.3123620803
Short name T414
Test name
Test status
Simulation time 9886703523 ps
CPU time 79.68 seconds
Started Jul 12 06:03:07 PM PDT 24
Finished Jul 12 06:04:28 PM PDT 24
Peak memory 306148 kb
Host smart-cbbe100f-8c7c-42d6-8478-30aa87cccf77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123620803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3123620803
Directory /workspace/33.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/33.sram_ctrl_smoke.883710617
Short name T877
Test name
Test status
Simulation time 1684351863 ps
CPU time 69.65 seconds
Started Jul 12 06:03:07 PM PDT 24
Finished Jul 12 06:04:17 PM PDT 24
Peak memory 333536 kb
Host smart-8bee0d7d-41d7-4e13-9be4-6c3eca9a0f45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883710617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.883710617
Directory /workspace/33.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/33.sram_ctrl_stress_all.67238045
Short name T790
Test name
Test status
Simulation time 47324201993 ps
CPU time 1945.71 seconds
Started Jul 12 06:03:16 PM PDT 24
Finished Jul 12 06:35:42 PM PDT 24
Peak memory 378644 kb
Host smart-db9b96e2-b51e-4b01-88bc-e97ad006e25e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67238045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.sram_ctrl_stress_all.67238045
Directory /workspace/33.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3765355394
Short name T115
Test name
Test status
Simulation time 4169950050 ps
CPU time 34.8 seconds
Started Jul 12 06:03:16 PM PDT 24
Finished Jul 12 06:03:51 PM PDT 24
Peak memory 211088 kb
Host smart-720ef938-88df-4f10-a358-1bc93fd5288d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3765355394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3765355394
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1126843903
Short name T810
Test name
Test status
Simulation time 5183848595 ps
CPU time 320.76 seconds
Started Jul 12 06:03:07 PM PDT 24
Finished Jul 12 06:08:29 PM PDT 24
Peak memory 202804 kb
Host smart-9330af48-f7cb-45ed-bb1a-4eb4f2df9a96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126843903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.1126843903
Directory /workspace/33.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3699819451
Short name T733
Test name
Test status
Simulation time 4270040419 ps
CPU time 10.07 seconds
Started Jul 12 06:03:06 PM PDT 24
Finished Jul 12 06:03:17 PM PDT 24
Peak memory 224184 kb
Host smart-81f51891-bfef-467c-b85a-cd40bd48b44c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699819451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3699819451
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.4225280243
Short name T3
Test name
Test status
Simulation time 61774404711 ps
CPU time 1515.92 seconds
Started Jul 12 06:03:30 PM PDT 24
Finished Jul 12 06:28:47 PM PDT 24
Peak memory 375396 kb
Host smart-5f4a645c-4d06-42d5-b237-d8b208d72069
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225280243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.4225280243
Directory /workspace/34.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/34.sram_ctrl_alert_test.2361290661
Short name T850
Test name
Test status
Simulation time 22368648 ps
CPU time 0.67 seconds
Started Jul 12 06:03:25 PM PDT 24
Finished Jul 12 06:03:27 PM PDT 24
Peak memory 202292 kb
Host smart-bd93227f-2c9f-45eb-b8b3-86fef667fba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361290661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.2361290661
Directory /workspace/34.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/34.sram_ctrl_bijection.3726100891
Short name T316
Test name
Test status
Simulation time 61113799295 ps
CPU time 1001.38 seconds
Started Jul 12 06:03:20 PM PDT 24
Finished Jul 12 06:20:02 PM PDT 24
Peak memory 203428 kb
Host smart-13db1e9f-c611-4767-89b3-683d030a3a2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726100891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.3726100891
Directory /workspace/34.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/34.sram_ctrl_executable.1320919494
Short name T643
Test name
Test status
Simulation time 4468830179 ps
CPU time 349.77 seconds
Started Jul 12 06:03:23 PM PDT 24
Finished Jul 12 06:09:13 PM PDT 24
Peak memory 359156 kb
Host smart-242ece7b-3ab5-470a-8897-52ab1cc21506
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320919494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.1320919494
Directory /workspace/34.sram_ctrl_executable/latest


Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.3631330450
Short name T383
Test name
Test status
Simulation time 20450472771 ps
CPU time 33.88 seconds
Started Jul 12 06:03:25 PM PDT 24
Finished Jul 12 06:03:59 PM PDT 24
Peak memory 211032 kb
Host smart-01b222cb-6fe2-4553-b232-f211c905ca98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631330450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.3631330450
Directory /workspace/34.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.4152956147
Short name T423
Test name
Test status
Simulation time 2668725320 ps
CPU time 68.61 seconds
Started Jul 12 06:03:25 PM PDT 24
Finished Jul 12 06:04:34 PM PDT 24
Peak memory 338616 kb
Host smart-4506d635-de3f-4d86-93a9-7ef5f7a68e12
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152956147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.4152956147
Directory /workspace/34.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1647753088
Short name T846
Test name
Test status
Simulation time 5233253602 ps
CPU time 168.86 seconds
Started Jul 12 06:03:25 PM PDT 24
Finished Jul 12 06:06:15 PM PDT 24
Peak memory 219116 kb
Host smart-5a869997-496e-4ef7-83ab-211424846a0a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647753088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.1647753088
Directory /workspace/34.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.1767875490
Short name T49
Test name
Test status
Simulation time 43135348477 ps
CPU time 179.54 seconds
Started Jul 12 06:03:26 PM PDT 24
Finished Jul 12 06:06:26 PM PDT 24
Peak memory 210916 kb
Host smart-7dc7e0ab-a5a1-4fea-ac2e-96b131b2e08b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767875490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.1767875490
Directory /workspace/34.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.2428668334
Short name T188
Test name
Test status
Simulation time 135740880027 ps
CPU time 1522.89 seconds
Started Jul 12 06:03:15 PM PDT 24
Finished Jul 12 06:28:39 PM PDT 24
Peak memory 376656 kb
Host smart-2bf4c377-acec-430f-9750-3b8649333ac0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428668334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.2428668334
Directory /workspace/34.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/34.sram_ctrl_partial_access.623471575
Short name T302
Test name
Test status
Simulation time 671997337 ps
CPU time 33.84 seconds
Started Jul 12 06:03:15 PM PDT 24
Finished Jul 12 06:03:49 PM PDT 24
Peak memory 277824 kb
Host smart-70e0ef61-c756-4818-b342-a6f093dfd4ce
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623471575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.s
ram_ctrl_partial_access.623471575
Directory /workspace/34.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2363891630
Short name T435
Test name
Test status
Simulation time 13966369621 ps
CPU time 414.98 seconds
Started Jul 12 06:03:23 PM PDT 24
Finished Jul 12 06:10:18 PM PDT 24
Peak memory 202744 kb
Host smart-08f33f9d-7da0-4ca5-9b98-60d54e9104c8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363891630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.2363891630
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.3831345680
Short name T706
Test name
Test status
Simulation time 364777021 ps
CPU time 3.08 seconds
Started Jul 12 06:03:26 PM PDT 24
Finished Jul 12 06:03:30 PM PDT 24
Peak memory 202788 kb
Host smart-643b1d7e-1214-45a1-9876-51d34aac655b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831345680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3831345680
Directory /workspace/34.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/34.sram_ctrl_regwen.1682461723
Short name T659
Test name
Test status
Simulation time 33464434449 ps
CPU time 1093.46 seconds
Started Jul 12 06:03:24 PM PDT 24
Finished Jul 12 06:21:38 PM PDT 24
Peak memory 380640 kb
Host smart-4423f218-84e0-4398-bb0c-2a998a0b5d92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682461723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1682461723
Directory /workspace/34.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/34.sram_ctrl_smoke.896325987
Short name T711
Test name
Test status
Simulation time 2853002794 ps
CPU time 23.7 seconds
Started Jul 12 06:03:18 PM PDT 24
Finished Jul 12 06:03:42 PM PDT 24
Peak memory 202644 kb
Host smart-6d2520c3-9e92-4b4c-9b06-2555a826ad9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896325987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.896325987
Directory /workspace/34.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/34.sram_ctrl_stress_all.3768076232
Short name T525
Test name
Test status
Simulation time 1792969424074 ps
CPU time 8392.52 seconds
Started Jul 12 06:03:24 PM PDT 24
Finished Jul 12 08:23:18 PM PDT 24
Peak memory 376648 kb
Host smart-354fae0b-8a50-4cf3-bf06-8c4b4a78a001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768076232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.3768076232
Directory /workspace/34.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2541425404
Short name T22
Test name
Test status
Simulation time 358353450 ps
CPU time 6.42 seconds
Started Jul 12 06:03:30 PM PDT 24
Finished Jul 12 06:03:37 PM PDT 24
Peak memory 210996 kb
Host smart-603826e8-7675-4f88-a211-80f065031fc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2541425404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2541425404
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2882979322
Short name T175
Test name
Test status
Simulation time 6003297699 ps
CPU time 367.14 seconds
Started Jul 12 06:03:17 PM PDT 24
Finished Jul 12 06:09:25 PM PDT 24
Peak memory 202640 kb
Host smart-394ef4bc-1df2-490a-8db4-d526d1d06e34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882979322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.2882979322
Directory /workspace/34.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1944126531
Short name T150
Test name
Test status
Simulation time 3037831779 ps
CPU time 6.64 seconds
Started Jul 12 06:08:48 PM PDT 24
Finished Jul 12 06:10:11 PM PDT 24
Peak memory 210996 kb
Host smart-51d868f1-4a3f-46bd-b162-61d1a8882872
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944126531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1944126531
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1270770270
Short name T459
Test name
Test status
Simulation time 12107159067 ps
CPU time 811.21 seconds
Started Jul 12 06:03:32 PM PDT 24
Finished Jul 12 06:17:05 PM PDT 24
Peak memory 372016 kb
Host smart-e18bc039-9f62-459e-a034-40f59d605721
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270770270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.1270770270
Directory /workspace/35.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/35.sram_ctrl_alert_test.3901374545
Short name T495
Test name
Test status
Simulation time 31794779 ps
CPU time 0.65 seconds
Started Jul 12 06:03:33 PM PDT 24
Finished Jul 12 06:03:34 PM PDT 24
Peak memory 202256 kb
Host smart-caee9b77-5cf4-4b49-9e77-0491c66a5325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901374545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.3901374545
Directory /workspace/35.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/35.sram_ctrl_bijection.1053715257
Short name T852
Test name
Test status
Simulation time 23607799363 ps
CPU time 1602.73 seconds
Started Jul 12 06:03:31 PM PDT 24
Finished Jul 12 06:30:14 PM PDT 24
Peak memory 203340 kb
Host smart-6d5c402e-980a-49d9-a80e-7be70162a509
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053715257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.1053715257
Directory /workspace/35.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/35.sram_ctrl_executable.3854350210
Short name T363
Test name
Test status
Simulation time 28690906681 ps
CPU time 823.24 seconds
Started Jul 12 06:03:33 PM PDT 24
Finished Jul 12 06:17:17 PM PDT 24
Peak memory 373576 kb
Host smart-719a225b-10cd-4bd3-aa07-b5ac54a82d98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854350210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.3854350210
Directory /workspace/35.sram_ctrl_executable/latest


Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.3245614137
Short name T226
Test name
Test status
Simulation time 25553229652 ps
CPU time 58.01 seconds
Started Jul 12 06:03:31 PM PDT 24
Finished Jul 12 06:04:30 PM PDT 24
Peak memory 211040 kb
Host smart-f5ccb1a6-b318-4a57-96f7-786db434ca5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245614137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.3245614137
Directory /workspace/35.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.2669077625
Short name T471
Test name
Test status
Simulation time 3477177919 ps
CPU time 67.72 seconds
Started Jul 12 06:03:31 PM PDT 24
Finished Jul 12 06:04:39 PM PDT 24
Peak memory 309448 kb
Host smart-b388acdd-d552-451b-b615-93b231791d82
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669077625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.2669077625
Directory /workspace/35.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3657289275
Short name T895
Test name
Test status
Simulation time 50360205773 ps
CPU time 172.95 seconds
Started Jul 12 06:03:34 PM PDT 24
Finished Jul 12 06:06:28 PM PDT 24
Peak memory 210552 kb
Host smart-c872a358-309a-4e74-99d6-13e7f7ecbff5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657289275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.3657289275
Directory /workspace/35.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.3097445537
Short name T894
Test name
Test status
Simulation time 2040948254 ps
CPU time 124.98 seconds
Started Jul 12 06:03:31 PM PDT 24
Finished Jul 12 06:05:37 PM PDT 24
Peak memory 210804 kb
Host smart-f62b41f3-f8b4-430f-b94d-78e81b8bae66
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097445537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.3097445537
Directory /workspace/35.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.3109278770
Short name T144
Test name
Test status
Simulation time 47557575212 ps
CPU time 976.71 seconds
Started Jul 12 06:03:32 PM PDT 24
Finished Jul 12 06:19:50 PM PDT 24
Peak memory 378552 kb
Host smart-39d98f38-c9e6-4a77-89ae-68624f5f680f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109278770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.3109278770
Directory /workspace/35.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/35.sram_ctrl_partial_access.1683777926
Short name T890
Test name
Test status
Simulation time 8328342091 ps
CPU time 6.65 seconds
Started Jul 12 06:03:34 PM PDT 24
Finished Jul 12 06:03:41 PM PDT 24
Peak memory 201744 kb
Host smart-60c5b8e1-7066-437d-85eb-161e267b8f36
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683777926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.1683777926
Directory /workspace/35.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3184228040
Short name T774
Test name
Test status
Simulation time 40804754342 ps
CPU time 480.2 seconds
Started Jul 12 06:03:32 PM PDT 24
Finished Jul 12 06:11:33 PM PDT 24
Peak memory 202772 kb
Host smart-41c67b2b-6537-4e6d-b614-b155b43900ea
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184228040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.3184228040
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2690229624
Short name T180
Test name
Test status
Simulation time 707833002 ps
CPU time 3.43 seconds
Started Jul 12 06:03:34 PM PDT 24
Finished Jul 12 06:03:38 PM PDT 24
Peak memory 202812 kb
Host smart-92420e33-9342-41a5-a81f-3d0aedc54512
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690229624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2690229624
Directory /workspace/35.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/35.sram_ctrl_regwen.1805440362
Short name T19
Test name
Test status
Simulation time 16831456014 ps
CPU time 2155.33 seconds
Started Jul 12 06:03:31 PM PDT 24
Finished Jul 12 06:39:27 PM PDT 24
Peak memory 381752 kb
Host smart-edd2f12e-d42b-4585-8d12-8c024e6718a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805440362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1805440362
Directory /workspace/35.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/35.sram_ctrl_smoke.2768626027
Short name T416
Test name
Test status
Simulation time 395450477 ps
CPU time 33.66 seconds
Started Jul 12 06:03:31 PM PDT 24
Finished Jul 12 06:04:06 PM PDT 24
Peak memory 284752 kb
Host smart-cc4e5e5d-e35a-4bd3-a11d-8cc2bea983e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768626027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2768626027
Directory /workspace/35.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/35.sram_ctrl_stress_all.1069567427
Short name T322
Test name
Test status
Simulation time 181176473022 ps
CPU time 6655.72 seconds
Started Jul 12 06:03:32 PM PDT 24
Finished Jul 12 07:54:30 PM PDT 24
Peak memory 386784 kb
Host smart-d2bbd0ee-1478-4833-8c02-90cf011db08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069567427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.1069567427
Directory /workspace/35.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3601816632
Short name T69
Test name
Test status
Simulation time 367435350 ps
CPU time 11.98 seconds
Started Jul 12 06:03:31 PM PDT 24
Finished Jul 12 06:03:44 PM PDT 24
Peak memory 211032 kb
Host smart-b51b1d23-9637-418f-b12c-cd3f56440824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3601816632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3601816632
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1436597345
Short name T200
Test name
Test status
Simulation time 9217371401 ps
CPU time 337.71 seconds
Started Jul 12 06:03:32 PM PDT 24
Finished Jul 12 06:09:11 PM PDT 24
Peak memory 202820 kb
Host smart-63dc97b1-72be-4fe0-8a8a-cc36c970ad9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436597345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.1436597345
Directory /workspace/35.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.74873476
Short name T914
Test name
Test status
Simulation time 801704553 ps
CPU time 129.38 seconds
Started Jul 12 06:03:33 PM PDT 24
Finished Jul 12 06:05:43 PM PDT 24
Peak memory 370320 kb
Host smart-0d8464d9-5935-4b32-a1b3-c31e03dc5e7b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74873476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.sram_ctrl_throughput_w_partial_write.74873476
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.253515474
Short name T446
Test name
Test status
Simulation time 155248441864 ps
CPU time 1171.54 seconds
Started Jul 12 06:03:43 PM PDT 24
Finished Jul 12 06:23:15 PM PDT 24
Peak memory 379676 kb
Host smart-a8cdef77-36e1-4dcd-875b-bb3ac62f847c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253515474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.sram_ctrl_access_during_key_req.253515474
Directory /workspace/36.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/36.sram_ctrl_alert_test.990845780
Short name T303
Test name
Test status
Simulation time 11158428 ps
CPU time 0.67 seconds
Started Jul 12 06:03:41 PM PDT 24
Finished Jul 12 06:03:43 PM PDT 24
Peak memory 202032 kb
Host smart-9ffb5bf0-e193-428a-9ffb-e766f372e09f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990845780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.990845780
Directory /workspace/36.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/36.sram_ctrl_bijection.3285100580
Short name T717
Test name
Test status
Simulation time 230109493133 ps
CPU time 2532.65 seconds
Started Jul 12 06:03:38 PM PDT 24
Finished Jul 12 06:45:51 PM PDT 24
Peak memory 203364 kb
Host smart-cca18de3-7dc6-4305-b93c-18bde5c13f25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285100580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.3285100580
Directory /workspace/36.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/36.sram_ctrl_executable.3376936495
Short name T614
Test name
Test status
Simulation time 36596296600 ps
CPU time 1896.48 seconds
Started Jul 12 06:03:38 PM PDT 24
Finished Jul 12 06:35:15 PM PDT 24
Peak memory 380716 kb
Host smart-0c82b3b9-fa9b-4644-8e5b-86667bbcf956
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376936495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.3376936495
Directory /workspace/36.sram_ctrl_executable/latest


Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.1495632990
Short name T913
Test name
Test status
Simulation time 10014741330 ps
CPU time 49.47 seconds
Started Jul 12 06:03:39 PM PDT 24
Finished Jul 12 06:04:29 PM PDT 24
Peak memory 211020 kb
Host smart-3fc4f19c-ab20-4ff7-9715-234dcfd239e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495632990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.1495632990
Directory /workspace/36.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.3545245231
Short name T283
Test name
Test status
Simulation time 3020583545 ps
CPU time 74.19 seconds
Started Jul 12 06:03:41 PM PDT 24
Finished Jul 12 06:04:56 PM PDT 24
Peak memory 351940 kb
Host smart-1a6e891f-bc56-46e0-afc5-2935faaf2e71
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545245231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.3545245231
Directory /workspace/36.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2277113631
Short name T743
Test name
Test status
Simulation time 2774055303 ps
CPU time 73.31 seconds
Started Jul 12 06:03:39 PM PDT 24
Finished Jul 12 06:04:53 PM PDT 24
Peak memory 210912 kb
Host smart-2f6dab61-dcf4-46ef-85c9-ffc9101cd69e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277113631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.2277113631
Directory /workspace/36.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.1365583997
Short name T184
Test name
Test status
Simulation time 2018788139 ps
CPU time 126.73 seconds
Started Jul 12 06:03:39 PM PDT 24
Finished Jul 12 06:05:46 PM PDT 24
Peak memory 210820 kb
Host smart-422af9ed-20ef-4883-9994-2ffc08f8151d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365583997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.1365583997
Directory /workspace/36.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.3156360241
Short name T500
Test name
Test status
Simulation time 61002062211 ps
CPU time 747.73 seconds
Started Jul 12 06:03:43 PM PDT 24
Finished Jul 12 06:16:11 PM PDT 24
Peak memory 365324 kb
Host smart-ef6f19d5-4af3-4ba9-a6b9-70d59a106e8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156360241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.3156360241
Directory /workspace/36.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/36.sram_ctrl_partial_access.3601951074
Short name T639
Test name
Test status
Simulation time 3479330622 ps
CPU time 93.83 seconds
Started Jul 12 06:03:41 PM PDT 24
Finished Jul 12 06:05:15 PM PDT 24
Peak memory 362172 kb
Host smart-55199b80-88d4-466f-9d5f-284ccc3c272b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601951074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.3601951074
Directory /workspace/36.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.4293919871
Short name T842
Test name
Test status
Simulation time 153987765609 ps
CPU time 449.21 seconds
Started Jul 12 06:03:41 PM PDT 24
Finished Jul 12 06:11:11 PM PDT 24
Peak memory 202800 kb
Host smart-128f4578-7e82-4fe3-8502-42addbf6d3cc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293919871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.4293919871
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.1839243450
Short name T204
Test name
Test status
Simulation time 349949128 ps
CPU time 3.29 seconds
Started Jul 12 06:03:40 PM PDT 24
Finished Jul 12 06:03:44 PM PDT 24
Peak memory 202772 kb
Host smart-346c623d-1358-4083-ab66-419ec3b4ab26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839243450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1839243450
Directory /workspace/36.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/36.sram_ctrl_regwen.1389752346
Short name T580
Test name
Test status
Simulation time 12568806247 ps
CPU time 784.25 seconds
Started Jul 12 06:03:40 PM PDT 24
Finished Jul 12 06:16:45 PM PDT 24
Peak memory 363304 kb
Host smart-21262ded-1d0e-42ff-a5c1-1ebfcaccfb31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389752346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1389752346
Directory /workspace/36.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/36.sram_ctrl_smoke.2665408721
Short name T892
Test name
Test status
Simulation time 1281267261 ps
CPU time 25.61 seconds
Started Jul 12 06:03:43 PM PDT 24
Finished Jul 12 06:04:09 PM PDT 24
Peak memory 273908 kb
Host smart-075cdbd6-e528-48cc-847c-1e921add570a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665408721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2665408721
Directory /workspace/36.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/36.sram_ctrl_stress_all.3158046579
Short name T839
Test name
Test status
Simulation time 43584919066 ps
CPU time 1832.64 seconds
Started Jul 12 06:03:39 PM PDT 24
Finished Jul 12 06:34:12 PM PDT 24
Peak memory 383736 kb
Host smart-7a0fdb13-7cc7-4583-ad51-8fa44a25a5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158046579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.3158046579
Directory /workspace/36.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3158189013
Short name T278
Test name
Test status
Simulation time 701951625 ps
CPU time 5.9 seconds
Started Jul 12 06:03:41 PM PDT 24
Finished Jul 12 06:03:47 PM PDT 24
Peak memory 210968 kb
Host smart-aaa8adde-b437-4a3a-b50c-99a2a4663665
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3158189013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3158189013
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2227473480
Short name T425
Test name
Test status
Simulation time 9997836695 ps
CPU time 188.78 seconds
Started Jul 12 06:03:39 PM PDT 24
Finished Jul 12 06:06:49 PM PDT 24
Peak memory 202748 kb
Host smart-6fb9ed4e-1d29-4c6d-82bc-bdfe78f6d15e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227473480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.2227473480
Directory /workspace/36.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3910564386
Short name T222
Test name
Test status
Simulation time 797556865 ps
CPU time 124.27 seconds
Started Jul 12 06:03:40 PM PDT 24
Finished Jul 12 06:05:45 PM PDT 24
Peak memory 352052 kb
Host smart-501c096e-3348-47db-9fde-da4165583b16
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910564386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.3910564386
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1468980891
Short name T405
Test name
Test status
Simulation time 1161913331 ps
CPU time 108.03 seconds
Started Jul 12 06:03:46 PM PDT 24
Finished Jul 12 06:05:34 PM PDT 24
Peak memory 352872 kb
Host smart-4c5965d3-b374-47fd-b514-b0426431cad5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468980891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.1468980891
Directory /workspace/37.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/37.sram_ctrl_alert_test.505739656
Short name T11
Test name
Test status
Simulation time 124274005 ps
CPU time 0.66 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:03:56 PM PDT 24
Peak memory 202348 kb
Host smart-d34ce018-2d18-40fb-992e-179b76719b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505739656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.505739656
Directory /workspace/37.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/37.sram_ctrl_bijection.1412447889
Short name T747
Test name
Test status
Simulation time 526131446247 ps
CPU time 2650.92 seconds
Started Jul 12 06:03:44 PM PDT 24
Finished Jul 12 06:47:56 PM PDT 24
Peak memory 203316 kb
Host smart-1c90f9d8-3ebe-49bf-a71e-eb71d7482604
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412447889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.1412447889
Directory /workspace/37.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/37.sram_ctrl_executable.3797235726
Short name T929
Test name
Test status
Simulation time 14187875667 ps
CPU time 780.2 seconds
Started Jul 12 06:03:57 PM PDT 24
Finished Jul 12 06:16:58 PM PDT 24
Peak memory 374708 kb
Host smart-4976f239-c56f-4480-88c2-64ca992b83d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797235726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.3797235726
Directory /workspace/37.sram_ctrl_executable/latest


Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.2788611968
Short name T7
Test name
Test status
Simulation time 48650101260 ps
CPU time 71.63 seconds
Started Jul 12 06:03:49 PM PDT 24
Finished Jul 12 06:05:02 PM PDT 24
Peak memory 210984 kb
Host smart-d62f8ba3-7318-4095-8c97-94d411ceb0c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788611968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.2788611968
Directory /workspace/37.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.477728643
Short name T380
Test name
Test status
Simulation time 1481436408 ps
CPU time 28.94 seconds
Started Jul 12 06:03:47 PM PDT 24
Finished Jul 12 06:04:17 PM PDT 24
Peak memory 278688 kb
Host smart-803a7a7e-d68d-4a67-8701-54d127af0249
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477728643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.sram_ctrl_max_throughput.477728643
Directory /workspace/37.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.3747282438
Short name T815
Test name
Test status
Simulation time 8663451558 ps
CPU time 83.77 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:05:19 PM PDT 24
Peak memory 219092 kb
Host smart-b92540e9-7ff3-422d-bc1d-b54bd131ac48
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747282438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.3747282438
Directory /workspace/37.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.3608491881
Short name T909
Test name
Test status
Simulation time 5366902471 ps
CPU time 146.82 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:06:22 PM PDT 24
Peak memory 210960 kb
Host smart-8452791c-83b3-4de2-a05f-fdbd2684d52c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608491881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.3608491881
Directory /workspace/37.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.3057188700
Short name T763
Test name
Test status
Simulation time 24828274695 ps
CPU time 1692.7 seconds
Started Jul 12 06:03:47 PM PDT 24
Finished Jul 12 06:32:00 PM PDT 24
Peak memory 380744 kb
Host smart-248a0e3b-99f8-465b-875f-9c88db5bd4eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057188700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.3057188700
Directory /workspace/37.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/37.sram_ctrl_partial_access.4026180178
Short name T82
Test name
Test status
Simulation time 1841762072 ps
CPU time 69.61 seconds
Started Jul 12 06:03:48 PM PDT 24
Finished Jul 12 06:04:58 PM PDT 24
Peak memory 313480 kb
Host smart-e5f55be0-9f43-462f-858c-ba5b281f7b26
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026180178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.4026180178
Directory /workspace/37.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3072742335
Short name T751
Test name
Test status
Simulation time 6526109294 ps
CPU time 356.82 seconds
Started Jul 12 06:03:46 PM PDT 24
Finished Jul 12 06:09:43 PM PDT 24
Peak memory 202784 kb
Host smart-2d89f2bf-f9fc-4d6e-9e84-1b3f49a3c8a2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072742335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.3072742335
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.3237371563
Short name T365
Test name
Test status
Simulation time 1471428810 ps
CPU time 3.75 seconds
Started Jul 12 06:03:56 PM PDT 24
Finished Jul 12 06:04:00 PM PDT 24
Peak memory 202776 kb
Host smart-0449ba4f-6a58-4444-bffc-f986e247df8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237371563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3237371563
Directory /workspace/37.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/37.sram_ctrl_regwen.1856188872
Short name T148
Test name
Test status
Simulation time 22287074946 ps
CPU time 533.11 seconds
Started Jul 12 06:03:53 PM PDT 24
Finished Jul 12 06:12:47 PM PDT 24
Peak memory 373528 kb
Host smart-521499e4-d00d-47a1-805e-6dfd6a47c923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856188872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1856188872
Directory /workspace/37.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/37.sram_ctrl_smoke.3542700846
Short name T196
Test name
Test status
Simulation time 2317578241 ps
CPU time 88.27 seconds
Started Jul 12 06:03:47 PM PDT 24
Finished Jul 12 06:05:16 PM PDT 24
Peak memory 339960 kb
Host smart-156ead9e-f499-4e56-a6a9-8a18abfd1eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542700846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3542700846
Directory /workspace/37.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/37.sram_ctrl_stress_all.2880150508
Short name T875
Test name
Test status
Simulation time 63059800495 ps
CPU time 628.35 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:14:24 PM PDT 24
Peak memory 378704 kb
Host smart-fa8441ed-207b-4cb3-88ff-45569c275017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880150508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.2880150508
Directory /workspace/37.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2502381355
Short name T432
Test name
Test status
Simulation time 8340639789 ps
CPU time 53.17 seconds
Started Jul 12 06:03:59 PM PDT 24
Finished Jul 12 06:04:53 PM PDT 24
Peak memory 213804 kb
Host smart-0bdd7798-25ab-4762-8c7a-4f9fe60ac4d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2502381355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2502381355
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.913747544
Short name T444
Test name
Test status
Simulation time 9064670671 ps
CPU time 187.15 seconds
Started Jul 12 06:03:47 PM PDT 24
Finished Jul 12 06:06:55 PM PDT 24
Peak memory 202820 kb
Host smart-5aa39ac2-e3fd-4bac-bafc-a9d7776ab531
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913747544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.sram_ctrl_stress_pipeline.913747544
Directory /workspace/37.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4005251967
Short name T385
Test name
Test status
Simulation time 10805047144 ps
CPU time 90.61 seconds
Started Jul 12 06:03:46 PM PDT 24
Finished Jul 12 06:05:18 PM PDT 24
Peak memory 331868 kb
Host smart-6cd354e5-80b9-4c41-a932-81a22a87ef24
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005251967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.4005251967
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.341766118
Short name T804
Test name
Test status
Simulation time 23555636680 ps
CPU time 611.95 seconds
Started Jul 12 06:03:53 PM PDT 24
Finished Jul 12 06:14:05 PM PDT 24
Peak memory 345884 kb
Host smart-a1661818-b9d6-40f8-bb68-d862e79ec560
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341766118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.sram_ctrl_access_during_key_req.341766118
Directory /workspace/38.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/38.sram_ctrl_alert_test.1833780550
Short name T400
Test name
Test status
Simulation time 17360051 ps
CPU time 0.7 seconds
Started Jul 12 06:04:02 PM PDT 24
Finished Jul 12 06:04:04 PM PDT 24
Peak memory 202320 kb
Host smart-7d9cf416-566f-41db-bf41-1936b34c5235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833780550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.1833780550
Directory /workspace/38.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/38.sram_ctrl_bijection.3322535042
Short name T627
Test name
Test status
Simulation time 133690763664 ps
CPU time 582 seconds
Started Jul 12 06:03:56 PM PDT 24
Finished Jul 12 06:13:39 PM PDT 24
Peak memory 203480 kb
Host smart-ec97e76e-30cb-4062-bc8d-65ec04978e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322535042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.3322535042
Directory /workspace/38.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/38.sram_ctrl_executable.3654828916
Short name T514
Test name
Test status
Simulation time 42522277822 ps
CPU time 994.91 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:20:30 PM PDT 24
Peak memory 379696 kb
Host smart-a09b72e8-1948-4842-860d-709afaf06e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654828916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.3654828916
Directory /workspace/38.sram_ctrl_executable/latest


Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.4224527586
Short name T785
Test name
Test status
Simulation time 29621843897 ps
CPU time 29.74 seconds
Started Jul 12 06:03:54 PM PDT 24
Finished Jul 12 06:04:25 PM PDT 24
Peak memory 210984 kb
Host smart-67121cf5-d6e3-44a5-b4f1-0c1e6120f34f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224527586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.4224527586
Directory /workspace/38.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.3080329264
Short name T576
Test name
Test status
Simulation time 728114978 ps
CPU time 18.78 seconds
Started Jul 12 06:03:57 PM PDT 24
Finished Jul 12 06:04:16 PM PDT 24
Peak memory 251708 kb
Host smart-84b1baf3-1607-487f-a3eb-bb4f92b9090b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080329264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.3080329264
Directory /workspace/38.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2670313193
Short name T741
Test name
Test status
Simulation time 2424767575 ps
CPU time 75.28 seconds
Started Jul 12 06:04:01 PM PDT 24
Finished Jul 12 06:05:17 PM PDT 24
Peak memory 210996 kb
Host smart-74f3bc81-252b-4e85-be90-cbbe641908e0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670313193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.2670313193
Directory /workspace/38.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.3183737224
Short name T266
Test name
Test status
Simulation time 21118759226 ps
CPU time 174.2 seconds
Started Jul 12 06:04:01 PM PDT 24
Finished Jul 12 06:06:56 PM PDT 24
Peak memory 210952 kb
Host smart-e9e09632-eeeb-40ad-b220-5b4d7e9f2ae7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183737224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.3183737224
Directory /workspace/38.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.1964644014
Short name T789
Test name
Test status
Simulation time 3756105673 ps
CPU time 508.95 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:12:24 PM PDT 24
Peak memory 376548 kb
Host smart-63a8b2f1-6bd3-40fb-9128-ea665c528b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964644014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.1964644014
Directory /workspace/38.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/38.sram_ctrl_partial_access.2335017869
Short name T299
Test name
Test status
Simulation time 1933582908 ps
CPU time 22.81 seconds
Started Jul 12 06:03:58 PM PDT 24
Finished Jul 12 06:04:21 PM PDT 24
Peak memory 202668 kb
Host smart-14ac6726-0bca-4686-aad3-4552e86a1898
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335017869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.2335017869
Directory /workspace/38.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1008747550
Short name T272
Test name
Test status
Simulation time 69082426657 ps
CPU time 394.79 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:10:31 PM PDT 24
Peak memory 202752 kb
Host smart-99328a96-deb5-4313-a311-9518a9f52519
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008747550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.1008747550
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.556218557
Short name T662
Test name
Test status
Simulation time 1527350038 ps
CPU time 3.64 seconds
Started Jul 12 06:04:01 PM PDT 24
Finished Jul 12 06:04:06 PM PDT 24
Peak memory 202812 kb
Host smart-3d184cea-70c5-4123-8f16-0e3a3e6d75d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556218557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.556218557
Directory /workspace/38.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/38.sram_ctrl_regwen.1991883328
Short name T456
Test name
Test status
Simulation time 1572954794 ps
CPU time 719.08 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:15:55 PM PDT 24
Peak memory 378576 kb
Host smart-3b00f1f8-7d4d-43ea-9237-059f10ca9f2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991883328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1991883328
Directory /workspace/38.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/38.sram_ctrl_smoke.782050749
Short name T304
Test name
Test status
Simulation time 2708294889 ps
CPU time 117.48 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:05:53 PM PDT 24
Peak memory 348020 kb
Host smart-edd0809a-70cd-4313-bd8f-f8b9642c0f8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782050749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.782050749
Directory /workspace/38.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/38.sram_ctrl_stress_all.2919931543
Short name T768
Test name
Test status
Simulation time 682200287857 ps
CPU time 5841.71 seconds
Started Jul 12 06:04:01 PM PDT 24
Finished Jul 12 07:41:25 PM PDT 24
Peak memory 388876 kb
Host smart-f1f19512-9cd6-43bc-902e-075fbf7d7a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919931543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.2919931543
Directory /workspace/38.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.4098270542
Short name T461
Test name
Test status
Simulation time 799287593 ps
CPU time 41.01 seconds
Started Jul 12 06:04:01 PM PDT 24
Finished Jul 12 06:04:43 PM PDT 24
Peak memory 212592 kb
Host smart-296360bb-456e-44cc-b2af-cda94b1dfc83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4098270542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.4098270542
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3367889304
Short name T296
Test name
Test status
Simulation time 3633802913 ps
CPU time 237.86 seconds
Started Jul 12 06:03:55 PM PDT 24
Finished Jul 12 06:07:53 PM PDT 24
Peak memory 202760 kb
Host smart-3fe86b95-6a2f-4080-bfdc-cfc0733bc255
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367889304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.3367889304
Directory /workspace/38.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.385378792
Short name T155
Test name
Test status
Simulation time 2792502652 ps
CPU time 186.55 seconds
Started Jul 12 06:03:54 PM PDT 24
Finished Jul 12 06:07:01 PM PDT 24
Peak memory 371384 kb
Host smart-f65c7495-ec07-45b7-b0d2-f01832ac8750
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385378792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.385378792
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3194405801
Short name T103
Test name
Test status
Simulation time 24899061870 ps
CPU time 1111.27 seconds
Started Jul 12 06:04:01 PM PDT 24
Finished Jul 12 06:22:33 PM PDT 24
Peak memory 377664 kb
Host smart-3a7cff6c-3811-49e9-b3d2-372239248154
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194405801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.3194405801
Directory /workspace/39.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/39.sram_ctrl_alert_test.2602342223
Short name T642
Test name
Test status
Simulation time 98019772 ps
CPU time 0.64 seconds
Started Jul 12 06:04:10 PM PDT 24
Finished Jul 12 06:04:11 PM PDT 24
Peak memory 202304 kb
Host smart-6d46d5f7-5ebe-4ebf-93fb-505d3c835021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602342223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.2602342223
Directory /workspace/39.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/39.sram_ctrl_bijection.1081175076
Short name T619
Test name
Test status
Simulation time 33128617600 ps
CPU time 2316.39 seconds
Started Jul 12 06:04:07 PM PDT 24
Finished Jul 12 06:42:44 PM PDT 24
Peak memory 203428 kb
Host smart-0c6b6559-5a9e-4ec3-99ce-4f1bc0fe3e6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081175076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.1081175076
Directory /workspace/39.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/39.sram_ctrl_executable.2021816213
Short name T679
Test name
Test status
Simulation time 18583793061 ps
CPU time 562.31 seconds
Started Jul 12 06:04:02 PM PDT 24
Finished Jul 12 06:13:25 PM PDT 24
Peak memory 376696 kb
Host smart-6d3dfb93-9f14-4160-a916-29c6014af121
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021816213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.2021816213
Directory /workspace/39.sram_ctrl_executable/latest


Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.3629852955
Short name T683
Test name
Test status
Simulation time 15241385646 ps
CPU time 89.06 seconds
Started Jul 12 06:04:06 PM PDT 24
Finished Jul 12 06:05:35 PM PDT 24
Peak memory 202844 kb
Host smart-fdb4d8d3-f980-4389-9576-fe21df922818
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629852955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.3629852955
Directory /workspace/39.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.3326569384
Short name T232
Test name
Test status
Simulation time 1442567858 ps
CPU time 25.68 seconds
Started Jul 12 06:04:01 PM PDT 24
Finished Jul 12 06:04:27 PM PDT 24
Peak memory 267192 kb
Host smart-8648dd0f-35e6-4c7a-955e-a1509cc1ae5d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326569384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.3326569384
Directory /workspace/39.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.210103806
Short name T725
Test name
Test status
Simulation time 2999238817 ps
CPU time 89.57 seconds
Started Jul 12 06:04:06 PM PDT 24
Finished Jul 12 06:05:36 PM PDT 24
Peak memory 219164 kb
Host smart-4b93f44c-6aa0-4d25-b4ff-794277090012
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210103806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_mem_partial_access.210103806
Directory /workspace/39.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.3497056850
Short name T677
Test name
Test status
Simulation time 32114147919 ps
CPU time 322.98 seconds
Started Jul 12 06:04:01 PM PDT 24
Finished Jul 12 06:09:25 PM PDT 24
Peak memory 212008 kb
Host smart-e5a05278-43bd-436b-b8dc-ab7701305fb8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497056850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.3497056850
Directory /workspace/39.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.2764503856
Short name T269
Test name
Test status
Simulation time 26870991852 ps
CPU time 745.35 seconds
Started Jul 12 06:04:01 PM PDT 24
Finished Jul 12 06:16:28 PM PDT 24
Peak memory 375768 kb
Host smart-a21337ee-81af-4c46-b8a3-d3ecf1ab195d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764503856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.2764503856
Directory /workspace/39.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/39.sram_ctrl_partial_access.2925447609
Short name T436
Test name
Test status
Simulation time 412310327 ps
CPU time 16.8 seconds
Started Jul 12 06:04:04 PM PDT 24
Finished Jul 12 06:04:21 PM PDT 24
Peak memory 258192 kb
Host smart-350f769f-4132-41f5-8b5a-3d9cc06fcdf6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925447609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.2925447609
Directory /workspace/39.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.2105606913
Short name T551
Test name
Test status
Simulation time 490204886 ps
CPU time 3.04 seconds
Started Jul 12 06:04:02 PM PDT 24
Finished Jul 12 06:04:06 PM PDT 24
Peak memory 202856 kb
Host smart-e70858ba-db64-494e-8536-0e50bebd74ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105606913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2105606913
Directory /workspace/39.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/39.sram_ctrl_regwen.1372180450
Short name T658
Test name
Test status
Simulation time 69011855657 ps
CPU time 714.79 seconds
Started Jul 12 06:04:03 PM PDT 24
Finished Jul 12 06:15:59 PM PDT 24
Peak memory 348020 kb
Host smart-bc8be78d-b172-4ccb-b210-78cd4dfba0a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372180450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1372180450
Directory /workspace/39.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/39.sram_ctrl_smoke.2711240891
Short name T458
Test name
Test status
Simulation time 1780561656 ps
CPU time 84.3 seconds
Started Jul 12 06:04:05 PM PDT 24
Finished Jul 12 06:05:30 PM PDT 24
Peak memory 329700 kb
Host smart-d5acd2a4-151d-4f60-a154-9d635bcd1d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711240891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2711240891
Directory /workspace/39.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/39.sram_ctrl_stress_all.1917573532
Short name T819
Test name
Test status
Simulation time 18246988160 ps
CPU time 1480.28 seconds
Started Jul 12 06:04:10 PM PDT 24
Finished Jul 12 06:28:51 PM PDT 24
Peak memory 383752 kb
Host smart-702775fa-9df9-4dcd-ae9b-9e6e33e2c8b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917573532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.1917573532
Directory /workspace/39.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.841924786
Short name T726
Test name
Test status
Simulation time 7083763083 ps
CPU time 45.1 seconds
Started Jul 12 06:04:12 PM PDT 24
Finished Jul 12 06:04:57 PM PDT 24
Peak memory 211960 kb
Host smart-95a371e2-54da-45f3-9f07-f78284d28fd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=841924786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.841924786
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.479174690
Short name T440
Test name
Test status
Simulation time 19699681857 ps
CPU time 257.95 seconds
Started Jul 12 06:04:07 PM PDT 24
Finished Jul 12 06:08:26 PM PDT 24
Peak memory 202740 kb
Host smart-58ddf1e8-d623-4dbd-bce2-12d47d83711a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479174690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_stress_pipeline.479174690
Directory /workspace/39.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2438676076
Short name T463
Test name
Test status
Simulation time 765985557 ps
CPU time 101.74 seconds
Started Jul 12 06:04:05 PM PDT 24
Finished Jul 12 06:05:47 PM PDT 24
Peak memory 341712 kb
Host smart-ad4c547f-bbd6-4a62-85e5-aa2abc328a78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438676076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.2438676076
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1821174256
Short name T494
Test name
Test status
Simulation time 12238181791 ps
CPU time 565.68 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:10:15 PM PDT 24
Peak memory 307812 kb
Host smart-abc7aa8a-31db-40f2-bf63-a2384bb6b53d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821174256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.1821174256
Directory /workspace/4.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/4.sram_ctrl_alert_test.2533675529
Short name T225
Test name
Test status
Simulation time 32773561 ps
CPU time 0.66 seconds
Started Jul 12 06:00:50 PM PDT 24
Finished Jul 12 06:00:52 PM PDT 24
Peak memory 202332 kb
Host smart-8c185759-15fb-470e-ba4e-bde8f6895258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533675529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.2533675529
Directory /workspace/4.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/4.sram_ctrl_bijection.3918138784
Short name T249
Test name
Test status
Simulation time 56850694065 ps
CPU time 656.01 seconds
Started Jul 12 06:00:39 PM PDT 24
Finished Jul 12 06:11:36 PM PDT 24
Peak memory 203464 kb
Host smart-fa3fdd06-32d1-4a85-bc1e-b8327d3ed6fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918138784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
3918138784
Directory /workspace/4.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/4.sram_ctrl_executable.2473940970
Short name T439
Test name
Test status
Simulation time 140579292911 ps
CPU time 650.62 seconds
Started Jul 12 06:00:36 PM PDT 24
Finished Jul 12 06:11:28 PM PDT 24
Peak memory 378740 kb
Host smart-a5810ea7-509b-46a0-9a8f-e5b87d9e6383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473940970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.2473940970
Directory /workspace/4.sram_ctrl_executable/latest


Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.4114860830
Short name T602
Test name
Test status
Simulation time 9574251002 ps
CPU time 64.85 seconds
Started Jul 12 06:00:41 PM PDT 24
Finished Jul 12 06:01:47 PM PDT 24
Peak memory 215576 kb
Host smart-78ba438c-4ee2-417b-844c-f5d831201db0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114860830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.4114860830
Directory /workspace/4.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.1195681821
Short name T818
Test name
Test status
Simulation time 2664007896 ps
CPU time 14.5 seconds
Started Jul 12 06:00:42 PM PDT 24
Finished Jul 12 06:00:57 PM PDT 24
Peak memory 243880 kb
Host smart-29b49b75-1c29-4b28-a483-015db61da76f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195681821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.1195681821
Directory /workspace/4.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3031533804
Short name T591
Test name
Test status
Simulation time 33430869174 ps
CPU time 169.04 seconds
Started Jul 12 06:00:35 PM PDT 24
Finished Jul 12 06:03:26 PM PDT 24
Peak memory 210992 kb
Host smart-06e660b4-0f8d-4703-94ab-5e9b6a897b55
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031533804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.3031533804
Directory /workspace/4.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.449106271
Short name T360
Test name
Test status
Simulation time 7213657334 ps
CPU time 162.9 seconds
Started Jul 12 06:00:36 PM PDT 24
Finished Jul 12 06:03:20 PM PDT 24
Peak memory 203148 kb
Host smart-53cc0f34-58fc-45ad-8329-f4fbd91400e8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449106271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_
mem_walk.449106271
Directory /workspace/4.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.1247284891
Short name T371
Test name
Test status
Simulation time 34842173770 ps
CPU time 726.65 seconds
Started Jul 12 06:00:50 PM PDT 24
Finished Jul 12 06:12:58 PM PDT 24
Peak memory 363348 kb
Host smart-5c5ec91b-62bb-4574-8d92-a4a6067ff2bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247284891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.1247284891
Directory /workspace/4.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/4.sram_ctrl_partial_access.3718721254
Short name T4
Test name
Test status
Simulation time 968386833 ps
CPU time 5.32 seconds
Started Jul 12 06:00:36 PM PDT 24
Finished Jul 12 06:00:43 PM PDT 24
Peak memory 211416 kb
Host smart-9c6cda40-a4bf-4b85-94b2-706aa20ca783
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718721254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.3718721254
Directory /workspace/4.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2065836712
Short name T603
Test name
Test status
Simulation time 33260655186 ps
CPU time 424.93 seconds
Started Jul 12 06:00:48 PM PDT 24
Finished Jul 12 06:07:55 PM PDT 24
Peak memory 202740 kb
Host smart-f9f148fc-85de-4c39-9a8f-65ebe941a001
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065836712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.2065836712
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.234236495
Short name T409
Test name
Test status
Simulation time 457749781 ps
CPU time 3.15 seconds
Started Jul 12 06:00:38 PM PDT 24
Finished Jul 12 06:00:41 PM PDT 24
Peak memory 202752 kb
Host smart-8e94a8dd-aa63-46db-8ca7-1db986b46a79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234236495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.234236495
Directory /workspace/4.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/4.sram_ctrl_regwen.3036083532
Short name T697
Test name
Test status
Simulation time 5446104212 ps
CPU time 493.22 seconds
Started Jul 12 06:00:48 PM PDT 24
Finished Jul 12 06:09:04 PM PDT 24
Peak memory 377736 kb
Host smart-9bc35b3e-04e0-4dec-a472-0a4064bf630c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036083532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3036083532
Directory /workspace/4.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/4.sram_ctrl_smoke.4242114976
Short name T368
Test name
Test status
Simulation time 2192553184 ps
CPU time 19.79 seconds
Started Jul 12 06:00:33 PM PDT 24
Finished Jul 12 06:00:54 PM PDT 24
Peak memory 202740 kb
Host smart-a6a85e27-9a06-45a4-9c0a-cb6c92b0809f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242114976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.4242114976
Directory /workspace/4.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/4.sram_ctrl_stress_all.590530018
Short name T336
Test name
Test status
Simulation time 357317791256 ps
CPU time 7766.49 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 08:10:17 PM PDT 24
Peak memory 386340 kb
Host smart-e0858901-d67a-4b68-a964-593662ea568f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590530018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_stress_all.590530018
Directory /workspace/4.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.599084915
Short name T715
Test name
Test status
Simulation time 387391850 ps
CPU time 11.11 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:00:59 PM PDT 24
Peak memory 210976 kb
Host smart-0556ee17-28ce-4ff8-8d46-f49b49dddf26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=599084915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.599084915
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.1231721677
Short name T883
Test name
Test status
Simulation time 18790045135 ps
CPU time 335.21 seconds
Started Jul 12 06:00:39 PM PDT 24
Finished Jul 12 06:06:15 PM PDT 24
Peak memory 202812 kb
Host smart-c02bc9d3-5eff-4734-9571-c5f2cb257412
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231721677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.1231721677
Directory /workspace/4.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1051857057
Short name T698
Test name
Test status
Simulation time 4592287846 ps
CPU time 38.34 seconds
Started Jul 12 06:00:41 PM PDT 24
Finished Jul 12 06:01:21 PM PDT 24
Peak memory 300944 kb
Host smart-00ef1d73-ae41-4eb6-a83a-e62691ade804
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051857057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1051857057
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3345508060
Short name T473
Test name
Test status
Simulation time 25328335414 ps
CPU time 1565.41 seconds
Started Jul 12 06:04:09 PM PDT 24
Finished Jul 12 06:30:16 PM PDT 24
Peak memory 379328 kb
Host smart-8cbd9d77-d943-4b6b-87fd-b370e4d8585f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345508060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.3345508060
Directory /workspace/40.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/40.sram_ctrl_alert_test.1060659143
Short name T631
Test name
Test status
Simulation time 49938218 ps
CPU time 0.66 seconds
Started Jul 12 06:04:17 PM PDT 24
Finished Jul 12 06:04:19 PM PDT 24
Peak memory 202304 kb
Host smart-a4172c95-1409-4f98-ab86-54fd3c3436ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060659143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.1060659143
Directory /workspace/40.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/40.sram_ctrl_bijection.1055529615
Short name T213
Test name
Test status
Simulation time 522356321156 ps
CPU time 1854.36 seconds
Started Jul 12 06:04:10 PM PDT 24
Finished Jul 12 06:35:05 PM PDT 24
Peak memory 202828 kb
Host smart-93eb6d85-fe1e-47a9-bf3d-6978e769fa8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055529615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.1055529615
Directory /workspace/40.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/40.sram_ctrl_executable.3112586366
Short name T501
Test name
Test status
Simulation time 2049202812 ps
CPU time 250.59 seconds
Started Jul 12 06:04:09 PM PDT 24
Finished Jul 12 06:08:20 PM PDT 24
Peak memory 353948 kb
Host smart-e1cf81c1-53e6-4294-8e60-fd9bb1222a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112586366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.3112586366
Directory /workspace/40.sram_ctrl_executable/latest


Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.705203950
Short name T252
Test name
Test status
Simulation time 20134022239 ps
CPU time 54.29 seconds
Started Jul 12 06:04:10 PM PDT 24
Finished Jul 12 06:05:05 PM PDT 24
Peak memory 210996 kb
Host smart-0bc82d1b-07cc-49fe-b3e7-d1c3db2cef20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705203950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc
alation.705203950
Directory /workspace/40.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.2002658858
Short name T308
Test name
Test status
Simulation time 3629272961 ps
CPU time 136.72 seconds
Started Jul 12 06:04:09 PM PDT 24
Finished Jul 12 06:06:26 PM PDT 24
Peak memory 370640 kb
Host smart-4428dd78-f57a-45ab-9060-c2bcc092773a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002658858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.2002658858
Directory /workspace/40.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2515204305
Short name T46
Test name
Test status
Simulation time 14930546198 ps
CPU time 82.28 seconds
Started Jul 12 06:04:16 PM PDT 24
Finished Jul 12 06:05:39 PM PDT 24
Peak memory 210952 kb
Host smart-487d3497-09de-4c07-b316-0f72ca5bdec8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515204305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.2515204305
Directory /workspace/40.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.912079135
Short name T546
Test name
Test status
Simulation time 55264712061 ps
CPU time 325.03 seconds
Started Jul 12 06:04:10 PM PDT 24
Finished Jul 12 06:09:35 PM PDT 24
Peak memory 210908 kb
Host smart-6d30e6a2-f96d-4a47-9698-1a99a53fdd71
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912079135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl
_mem_walk.912079135
Directory /workspace/40.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.4209478478
Short name T585
Test name
Test status
Simulation time 3339659443 ps
CPU time 182.52 seconds
Started Jul 12 06:04:09 PM PDT 24
Finished Jul 12 06:07:12 PM PDT 24
Peak memory 303020 kb
Host smart-107839d8-8c0d-4044-8cf2-5cd244491700
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209478478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.4209478478
Directory /workspace/40.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/40.sram_ctrl_partial_access.953603538
Short name T319
Test name
Test status
Simulation time 780328908 ps
CPU time 14.04 seconds
Started Jul 12 06:04:12 PM PDT 24
Finished Jul 12 06:04:27 PM PDT 24
Peak memory 242116 kb
Host smart-e2104131-36e8-42a7-a622-429d8885c7f6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953603538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s
ram_ctrl_partial_access.953603538
Directory /workspace/40.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.35073438
Short name T389
Test name
Test status
Simulation time 5475731742 ps
CPU time 273.65 seconds
Started Jul 12 06:04:09 PM PDT 24
Finished Jul 12 06:08:43 PM PDT 24
Peak memory 202796 kb
Host smart-0406d5d6-a108-4419-ad79-6646d4a76e93
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35073438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_partial_access_b2b.35073438
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.3635283937
Short name T23
Test name
Test status
Simulation time 1530928993 ps
CPU time 3.65 seconds
Started Jul 12 06:04:11 PM PDT 24
Finished Jul 12 06:04:15 PM PDT 24
Peak memory 202756 kb
Host smart-b2bf49f9-d700-4d62-b5e2-efe0e3a44a78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635283937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3635283937
Directory /workspace/40.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/40.sram_ctrl_regwen.1222398688
Short name T122
Test name
Test status
Simulation time 5603921655 ps
CPU time 289.84 seconds
Started Jul 12 06:04:08 PM PDT 24
Finished Jul 12 06:08:59 PM PDT 24
Peak memory 331704 kb
Host smart-ff62d598-f4b6-40d4-9f9f-73e6342ce8e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222398688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1222398688
Directory /workspace/40.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/40.sram_ctrl_smoke.2882387828
Short name T807
Test name
Test status
Simulation time 1059558321 ps
CPU time 84.15 seconds
Started Jul 12 06:04:12 PM PDT 24
Finished Jul 12 06:05:37 PM PDT 24
Peak memory 323288 kb
Host smart-4f65b18a-6402-4d23-b694-0496d2145ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882387828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2882387828
Directory /workspace/40.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/40.sram_ctrl_stress_all.166937828
Short name T808
Test name
Test status
Simulation time 47956535592 ps
CPU time 6462.47 seconds
Started Jul 12 06:04:17 PM PDT 24
Finished Jul 12 07:52:00 PM PDT 24
Peak memory 398096 kb
Host smart-3d7ed9ed-977a-4cdf-afa4-3628843e2603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166937828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_stress_all.166937828
Directory /workspace/40.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1136477857
Short name T672
Test name
Test status
Simulation time 6345201685 ps
CPU time 59.68 seconds
Started Jul 12 06:04:16 PM PDT 24
Finished Jul 12 06:05:17 PM PDT 24
Peak memory 304036 kb
Host smart-183c716b-23ff-4284-b61b-47bf8878ec05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1136477857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1136477857
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1286471299
Short name T442
Test name
Test status
Simulation time 16823864512 ps
CPU time 293.37 seconds
Started Jul 12 06:04:09 PM PDT 24
Finished Jul 12 06:09:03 PM PDT 24
Peak memory 202796 kb
Host smart-2ccaf3f0-472f-45fc-8a0d-b30c09dd85da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286471299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.1286471299
Directory /workspace/40.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1316307780
Short name T210
Test name
Test status
Simulation time 952538331 ps
CPU time 46.27 seconds
Started Jul 12 06:04:08 PM PDT 24
Finished Jul 12 06:04:55 PM PDT 24
Peak memory 306792 kb
Host smart-86457a43-da64-46f7-8ae2-dd55392b0c1c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316307780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1316307780
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2758055189
Short name T205
Test name
Test status
Simulation time 10843917642 ps
CPU time 522.8 seconds
Started Jul 12 06:04:17 PM PDT 24
Finished Jul 12 06:13:01 PM PDT 24
Peak memory 377008 kb
Host smart-a9593975-49bc-4a44-8a09-7d88ee62b7f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758055189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.2758055189
Directory /workspace/41.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/41.sram_ctrl_alert_test.1587472495
Short name T871
Test name
Test status
Simulation time 110965907 ps
CPU time 0.72 seconds
Started Jul 12 06:04:25 PM PDT 24
Finished Jul 12 06:04:27 PM PDT 24
Peak memory 202336 kb
Host smart-f2b80d9f-e88d-45f5-9b14-0db72528ad11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587472495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.1587472495
Directory /workspace/41.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/41.sram_ctrl_bijection.2239290304
Short name T345
Test name
Test status
Simulation time 91163354490 ps
CPU time 1966.99 seconds
Started Jul 12 06:04:16 PM PDT 24
Finished Jul 12 06:37:03 PM PDT 24
Peak memory 203348 kb
Host smart-92dab031-19c2-4085-b0b4-e495287c5685
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239290304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.2239290304
Directory /workspace/41.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/41.sram_ctrl_executable.4252937283
Short name T520
Test name
Test status
Simulation time 9257328338 ps
CPU time 797.07 seconds
Started Jul 12 06:04:23 PM PDT 24
Finished Jul 12 06:17:41 PM PDT 24
Peak memory 358340 kb
Host smart-945bcc7a-db70-4bf0-b2b7-a2bf0956107e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252937283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.4252937283
Directory /workspace/41.sram_ctrl_executable/latest


Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.3901701668
Short name T857
Test name
Test status
Simulation time 14998286093 ps
CPU time 83.26 seconds
Started Jul 12 06:04:17 PM PDT 24
Finished Jul 12 06:05:41 PM PDT 24
Peak memory 202776 kb
Host smart-9359d3d9-b259-499f-830c-7451964de266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901701668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.3901701668
Directory /workspace/41.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.209581662
Short name T548
Test name
Test status
Simulation time 754594669 ps
CPU time 47.56 seconds
Started Jul 12 06:04:17 PM PDT 24
Finished Jul 12 06:05:05 PM PDT 24
Peak memory 293432 kb
Host smart-6e187d8d-48da-4e42-8541-a6120937de0f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209581662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.sram_ctrl_max_throughput.209581662
Directory /workspace/41.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2871329618
Short name T695
Test name
Test status
Simulation time 2899536754 ps
CPU time 145.2 seconds
Started Jul 12 06:04:23 PM PDT 24
Finished Jul 12 06:06:49 PM PDT 24
Peak memory 210980 kb
Host smart-53c15b18-2383-4fe0-ba84-387cb02202ee
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871329618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.2871329618
Directory /workspace/41.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.1469396236
Short name T637
Test name
Test status
Simulation time 10106900904 ps
CPU time 150.74 seconds
Started Jul 12 06:04:22 PM PDT 24
Finished Jul 12 06:06:54 PM PDT 24
Peak memory 210864 kb
Host smart-9a8fcc4d-dbb9-4e2d-b13e-751ef5f5aed1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469396236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.1469396236
Directory /workspace/41.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.1856020288
Short name T628
Test name
Test status
Simulation time 15819244174 ps
CPU time 896.46 seconds
Started Jul 12 06:04:19 PM PDT 24
Finished Jul 12 06:19:16 PM PDT 24
Peak memory 381764 kb
Host smart-c727c723-9c3b-476e-9810-e8c4920f8ba5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856020288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.1856020288
Directory /workspace/41.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/41.sram_ctrl_partial_access.2625367975
Short name T197
Test name
Test status
Simulation time 12398656782 ps
CPU time 30.08 seconds
Started Jul 12 06:04:16 PM PDT 24
Finished Jul 12 06:04:46 PM PDT 24
Peak memory 272648 kb
Host smart-0362866f-1b5b-4a19-aaa4-145a6259781e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625367975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.2625367975
Directory /workspace/41.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.165834270
Short name T41
Test name
Test status
Simulation time 16174788452 ps
CPU time 206.06 seconds
Started Jul 12 06:04:19 PM PDT 24
Finished Jul 12 06:07:46 PM PDT 24
Peak memory 202828 kb
Host smart-0f21022b-e2f8-4bdb-a75f-b0d4444f03f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165834270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.sram_ctrl_partial_access_b2b.165834270
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.2518227922
Short name T182
Test name
Test status
Simulation time 1968700446 ps
CPU time 3.49 seconds
Started Jul 12 06:04:22 PM PDT 24
Finished Jul 12 06:04:26 PM PDT 24
Peak memory 202812 kb
Host smart-a485ca83-20da-452b-9458-5aeb51bb3e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518227922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2518227922
Directory /workspace/41.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/41.sram_ctrl_regwen.78046005
Short name T648
Test name
Test status
Simulation time 54178499316 ps
CPU time 1470.64 seconds
Started Jul 12 06:04:23 PM PDT 24
Finished Jul 12 06:28:55 PM PDT 24
Peak memory 380732 kb
Host smart-86422007-b25f-4f2c-9af6-5f33bbb99626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78046005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.78046005
Directory /workspace/41.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/41.sram_ctrl_smoke.1097076008
Short name T33
Test name
Test status
Simulation time 824793479 ps
CPU time 15.89 seconds
Started Jul 12 06:04:17 PM PDT 24
Finished Jul 12 06:04:34 PM PDT 24
Peak memory 202708 kb
Host smart-2411f722-25be-4554-b27c-bc0a4686e45e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097076008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1097076008
Directory /workspace/41.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3139963473
Short name T292
Test name
Test status
Simulation time 2589205212 ps
CPU time 37.35 seconds
Started Jul 12 06:04:24 PM PDT 24
Finished Jul 12 06:05:02 PM PDT 24
Peak memory 211624 kb
Host smart-863d2b7b-3894-4c61-89a1-cc47c55529a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3139963473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3139963473
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3431761550
Short name T487
Test name
Test status
Simulation time 22399562195 ps
CPU time 225.1 seconds
Started Jul 12 06:04:16 PM PDT 24
Finished Jul 12 06:08:02 PM PDT 24
Peak memory 202784 kb
Host smart-d769e91b-87b8-41df-bc06-5873c6bd7a96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431761550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3431761550
Directory /workspace/41.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.4058228524
Short name T169
Test name
Test status
Simulation time 1499690673 ps
CPU time 75.36 seconds
Started Jul 12 06:04:18 PM PDT 24
Finished Jul 12 06:05:33 PM PDT 24
Peak memory 320212 kb
Host smart-aab401d9-a378-47d9-99d3-c4c8286d17c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058228524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.4058228524
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3970121005
Short name T372
Test name
Test status
Simulation time 9946282440 ps
CPU time 754.52 seconds
Started Jul 12 06:04:31 PM PDT 24
Finished Jul 12 06:17:06 PM PDT 24
Peak memory 378640 kb
Host smart-d9a8fee3-f629-4978-8a5c-71207abc7743
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970121005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.3970121005
Directory /workspace/42.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/42.sram_ctrl_alert_test.1684105254
Short name T517
Test name
Test status
Simulation time 16508693 ps
CPU time 0.69 seconds
Started Jul 12 06:04:39 PM PDT 24
Finished Jul 12 06:04:40 PM PDT 24
Peak memory 202520 kb
Host smart-dafc3f54-f4ec-4245-a71e-ec2e7fec62b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684105254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.1684105254
Directory /workspace/42.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/42.sram_ctrl_bijection.3250914107
Short name T597
Test name
Test status
Simulation time 247030981834 ps
CPU time 2274.84 seconds
Started Jul 12 06:04:31 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 203392 kb
Host smart-de221605-824d-4805-8221-167a66c919ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250914107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.3250914107
Directory /workspace/42.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/42.sram_ctrl_executable.1203562779
Short name T903
Test name
Test status
Simulation time 77201909786 ps
CPU time 301.53 seconds
Started Jul 12 06:04:33 PM PDT 24
Finished Jul 12 06:09:35 PM PDT 24
Peak memory 358244 kb
Host smart-dee8f69a-7f4f-4dbd-9862-7c3655b4a385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203562779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.1203562779
Directory /workspace/42.sram_ctrl_executable/latest


Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.2747366100
Short name T878
Test name
Test status
Simulation time 3874937314 ps
CPU time 22.06 seconds
Started Jul 12 06:04:30 PM PDT 24
Finished Jul 12 06:04:53 PM PDT 24
Peak memory 215504 kb
Host smart-f672fc85-6327-44e9-a044-d69f2fa19cbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747366100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.2747366100
Directory /workspace/42.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.1327678602
Short name T295
Test name
Test status
Simulation time 3162705969 ps
CPU time 152.41 seconds
Started Jul 12 06:04:32 PM PDT 24
Finished Jul 12 06:07:05 PM PDT 24
Peak memory 363236 kb
Host smart-d22189b9-6265-4993-a351-e80cb2385b95
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327678602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.1327678602
Directory /workspace/42.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.995097994
Short name T92
Test name
Test status
Simulation time 5453421941 ps
CPU time 85.95 seconds
Started Jul 12 06:04:32 PM PDT 24
Finished Jul 12 06:05:58 PM PDT 24
Peak memory 211016 kb
Host smart-b03a637f-8ff0-4f9d-bdd8-35b477cef894
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995097994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.sram_ctrl_mem_partial_access.995097994
Directory /workspace/42.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.3525077836
Short name T346
Test name
Test status
Simulation time 27616911151 ps
CPU time 330.78 seconds
Started Jul 12 06:04:31 PM PDT 24
Finished Jul 12 06:10:03 PM PDT 24
Peak memory 211776 kb
Host smart-bf13fde0-9e04-4b80-b5ec-cb183abc510f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525077836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.3525077836
Directory /workspace/42.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.507833169
Short name T499
Test name
Test status
Simulation time 8401521917 ps
CPU time 305.59 seconds
Started Jul 12 06:04:25 PM PDT 24
Finished Jul 12 06:09:32 PM PDT 24
Peak memory 346176 kb
Host smart-71062b36-9657-4607-b6b2-5ef3584ffcde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507833169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip
le_keys.507833169
Directory /workspace/42.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/42.sram_ctrl_partial_access.1934350190
Short name T166
Test name
Test status
Simulation time 1791716248 ps
CPU time 27.35 seconds
Started Jul 12 06:04:31 PM PDT 24
Finished Jul 12 06:04:59 PM PDT 24
Peak memory 202656 kb
Host smart-aad74801-403a-4b9e-8e1f-c8ca092b090b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934350190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.1934350190
Directory /workspace/42.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.970032713
Short name T143
Test name
Test status
Simulation time 64826193532 ps
CPU time 401.58 seconds
Started Jul 12 06:04:32 PM PDT 24
Finished Jul 12 06:11:14 PM PDT 24
Peak memory 202760 kb
Host smart-e92ee951-ce88-42e9-9d0b-19ed3325cbcc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970032713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.sram_ctrl_partial_access_b2b.970032713
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.280226254
Short name T902
Test name
Test status
Simulation time 679676334 ps
CPU time 3.21 seconds
Started Jul 12 06:04:30 PM PDT 24
Finished Jul 12 06:04:34 PM PDT 24
Peak memory 202796 kb
Host smart-ba9b811b-cae8-47eb-91bf-03d72efa6be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280226254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.280226254
Directory /workspace/42.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/42.sram_ctrl_regwen.3019201753
Short name T753
Test name
Test status
Simulation time 24402143064 ps
CPU time 481.07 seconds
Started Jul 12 06:04:30 PM PDT 24
Finished Jul 12 06:12:32 PM PDT 24
Peak memory 379700 kb
Host smart-e3bcbdb7-61da-4010-be51-154b5cb1b38f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019201753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3019201753
Directory /workspace/42.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/42.sram_ctrl_smoke.1364894124
Short name T891
Test name
Test status
Simulation time 878685309 ps
CPU time 136.17 seconds
Started Jul 12 06:04:23 PM PDT 24
Finished Jul 12 06:06:40 PM PDT 24
Peak memory 369224 kb
Host smart-242ed563-9d2d-4188-85ac-6a9541396244
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364894124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1364894124
Directory /workspace/42.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.4006385457
Short name T720
Test name
Test status
Simulation time 14275970250 ps
CPU time 217.01 seconds
Started Jul 12 06:04:30 PM PDT 24
Finished Jul 12 06:08:09 PM PDT 24
Peak memory 202816 kb
Host smart-254b5f51-45a0-4605-90b1-6d3b7108d768
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006385457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.4006385457
Directory /workspace/42.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2815270043
Short name T529
Test name
Test status
Simulation time 752901110 ps
CPU time 61.29 seconds
Started Jul 12 06:04:32 PM PDT 24
Finished Jul 12 06:05:34 PM PDT 24
Peak memory 323320 kb
Host smart-bd867655-0961-4ab5-bdb8-6759f4ff1e3e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815270043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2815270043
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3976133348
Short name T630
Test name
Test status
Simulation time 27028666782 ps
CPU time 1293.29 seconds
Started Jul 12 06:04:47 PM PDT 24
Finished Jul 12 06:26:21 PM PDT 24
Peak memory 379640 kb
Host smart-5fdeba7d-8522-4688-a393-355fce6235bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976133348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.3976133348
Directory /workspace/43.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/43.sram_ctrl_alert_test.2538740954
Short name T165
Test name
Test status
Simulation time 28535023 ps
CPU time 0.65 seconds
Started Jul 12 06:04:47 PM PDT 24
Finished Jul 12 06:04:48 PM PDT 24
Peak memory 202292 kb
Host smart-1be7899b-d7b8-45c1-a9fd-586aacf42d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538740954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.2538740954
Directory /workspace/43.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/43.sram_ctrl_bijection.3118015534
Short name T847
Test name
Test status
Simulation time 317024671476 ps
CPU time 1317.03 seconds
Started Jul 12 06:04:36 PM PDT 24
Finished Jul 12 06:26:34 PM PDT 24
Peak memory 202912 kb
Host smart-845d8bcf-ba37-43cc-b67f-be36904259fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118015534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.3118015534
Directory /workspace/43.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/43.sram_ctrl_executable.502581694
Short name T897
Test name
Test status
Simulation time 2533805887 ps
CPU time 361.91 seconds
Started Jul 12 06:04:47 PM PDT 24
Finished Jul 12 06:10:50 PM PDT 24
Peak memory 343916 kb
Host smart-efab726a-c2ca-4b1f-be9f-5939f970c78b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502581694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl
e.502581694
Directory /workspace/43.sram_ctrl_executable/latest


Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.329658429
Short name T760
Test name
Test status
Simulation time 16600256669 ps
CPU time 92.4 seconds
Started Jul 12 06:04:46 PM PDT 24
Finished Jul 12 06:06:19 PM PDT 24
Peak memory 202796 kb
Host smart-49bbe087-4656-41a7-a76a-2ab3b5f472c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329658429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc
alation.329658429
Directory /workspace/43.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.2310573399
Short name T8
Test name
Test status
Simulation time 718510437 ps
CPU time 8.88 seconds
Started Jul 12 06:04:41 PM PDT 24
Finished Jul 12 06:04:50 PM PDT 24
Peak memory 224464 kb
Host smart-d13027ff-7de2-46c0-be72-cff9e4fdcb50
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310573399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.2310573399
Directory /workspace/43.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3164844002
Short name T93
Test name
Test status
Simulation time 2487499337 ps
CPU time 153.56 seconds
Started Jul 12 06:04:47 PM PDT 24
Finished Jul 12 06:07:22 PM PDT 24
Peak memory 210980 kb
Host smart-95730e52-d5bf-4b86-ae06-d54740363126
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164844002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.3164844002
Directory /workspace/43.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.3806833577
Short name T770
Test name
Test status
Simulation time 7148217073 ps
CPU time 158.88 seconds
Started Jul 12 06:04:47 PM PDT 24
Finished Jul 12 06:07:27 PM PDT 24
Peak memory 210848 kb
Host smart-ac8de203-ee9a-49f4-b88f-cd956a415639
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806833577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.3806833577
Directory /workspace/43.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.1548399187
Short name T147
Test name
Test status
Simulation time 72182418104 ps
CPU time 1040 seconds
Started Jul 12 06:04:40 PM PDT 24
Finished Jul 12 06:22:00 PM PDT 24
Peak memory 380724 kb
Host smart-b45170b4-fe7f-48be-871e-9221c9c3f7ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548399187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.1548399187
Directory /workspace/43.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/43.sram_ctrl_partial_access.3681512180
Short name T151
Test name
Test status
Simulation time 3408109981 ps
CPU time 13.05 seconds
Started Jul 12 06:04:37 PM PDT 24
Finished Jul 12 06:04:51 PM PDT 24
Peak memory 202752 kb
Host smart-6d8b00eb-698b-4180-9823-7a83cafc098f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681512180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.3681512180
Directory /workspace/43.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1581459201
Short name T434
Test name
Test status
Simulation time 18430268256 ps
CPU time 447.23 seconds
Started Jul 12 06:04:38 PM PDT 24
Finished Jul 12 06:12:06 PM PDT 24
Peak memory 202752 kb
Host smart-0a834abd-9b12-42a3-b7c2-eb6dc08b1c57
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581459201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.1581459201
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.348732433
Short name T690
Test name
Test status
Simulation time 1351589128 ps
CPU time 3.9 seconds
Started Jul 12 06:04:47 PM PDT 24
Finished Jul 12 06:04:52 PM PDT 24
Peak memory 202820 kb
Host smart-689dffec-ef73-4685-90b5-2eb7675b569a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348732433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.348732433
Directory /workspace/43.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/43.sram_ctrl_regwen.2591449523
Short name T943
Test name
Test status
Simulation time 9240125289 ps
CPU time 623.94 seconds
Started Jul 12 06:04:47 PM PDT 24
Finished Jul 12 06:15:12 PM PDT 24
Peak memory 378616 kb
Host smart-5b92cc4b-cc87-4c8e-ad70-bc59313f8cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591449523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2591449523
Directory /workspace/43.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/43.sram_ctrl_smoke.2491783250
Short name T470
Test name
Test status
Simulation time 917797400 ps
CPU time 8.4 seconds
Started Jul 12 06:04:38 PM PDT 24
Finished Jul 12 06:04:48 PM PDT 24
Peak memory 222716 kb
Host smart-8575e8e4-cf27-40b6-8930-b5dc5fc766dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491783250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2491783250
Directory /workspace/43.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/43.sram_ctrl_stress_all.3088828124
Short name T887
Test name
Test status
Simulation time 284195193799 ps
CPU time 3261.92 seconds
Started Jul 12 06:04:46 PM PDT 24
Finished Jul 12 06:59:09 PM PDT 24
Peak memory 205048 kb
Host smart-ae703f65-befa-48d1-becf-a31618f2c5f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088828124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.sram_ctrl_stress_all.3088828124
Directory /workspace/43.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4037497509
Short name T71
Test name
Test status
Simulation time 6324761918 ps
CPU time 39.25 seconds
Started Jul 12 06:04:47 PM PDT 24
Finished Jul 12 06:05:27 PM PDT 24
Peak memory 211088 kb
Host smart-c077f094-5154-44c3-9df1-2b0394024302
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4037497509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.4037497509
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2632347133
Short name T655
Test name
Test status
Simulation time 9585538096 ps
CPU time 382.03 seconds
Started Jul 12 06:04:40 PM PDT 24
Finished Jul 12 06:11:02 PM PDT 24
Peak memory 202768 kb
Host smart-07ab2bde-497c-41a4-8606-bb13e3237f18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632347133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.2632347133
Directory /workspace/43.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1163242100
Short name T836
Test name
Test status
Simulation time 3264836916 ps
CPU time 150.84 seconds
Started Jul 12 06:04:42 PM PDT 24
Finished Jul 12 06:07:13 PM PDT 24
Peak memory 372544 kb
Host smart-7b3b3c85-a71c-465d-8ae9-376dc198b6a9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163242100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1163242100
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3903814369
Short name T315
Test name
Test status
Simulation time 20048033934 ps
CPU time 484.54 seconds
Started Jul 12 06:04:53 PM PDT 24
Finished Jul 12 06:12:59 PM PDT 24
Peak memory 375292 kb
Host smart-a15395d9-4188-4194-a628-aede9a282e8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903814369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.3903814369
Directory /workspace/44.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/44.sram_ctrl_alert_test.4245958079
Short name T939
Test name
Test status
Simulation time 73764842 ps
CPU time 0.7 seconds
Started Jul 12 06:04:53 PM PDT 24
Finished Jul 12 06:04:55 PM PDT 24
Peak memory 202504 kb
Host smart-1a58d335-5578-4ab8-a368-93d709408c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245958079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.4245958079
Directory /workspace/44.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/44.sram_ctrl_bijection.2795839401
Short name T382
Test name
Test status
Simulation time 502175180960 ps
CPU time 2598.54 seconds
Started Jul 12 06:04:48 PM PDT 24
Finished Jul 12 06:48:08 PM PDT 24
Peak memory 202980 kb
Host smart-1c6891af-76a0-4a0b-ae91-828303620383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795839401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.2795839401
Directory /workspace/44.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/44.sram_ctrl_executable.268343115
Short name T699
Test name
Test status
Simulation time 23464015076 ps
CPU time 1420.67 seconds
Started Jul 12 06:04:53 PM PDT 24
Finished Jul 12 06:28:35 PM PDT 24
Peak memory 377696 kb
Host smart-d0c934fb-412b-4bc4-b5fd-6ed60074e732
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268343115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl
e.268343115
Directory /workspace/44.sram_ctrl_executable/latest


Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.382992696
Short name T484
Test name
Test status
Simulation time 4270856301 ps
CPU time 11.37 seconds
Started Jul 12 06:04:51 PM PDT 24
Finished Jul 12 06:05:03 PM PDT 24
Peak memory 202724 kb
Host smart-81b8ba2e-d19a-4b66-b015-7aa13f0ced1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382992696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_esc
alation.382992696
Directory /workspace/44.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.3233541305
Short name T829
Test name
Test status
Simulation time 1519219044 ps
CPU time 65.29 seconds
Started Jul 12 06:04:52 PM PDT 24
Finished Jul 12 06:05:58 PM PDT 24
Peak memory 303892 kb
Host smart-a742bf1d-e19f-4a58-b9ea-9db3a09ce248
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233541305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.3233541305
Directory /workspace/44.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.1862121966
Short name T634
Test name
Test status
Simulation time 21554407483 ps
CPU time 355.36 seconds
Started Jul 12 06:04:53 PM PDT 24
Finished Jul 12 06:10:49 PM PDT 24
Peak memory 210944 kb
Host smart-a7aef161-9145-49cf-92c1-0582d1c4c9d1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862121966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.1862121966
Directory /workspace/44.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.2784838787
Short name T782
Test name
Test status
Simulation time 6762936258 ps
CPU time 54.5 seconds
Started Jul 12 06:04:46 PM PDT 24
Finished Jul 12 06:05:41 PM PDT 24
Peak memory 202804 kb
Host smart-ec91b244-8fff-4c0e-a0c3-f28e4bd3652e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784838787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.2784838787
Directory /workspace/44.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/44.sram_ctrl_partial_access.2067431404
Short name T485
Test name
Test status
Simulation time 1632577628 ps
CPU time 26.42 seconds
Started Jul 12 06:04:49 PM PDT 24
Finished Jul 12 06:05:16 PM PDT 24
Peak memory 202664 kb
Host smart-77de1565-1b12-473e-8c57-4065e6df0ecf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067431404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.2067431404
Directory /workspace/44.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1494907982
Short name T805
Test name
Test status
Simulation time 106774766596 ps
CPU time 373.89 seconds
Started Jul 12 06:04:49 PM PDT 24
Finished Jul 12 06:11:04 PM PDT 24
Peak memory 202772 kb
Host smart-9b4ebd4f-7cb1-403f-9b2f-c33e68398ade
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494907982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.1494907982
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.2753465728
Short name T528
Test name
Test status
Simulation time 1607005535 ps
CPU time 3.38 seconds
Started Jul 12 06:04:52 PM PDT 24
Finished Jul 12 06:04:56 PM PDT 24
Peak memory 202804 kb
Host smart-da4779c7-7703-4408-810b-4f97b52176a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753465728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2753465728
Directory /workspace/44.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/44.sram_ctrl_regwen.877273987
Short name T496
Test name
Test status
Simulation time 2695420355 ps
CPU time 1561.82 seconds
Started Jul 12 06:04:53 PM PDT 24
Finished Jul 12 06:30:56 PM PDT 24
Peak memory 381720 kb
Host smart-e9084a96-a996-4fa2-84c6-8c32f3aa8a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877273987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.877273987
Directory /workspace/44.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/44.sram_ctrl_smoke.1931442809
Short name T803
Test name
Test status
Simulation time 5927297448 ps
CPU time 30.44 seconds
Started Jul 12 06:04:45 PM PDT 24
Finished Jul 12 06:05:16 PM PDT 24
Peak memory 272568 kb
Host smart-6913fbc9-a574-48e2-888f-230e09c6ec05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931442809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1931442809
Directory /workspace/44.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/44.sram_ctrl_stress_all.2610677919
Short name T326
Test name
Test status
Simulation time 74906058089 ps
CPU time 7799.51 seconds
Started Jul 12 06:04:53 PM PDT 24
Finished Jul 12 08:14:54 PM PDT 24
Peak memory 380692 kb
Host smart-000ebcee-4d03-492f-a123-4f69b10054f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610677919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.2610677919
Directory /workspace/44.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3034611890
Short name T830
Test name
Test status
Simulation time 512427092 ps
CPU time 9.23 seconds
Started Jul 12 06:04:51 PM PDT 24
Finished Jul 12 06:05:01 PM PDT 24
Peak memory 210996 kb
Host smart-c086e31e-7fa6-4d7a-87f5-adbb9c9a1cc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3034611890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3034611890
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3636889780
Short name T558
Test name
Test status
Simulation time 39049068896 ps
CPU time 458.89 seconds
Started Jul 12 06:04:46 PM PDT 24
Finished Jul 12 06:12:25 PM PDT 24
Peak memory 202792 kb
Host smart-c1548373-2349-4cc7-8062-d842519d4c0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636889780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.3636889780
Directory /workspace/44.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2648151542
Short name T921
Test name
Test status
Simulation time 1732333958 ps
CPU time 7.81 seconds
Started Jul 12 06:04:52 PM PDT 24
Finished Jul 12 06:05:01 PM PDT 24
Peak memory 217512 kb
Host smart-497b5d84-e464-4868-a725-f60392232dee
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648151542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.2648151542
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.4120574059
Short name T358
Test name
Test status
Simulation time 17542891128 ps
CPU time 426.57 seconds
Started Jul 12 06:05:00 PM PDT 24
Finished Jul 12 06:12:07 PM PDT 24
Peak memory 373104 kb
Host smart-e480a948-d108-49eb-935f-c5b06ba767e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120574059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.4120574059
Directory /workspace/45.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/45.sram_ctrl_alert_test.3278104507
Short name T562
Test name
Test status
Simulation time 12259466 ps
CPU time 0.66 seconds
Started Jul 12 06:05:07 PM PDT 24
Finished Jul 12 06:05:09 PM PDT 24
Peak memory 202332 kb
Host smart-2b803a97-6a12-4ae6-bb26-f355164f9806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278104507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.3278104507
Directory /workspace/45.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/45.sram_ctrl_bijection.4256730367
Short name T845
Test name
Test status
Simulation time 498273797147 ps
CPU time 2471.17 seconds
Started Jul 12 06:04:52 PM PDT 24
Finished Jul 12 06:46:04 PM PDT 24
Peak memory 202880 kb
Host smart-dab5b090-e445-412b-a7e5-33ca0c0daa0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256730367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.4256730367
Directory /workspace/45.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/45.sram_ctrl_executable.3487125716
Short name T309
Test name
Test status
Simulation time 21865266434 ps
CPU time 946.85 seconds
Started Jul 12 06:04:59 PM PDT 24
Finished Jul 12 06:20:46 PM PDT 24
Peak memory 361392 kb
Host smart-7f939e72-1946-477e-a5cf-cb975ad8fc12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487125716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.3487125716
Directory /workspace/45.sram_ctrl_executable/latest


Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.3263710670
Short name T742
Test name
Test status
Simulation time 53285977267 ps
CPU time 59.93 seconds
Started Jul 12 06:04:58 PM PDT 24
Finished Jul 12 06:05:59 PM PDT 24
Peak memory 202776 kb
Host smart-1a009cb6-1434-4271-b0df-a32da278c16f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263710670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.3263710670
Directory /workspace/45.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.3497068036
Short name T814
Test name
Test status
Simulation time 1421517267 ps
CPU time 24.77 seconds
Started Jul 12 06:04:59 PM PDT 24
Finished Jul 12 06:05:24 PM PDT 24
Peak memory 271184 kb
Host smart-0eaaa753-b10c-4d41-ab83-645d4745d78d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497068036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.3497068036
Directory /workspace/45.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.75916838
Short name T550
Test name
Test status
Simulation time 1613206025 ps
CPU time 125.53 seconds
Started Jul 12 06:05:00 PM PDT 24
Finished Jul 12 06:07:06 PM PDT 24
Peak memory 210788 kb
Host smart-4d1d88ac-396c-4760-abef-2925e5e8f8e5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75916838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_mem_partial_access.75916838
Directory /workspace/45.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.1099611125
Short name T694
Test name
Test status
Simulation time 7144155920 ps
CPU time 166.33 seconds
Started Jul 12 06:05:00 PM PDT 24
Finished Jul 12 06:07:47 PM PDT 24
Peak memory 211784 kb
Host smart-36a9999f-bd61-4b2e-8ab4-dfebf2364be5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099611125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.1099611125
Directory /workspace/45.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.1110801251
Short name T616
Test name
Test status
Simulation time 97792670504 ps
CPU time 512.12 seconds
Started Jul 12 06:04:54 PM PDT 24
Finished Jul 12 06:13:27 PM PDT 24
Peak memory 348536 kb
Host smart-c73a6936-96a9-4937-bb72-2ddbc9910095
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110801251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.1110801251
Directory /workspace/45.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/45.sram_ctrl_partial_access.3242147354
Short name T796
Test name
Test status
Simulation time 2542089132 ps
CPU time 156.25 seconds
Started Jul 12 06:05:00 PM PDT 24
Finished Jul 12 06:07:37 PM PDT 24
Peak memory 368340 kb
Host smart-1cefd8bc-d344-4d4f-bc90-59cd65dc3533
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242147354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.3242147354
Directory /workspace/45.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2891414277
Short name T486
Test name
Test status
Simulation time 38763975070 ps
CPU time 482.28 seconds
Started Jul 12 06:05:01 PM PDT 24
Finished Jul 12 06:13:04 PM PDT 24
Peak memory 202788 kb
Host smart-d06a6cce-59d3-4e04-9c2d-60d404249146
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891414277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.2891414277
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.2709147330
Short name T543
Test name
Test status
Simulation time 1399239391 ps
CPU time 3.74 seconds
Started Jul 12 06:04:58 PM PDT 24
Finished Jul 12 06:05:03 PM PDT 24
Peak memory 202840 kb
Host smart-4ae910d4-d1db-4854-9ea8-f2895852cbf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709147330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2709147330
Directory /workspace/45.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/45.sram_ctrl_regwen.1931367111
Short name T632
Test name
Test status
Simulation time 22239138500 ps
CPU time 1017.02 seconds
Started Jul 12 06:05:00 PM PDT 24
Finished Jul 12 06:21:58 PM PDT 24
Peak memory 379704 kb
Host smart-5c8b653a-2c63-45b7-b1f3-2fc469473962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931367111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1931367111
Directory /workspace/45.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/45.sram_ctrl_smoke.1901683611
Short name T156
Test name
Test status
Simulation time 921576933 ps
CPU time 21.41 seconds
Started Jul 12 06:04:51 PM PDT 24
Finished Jul 12 06:05:13 PM PDT 24
Peak memory 202704 kb
Host smart-e67e5938-8ce7-48bb-b6e0-df19b6e3272a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901683611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1901683611
Directory /workspace/45.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/45.sram_ctrl_stress_all.1344506523
Short name T390
Test name
Test status
Simulation time 74004209770 ps
CPU time 4199.38 seconds
Started Jul 12 06:05:07 PM PDT 24
Finished Jul 12 07:15:09 PM PDT 24
Peak memory 379764 kb
Host smart-c55767ed-28e8-4166-9938-4a973da8be98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344506523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.1344506523
Directory /workspace/45.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1418558678
Short name T114
Test name
Test status
Simulation time 422406413 ps
CPU time 7.89 seconds
Started Jul 12 06:05:07 PM PDT 24
Finished Jul 12 06:05:16 PM PDT 24
Peak memory 210896 kb
Host smart-ffeb1f3c-a4db-476a-b2a3-adb647a14175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1418558678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1418558678
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2866885480
Short name T208
Test name
Test status
Simulation time 3886159567 ps
CPU time 229.04 seconds
Started Jul 12 06:04:54 PM PDT 24
Finished Jul 12 06:08:44 PM PDT 24
Peak memory 202748 kb
Host smart-1f724b3c-5180-4841-aeaf-4176d5cb3567
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866885480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.2866885480
Directory /workspace/45.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1742597466
Short name T154
Test name
Test status
Simulation time 12872465520 ps
CPU time 125.3 seconds
Started Jul 12 06:05:00 PM PDT 24
Finished Jul 12 06:07:06 PM PDT 24
Peak memory 361260 kb
Host smart-3774254b-ef64-4a1b-8a81-1db08f953d31
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742597466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1742597466
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1470288156
Short name T246
Test name
Test status
Simulation time 136999850202 ps
CPU time 620.06 seconds
Started Jul 12 06:05:05 PM PDT 24
Finished Jul 12 06:15:26 PM PDT 24
Peak memory 378708 kb
Host smart-5d39102e-113f-4943-a8ef-a515835a7db0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470288156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.1470288156
Directory /workspace/46.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/46.sram_ctrl_alert_test.3721484436
Short name T199
Test name
Test status
Simulation time 21785058 ps
CPU time 0.67 seconds
Started Jul 12 06:05:14 PM PDT 24
Finished Jul 12 06:05:15 PM PDT 24
Peak memory 202332 kb
Host smart-82ed001c-7f76-4a06-bae4-6406d333496a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721484436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.3721484436
Directory /workspace/46.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/46.sram_ctrl_bijection.1389647290
Short name T946
Test name
Test status
Simulation time 423270282857 ps
CPU time 2571.17 seconds
Started Jul 12 06:05:10 PM PDT 24
Finished Jul 12 06:48:02 PM PDT 24
Peak memory 203528 kb
Host smart-4d85286a-29cd-4b79-9ca6-3f4474a26d17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389647290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.1389647290
Directory /workspace/46.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/46.sram_ctrl_executable.3984761952
Short name T910
Test name
Test status
Simulation time 4674135115 ps
CPU time 635.65 seconds
Started Jul 12 06:05:08 PM PDT 24
Finished Jul 12 06:15:45 PM PDT 24
Peak memory 378660 kb
Host smart-32bb7dec-5565-4fc3-b2b5-b6e8abf8bf0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984761952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.3984761952
Directory /workspace/46.sram_ctrl_executable/latest


Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.496354361
Short name T119
Test name
Test status
Simulation time 19663230653 ps
CPU time 58.92 seconds
Started Jul 12 06:05:09 PM PDT 24
Finished Jul 12 06:06:09 PM PDT 24
Peak memory 211060 kb
Host smart-294c1cf2-214e-4dc4-851c-64d6848ed9e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496354361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_esc
alation.496354361
Directory /workspace/46.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.1291773644
Short name T825
Test name
Test status
Simulation time 2735866284 ps
CPU time 115.76 seconds
Started Jul 12 06:05:07 PM PDT 24
Finished Jul 12 06:07:04 PM PDT 24
Peak memory 370500 kb
Host smart-bff35804-a5e5-4b3b-b168-d5fd24348720
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291773644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.1291773644
Directory /workspace/46.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1151601015
Short name T314
Test name
Test status
Simulation time 10115173781 ps
CPU time 79.42 seconds
Started Jul 12 06:05:15 PM PDT 24
Finished Jul 12 06:06:35 PM PDT 24
Peak memory 211004 kb
Host smart-121bb6eb-8996-4009-a673-a71dae95fe33
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151601015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.1151601015
Directory /workspace/46.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.1333394358
Short name T253
Test name
Test status
Simulation time 6915934837 ps
CPU time 168.51 seconds
Started Jul 12 06:05:06 PM PDT 24
Finished Jul 12 06:07:55 PM PDT 24
Peak memory 202732 kb
Host smart-eee6ebae-186e-4900-90e3-cf4260c1fdf6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333394358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.1333394358
Directory /workspace/46.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.178944151
Short name T832
Test name
Test status
Simulation time 104791819382 ps
CPU time 2102.33 seconds
Started Jul 12 06:05:06 PM PDT 24
Finished Jul 12 06:40:10 PM PDT 24
Peak memory 377656 kb
Host smart-2fe3c3ac-217a-4160-aa0c-2de9d8ff513f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178944151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip
le_keys.178944151
Directory /workspace/46.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/46.sram_ctrl_partial_access.4243972262
Short name T229
Test name
Test status
Simulation time 3238748926 ps
CPU time 56.71 seconds
Started Jul 12 06:05:07 PM PDT 24
Finished Jul 12 06:06:06 PM PDT 24
Peak memory 304252 kb
Host smart-eec0b72a-011e-4ce8-b558-ac8f508892f7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243972262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.4243972262
Directory /workspace/46.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1042871940
Short name T700
Test name
Test status
Simulation time 99008938687 ps
CPU time 352.37 seconds
Started Jul 12 06:05:06 PM PDT 24
Finished Jul 12 06:11:00 PM PDT 24
Peak memory 202816 kb
Host smart-a4aac494-bfe1-410a-b747-e07b859adf72
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042871940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.1042871940
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.48063185
Short name T579
Test name
Test status
Simulation time 1403665858 ps
CPU time 3.61 seconds
Started Jul 12 06:05:06 PM PDT 24
Finished Jul 12 06:05:10 PM PDT 24
Peak memory 202784 kb
Host smart-833f3178-5100-48ec-aeeb-1e045bb2d71e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48063185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.48063185
Directory /workspace/46.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/46.sram_ctrl_regwen.2487474385
Short name T63
Test name
Test status
Simulation time 8358011829 ps
CPU time 1032.97 seconds
Started Jul 12 06:05:07 PM PDT 24
Finished Jul 12 06:22:22 PM PDT 24
Peak memory 380748 kb
Host smart-47b14854-eb76-4ad5-ae66-bf4ee6e545be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487474385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2487474385
Directory /workspace/46.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/46.sram_ctrl_smoke.2597995772
Short name T305
Test name
Test status
Simulation time 2700748497 ps
CPU time 66.22 seconds
Started Jul 12 06:05:09 PM PDT 24
Finished Jul 12 06:06:16 PM PDT 24
Peak memory 314184 kb
Host smart-46471f37-95fd-44de-ac6d-720d1ac270e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597995772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2597995772
Directory /workspace/46.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/46.sram_ctrl_stress_all.1686205848
Short name T872
Test name
Test status
Simulation time 118199735668 ps
CPU time 6216.27 seconds
Started Jul 12 06:05:13 PM PDT 24
Finished Jul 12 07:48:51 PM PDT 24
Peak memory 382812 kb
Host smart-3522c267-8965-4861-a87f-ddd645988acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686205848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.1686205848
Directory /workspace/46.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.19075546
Short name T535
Test name
Test status
Simulation time 659788606 ps
CPU time 11.32 seconds
Started Jul 12 06:05:15 PM PDT 24
Finished Jul 12 06:05:27 PM PDT 24
Peak memory 211012 kb
Host smart-4538d669-1b2c-4fad-ab87-69342dc86ba2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=19075546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.19075546
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2712537734
Short name T798
Test name
Test status
Simulation time 20501784275 ps
CPU time 332.23 seconds
Started Jul 12 06:05:05 PM PDT 24
Finished Jul 12 06:10:38 PM PDT 24
Peak memory 202804 kb
Host smart-37698cda-0df3-4f8c-9fd8-3518130aff8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712537734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.2712537734
Directory /workspace/46.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2469877437
Short name T919
Test name
Test status
Simulation time 1410446595 ps
CPU time 7.4 seconds
Started Jul 12 06:05:07 PM PDT 24
Finished Jul 12 06:05:16 PM PDT 24
Peak memory 211928 kb
Host smart-0b892234-6e85-4944-bfa8-373d12d147aa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469877437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2469877437
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1613373118
Short name T250
Test name
Test status
Simulation time 16285216696 ps
CPU time 253.83 seconds
Started Jul 12 06:05:23 PM PDT 24
Finished Jul 12 06:09:38 PM PDT 24
Peak memory 344788 kb
Host smart-7859b7ec-d4ec-4651-9b45-6ce44cab9c56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613373118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.1613373118
Directory /workspace/47.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/47.sram_ctrl_alert_test.2120651242
Short name T318
Test name
Test status
Simulation time 33908411 ps
CPU time 0.7 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:05:32 PM PDT 24
Peak memory 202360 kb
Host smart-385fb65f-7bb7-4142-a417-f645dca429bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120651242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.2120651242
Directory /workspace/47.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/47.sram_ctrl_bijection.1601625359
Short name T247
Test name
Test status
Simulation time 173580947603 ps
CPU time 688.16 seconds
Started Jul 12 06:05:22 PM PDT 24
Finished Jul 12 06:16:50 PM PDT 24
Peak memory 203492 kb
Host smart-7efcc8e9-d03b-4567-8eb6-b789d6ddf58a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601625359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.1601625359
Directory /workspace/47.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/47.sram_ctrl_executable.120379754
Short name T399
Test name
Test status
Simulation time 19968254709 ps
CPU time 1098.06 seconds
Started Jul 12 06:05:25 PM PDT 24
Finished Jul 12 06:23:44 PM PDT 24
Peak memory 376048 kb
Host smart-f0e037cf-4ff0-4159-a841-f503de6834e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120379754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executabl
e.120379754
Directory /workspace/47.sram_ctrl_executable/latest


Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.996165423
Short name T859
Test name
Test status
Simulation time 17947821560 ps
CPU time 37.76 seconds
Started Jul 12 06:05:22 PM PDT 24
Finished Jul 12 06:06:00 PM PDT 24
Peak memory 202860 kb
Host smart-18642c9e-38e2-41bc-9b0d-86ada147a9a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996165423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esc
alation.996165423
Directory /workspace/47.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.1424326178
Short name T693
Test name
Test status
Simulation time 3328432415 ps
CPU time 152.23 seconds
Started Jul 12 06:05:22 PM PDT 24
Finished Jul 12 06:07:55 PM PDT 24
Peak memory 371436 kb
Host smart-39a6f1ad-7470-4a42-91da-6a45a0864c86
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424326178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.1424326178
Directory /workspace/47.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2452725983
Short name T568
Test name
Test status
Simulation time 10917385021 ps
CPU time 172.38 seconds
Started Jul 12 06:05:23 PM PDT 24
Finished Jul 12 06:08:16 PM PDT 24
Peak memory 211016 kb
Host smart-250b7f00-6638-4128-a2fd-cbd72a266ead
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452725983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.2452725983
Directory /workspace/47.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.1229695131
Short name T52
Test name
Test status
Simulation time 7209756382 ps
CPU time 159.84 seconds
Started Jul 12 06:05:24 PM PDT 24
Finished Jul 12 06:08:05 PM PDT 24
Peak memory 203136 kb
Host smart-2a794d97-9952-410a-989b-4d37cac92c9f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229695131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.1229695131
Directory /workspace/47.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.3584334781
Short name T258
Test name
Test status
Simulation time 29665703935 ps
CPU time 778.32 seconds
Started Jul 12 06:05:17 PM PDT 24
Finished Jul 12 06:18:16 PM PDT 24
Peak memory 376600 kb
Host smart-f353813d-e6b3-429c-bd45-4c21da94a609
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584334781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.3584334781
Directory /workspace/47.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/47.sram_ctrl_partial_access.2357383064
Short name T176
Test name
Test status
Simulation time 14925099021 ps
CPU time 22.81 seconds
Started Jul 12 06:05:23 PM PDT 24
Finished Jul 12 06:05:46 PM PDT 24
Peak memory 202748 kb
Host smart-e66722a4-bf81-455f-85fc-1d82a0d0a150
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357383064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.2357383064
Directory /workspace/47.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.787316689
Short name T339
Test name
Test status
Simulation time 183939385863 ps
CPU time 503.55 seconds
Started Jul 12 06:05:22 PM PDT 24
Finished Jul 12 06:13:47 PM PDT 24
Peak memory 202744 kb
Host smart-f5ad0fa2-7756-4e4e-a7d0-7463072de14d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787316689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.sram_ctrl_partial_access_b2b.787316689
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.379490598
Short name T858
Test name
Test status
Simulation time 2590471880 ps
CPU time 3.18 seconds
Started Jul 12 06:05:28 PM PDT 24
Finished Jul 12 06:05:32 PM PDT 24
Peak memory 202916 kb
Host smart-287e71cc-d12a-4eb3-ab95-fc4dfef5ec85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379490598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.379490598
Directory /workspace/47.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/47.sram_ctrl_regwen.161679364
Short name T802
Test name
Test status
Simulation time 5432254228 ps
CPU time 455.36 seconds
Started Jul 12 06:05:29 PM PDT 24
Finished Jul 12 06:13:05 PM PDT 24
Peak memory 360268 kb
Host smart-1e595bbb-8c5f-4afa-b6f0-dcbc8e5a0853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161679364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.161679364
Directory /workspace/47.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/47.sram_ctrl_smoke.1144291588
Short name T387
Test name
Test status
Simulation time 821754771 ps
CPU time 14.9 seconds
Started Jul 12 06:05:15 PM PDT 24
Finished Jul 12 06:05:30 PM PDT 24
Peak memory 202640 kb
Host smart-f6bab07c-6222-47a0-a9b0-5ed187ea1733
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144291588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1144291588
Directory /workspace/47.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/47.sram_ctrl_stress_all.3433267935
Short name T194
Test name
Test status
Simulation time 20560225884 ps
CPU time 2666.17 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:49:57 PM PDT 24
Peak memory 389936 kb
Host smart-2913e184-7220-4946-9c52-5f963be1bfb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433267935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.3433267935
Directory /workspace/47.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3898089688
Short name T855
Test name
Test status
Simulation time 7635769547 ps
CPU time 138.82 seconds
Started Jul 12 06:05:24 PM PDT 24
Finished Jul 12 06:07:43 PM PDT 24
Peak memory 202792 kb
Host smart-55f883e7-2b40-4346-b0cd-cfaf009724ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898089688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.3898089688
Directory /workspace/47.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.623888721
Short name T359
Test name
Test status
Simulation time 2062541867 ps
CPU time 145.6 seconds
Started Jul 12 06:05:24 PM PDT 24
Finished Jul 12 06:07:50 PM PDT 24
Peak memory 360072 kb
Host smart-7ce8962e-1168-438d-b65d-b3359b006330
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623888721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.623888721
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2462773170
Short name T792
Test name
Test status
Simulation time 84215350852 ps
CPU time 1740.42 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:34:32 PM PDT 24
Peak memory 380156 kb
Host smart-0824f28d-8010-4dcc-bbcd-6d9bec3c31c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462773170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.2462773170
Directory /workspace/48.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/48.sram_ctrl_alert_test.1220361189
Short name T348
Test name
Test status
Simulation time 20813543 ps
CPU time 0.68 seconds
Started Jul 12 06:05:39 PM PDT 24
Finished Jul 12 06:05:41 PM PDT 24
Peak memory 202368 kb
Host smart-d5bd2e77-9a47-466e-96ac-1cc1f39e6785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220361189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.1220361189
Directory /workspace/48.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/48.sram_ctrl_bijection.2827080731
Short name T413
Test name
Test status
Simulation time 217735987989 ps
CPU time 2221.21 seconds
Started Jul 12 06:05:31 PM PDT 24
Finished Jul 12 06:42:33 PM PDT 24
Peak memory 202832 kb
Host smart-2cccc6cd-2f6d-4d89-9de5-3a47fce0793e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827080731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.2827080731
Directory /workspace/48.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/48.sram_ctrl_executable.2589296294
Short name T684
Test name
Test status
Simulation time 57951717108 ps
CPU time 1031.89 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:22:44 PM PDT 24
Peak memory 379636 kb
Host smart-bda2ddd0-d381-4f95-b1d4-3f4d571b96d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589296294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab
le.2589296294
Directory /workspace/48.sram_ctrl_executable/latest


Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.3639091889
Short name T189
Test name
Test status
Simulation time 35122877318 ps
CPU time 62.74 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:06:34 PM PDT 24
Peak memory 202864 kb
Host smart-772828fb-b9fd-4b7f-ba1c-63db572568d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639091889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.3639091889
Directory /workspace/48.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.3459224160
Short name T607
Test name
Test status
Simulation time 3089776068 ps
CPU time 99.54 seconds
Started Jul 12 06:05:31 PM PDT 24
Finished Jul 12 06:07:12 PM PDT 24
Peak memory 370392 kb
Host smart-b6c1a4a0-a7c3-4a90-9978-10c194f1fc89
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459224160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.3459224160
Directory /workspace/48.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.174890561
Short name T460
Test name
Test status
Simulation time 3316955425 ps
CPU time 125.24 seconds
Started Jul 12 06:05:29 PM PDT 24
Finished Jul 12 06:07:35 PM PDT 24
Peak memory 219100 kb
Host smart-fe205a3e-e6fb-4b18-968c-2fec08d9aa62
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174890561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_mem_partial_access.174890561
Directory /workspace/48.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.3180349377
Short name T483
Test name
Test status
Simulation time 9654097070 ps
CPU time 169.72 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:08:20 PM PDT 24
Peak memory 210900 kb
Host smart-9767e14d-e0a2-47b2-96e5-79c97700cfd5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180349377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.3180349377
Directory /workspace/48.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.556273697
Short name T586
Test name
Test status
Simulation time 12704644801 ps
CPU time 764.19 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:18:15 PM PDT 24
Peak memory 373696 kb
Host smart-eb855b58-3e3f-494a-917a-b2099950fe53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556273697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip
le_keys.556273697
Directory /workspace/48.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/48.sram_ctrl_partial_access.1918709218
Short name T291
Test name
Test status
Simulation time 1661093801 ps
CPU time 25.17 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:05:57 PM PDT 24
Peak memory 202676 kb
Host smart-d3c84c86-ab17-45b7-ac7c-b655aa6651a8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918709218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.1918709218
Directory /workspace/48.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.266997744
Short name T640
Test name
Test status
Simulation time 57027801210 ps
CPU time 245.79 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:09:37 PM PDT 24
Peak memory 202764 kb
Host smart-2bc83a9b-0f24-4631-a399-7f48a28e8c30
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266997744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.sram_ctrl_partial_access_b2b.266997744
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.1382086892
Short name T289
Test name
Test status
Simulation time 470126095 ps
CPU time 3.27 seconds
Started Jul 12 06:05:29 PM PDT 24
Finished Jul 12 06:05:34 PM PDT 24
Peak memory 202800 kb
Host smart-ba3d8abb-502a-4bcf-bb59-55c6f3f0a877
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382086892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1382086892
Directory /workspace/48.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/48.sram_ctrl_smoke.2171951996
Short name T848
Test name
Test status
Simulation time 2539859250 ps
CPU time 7.31 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:05:39 PM PDT 24
Peak memory 202760 kb
Host smart-e172bc61-dedf-4ec0-8c51-7c8d03e85313
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171951996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2171951996
Directory /workspace/48.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/48.sram_ctrl_stress_all.1726612558
Short name T676
Test name
Test status
Simulation time 301835943937 ps
CPU time 5093.99 seconds
Started Jul 12 06:05:38 PM PDT 24
Finished Jul 12 07:30:33 PM PDT 24
Peak memory 382596 kb
Host smart-64b97774-d0f7-48f6-a90f-7d866265eace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726612558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.1726612558
Directory /workspace/48.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2727636035
Short name T433
Test name
Test status
Simulation time 756454918 ps
CPU time 25.51 seconds
Started Jul 12 06:05:38 PM PDT 24
Finished Jul 12 06:06:05 PM PDT 24
Peak memory 211136 kb
Host smart-537c548e-2a73-4ef0-bf3a-dae338c71d24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2727636035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2727636035
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.870379303
Short name T918
Test name
Test status
Simulation time 9762648755 ps
CPU time 350.91 seconds
Started Jul 12 06:05:30 PM PDT 24
Finished Jul 12 06:11:22 PM PDT 24
Peak memory 202856 kb
Host smart-fcbd5acc-1b61-4275-bab5-60d688eb8d3d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870379303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_stress_pipeline.870379303
Directory /workspace/48.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.322975388
Short name T941
Test name
Test status
Simulation time 2468531101 ps
CPU time 135.03 seconds
Started Jul 12 06:05:28 PM PDT 24
Finished Jul 12 06:07:44 PM PDT 24
Peak memory 370392 kb
Host smart-0cd868b0-89cd-41c2-8948-ec591db47c5d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322975388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.322975388
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1621013536
Short name T218
Test name
Test status
Simulation time 246571848343 ps
CPU time 605.98 seconds
Started Jul 12 06:05:36 PM PDT 24
Finished Jul 12 06:15:42 PM PDT 24
Peak memory 373560 kb
Host smart-7711cda4-00f2-4b1c-897d-21143639c31f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621013536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.1621013536
Directory /workspace/49.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/49.sram_ctrl_alert_test.2983574510
Short name T328
Test name
Test status
Simulation time 41059859 ps
CPU time 0.65 seconds
Started Jul 12 06:05:45 PM PDT 24
Finished Jul 12 06:05:46 PM PDT 24
Peak memory 202252 kb
Host smart-b188b0f8-3579-42d2-9555-90e03c613f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983574510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.2983574510
Directory /workspace/49.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/49.sram_ctrl_bijection.3779628096
Short name T374
Test name
Test status
Simulation time 8380776009 ps
CPU time 559.63 seconds
Started Jul 12 06:05:39 PM PDT 24
Finished Jul 12 06:14:59 PM PDT 24
Peak memory 203492 kb
Host smart-fa036555-7b3b-44e6-a527-feac4ec914df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779628096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.3779628096
Directory /workspace/49.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/49.sram_ctrl_executable.4085806186
Short name T179
Test name
Test status
Simulation time 75075692747 ps
CPU time 1188.21 seconds
Started Jul 12 06:05:39 PM PDT 24
Finished Jul 12 06:25:28 PM PDT 24
Peak memory 379572 kb
Host smart-d5b1efbf-fadb-4c7a-b8a0-da2d8cbbe4b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085806186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.4085806186
Directory /workspace/49.sram_ctrl_executable/latest


Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.1220310805
Short name T124
Test name
Test status
Simulation time 48389318223 ps
CPU time 81.89 seconds
Started Jul 12 06:05:37 PM PDT 24
Finished Jul 12 06:06:59 PM PDT 24
Peak memory 211048 kb
Host smart-28d647d4-a60c-42ee-a687-a18bd920e3d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220310805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.1220310805
Directory /workspace/49.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.651249457
Short name T537
Test name
Test status
Simulation time 810668021 ps
CPU time 157.38 seconds
Started Jul 12 06:05:38 PM PDT 24
Finished Jul 12 06:08:16 PM PDT 24
Peak memory 367244 kb
Host smart-a919d080-dddb-4ba1-9958-5c4f27f59ed8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651249457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.sram_ctrl_max_throughput.651249457
Directory /workspace/49.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2605848416
Short name T30
Test name
Test status
Simulation time 4178841365 ps
CPU time 67.78 seconds
Started Jul 12 06:05:46 PM PDT 24
Finished Jul 12 06:06:54 PM PDT 24
Peak memory 210976 kb
Host smart-8e286986-1166-480b-9f0f-c057fde7cee2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605848416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.2605848416
Directory /workspace/49.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.264460902
Short name T710
Test name
Test status
Simulation time 2064093074 ps
CPU time 131.52 seconds
Started Jul 12 06:05:37 PM PDT 24
Finished Jul 12 06:07:50 PM PDT 24
Peak memory 210828 kb
Host smart-baa8b4bd-5682-4c09-b1ea-2cb78ea88b36
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264460902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl
_mem_walk.264460902
Directory /workspace/49.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.1127504529
Short name T759
Test name
Test status
Simulation time 6263127636 ps
CPU time 650.16 seconds
Started Jul 12 06:05:39 PM PDT 24
Finished Jul 12 06:16:30 PM PDT 24
Peak memory 378468 kb
Host smart-6c818846-3a3e-4f3a-8323-766fd5b26593
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127504529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.1127504529
Directory /workspace/49.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/49.sram_ctrl_partial_access.1019895841
Short name T593
Test name
Test status
Simulation time 1637104882 ps
CPU time 15.94 seconds
Started Jul 12 06:05:38 PM PDT 24
Finished Jul 12 06:05:55 PM PDT 24
Peak memory 202648 kb
Host smart-da2f6a09-4607-421c-a4ec-6571d7400af2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019895841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.1019895841
Directory /workspace/49.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.273488759
Short name T775
Test name
Test status
Simulation time 11009939994 ps
CPU time 268.51 seconds
Started Jul 12 06:05:37 PM PDT 24
Finished Jul 12 06:10:06 PM PDT 24
Peak memory 202792 kb
Host smart-596242ba-baad-43a5-ac55-859b8ccf107d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273488759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.sram_ctrl_partial_access_b2b.273488759
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.4136156005
Short name T678
Test name
Test status
Simulation time 3374019104 ps
CPU time 3.97 seconds
Started Jul 12 06:05:38 PM PDT 24
Finished Jul 12 06:05:43 PM PDT 24
Peak memory 202872 kb
Host smart-42d67b0e-1851-4df9-bc8c-b47f5d889b99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136156005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.4136156005
Directory /workspace/49.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/49.sram_ctrl_regwen.15995878
Short name T223
Test name
Test status
Simulation time 37892422437 ps
CPU time 477.27 seconds
Started Jul 12 06:05:38 PM PDT 24
Finished Jul 12 06:13:36 PM PDT 24
Peak memory 370716 kb
Host smart-87e7d6ba-bdd9-4701-ba00-924b503ac876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15995878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.15995878
Directory /workspace/49.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/49.sram_ctrl_smoke.3290149930
Short name T35
Test name
Test status
Simulation time 2412871685 ps
CPU time 61.86 seconds
Started Jul 12 06:05:36 PM PDT 24
Finished Jul 12 06:06:38 PM PDT 24
Peak memory 329636 kb
Host smart-a3188434-3992-486d-849e-51894fce43dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290149930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3290149930
Directory /workspace/49.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/49.sram_ctrl_stress_all.1910521056
Short name T267
Test name
Test status
Simulation time 277120759604 ps
CPU time 5059.66 seconds
Started Jul 12 06:05:49 PM PDT 24
Finished Jul 12 07:30:10 PM PDT 24
Peak memory 388924 kb
Host smart-ceab6586-099b-4ac9-9f13-4e21aaaa376b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910521056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.1910521056
Directory /workspace/49.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2181182831
Short name T172
Test name
Test status
Simulation time 4147097765 ps
CPU time 250.72 seconds
Started Jul 12 06:05:37 PM PDT 24
Finished Jul 12 06:09:49 PM PDT 24
Peak memory 202800 kb
Host smart-be20b79f-0b1c-44ad-9e4b-c005f79f7821
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181182831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.2181182831
Directory /workspace/49.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2635385752
Short name T567
Test name
Test status
Simulation time 2775168701 ps
CPU time 15.24 seconds
Started Jul 12 06:05:37 PM PDT 24
Finished Jul 12 06:05:53 PM PDT 24
Peak memory 238544 kb
Host smart-58bb06da-a237-4bae-b5eb-2d3e8a8d32ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635385752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2635385752
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3240363812
Short name T522
Test name
Test status
Simulation time 53594736602 ps
CPU time 539.78 seconds
Started Jul 12 06:00:38 PM PDT 24
Finished Jul 12 06:09:39 PM PDT 24
Peak memory 349088 kb
Host smart-1c5417e8-8762-4fdf-ac8d-0bf4104f5941
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240363812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.3240363812
Directory /workspace/5.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/5.sram_ctrl_alert_test.54178049
Short name T575
Test name
Test status
Simulation time 16611388 ps
CPU time 0.66 seconds
Started Jul 12 06:00:41 PM PDT 24
Finished Jul 12 06:00:43 PM PDT 24
Peak memory 202360 kb
Host smart-ea53f9e6-25e7-4e6b-a335-de641e260bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54178049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_alert_test.54178049
Directory /workspace/5.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/5.sram_ctrl_bijection.2228590690
Short name T565
Test name
Test status
Simulation time 659712161717 ps
CPU time 2619.71 seconds
Started Jul 12 06:00:50 PM PDT 24
Finished Jul 12 06:44:32 PM PDT 24
Peak memory 203316 kb
Host smart-80ef645b-54ad-42b2-8db0-6246e35f2002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228590690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
2228590690
Directory /workspace/5.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/5.sram_ctrl_executable.3278499357
Short name T480
Test name
Test status
Simulation time 26324673450 ps
CPU time 1915.4 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:32:44 PM PDT 24
Peak memory 379740 kb
Host smart-6be88486-b7d6-45f3-8e5e-3d5c70c3ad3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278499357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.3278499357
Directory /workspace/5.sram_ctrl_executable/latest


Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.397761868
Short name T827
Test name
Test status
Simulation time 8926332412 ps
CPU time 33.65 seconds
Started Jul 12 06:00:37 PM PDT 24
Finished Jul 12 06:01:12 PM PDT 24
Peak memory 211028 kb
Host smart-147a2672-e9b6-4954-bd70-0fbc47270572
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397761868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esca
lation.397761868
Directory /workspace/5.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.2088021733
Short name T938
Test name
Test status
Simulation time 1500362070 ps
CPU time 34.04 seconds
Started Jul 12 06:00:45 PM PDT 24
Finished Jul 12 06:01:19 PM PDT 24
Peak memory 284336 kb
Host smart-4e8b5e53-7b0e-4406-840a-97bd461e62e7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088021733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.2088021733
Directory /workspace/5.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3411569309
Short name T863
Test name
Test status
Simulation time 1600217558 ps
CPU time 126.55 seconds
Started Jul 12 06:00:37 PM PDT 24
Finished Jul 12 06:02:44 PM PDT 24
Peak memory 219072 kb
Host smart-92b27218-aa0e-490c-901d-17094e102ba2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411569309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.3411569309
Directory /workspace/5.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.3421322972
Short name T571
Test name
Test status
Simulation time 20682045079 ps
CPU time 365.72 seconds
Started Jul 12 06:00:37 PM PDT 24
Finished Jul 12 06:06:44 PM PDT 24
Peak memory 210900 kb
Host smart-2d27b997-fa1a-44c9-befa-a6428de7eaa5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421322972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.3421322972
Directory /workspace/5.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.1993453711
Short name T212
Test name
Test status
Simulation time 19802122357 ps
CPU time 733.16 seconds
Started Jul 12 06:00:35 PM PDT 24
Finished Jul 12 06:12:50 PM PDT 24
Peak memory 352456 kb
Host smart-76b8811c-0847-4814-a9a0-caf4a93d1e46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993453711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.1993453711
Directory /workspace/5.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/5.sram_ctrl_partial_access.1194221735
Short name T270
Test name
Test status
Simulation time 3446743551 ps
CPU time 21.35 seconds
Started Jul 12 06:00:45 PM PDT 24
Finished Jul 12 06:01:07 PM PDT 24
Peak memory 202932 kb
Host smart-6c50d5f1-37a8-4c39-a621-397b1a340c4e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194221735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.1194221735
Directory /workspace/5.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1302987136
Short name T109
Test name
Test status
Simulation time 71382173260 ps
CPU time 444.82 seconds
Started Jul 12 06:00:48 PM PDT 24
Finished Jul 12 06:08:15 PM PDT 24
Peak memory 202784 kb
Host smart-353f9edb-d2e4-49df-b7c7-1c6208a0622d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302987136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.1302987136
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.1441205246
Short name T592
Test name
Test status
Simulation time 1410243175 ps
CPU time 3.69 seconds
Started Jul 12 06:00:39 PM PDT 24
Finished Jul 12 06:00:44 PM PDT 24
Peak memory 202808 kb
Host smart-ccf03ef3-92db-4626-8412-5ba2cc26b369
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441205246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1441205246
Directory /workspace/5.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/5.sram_ctrl_regwen.2435803037
Short name T282
Test name
Test status
Simulation time 24117732079 ps
CPU time 250.49 seconds
Started Jul 12 06:00:37 PM PDT 24
Finished Jul 12 06:04:48 PM PDT 24
Peak memory 318348 kb
Host smart-68f6b542-b2d8-4280-aee3-971adff76bc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435803037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2435803037
Directory /workspace/5.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/5.sram_ctrl_smoke.2927875985
Short name T922
Test name
Test status
Simulation time 1085628194 ps
CPU time 6.31 seconds
Started Jul 12 06:00:45 PM PDT 24
Finished Jul 12 06:00:52 PM PDT 24
Peak memory 202456 kb
Host smart-894957ca-9a98-4b11-b91d-1c448c01b8d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927875985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2927875985
Directory /workspace/5.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/5.sram_ctrl_stress_all.3076043189
Short name T821
Test name
Test status
Simulation time 474026192689 ps
CPU time 6181.69 seconds
Started Jul 12 06:00:50 PM PDT 24
Finished Jul 12 07:43:54 PM PDT 24
Peak memory 380948 kb
Host smart-77cf4add-f5fe-472a-8f0d-5e4bff50a122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076043189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.3076043189
Directory /workspace/5.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3562085098
Short name T55
Test name
Test status
Simulation time 11231194994 ps
CPU time 204.65 seconds
Started Jul 12 06:00:39 PM PDT 24
Finished Jul 12 06:04:05 PM PDT 24
Peak memory 381440 kb
Host smart-b4b8a923-0486-4efe-8392-56d400a4f64c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3562085098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3562085098
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1398291063
Short name T101
Test name
Test status
Simulation time 5002070826 ps
CPU time 205.76 seconds
Started Jul 12 06:00:38 PM PDT 24
Finished Jul 12 06:04:05 PM PDT 24
Peak memory 202820 kb
Host smart-1538ac16-f5cb-4eb4-ab67-9af2ecfbd1fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398291063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.1398291063
Directory /workspace/5.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2311597942
Short name T286
Test name
Test status
Simulation time 3264703358 ps
CPU time 130.25 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:02:57 PM PDT 24
Peak memory 371396 kb
Host smart-4ace2d7e-078b-4cc1-aeae-31f91dc68b1a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311597942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2311597942
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2526088852
Short name T572
Test name
Test status
Simulation time 13379798631 ps
CPU time 1352.28 seconds
Started Jul 12 06:00:50 PM PDT 24
Finished Jul 12 06:23:24 PM PDT 24
Peak memory 377684 kb
Host smart-cefcdd4a-00a6-4272-9a42-5d17ff9b18fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526088852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.2526088852
Directory /workspace/6.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/6.sram_ctrl_alert_test.1328634477
Short name T327
Test name
Test status
Simulation time 27760293 ps
CPU time 0.68 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:00:49 PM PDT 24
Peak memory 202500 kb
Host smart-ef8e4f85-4d15-4b81-bc0e-2a83bdb0d6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328634477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.1328634477
Directory /workspace/6.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/6.sram_ctrl_bijection.3239297010
Short name T682
Test name
Test status
Simulation time 87484427332 ps
CPU time 860.2 seconds
Started Jul 12 06:00:40 PM PDT 24
Finished Jul 12 06:15:01 PM PDT 24
Peak memory 203388 kb
Host smart-cfb782f3-1e92-4e30-b04f-165665534c42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239297010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
3239297010
Directory /workspace/6.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/6.sram_ctrl_executable.2512054684
Short name T811
Test name
Test status
Simulation time 4303243271 ps
CPU time 512.61 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:09:31 PM PDT 24
Peak memory 371572 kb
Host smart-fb7688eb-b332-4abb-86cb-9e22ea152d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512054684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.2512054684
Directory /workspace/6.sram_ctrl_executable/latest


Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.1178569276
Short name T306
Test name
Test status
Simulation time 5880453745 ps
CPU time 36.62 seconds
Started Jul 12 06:00:55 PM PDT 24
Finished Jul 12 06:01:33 PM PDT 24
Peak memory 202832 kb
Host smart-b5dd68a2-7351-464d-8819-779487efb691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178569276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.1178569276
Directory /workspace/6.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.1628042110
Short name T13
Test name
Test status
Simulation time 744969013 ps
CPU time 38.15 seconds
Started Jul 12 06:00:40 PM PDT 24
Finished Jul 12 06:01:19 PM PDT 24
Peak memory 290380 kb
Host smart-46509cab-aeae-4143-8002-64377f9becfd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628042110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.1628042110
Directory /workspace/6.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1828849409
Short name T91
Test name
Test status
Simulation time 4757361265 ps
CPU time 148.01 seconds
Started Jul 12 06:00:57 PM PDT 24
Finished Jul 12 06:03:26 PM PDT 24
Peak memory 219180 kb
Host smart-5e9be3f9-d8c1-494e-bccf-f9cf3f454fa9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828849409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.1828849409
Directory /workspace/6.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3798503603
Short name T417
Test name
Test status
Simulation time 2688189985 ps
CPU time 157.95 seconds
Started Jul 12 06:00:41 PM PDT 24
Finished Jul 12 06:03:20 PM PDT 24
Peak memory 210968 kb
Host smart-45e805c7-b557-499c-875a-131d0a32c46d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798503603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3798503603
Directory /workspace/6.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.2709789012
Short name T898
Test name
Test status
Simulation time 9844345508 ps
CPU time 275.55 seconds
Started Jul 12 06:00:41 PM PDT 24
Finished Jul 12 06:05:17 PM PDT 24
Peak memory 350588 kb
Host smart-fac595b3-e7f6-4a7e-81bc-af51358b1329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709789012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.2709789012
Directory /workspace/6.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/6.sram_ctrl_partial_access.1484837438
Short name T776
Test name
Test status
Simulation time 1111926424 ps
CPU time 15.23 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:01:05 PM PDT 24
Peak memory 202096 kb
Host smart-6d98359b-a503-4c96-b000-dcb4e445f5b6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484837438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.1484837438
Directory /workspace/6.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3944803639
Short name T621
Test name
Test status
Simulation time 3723331474 ps
CPU time 148.2 seconds
Started Jul 12 06:00:55 PM PDT 24
Finished Jul 12 06:03:25 PM PDT 24
Peak memory 202828 kb
Host smart-d8cb00e3-e7d0-422d-a427-29347aa6f60b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944803639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.3944803639
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.952126265
Short name T256
Test name
Test status
Simulation time 351062743 ps
CPU time 3.42 seconds
Started Jul 12 06:00:40 PM PDT 24
Finished Jul 12 06:00:45 PM PDT 24
Peak memory 202828 kb
Host smart-7e68de77-2e91-4d96-b50e-8438685161f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952126265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.952126265
Directory /workspace/6.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/6.sram_ctrl_regwen.2193555706
Short name T297
Test name
Test status
Simulation time 15035600600 ps
CPU time 1056.67 seconds
Started Jul 12 06:00:42 PM PDT 24
Finished Jul 12 06:18:20 PM PDT 24
Peak memory 381132 kb
Host smart-4ab86e25-fd11-48fb-9c98-7c5a04eaf52a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193555706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2193555706
Directory /workspace/6.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/6.sram_ctrl_smoke.1234008520
Short name T384
Test name
Test status
Simulation time 4364416438 ps
CPU time 38.39 seconds
Started Jul 12 06:00:43 PM PDT 24
Finished Jul 12 06:01:22 PM PDT 24
Peak memory 289960 kb
Host smart-62f0fff2-2021-4e3d-8752-b1fb958cb4a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234008520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1234008520
Directory /workspace/6.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/6.sram_ctrl_stress_all.1731077004
Short name T262
Test name
Test status
Simulation time 45082218605 ps
CPU time 1451.93 seconds
Started Jul 12 06:00:43 PM PDT 24
Finished Jul 12 06:24:56 PM PDT 24
Peak memory 382752 kb
Host smart-e0f47b03-c5ae-4819-8411-67370c106f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731077004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.1731077004
Directory /workspace/6.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3792964510
Short name T113
Test name
Test status
Simulation time 2160554598 ps
CPU time 15.35 seconds
Started Jul 12 06:00:43 PM PDT 24
Finished Jul 12 06:00:59 PM PDT 24
Peak memory 211136 kb
Host smart-4a407d1e-9871-4d5b-b94d-a37ae2b2375f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3792964510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3792964510
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.1297737611
Short name T758
Test name
Test status
Simulation time 19907990408 ps
CPU time 263.54 seconds
Started Jul 12 06:00:45 PM PDT 24
Finished Jul 12 06:05:09 PM PDT 24
Peak memory 202900 kb
Host smart-a9552a49-7e83-4aa9-b51d-2a2e6aa7174a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297737611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.1297737611
Directory /workspace/6.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.992082395
Short name T158
Test name
Test status
Simulation time 3228544863 ps
CPU time 126.92 seconds
Started Jul 12 06:00:55 PM PDT 24
Finished Jul 12 06:03:03 PM PDT 24
Peak memory 361240 kb
Host smart-52f45c26-f659-478e-9c71-d784fa52b361
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992082395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.992082395
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3623276708
Short name T623
Test name
Test status
Simulation time 29804945189 ps
CPU time 453.54 seconds
Started Jul 12 06:00:45 PM PDT 24
Finished Jul 12 06:08:19 PM PDT 24
Peak memory 350008 kb
Host smart-38651e31-950c-471b-9d29-45a696614c73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623276708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.3623276708
Directory /workspace/7.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/7.sram_ctrl_alert_test.1014875913
Short name T730
Test name
Test status
Simulation time 196381602 ps
CPU time 0.68 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:00:47 PM PDT 24
Peak memory 202300 kb
Host smart-5e46789a-1f88-42b8-a91c-4d6ff08d4e56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014875913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.1014875913
Directory /workspace/7.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/7.sram_ctrl_bijection.1837600413
Short name T121
Test name
Test status
Simulation time 876991932604 ps
CPU time 2549.71 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:43:19 PM PDT 24
Peak memory 202384 kb
Host smart-d757df13-8c77-4c92-855a-72ecc9b9611b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837600413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
1837600413
Directory /workspace/7.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/7.sram_ctrl_executable.1997426892
Short name T762
Test name
Test status
Simulation time 8724799385 ps
CPU time 1867.4 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:31:57 PM PDT 24
Peak memory 377652 kb
Host smart-1737e2da-6f63-4114-b0e8-dce9df8db6b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997426892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl
e.1997426892
Directory /workspace/7.sram_ctrl_executable/latest


Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.2710316558
Short name T886
Test name
Test status
Simulation time 72069505571 ps
CPU time 100.62 seconds
Started Jul 12 06:00:42 PM PDT 24
Finished Jul 12 06:02:24 PM PDT 24
Peak memory 202776 kb
Host smart-d322d44f-c1b5-4b5d-a450-11d28290bf3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710316558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.2710316558
Directory /workspace/7.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.1294124607
Short name T288
Test name
Test status
Simulation time 2942271953 ps
CPU time 149.79 seconds
Started Jul 12 06:00:39 PM PDT 24
Finished Jul 12 06:03:10 PM PDT 24
Peak memory 367204 kb
Host smart-96db461b-a472-44d4-aa77-11db7b603446
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294124607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.1294124607
Directory /workspace/7.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2910268245
Short name T749
Test name
Test status
Simulation time 2932810071 ps
CPU time 88.04 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:02:25 PM PDT 24
Peak memory 211016 kb
Host smart-ea601265-e957-49f9-a11c-8819e9becd67
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910268245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.2910268245
Directory /workspace/7.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.178998532
Short name T51
Test name
Test status
Simulation time 5417490462 ps
CPU time 279.14 seconds
Started Jul 12 06:00:43 PM PDT 24
Finished Jul 12 06:05:23 PM PDT 24
Peak memory 202728 kb
Host smart-98be6476-e6ec-4011-aca6-060b9c32abb5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178998532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_
mem_walk.178998532
Directory /workspace/7.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.255390617
Short name T219
Test name
Test status
Simulation time 34803990075 ps
CPU time 855.47 seconds
Started Jul 12 06:00:43 PM PDT 24
Finished Jul 12 06:14:59 PM PDT 24
Peak memory 372556 kb
Host smart-611df5ae-3e01-4dcb-818a-08355d304046
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255390617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multipl
e_keys.255390617
Directory /workspace/7.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/7.sram_ctrl_partial_access.1429073600
Short name T864
Test name
Test status
Simulation time 1290821700 ps
CPU time 62.33 seconds
Started Jul 12 06:00:41 PM PDT 24
Finished Jul 12 06:01:44 PM PDT 24
Peak memory 294648 kb
Host smart-4bd985fe-b54f-4c88-b037-14abffc93969
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429073600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.1429073600
Directory /workspace/7.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.235545521
Short name T248
Test name
Test status
Simulation time 26423639902 ps
CPU time 367.46 seconds
Started Jul 12 06:04:42 PM PDT 24
Finished Jul 12 06:10:50 PM PDT 24
Peak memory 202764 kb
Host smart-f8dfe87f-cad7-4ffe-882b-6aa0614c8741
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235545521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.sram_ctrl_partial_access_b2b.235545521
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3026959256
Short name T645
Test name
Test status
Simulation time 1401669679 ps
CPU time 3.47 seconds
Started Jul 12 06:00:42 PM PDT 24
Finished Jul 12 06:00:46 PM PDT 24
Peak memory 202732 kb
Host smart-9d62ef90-025b-4ac7-8e41-941c79ff3546
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026959256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3026959256
Directory /workspace/7.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/7.sram_ctrl_regwen.1145127512
Short name T353
Test name
Test status
Simulation time 18647415350 ps
CPU time 1379.16 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:23:57 PM PDT 24
Peak memory 379720 kb
Host smart-beb562ce-52a2-4c20-9bff-0a8e9ed7e6f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145127512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1145127512
Directory /workspace/7.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/7.sram_ctrl_smoke.2125383488
Short name T838
Test name
Test status
Simulation time 1758370247 ps
CPU time 7.54 seconds
Started Jul 12 06:00:40 PM PDT 24
Finished Jul 12 06:00:48 PM PDT 24
Peak memory 219116 kb
Host smart-5050e699-ca94-4b33-9915-a496a4f92948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125383488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2125383488
Directory /workspace/7.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/7.sram_ctrl_stress_all.457897535
Short name T904
Test name
Test status
Simulation time 1365786505189 ps
CPU time 4603.75 seconds
Started Jul 12 06:00:55 PM PDT 24
Finished Jul 12 07:17:41 PM PDT 24
Peak memory 380768 kb
Host smart-fbfbc868-7568-4c03-955c-984e7dbc4cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457897535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_stress_all.457897535
Directory /workspace/7.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3270365993
Short name T112
Test name
Test status
Simulation time 15041962876 ps
CPU time 82.87 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:02:20 PM PDT 24
Peak memory 314344 kb
Host smart-4f8714c6-b4d1-4c7b-9674-b61ad58c4474
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3270365993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3270365993
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.4112235700
Short name T235
Test name
Test status
Simulation time 4832395879 ps
CPU time 246.22 seconds
Started Jul 12 06:00:56 PM PDT 24
Finished Jul 12 06:05:04 PM PDT 24
Peak memory 202768 kb
Host smart-250f11af-7901-4832-b55a-15293b68bbda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112235700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.4112235700
Directory /workspace/7.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2520581090
Short name T523
Test name
Test status
Simulation time 12706162369 ps
CPU time 82.41 seconds
Started Jul 12 06:00:42 PM PDT 24
Finished Jul 12 06:02:05 PM PDT 24
Peak memory 345712 kb
Host smart-dfd901ad-a23e-49b5-906d-8fd3dcb5411a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520581090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2520581090
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.267375252
Short name T837
Test name
Test status
Simulation time 300405351575 ps
CPU time 914.83 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:16:03 PM PDT 24
Peak memory 367732 kb
Host smart-d1bcdf80-7a93-4734-8776-c6f9cfcb5443
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267375252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.sram_ctrl_access_during_key_req.267375252
Directory /workspace/8.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/8.sram_ctrl_alert_test.646318212
Short name T806
Test name
Test status
Simulation time 11256704 ps
CPU time 0.65 seconds
Started Jul 12 06:00:51 PM PDT 24
Finished Jul 12 06:00:53 PM PDT 24
Peak memory 202324 kb
Host smart-d90f1a14-9bf1-493a-9cb6-339d4031bf39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646318212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.646318212
Directory /workspace/8.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/8.sram_ctrl_bijection.933099592
Short name T926
Test name
Test status
Simulation time 21528792917 ps
CPU time 1525.58 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:26:14 PM PDT 24
Peak memory 203580 kb
Host smart-144eba94-88bc-4466-acda-b61a7deecc46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933099592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.933099592
Directory /workspace/8.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.1256082345
Short name T924
Test name
Test status
Simulation time 7303279560 ps
CPU time 44.06 seconds
Started Jul 12 06:00:52 PM PDT 24
Finished Jul 12 06:01:37 PM PDT 24
Peak memory 215840 kb
Host smart-1724ce54-c986-47b3-ab22-ef9825f17e25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256082345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.1256082345
Directory /workspace/8.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.1464082083
Short name T549
Test name
Test status
Simulation time 730006625 ps
CPU time 36.67 seconds
Started Jul 12 06:00:49 PM PDT 24
Finished Jul 12 06:01:27 PM PDT 24
Peak memory 284508 kb
Host smart-76d1d1a5-c5b1-40f5-94b7-afc27a7b198a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464082083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.1464082083
Directory /workspace/8.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.575137088
Short name T34
Test name
Test status
Simulation time 10208056624 ps
CPU time 156.41 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:03:26 PM PDT 24
Peak memory 210992 kb
Host smart-9ecae7aa-4e02-4a29-8b14-c15471aefef9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575137088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
sram_ctrl_mem_partial_access.575137088
Directory /workspace/8.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.1705090042
Short name T490
Test name
Test status
Simulation time 149592395138 ps
CPU time 214.43 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:04:23 PM PDT 24
Peak memory 210968 kb
Host smart-555cf6c7-9d7e-4b62-8c3b-f8d6d6b73668
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705090042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.1705090042
Directory /workspace/8.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.2419640318
Short name T651
Test name
Test status
Simulation time 9095441572 ps
CPU time 432.4 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:08:01 PM PDT 24
Peak memory 371508 kb
Host smart-4c7adc17-9e71-4402-8c76-7146c6e15271
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419640318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.2419640318
Directory /workspace/8.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/8.sram_ctrl_partial_access.390933339
Short name T475
Test name
Test status
Simulation time 1863305166 ps
CPU time 25.23 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:01:15 PM PDT 24
Peak memory 202636 kb
Host smart-7f3982af-279a-43b1-988d-eef71f9f69a8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390933339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr
am_ctrl_partial_access.390933339
Directory /workspace/8.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2533617364
Short name T36
Test name
Test status
Simulation time 306418512543 ps
CPU time 563.76 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:10:12 PM PDT 24
Peak memory 202796 kb
Host smart-6e4398ca-aa26-4468-a18f-08ab15061b60
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533617364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.2533617364
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.1390400419
Short name T779
Test name
Test status
Simulation time 361526254 ps
CPU time 3.27 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:00:53 PM PDT 24
Peak memory 202784 kb
Host smart-465efa18-b536-4ab9-b008-3d2d0c50d773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390400419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1390400419
Directory /workspace/8.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/8.sram_ctrl_regwen.3345982281
Short name T72
Test name
Test status
Simulation time 89070079375 ps
CPU time 317.57 seconds
Started Jul 12 06:00:48 PM PDT 24
Finished Jul 12 06:06:08 PM PDT 24
Peak memory 323760 kb
Host smart-91f3b22a-d0b5-499a-a8d2-f1281c40a7b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345982281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3345982281
Directory /workspace/8.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/8.sram_ctrl_smoke.1185393632
Short name T431
Test name
Test status
Simulation time 5897303123 ps
CPU time 21.57 seconds
Started Jul 12 06:00:51 PM PDT 24
Finished Jul 12 06:01:14 PM PDT 24
Peak memory 202788 kb
Host smart-e7cbb947-3fd8-4ca2-8d42-3483a68e7fd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185393632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1185393632
Directory /workspace/8.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/8.sram_ctrl_stress_all.291114425
Short name T227
Test name
Test status
Simulation time 399188828133 ps
CPU time 8660.98 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 08:25:10 PM PDT 24
Peak memory 386908 kb
Host smart-43ce97d0-e0ab-4949-a31f-91018d51ff53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291114425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_stress_all.291114425
Directory /workspace/8.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3342502396
Short name T65
Test name
Test status
Simulation time 345529744 ps
CPU time 17.08 seconds
Started Jul 12 06:01:00 PM PDT 24
Finished Jul 12 06:01:19 PM PDT 24
Peak memory 211028 kb
Host smart-6c66d7aa-eb9f-4c29-ae64-1feff74177cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3342502396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3342502396
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2154217377
Short name T531
Test name
Test status
Simulation time 8660474143 ps
CPU time 309.01 seconds
Started Jul 12 06:00:52 PM PDT 24
Finished Jul 12 06:06:02 PM PDT 24
Peak memory 202856 kb
Host smart-83bb46cf-e1ea-45f4-9a8a-232371bfcd7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154217377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2154217377
Directory /workspace/8.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2749840920
Short name T896
Test name
Test status
Simulation time 781092585 ps
CPU time 89.71 seconds
Started Jul 12 06:00:49 PM PDT 24
Finished Jul 12 06:02:21 PM PDT 24
Peak memory 354964 kb
Host smart-a6d5b978-6336-4437-909b-8b0f200fdbb2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749840920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2749840920
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest


Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2099848473
Short name T809
Test name
Test status
Simulation time 87285453107 ps
CPU time 706.63 seconds
Started Jul 12 06:00:50 PM PDT 24
Finished Jul 12 06:12:38 PM PDT 24
Peak memory 377660 kb
Host smart-033ce0c0-fb2f-405f-9d03-5714c3140c73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099848473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.2099848473
Directory /workspace/9.sram_ctrl_access_during_key_req/latest


Test location /workspace/coverage/default/9.sram_ctrl_alert_test.1619351058
Short name T721
Test name
Test status
Simulation time 43484847 ps
CPU time 0.68 seconds
Started Jul 12 06:00:52 PM PDT 24
Finished Jul 12 06:00:54 PM PDT 24
Peak memory 202516 kb
Host smart-69b773b3-522d-4ccc-a9d3-04dda9a9e991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619351058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.1619351058
Directory /workspace/9.sram_ctrl_alert_test/latest


Test location /workspace/coverage/default/9.sram_ctrl_bijection.2206830289
Short name T187
Test name
Test status
Simulation time 50024615304 ps
CPU time 790.7 seconds
Started Jul 12 06:00:50 PM PDT 24
Finished Jul 12 06:14:02 PM PDT 24
Peak memory 203380 kb
Host smart-8f7de86a-b235-41f0-a2f7-adda1518e272
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206830289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
2206830289
Directory /workspace/9.sram_ctrl_bijection/latest


Test location /workspace/coverage/default/9.sram_ctrl_executable.1968881276
Short name T468
Test name
Test status
Simulation time 12553503540 ps
CPU time 844.96 seconds
Started Jul 12 06:00:49 PM PDT 24
Finished Jul 12 06:14:56 PM PDT 24
Peak memory 378676 kb
Host smart-eeb77883-0644-40a7-9d6f-112706b5990f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968881276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.1968881276
Directory /workspace/9.sram_ctrl_executable/latest


Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.3929908511
Short name T117
Test name
Test status
Simulation time 2820176070 ps
CPU time 15.77 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:01:03 PM PDT 24
Peak memory 202828 kb
Host smart-08479305-33c4-473c-8925-bd6bf9e94529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929908511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.3929908511
Directory /workspace/9.sram_ctrl_lc_escalation/latest


Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.1302086639
Short name T577
Test name
Test status
Simulation time 739949145 ps
CPU time 17.72 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:01:07 PM PDT 24
Peak memory 252828 kb
Host smart-4b3abd13-7561-49b3-8345-ce337840ddcb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302086639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.1302086639
Directory /workspace/9.sram_ctrl_max_throughput/latest


Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.4061262701
Short name T769
Test name
Test status
Simulation time 4829812205 ps
CPU time 77.68 seconds
Started Jul 12 06:00:48 PM PDT 24
Finished Jul 12 06:02:07 PM PDT 24
Peak memory 211016 kb
Host smart-33f76474-2eb9-4a65-ba59-5c656ade6786
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061262701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.4061262701
Directory /workspace/9.sram_ctrl_mem_partial_access/latest


Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.1164908044
Short name T600
Test name
Test status
Simulation time 90017521736 ps
CPU time 333.37 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:06:23 PM PDT 24
Peak memory 211140 kb
Host smart-eab67ea4-ad72-4a74-8fd1-c6fbd2f62eb8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164908044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.1164908044
Directory /workspace/9.sram_ctrl_mem_walk/latest


Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.58385078
Short name T732
Test name
Test status
Simulation time 22211458765 ps
CPU time 243.99 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:04:51 PM PDT 24
Peak memory 323124 kb
Host smart-0368e725-83f3-4dc5-96b4-11eee1fbe80d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58385078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple
_keys.58385078
Directory /workspace/9.sram_ctrl_multiple_keys/latest


Test location /workspace/coverage/default/9.sram_ctrl_partial_access.1161831987
Short name T230
Test name
Test status
Simulation time 1749028893 ps
CPU time 151.94 seconds
Started Jul 12 06:00:44 PM PDT 24
Finished Jul 12 06:03:17 PM PDT 24
Peak memory 369260 kb
Host smart-b09d9b14-9a45-47ff-ad36-d1d53dcb23b3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161831987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.1161831987
Directory /workspace/9.sram_ctrl_partial_access/latest


Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2091333542
Short name T260
Test name
Test status
Simulation time 19841063765 ps
CPU time 413.85 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:07:41 PM PDT 24
Peak memory 202768 kb
Host smart-9c68896c-c491-436a-88c3-dca3d2b8537d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091333542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.2091333542
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest


Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.351803739
Short name T780
Test name
Test status
Simulation time 349159430 ps
CPU time 3.26 seconds
Started Jul 12 06:00:48 PM PDT 24
Finished Jul 12 06:00:54 PM PDT 24
Peak memory 203020 kb
Host smart-b8a7d5be-47d7-4dae-9035-1fd19905e6aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351803739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.351803739
Directory /workspace/9.sram_ctrl_ram_cfg/latest


Test location /workspace/coverage/default/9.sram_ctrl_regwen.529668317
Short name T443
Test name
Test status
Simulation time 6123615713 ps
CPU time 116.45 seconds
Started Jul 12 06:00:48 PM PDT 24
Finished Jul 12 06:02:46 PM PDT 24
Peak memory 328896 kb
Host smart-3c9c1b77-5ac5-4a32-913e-c870a3c7eb85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529668317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.529668317
Directory /workspace/9.sram_ctrl_regwen/latest


Test location /workspace/coverage/default/9.sram_ctrl_smoke.1308482542
Short name T589
Test name
Test status
Simulation time 2997049338 ps
CPU time 19.56 seconds
Started Jul 12 06:00:47 PM PDT 24
Finished Jul 12 06:01:09 PM PDT 24
Peak memory 202832 kb
Host smart-b7c653f7-f71e-4eb0-8739-97b8ab045a12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308482542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1308482542
Directory /workspace/9.sram_ctrl_smoke/latest


Test location /workspace/coverage/default/9.sram_ctrl_stress_all.776008395
Short name T822
Test name
Test status
Simulation time 116272798147 ps
CPU time 4523.89 seconds
Started Jul 12 06:00:48 PM PDT 24
Finished Jul 12 07:16:15 PM PDT 24
Peak memory 397548 kb
Host smart-0654e54a-9081-419b-9457-35689fb77cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776008395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_stress_all.776008395
Directory /workspace/9.sram_ctrl_stress_all/latest


Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1978641121
Short name T54
Test name
Test status
Simulation time 17823413120 ps
CPU time 379.4 seconds
Started Jul 12 06:00:46 PM PDT 24
Finished Jul 12 06:07:08 PM PDT 24
Peak memory 354200 kb
Host smart-3e8952b1-6ec2-4e56-8faf-d11c51c331f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1978641121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1978641121
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1795567233
Short name T879
Test name
Test status
Simulation time 3902436256 ps
CPU time 218.24 seconds
Started Jul 12 06:00:51 PM PDT 24
Finished Jul 12 06:04:30 PM PDT 24
Peak memory 202780 kb
Host smart-b36e170d-95dd-430f-b0d0-9d545ced3b50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795567233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.1795567233
Directory /workspace/9.sram_ctrl_stress_pipeline/latest


Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3674143551
Short name T207
Test name
Test status
Simulation time 3868614449 ps
CPU time 142.11 seconds
Started Jul 12 06:00:55 PM PDT 24
Finished Jul 12 06:03:18 PM PDT 24
Peak memory 361188 kb
Host smart-083a2518-d50e-406f-addf-9348bd30cce9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674143551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3674143551
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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