| T793 |
/workspace/coverage/default/40.sram_ctrl_partial_access.695123703 |
|
|
Jul 15 06:19:27 PM PDT 24 |
Jul 15 06:19:40 PM PDT 24 |
978233649 ps |
| T794 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3143501209 |
|
|
Jul 15 06:19:51 PM PDT 24 |
Jul 15 06:22:35 PM PDT 24 |
10664221771 ps |
| T795 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3774705681 |
|
|
Jul 15 06:16:57 PM PDT 24 |
Jul 15 06:20:40 PM PDT 24 |
4029042638 ps |
| T796 |
/workspace/coverage/default/36.sram_ctrl_bijection.1171489699 |
|
|
Jul 15 06:18:32 PM PDT 24 |
Jul 15 06:51:52 PM PDT 24 |
28438680522 ps |
| T797 |
/workspace/coverage/default/46.sram_ctrl_bijection.45248983 |
|
|
Jul 15 06:20:14 PM PDT 24 |
Jul 15 07:00:59 PM PDT 24 |
689902217531 ps |
| T798 |
/workspace/coverage/default/6.sram_ctrl_regwen.2860164597 |
|
|
Jul 15 06:15:43 PM PDT 24 |
Jul 15 06:16:19 PM PDT 24 |
9790963687 ps |
| T799 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2902690345 |
|
|
Jul 15 06:15:34 PM PDT 24 |
Jul 15 06:18:53 PM PDT 24 |
3173703295 ps |
| T800 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.3327653420 |
|
|
Jul 15 06:16:52 PM PDT 24 |
Jul 15 06:30:45 PM PDT 24 |
38305035564 ps |
| T801 |
/workspace/coverage/default/4.sram_ctrl_bijection.4104927961 |
|
|
Jul 15 06:15:40 PM PDT 24 |
Jul 15 06:28:13 PM PDT 24 |
64917001303 ps |
| T802 |
/workspace/coverage/default/36.sram_ctrl_smoke.992386810 |
|
|
Jul 15 06:18:30 PM PDT 24 |
Jul 15 06:18:38 PM PDT 24 |
849808275 ps |
| T803 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.678410585 |
|
|
Jul 15 06:16:43 PM PDT 24 |
Jul 15 06:22:33 PM PDT 24 |
10146516317 ps |
| T804 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1685572665 |
|
|
Jul 15 06:15:33 PM PDT 24 |
Jul 15 06:15:43 PM PDT 24 |
1742882689 ps |
| T805 |
/workspace/coverage/default/28.sram_ctrl_bijection.3590788455 |
|
|
Jul 15 06:17:32 PM PDT 24 |
Jul 15 06:47:30 PM PDT 24 |
307264468344 ps |
| T806 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2916546629 |
|
|
Jul 15 06:19:22 PM PDT 24 |
Jul 15 06:27:10 PM PDT 24 |
21393823675 ps |
| T807 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.63586304 |
|
|
Jul 15 06:15:33 PM PDT 24 |
Jul 15 06:20:53 PM PDT 24 |
17985758421 ps |
| T808 |
/workspace/coverage/default/25.sram_ctrl_smoke.169966306 |
|
|
Jul 15 06:17:10 PM PDT 24 |
Jul 15 06:17:27 PM PDT 24 |
531569174 ps |
| T809 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.289845807 |
|
|
Jul 15 06:15:48 PM PDT 24 |
Jul 15 06:18:33 PM PDT 24 |
52561752891 ps |
| T810 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1541733141 |
|
|
Jul 15 06:15:30 PM PDT 24 |
Jul 15 06:22:57 PM PDT 24 |
8415870980 ps |
| T811 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.870623086 |
|
|
Jul 15 06:17:38 PM PDT 24 |
Jul 15 06:20:22 PM PDT 24 |
11008270438 ps |
| T812 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.4274233637 |
|
|
Jul 15 06:16:45 PM PDT 24 |
Jul 15 06:38:24 PM PDT 24 |
77227233481 ps |
| T813 |
/workspace/coverage/default/22.sram_ctrl_stress_all.1121376841 |
|
|
Jul 15 06:16:56 PM PDT 24 |
Jul 15 07:41:43 PM PDT 24 |
38196106688 ps |
| T814 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2916210088 |
|
|
Jul 15 06:18:14 PM PDT 24 |
Jul 15 06:53:02 PM PDT 24 |
291503346471 ps |
| T815 |
/workspace/coverage/default/29.sram_ctrl_regwen.1618324400 |
|
|
Jul 15 06:17:43 PM PDT 24 |
Jul 15 06:23:08 PM PDT 24 |
19491280023 ps |
| T816 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.995815276 |
|
|
Jul 15 06:16:42 PM PDT 24 |
Jul 15 06:17:04 PM PDT 24 |
767410601 ps |
| T817 |
/workspace/coverage/default/29.sram_ctrl_smoke.1626632596 |
|
|
Jul 15 06:17:39 PM PDT 24 |
Jul 15 06:18:22 PM PDT 24 |
2891836808 ps |
| T818 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4285996931 |
|
|
Jul 15 06:15:58 PM PDT 24 |
Jul 15 06:16:48 PM PDT 24 |
4043589969 ps |
| T819 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.4108868558 |
|
|
Jul 15 06:16:05 PM PDT 24 |
Jul 15 06:18:09 PM PDT 24 |
845597323 ps |
| T820 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.365809935 |
|
|
Jul 15 06:15:59 PM PDT 24 |
Jul 15 06:16:44 PM PDT 24 |
1626934813 ps |
| T821 |
/workspace/coverage/default/19.sram_ctrl_bijection.3394187803 |
|
|
Jul 15 06:16:29 PM PDT 24 |
Jul 15 06:39:25 PM PDT 24 |
20014427529 ps |
| T822 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3761557488 |
|
|
Jul 15 06:18:10 PM PDT 24 |
Jul 15 06:18:11 PM PDT 24 |
13365584 ps |
| T823 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3071254813 |
|
|
Jul 15 06:15:34 PM PDT 24 |
Jul 15 06:17:13 PM PDT 24 |
62632442350 ps |
| T824 |
/workspace/coverage/default/23.sram_ctrl_regwen.312431820 |
|
|
Jul 15 06:16:57 PM PDT 24 |
Jul 15 06:33:47 PM PDT 24 |
11455756863 ps |
| T825 |
/workspace/coverage/default/13.sram_ctrl_bijection.916689073 |
|
|
Jul 15 06:16:02 PM PDT 24 |
Jul 15 06:49:37 PM PDT 24 |
28084712778 ps |
| T826 |
/workspace/coverage/default/24.sram_ctrl_executable.275011520 |
|
|
Jul 15 06:17:05 PM PDT 24 |
Jul 15 06:41:04 PM PDT 24 |
43850869081 ps |
| T827 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2588707243 |
|
|
Jul 15 06:16:06 PM PDT 24 |
Jul 15 06:16:10 PM PDT 24 |
346407630 ps |
| T828 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.4003510125 |
|
|
Jul 15 06:16:18 PM PDT 24 |
Jul 15 06:21:21 PM PDT 24 |
28244933867 ps |
| T829 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3675129092 |
|
|
Jul 15 06:18:44 PM PDT 24 |
Jul 15 06:23:09 PM PDT 24 |
54705342229 ps |
| T830 |
/workspace/coverage/default/1.sram_ctrl_bijection.3338966020 |
|
|
Jul 15 06:15:27 PM PDT 24 |
Jul 15 06:47:25 PM PDT 24 |
279727679271 ps |
| T831 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1650666220 |
|
|
Jul 15 06:16:51 PM PDT 24 |
Jul 15 06:17:09 PM PDT 24 |
1072894316 ps |
| T832 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.3401289199 |
|
|
Jul 15 06:19:23 PM PDT 24 |
Jul 15 06:20:21 PM PDT 24 |
1518485427 ps |
| T833 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2310034299 |
|
|
Jul 15 06:17:48 PM PDT 24 |
Jul 15 06:30:27 PM PDT 24 |
10500837037 ps |
| T834 |
/workspace/coverage/default/0.sram_ctrl_regwen.3110136101 |
|
|
Jul 15 06:15:27 PM PDT 24 |
Jul 15 06:25:06 PM PDT 24 |
9420856384 ps |
| T835 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.453305110 |
|
|
Jul 15 06:16:07 PM PDT 24 |
Jul 15 06:17:39 PM PDT 24 |
1996631452 ps |
| T836 |
/workspace/coverage/default/23.sram_ctrl_stress_all.4266551516 |
|
|
Jul 15 06:17:05 PM PDT 24 |
Jul 15 07:07:07 PM PDT 24 |
45858714103 ps |
| T837 |
/workspace/coverage/default/46.sram_ctrl_regwen.2154357689 |
|
|
Jul 15 06:20:20 PM PDT 24 |
Jul 15 06:41:13 PM PDT 24 |
90930714976 ps |
| T838 |
/workspace/coverage/default/23.sram_ctrl_alert_test.277511943 |
|
|
Jul 15 06:17:07 PM PDT 24 |
Jul 15 06:17:08 PM PDT 24 |
34888324 ps |
| T839 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1106248632 |
|
|
Jul 15 06:17:34 PM PDT 24 |
Jul 15 06:35:56 PM PDT 24 |
14779918475 ps |
| T840 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3593413378 |
|
|
Jul 15 06:17:02 PM PDT 24 |
Jul 15 06:17:10 PM PDT 24 |
712524276 ps |
| T841 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4058640606 |
|
|
Jul 15 06:15:22 PM PDT 24 |
Jul 15 06:16:01 PM PDT 24 |
1874260561 ps |
| T842 |
/workspace/coverage/default/21.sram_ctrl_bijection.307373685 |
|
|
Jul 15 06:16:41 PM PDT 24 |
Jul 15 07:06:25 PM PDT 24 |
177855704673 ps |
| T843 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.751410176 |
|
|
Jul 15 06:18:02 PM PDT 24 |
Jul 15 06:21:15 PM PDT 24 |
37429393905 ps |
| T844 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.279711278 |
|
|
Jul 15 06:17:56 PM PDT 24 |
Jul 15 06:19:08 PM PDT 24 |
10776139375 ps |
| T845 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.1614583496 |
|
|
Jul 15 06:15:31 PM PDT 24 |
Jul 15 06:19:28 PM PDT 24 |
63757633811 ps |
| T846 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.552542260 |
|
|
Jul 15 06:15:51 PM PDT 24 |
Jul 15 06:16:22 PM PDT 24 |
2001663550 ps |
| T847 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1467984479 |
|
|
Jul 15 06:16:02 PM PDT 24 |
Jul 15 06:16:25 PM PDT 24 |
6041326964 ps |
| T848 |
/workspace/coverage/default/8.sram_ctrl_bijection.4076083151 |
|
|
Jul 15 06:15:47 PM PDT 24 |
Jul 15 06:47:30 PM PDT 24 |
26832955522 ps |
| T849 |
/workspace/coverage/default/34.sram_ctrl_alert_test.1599229177 |
|
|
Jul 15 06:18:16 PM PDT 24 |
Jul 15 06:18:17 PM PDT 24 |
21774507 ps |
| T850 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2080391257 |
|
|
Jul 15 06:17:22 PM PDT 24 |
Jul 15 06:21:39 PM PDT 24 |
9688671447 ps |
| T851 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.925736809 |
|
|
Jul 15 06:20:13 PM PDT 24 |
Jul 15 06:21:13 PM PDT 24 |
2764221179 ps |
| T852 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1622882217 |
|
|
Jul 15 06:17:57 PM PDT 24 |
Jul 15 06:18:13 PM PDT 24 |
1452973813 ps |
| T853 |
/workspace/coverage/default/9.sram_ctrl_smoke.3296994776 |
|
|
Jul 15 06:15:51 PM PDT 24 |
Jul 15 06:17:41 PM PDT 24 |
1067780915 ps |
| T854 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.2646735227 |
|
|
Jul 15 06:16:43 PM PDT 24 |
Jul 15 06:19:42 PM PDT 24 |
103569719907 ps |
| T855 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.553435835 |
|
|
Jul 15 06:18:00 PM PDT 24 |
Jul 15 06:19:11 PM PDT 24 |
11512616342 ps |
| T856 |
/workspace/coverage/default/32.sram_ctrl_executable.754373850 |
|
|
Jul 15 06:18:03 PM PDT 24 |
Jul 15 06:47:23 PM PDT 24 |
25088382362 ps |
| T857 |
/workspace/coverage/default/48.sram_ctrl_smoke.3162496665 |
|
|
Jul 15 06:20:31 PM PDT 24 |
Jul 15 06:20:38 PM PDT 24 |
671655580 ps |
| T858 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.224420360 |
|
|
Jul 15 06:19:56 PM PDT 24 |
Jul 15 06:32:10 PM PDT 24 |
18208826278 ps |
| T859 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3283920612 |
|
|
Jul 15 06:15:25 PM PDT 24 |
Jul 15 06:21:45 PM PDT 24 |
10941339149 ps |
| T860 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2014579303 |
|
|
Jul 15 06:16:17 PM PDT 24 |
Jul 15 06:16:52 PM PDT 24 |
9820495658 ps |
| T861 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.500950350 |
|
|
Jul 15 06:16:07 PM PDT 24 |
Jul 15 06:20:19 PM PDT 24 |
4122961876 ps |
| T862 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2834313214 |
|
|
Jul 15 06:19:51 PM PDT 24 |
Jul 15 06:19:56 PM PDT 24 |
1366874859 ps |
| T863 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.1768396980 |
|
|
Jul 15 06:17:56 PM PDT 24 |
Jul 15 06:26:38 PM PDT 24 |
25758022697 ps |
| T864 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1754612578 |
|
|
Jul 15 06:19:54 PM PDT 24 |
Jul 15 06:19:58 PM PDT 24 |
360231580 ps |
| T865 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.3053866304 |
|
|
Jul 15 06:16:44 PM PDT 24 |
Jul 15 06:19:15 PM PDT 24 |
27146908609 ps |
| T866 |
/workspace/coverage/default/17.sram_ctrl_smoke.2876924951 |
|
|
Jul 15 06:16:16 PM PDT 24 |
Jul 15 06:16:31 PM PDT 24 |
525800204 ps |
| T867 |
/workspace/coverage/default/7.sram_ctrl_bijection.2519800523 |
|
|
Jul 15 06:15:46 PM PDT 24 |
Jul 15 06:27:05 PM PDT 24 |
44292476699 ps |
| T868 |
/workspace/coverage/default/49.sram_ctrl_bijection.2741330629 |
|
|
Jul 15 06:20:43 PM PDT 24 |
Jul 15 06:50:12 PM PDT 24 |
461510736483 ps |
| T869 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3840627038 |
|
|
Jul 15 06:20:34 PM PDT 24 |
Jul 15 06:42:17 PM PDT 24 |
74565337834 ps |
| T870 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.857218590 |
|
|
Jul 15 06:16:10 PM PDT 24 |
Jul 15 06:18:28 PM PDT 24 |
1080430342 ps |
| T871 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1609175047 |
|
|
Jul 15 06:20:20 PM PDT 24 |
Jul 15 06:21:03 PM PDT 24 |
6177873775 ps |
| T872 |
/workspace/coverage/default/10.sram_ctrl_smoke.239928886 |
|
|
Jul 15 06:15:56 PM PDT 24 |
Jul 15 06:16:54 PM PDT 24 |
9486044683 ps |
| T873 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3375833343 |
|
|
Jul 15 06:15:53 PM PDT 24 |
Jul 15 06:17:26 PM PDT 24 |
778059368 ps |
| T874 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2491924360 |
|
|
Jul 15 06:16:08 PM PDT 24 |
Jul 15 06:18:52 PM PDT 24 |
2920299512 ps |
| T875 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2196642693 |
|
|
Jul 15 06:20:24 PM PDT 24 |
Jul 15 06:26:44 PM PDT 24 |
46486173015 ps |
| T876 |
/workspace/coverage/default/41.sram_ctrl_executable.2391931504 |
|
|
Jul 15 06:19:37 PM PDT 24 |
Jul 15 06:20:11 PM PDT 24 |
2418090932 ps |
| T877 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3254343733 |
|
|
Jul 15 06:15:56 PM PDT 24 |
Jul 15 06:16:44 PM PDT 24 |
3478734027 ps |
| T878 |
/workspace/coverage/default/3.sram_ctrl_executable.2877756602 |
|
|
Jul 15 06:15:35 PM PDT 24 |
Jul 15 06:28:07 PM PDT 24 |
11924170297 ps |
| T879 |
/workspace/coverage/default/38.sram_ctrl_executable.3520440116 |
|
|
Jul 15 06:19:09 PM PDT 24 |
Jul 15 06:37:50 PM PDT 24 |
54149028965 ps |
| T880 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.810834082 |
|
|
Jul 15 06:16:56 PM PDT 24 |
Jul 15 06:18:38 PM PDT 24 |
2291838077 ps |
| T881 |
/workspace/coverage/default/23.sram_ctrl_smoke.3769254838 |
|
|
Jul 15 06:16:59 PM PDT 24 |
Jul 15 06:17:18 PM PDT 24 |
3739490814 ps |
| T882 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3612490794 |
|
|
Jul 15 06:16:02 PM PDT 24 |
Jul 15 06:16:04 PM PDT 24 |
51361406 ps |
| T883 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.1873040023 |
|
|
Jul 15 06:19:06 PM PDT 24 |
Jul 15 06:19:12 PM PDT 24 |
1527251970 ps |
| T884 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.934284742 |
|
|
Jul 15 06:16:54 PM PDT 24 |
Jul 15 06:17:32 PM PDT 24 |
770799458 ps |
| T885 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1039887164 |
|
|
Jul 15 06:15:38 PM PDT 24 |
Jul 15 06:18:11 PM PDT 24 |
13136612754 ps |
| T886 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2449298447 |
|
|
Jul 15 06:17:48 PM PDT 24 |
Jul 15 06:20:19 PM PDT 24 |
1577555409 ps |
| T887 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1131284723 |
|
|
Jul 15 06:15:25 PM PDT 24 |
Jul 15 06:18:37 PM PDT 24 |
13969971698 ps |
| T888 |
/workspace/coverage/default/32.sram_ctrl_alert_test.1700431198 |
|
|
Jul 15 06:18:02 PM PDT 24 |
Jul 15 06:18:03 PM PDT 24 |
40147838 ps |
| T889 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3870424050 |
|
|
Jul 15 06:15:37 PM PDT 24 |
Jul 15 06:15:41 PM PDT 24 |
1461850045 ps |
| T890 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.259529629 |
|
|
Jul 15 06:15:31 PM PDT 24 |
Jul 15 06:25:21 PM PDT 24 |
17125238572 ps |
| T891 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1383005181 |
|
|
Jul 15 06:17:04 PM PDT 24 |
Jul 15 06:24:48 PM PDT 24 |
7207680600 ps |
| T892 |
/workspace/coverage/default/38.sram_ctrl_partial_access.3914539010 |
|
|
Jul 15 06:19:00 PM PDT 24 |
Jul 15 06:19:24 PM PDT 24 |
3242791987 ps |
| T893 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3135899981 |
|
|
Jul 15 06:16:09 PM PDT 24 |
Jul 15 06:16:11 PM PDT 24 |
34665208 ps |
| T894 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.3599169764 |
|
|
Jul 15 06:17:04 PM PDT 24 |
Jul 15 06:18:32 PM PDT 24 |
1783398747 ps |
| T895 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3748428655 |
|
|
Jul 15 06:16:53 PM PDT 24 |
Jul 15 06:17:06 PM PDT 24 |
1370934155 ps |
| T896 |
/workspace/coverage/default/20.sram_ctrl_alert_test.291761589 |
|
|
Jul 15 06:16:43 PM PDT 24 |
Jul 15 06:16:45 PM PDT 24 |
22448443 ps |
| T897 |
/workspace/coverage/default/25.sram_ctrl_stress_all.1891569659 |
|
|
Jul 15 06:17:23 PM PDT 24 |
Jul 15 07:28:10 PM PDT 24 |
102171032543 ps |
| T898 |
/workspace/coverage/default/24.sram_ctrl_partial_access.998468726 |
|
|
Jul 15 06:17:03 PM PDT 24 |
Jul 15 06:17:19 PM PDT 24 |
840603043 ps |
| T899 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.346353103 |
|
|
Jul 15 06:20:32 PM PDT 24 |
Jul 15 06:27:19 PM PDT 24 |
35526955724 ps |
| T900 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2885502382 |
|
|
Jul 15 06:20:52 PM PDT 24 |
Jul 15 07:45:08 PM PDT 24 |
244349074140 ps |
| T901 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.195323139 |
|
|
Jul 15 06:19:51 PM PDT 24 |
Jul 15 06:21:57 PM PDT 24 |
7897783909 ps |
| T902 |
/workspace/coverage/default/33.sram_ctrl_regwen.3613601945 |
|
|
Jul 15 06:18:09 PM PDT 24 |
Jul 15 06:37:53 PM PDT 24 |
28707776899 ps |
| T903 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3249766000 |
|
|
Jul 15 06:17:10 PM PDT 24 |
Jul 15 06:17:11 PM PDT 24 |
15406436 ps |
| T904 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1961946099 |
|
|
Jul 15 06:16:56 PM PDT 24 |
Jul 15 06:21:54 PM PDT 24 |
10942493148 ps |
| T905 |
/workspace/coverage/default/24.sram_ctrl_stress_all.438804593 |
|
|
Jul 15 06:17:10 PM PDT 24 |
Jul 15 07:57:18 PM PDT 24 |
580346459956 ps |
| T906 |
/workspace/coverage/default/4.sram_ctrl_partial_access.2709825164 |
|
|
Jul 15 06:15:34 PM PDT 24 |
Jul 15 06:15:51 PM PDT 24 |
845463147 ps |
| T907 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3684264108 |
|
|
Jul 15 06:16:08 PM PDT 24 |
Jul 15 06:18:57 PM PDT 24 |
5024526316 ps |
| T908 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.873256627 |
|
|
Jul 15 06:19:16 PM PDT 24 |
Jul 15 06:40:58 PM PDT 24 |
18879893096 ps |
| T909 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.690437722 |
|
|
Jul 15 06:16:24 PM PDT 24 |
Jul 15 06:19:46 PM PDT 24 |
3433332902 ps |
| T910 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3943559109 |
|
|
Jul 15 06:17:39 PM PDT 24 |
Jul 15 06:21:13 PM PDT 24 |
12463881052 ps |
| T911 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2124775513 |
|
|
Jul 15 06:16:40 PM PDT 24 |
Jul 15 06:17:41 PM PDT 24 |
18977099608 ps |
| T912 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.4067184206 |
|
|
Jul 15 06:19:37 PM PDT 24 |
Jul 15 06:21:06 PM PDT 24 |
73330522372 ps |
| T913 |
/workspace/coverage/default/17.sram_ctrl_executable.1821520218 |
|
|
Jul 15 06:16:23 PM PDT 24 |
Jul 15 06:48:25 PM PDT 24 |
147623236431 ps |
| T914 |
/workspace/coverage/default/40.sram_ctrl_executable.3471228121 |
|
|
Jul 15 06:19:28 PM PDT 24 |
Jul 15 06:50:39 PM PDT 24 |
57045698044 ps |
| T915 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.388676825 |
|
|
Jul 15 06:15:31 PM PDT 24 |
Jul 15 06:17:39 PM PDT 24 |
3954349113 ps |
| T916 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2186247776 |
|
|
Jul 15 06:20:32 PM PDT 24 |
Jul 15 06:23:48 PM PDT 24 |
13339458915 ps |
| T917 |
/workspace/coverage/default/7.sram_ctrl_smoke.3859568491 |
|
|
Jul 15 06:15:49 PM PDT 24 |
Jul 15 06:16:13 PM PDT 24 |
887902858 ps |
| T918 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.2374148772 |
|
|
Jul 15 06:16:09 PM PDT 24 |
Jul 15 06:18:42 PM PDT 24 |
2713294785 ps |
| T919 |
/workspace/coverage/default/1.sram_ctrl_smoke.638155746 |
|
|
Jul 15 06:15:27 PM PDT 24 |
Jul 15 06:15:37 PM PDT 24 |
3020593110 ps |
| T920 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2577434928 |
|
|
Jul 15 06:20:42 PM PDT 24 |
Jul 15 06:20:43 PM PDT 24 |
19135107 ps |
| T921 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1388326308 |
|
|
Jul 15 06:19:51 PM PDT 24 |
Jul 15 06:28:31 PM PDT 24 |
39610349167 ps |
| T922 |
/workspace/coverage/default/44.sram_ctrl_regwen.1738223514 |
|
|
Jul 15 06:20:07 PM PDT 24 |
Jul 15 06:23:40 PM PDT 24 |
10132204710 ps |
| T923 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2974009968 |
|
|
Jul 15 06:15:27 PM PDT 24 |
Jul 15 06:15:32 PM PDT 24 |
1343803437 ps |
| T924 |
/workspace/coverage/default/15.sram_ctrl_bijection.2290689361 |
|
|
Jul 15 06:16:10 PM PDT 24 |
Jul 15 06:37:48 PM PDT 24 |
19270586506 ps |
| T925 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.4146897812 |
|
|
Jul 15 06:15:39 PM PDT 24 |
Jul 15 06:16:16 PM PDT 24 |
12005186522 ps |
| T926 |
/workspace/coverage/default/36.sram_ctrl_executable.1366519118 |
|
|
Jul 15 06:18:40 PM PDT 24 |
Jul 15 06:41:20 PM PDT 24 |
21121960441 ps |
| T927 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1802274961 |
|
|
Jul 15 06:20:09 PM PDT 24 |
Jul 15 06:51:58 PM PDT 24 |
97212564667 ps |
| T928 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.1537842832 |
|
|
Jul 15 06:15:43 PM PDT 24 |
Jul 15 06:21:57 PM PDT 24 |
82704459269 ps |
| T929 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2460190151 |
|
|
Jul 15 06:18:10 PM PDT 24 |
Jul 15 06:20:59 PM PDT 24 |
8804921595 ps |
| T930 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2905831673 |
|
|
Jul 15 06:18:32 PM PDT 24 |
Jul 15 06:18:36 PM PDT 24 |
350716442 ps |
| T931 |
/workspace/coverage/default/31.sram_ctrl_partial_access.778537884 |
|
|
Jul 15 06:17:59 PM PDT 24 |
Jul 15 06:18:09 PM PDT 24 |
2857323627 ps |
| T932 |
/workspace/coverage/default/12.sram_ctrl_smoke.1162190849 |
|
|
Jul 15 06:16:02 PM PDT 24 |
Jul 15 06:16:23 PM PDT 24 |
939888003 ps |
| T933 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3437548070 |
|
|
Jul 15 06:19:45 PM PDT 24 |
Jul 15 07:38:29 PM PDT 24 |
139946190970 ps |
| T934 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.4002014915 |
|
|
Jul 15 06:16:08 PM PDT 24 |
Jul 15 06:17:10 PM PDT 24 |
66837785786 ps |
| T935 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1453032916 |
|
|
Jul 15 06:15:56 PM PDT 24 |
Jul 15 06:35:51 PM PDT 24 |
65839482762 ps |
| T936 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1147055690 |
|
|
Jul 15 06:20:26 PM PDT 24 |
Jul 15 06:20:41 PM PDT 24 |
1116906867 ps |
| T937 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3076666249 |
|
|
Jul 15 06:15:28 PM PDT 24 |
Jul 15 06:15:30 PM PDT 24 |
43398487 ps |
| T938 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1871007431 |
|
|
Jul 15 06:20:49 PM PDT 24 |
Jul 15 06:21:16 PM PDT 24 |
17377017249 ps |
| T939 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2461771441 |
|
|
Jul 15 06:15:49 PM PDT 24 |
Jul 15 06:17:15 PM PDT 24 |
12081685880 ps |
| T940 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1187109214 |
|
|
Jul 15 06:19:49 PM PDT 24 |
Jul 15 06:25:45 PM PDT 24 |
27625641588 ps |
| T941 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.4257552386 |
|
|
Jul 15 06:16:59 PM PDT 24 |
Jul 15 06:25:06 PM PDT 24 |
5363252099 ps |
| T942 |
/workspace/coverage/default/43.sram_ctrl_stress_all.3489562673 |
|
|
Jul 15 06:19:51 PM PDT 24 |
Jul 15 07:52:24 PM PDT 24 |
956154849175 ps |
| T76 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1465552181 |
|
|
Jul 15 07:37:51 PM PDT 24 |
Jul 15 07:38:43 PM PDT 24 |
8934651070 ps |
| T77 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.168644154 |
|
|
Jul 15 07:38:04 PM PDT 24 |
Jul 15 07:38:06 PM PDT 24 |
26741222 ps |
| T78 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4272130700 |
|
|
Jul 15 07:37:53 PM PDT 24 |
Jul 15 07:37:55 PM PDT 24 |
13765431 ps |
| T112 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2376157473 |
|
|
Jul 15 07:37:36 PM PDT 24 |
Jul 15 07:37:37 PM PDT 24 |
56058581 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1356239373 |
|
|
Jul 15 07:37:23 PM PDT 24 |
Jul 15 07:37:25 PM PDT 24 |
15913532 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3765573081 |
|
|
Jul 15 07:38:00 PM PDT 24 |
Jul 15 07:38:28 PM PDT 24 |
4054111082 ps |
| T117 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.675055792 |
|
|
Jul 15 07:37:45 PM PDT 24 |
Jul 15 07:37:46 PM PDT 24 |
20202737 ps |
| T943 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3655694246 |
|
|
Jul 15 07:37:51 PM PDT 24 |
Jul 15 07:37:54 PM PDT 24 |
114286000 ps |
| T113 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.819371326 |
|
|
Jul 15 07:37:58 PM PDT 24 |
Jul 15 07:38:27 PM PDT 24 |
9118999302 ps |
| T89 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.846567899 |
|
|
Jul 15 07:37:29 PM PDT 24 |
Jul 15 07:37:31 PM PDT 24 |
14595492 ps |
| T944 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3292175415 |
|
|
Jul 15 07:37:47 PM PDT 24 |
Jul 15 07:37:52 PM PDT 24 |
366034666 ps |
| T72 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.612686667 |
|
|
Jul 15 07:37:37 PM PDT 24 |
Jul 15 07:37:41 PM PDT 24 |
988247781 ps |
| T90 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2262942069 |
|
|
Jul 15 07:37:25 PM PDT 24 |
Jul 15 07:37:26 PM PDT 24 |
102066454 ps |
| T945 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4160947106 |
|
|
Jul 15 07:37:35 PM PDT 24 |
Jul 15 07:37:40 PM PDT 24 |
218303403 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3647604177 |
|
|
Jul 15 07:37:35 PM PDT 24 |
Jul 15 07:37:39 PM PDT 24 |
355164929 ps |
| T114 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1895897493 |
|
|
Jul 15 07:37:47 PM PDT 24 |
Jul 15 07:37:49 PM PDT 24 |
22083487 ps |
| T947 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3088843689 |
|
|
Jul 15 07:37:54 PM PDT 24 |
Jul 15 07:38:00 PM PDT 24 |
607439371 ps |
| T91 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2035501597 |
|
|
Jul 15 07:37:49 PM PDT 24 |
Jul 15 07:37:50 PM PDT 24 |
34511944 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.204682081 |
|
|
Jul 15 07:37:21 PM PDT 24 |
Jul 15 07:37:50 PM PDT 24 |
14787040893 ps |
| T93 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3233876800 |
|
|
Jul 15 07:37:26 PM PDT 24 |
Jul 15 07:37:28 PM PDT 24 |
15615609 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3374347317 |
|
|
Jul 15 07:37:50 PM PDT 24 |
Jul 15 07:37:54 PM PDT 24 |
4922774731 ps |
| T949 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.197875442 |
|
|
Jul 15 07:37:37 PM PDT 24 |
Jul 15 07:37:38 PM PDT 24 |
23303011 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2566731338 |
|
|
Jul 15 07:37:24 PM PDT 24 |
Jul 15 07:37:25 PM PDT 24 |
80745129 ps |
| T951 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2929629097 |
|
|
Jul 15 07:37:56 PM PDT 24 |
Jul 15 07:38:01 PM PDT 24 |
366401098 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.699126489 |
|
|
Jul 15 07:37:25 PM PDT 24 |
Jul 15 07:37:26 PM PDT 24 |
31365878 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.35685366 |
|
|
Jul 15 07:37:22 PM PDT 24 |
Jul 15 07:37:24 PM PDT 24 |
26090865 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2270708865 |
|
|
Jul 15 07:37:23 PM PDT 24 |
Jul 15 07:37:27 PM PDT 24 |
156320830 ps |
| T74 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1684671368 |
|
|
Jul 15 07:37:57 PM PDT 24 |
Jul 15 07:37:59 PM PDT 24 |
331106283 ps |
| T133 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.110792966 |
|
|
Jul 15 07:37:35 PM PDT 24 |
Jul 15 07:37:39 PM PDT 24 |
747361423 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3919693525 |
|
|
Jul 15 07:37:29 PM PDT 24 |
Jul 15 07:37:30 PM PDT 24 |
30624797 ps |
| T94 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2772964769 |
|
|
Jul 15 07:37:46 PM PDT 24 |
Jul 15 07:38:38 PM PDT 24 |
7076396457 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.183917739 |
|
|
Jul 15 07:37:45 PM PDT 24 |
Jul 15 07:37:46 PM PDT 24 |
17046793 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1512024936 |
|
|
Jul 15 07:37:53 PM PDT 24 |
Jul 15 07:38:48 PM PDT 24 |
14430846610 ps |
| T957 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1955893552 |
|
|
Jul 15 07:37:57 PM PDT 24 |
Jul 15 07:38:01 PM PDT 24 |
77244670 ps |
| T95 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2188278038 |
|
|
Jul 15 07:37:31 PM PDT 24 |
Jul 15 07:38:28 PM PDT 24 |
29424306838 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3270769285 |
|
|
Jul 15 07:37:23 PM PDT 24 |
Jul 15 07:37:24 PM PDT 24 |
23690146 ps |
| T96 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1557389785 |
|
|
Jul 15 07:37:49 PM PDT 24 |
Jul 15 07:39:02 PM PDT 24 |
64171352176 ps |
| T959 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.640389442 |
|
|
Jul 15 07:37:52 PM PDT 24 |
Jul 15 07:37:57 PM PDT 24 |
703463484 ps |
| T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4028078767 |
|
|
Jul 15 07:37:56 PM PDT 24 |
Jul 15 07:37:59 PM PDT 24 |
145351744 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.390158083 |
|
|
Jul 15 07:37:16 PM PDT 24 |
Jul 15 07:37:48 PM PDT 24 |
15419808775 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3089981031 |
|
|
Jul 15 07:37:32 PM PDT 24 |
Jul 15 07:37:34 PM PDT 24 |
64816775 ps |
| T963 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1268247682 |
|
|
Jul 15 07:37:34 PM PDT 24 |
Jul 15 07:37:37 PM PDT 24 |
27338477 ps |
| T129 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1112222281 |
|
|
Jul 15 07:37:28 PM PDT 24 |
Jul 15 07:37:30 PM PDT 24 |
272799120 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3700442026 |
|
|
Jul 15 07:37:18 PM PDT 24 |
Jul 15 07:37:24 PM PDT 24 |
649421338 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3268186387 |
|
|
Jul 15 07:38:04 PM PDT 24 |
Jul 15 07:38:08 PM PDT 24 |
362484199 ps |
| T130 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3655541988 |
|
|
Jul 15 07:37:53 PM PDT 24 |
Jul 15 07:37:57 PM PDT 24 |
205323804 ps |
| T966 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3015018584 |
|
|
Jul 15 07:37:46 PM PDT 24 |
Jul 15 07:37:48 PM PDT 24 |
27211329 ps |
| T967 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3592004735 |
|
|
Jul 15 07:37:50 PM PDT 24 |
Jul 15 07:37:51 PM PDT 24 |
48403412 ps |
| T131 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3242777866 |
|
|
Jul 15 07:37:58 PM PDT 24 |
Jul 15 07:38:01 PM PDT 24 |
174779708 ps |
| T97 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.228406078 |
|
|
Jul 15 07:37:23 PM PDT 24 |
Jul 15 07:37:52 PM PDT 24 |
7786775733 ps |
| T98 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2191654483 |
|
|
Jul 15 07:37:29 PM PDT 24 |
Jul 15 07:38:23 PM PDT 24 |
13616310180 ps |
| T968 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.772844150 |
|
|
Jul 15 07:37:50 PM PDT 24 |
Jul 15 07:37:51 PM PDT 24 |
72421147 ps |
| T138 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.66865025 |
|
|
Jul 15 07:37:52 PM PDT 24 |
Jul 15 07:37:55 PM PDT 24 |
210914139 ps |
| T969 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1982045696 |
|
|
Jul 15 07:38:09 PM PDT 24 |
Jul 15 07:38:14 PM PDT 24 |
117774462 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3649512115 |
|
|
Jul 15 07:37:38 PM PDT 24 |
Jul 15 07:37:40 PM PDT 24 |
12372781 ps |
| T971 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1812964877 |
|
|
Jul 15 07:37:44 PM PDT 24 |
Jul 15 07:37:45 PM PDT 24 |
20123224 ps |
| T972 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4078467834 |
|
|
Jul 15 07:37:35 PM PDT 24 |
Jul 15 07:37:41 PM PDT 24 |
310750631 ps |
| T973 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3973219830 |
|
|
Jul 15 07:37:57 PM PDT 24 |
Jul 15 07:37:59 PM PDT 24 |
15496454 ps |
| T99 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.223838994 |
|
|
Jul 15 07:38:06 PM PDT 24 |
Jul 15 07:38:08 PM PDT 24 |
15558814 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2008973827 |
|
|
Jul 15 07:37:24 PM PDT 24 |
Jul 15 07:37:26 PM PDT 24 |
41269022 ps |
| T134 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2891510904 |
|
|
Jul 15 07:37:35 PM PDT 24 |
Jul 15 07:37:38 PM PDT 24 |
252797296 ps |
| T975 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3870109587 |
|
|
Jul 15 07:37:35 PM PDT 24 |
Jul 15 07:37:37 PM PDT 24 |
27414413 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3425225354 |
|
|
Jul 15 07:37:34 PM PDT 24 |
Jul 15 07:37:36 PM PDT 24 |
39807427 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.404886455 |
|
|
Jul 15 07:37:30 PM PDT 24 |
Jul 15 07:37:34 PM PDT 24 |
38172504 ps |
| T136 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1858659074 |
|
|
Jul 15 07:38:09 PM PDT 24 |
Jul 15 07:38:12 PM PDT 24 |
152428764 ps |
| T978 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1147676118 |
|
|
Jul 15 07:37:31 PM PDT 24 |
Jul 15 07:37:36 PM PDT 24 |
1453915876 ps |
| T979 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2864191980 |
|
|
Jul 15 07:37:42 PM PDT 24 |
Jul 15 07:38:11 PM PDT 24 |
14781654928 ps |
| T980 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4167013483 |
|
|
Jul 15 07:37:47 PM PDT 24 |
Jul 15 07:37:50 PM PDT 24 |
122672625 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3962426178 |
|
|
Jul 15 07:38:08 PM PDT 24 |
Jul 15 07:38:10 PM PDT 24 |
56005501 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1947782117 |
|
|
Jul 15 07:37:58 PM PDT 24 |
Jul 15 07:38:00 PM PDT 24 |
104938304 ps |
| T105 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.928861431 |
|
|
Jul 15 07:38:06 PM PDT 24 |
Jul 15 07:38:08 PM PDT 24 |
46872933 ps |
| T135 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1975272084 |
|
|
Jul 15 07:37:43 PM PDT 24 |
Jul 15 07:37:46 PM PDT 24 |
324266930 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.82683407 |
|
|
Jul 15 07:37:58 PM PDT 24 |
Jul 15 07:38:01 PM PDT 24 |
150147044 ps |
| T984 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4182363575 |
|
|
Jul 15 07:37:59 PM PDT 24 |
Jul 15 07:38:03 PM PDT 24 |
1449866057 ps |
| T985 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4220434402 |
|
|
Jul 15 07:37:45 PM PDT 24 |
Jul 15 07:37:46 PM PDT 24 |
33817274 ps |
| T109 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.987191868 |
|
|
Jul 15 07:37:50 PM PDT 24 |
Jul 15 07:38:20 PM PDT 24 |
7094506488 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2407075467 |
|
|
Jul 15 07:37:31 PM PDT 24 |
Jul 15 07:37:32 PM PDT 24 |
17532028 ps |
| T987 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2459809675 |
|
|
Jul 15 07:37:45 PM PDT 24 |
Jul 15 07:37:49 PM PDT 24 |
350056108 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2870900399 |
|
|
Jul 15 07:38:00 PM PDT 24 |
Jul 15 07:38:01 PM PDT 24 |
16156967 ps |
| T989 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2090581495 |
|
|
Jul 15 07:37:31 PM PDT 24 |
Jul 15 07:37:36 PM PDT 24 |
717582874 ps |
| T990 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4014848879 |
|
|
Jul 15 07:37:58 PM PDT 24 |
Jul 15 07:38:03 PM PDT 24 |
375616789 ps |
| T991 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.319555412 |
|
|
Jul 15 07:37:34 PM PDT 24 |
Jul 15 07:37:39 PM PDT 24 |
368185473 ps |
| T992 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3447844149 |
|
|
Jul 15 07:37:29 PM PDT 24 |
Jul 15 07:37:33 PM PDT 24 |
40901274 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1543713591 |
|
|
Jul 15 07:37:22 PM PDT 24 |
Jul 15 07:37:26 PM PDT 24 |
366465556 ps |
| T994 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1470250039 |
|
|
Jul 15 07:37:52 PM PDT 24 |
Jul 15 07:37:57 PM PDT 24 |
117032339 ps |
| T106 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1310134031 |
|
|
Jul 15 07:38:05 PM PDT 24 |
Jul 15 07:38:35 PM PDT 24 |
13185890087 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1956897382 |
|
|
Jul 15 07:37:31 PM PDT 24 |
Jul 15 07:37:33 PM PDT 24 |
14641143 ps |
| T139 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4257182936 |
|
|
Jul 15 07:37:35 PM PDT 24 |
Jul 15 07:37:37 PM PDT 24 |
430606772 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2390933781 |
|
|
Jul 15 07:37:34 PM PDT 24 |
Jul 15 07:37:35 PM PDT 24 |
43044527 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.664579458 |
|
|
Jul 15 07:37:17 PM PDT 24 |
Jul 15 07:37:19 PM PDT 24 |
407691839 ps |
| T132 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3693611906 |
|
|
Jul 15 07:37:51 PM PDT 24 |
Jul 15 07:37:54 PM PDT 24 |
873502143 ps |
| T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2857274797 |
|
|
Jul 15 07:37:56 PM PDT 24 |
Jul 15 07:37:57 PM PDT 24 |
137831673 ps |
| T107 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2387872864 |
|
|
Jul 15 07:37:23 PM PDT 24 |
Jul 15 07:37:25 PM PDT 24 |
381028125 ps |
| T110 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.771344454 |
|
|
Jul 15 07:37:58 PM PDT 24 |
Jul 15 07:38:29 PM PDT 24 |
7396610409 ps |
| T111 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3812729280 |
|
|
Jul 15 07:37:37 PM PDT 24 |
Jul 15 07:38:24 PM PDT 24 |
8178797246 ps |
| T999 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2358042586 |
|
|
Jul 15 07:37:33 PM PDT 24 |
Jul 15 07:37:38 PM PDT 24 |
44310943 ps |
| T1000 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1581356011 |
|
|
Jul 15 07:37:58 PM PDT 24 |
Jul 15 07:37:59 PM PDT 24 |
25865732 ps |
| T1001 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1721050519 |
|
|
Jul 15 07:37:55 PM PDT 24 |
Jul 15 07:37:58 PM PDT 24 |
604869693 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1665591251 |
|
|
Jul 15 07:37:34 PM PDT 24 |
Jul 15 07:37:36 PM PDT 24 |
67800788 ps |
| T1003 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.545740634 |
|
|
Jul 15 07:37:54 PM PDT 24 |
Jul 15 07:37:58 PM PDT 24 |
388011973 ps |