SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.99 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.62 |
T1004 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1469074030 | Jul 15 07:37:45 PM PDT 24 | Jul 15 07:37:49 PM PDT 24 | 1425001924 ps | ||
T108 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.374134792 | Jul 15 07:37:35 PM PDT 24 | Jul 15 07:38:28 PM PDT 24 | 7177372580 ps | ||
T140 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.74528837 | Jul 15 07:37:29 PM PDT 24 | Jul 15 07:37:32 PM PDT 24 | 193523418 ps | ||
T1005 | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1190760564 | Jul 15 07:37:43 PM PDT 24 | Jul 15 07:38:12 PM PDT 24 | 3851382465 ps | ||
T1006 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2816935017 | Jul 15 07:37:43 PM PDT 24 | Jul 15 07:37:45 PM PDT 24 | 196298228 ps | ||
T1007 | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3990675457 | Jul 15 07:37:36 PM PDT 24 | Jul 15 07:37:37 PM PDT 24 | 43994789 ps | ||
T1008 | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2092192595 | Jul 15 07:37:44 PM PDT 24 | Jul 15 07:37:45 PM PDT 24 | 21235942 ps | ||
T1009 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4039531849 | Jul 15 07:37:24 PM PDT 24 | Jul 15 07:37:30 PM PDT 24 | 135635260 ps | ||
T1010 | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2238550874 | Jul 15 07:37:51 PM PDT 24 | Jul 15 07:37:52 PM PDT 24 | 18393965 ps | ||
T1011 | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.610610015 | Jul 15 07:37:56 PM PDT 24 | Jul 15 07:37:58 PM PDT 24 | 26376471 ps | ||
T1012 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.960001102 | Jul 15 07:37:47 PM PDT 24 | Jul 15 07:37:52 PM PDT 24 | 353774971 ps | ||
T1013 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4229537121 | Jul 15 07:37:50 PM PDT 24 | Jul 15 07:37:54 PM PDT 24 | 357521026 ps | ||
T1014 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.899178019 | Jul 15 07:38:04 PM PDT 24 | Jul 15 07:38:08 PM PDT 24 | 774155809 ps | ||
T1015 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.506034118 | Jul 15 07:38:06 PM PDT 24 | Jul 15 07:38:11 PM PDT 24 | 1443162173 ps | ||
T1016 | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3778058095 | Jul 15 07:37:37 PM PDT 24 | Jul 15 07:37:39 PM PDT 24 | 51274980 ps | ||
T1017 | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2737123464 | Jul 15 07:37:36 PM PDT 24 | Jul 15 07:38:06 PM PDT 24 | 3702641453 ps | ||
T1018 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3570108321 | Jul 15 07:37:31 PM PDT 24 | Jul 15 07:37:33 PM PDT 24 | 26443049 ps | ||
T137 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1198163821 | Jul 15 07:37:44 PM PDT 24 | Jul 15 07:37:47 PM PDT 24 | 174096532 ps | ||
T1019 | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2995786351 | Jul 15 07:37:55 PM PDT 24 | Jul 15 07:38:24 PM PDT 24 | 3698894923 ps | ||
T1020 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.428897026 | Jul 15 07:37:56 PM PDT 24 | Jul 15 07:37:57 PM PDT 24 | 17354543 ps | ||
T1021 | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4256897583 | Jul 15 07:37:29 PM PDT 24 | Jul 15 07:37:30 PM PDT 24 | 72522407 ps | ||
T1022 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2787778052 | Jul 15 07:38:00 PM PDT 24 | Jul 15 07:38:05 PM PDT 24 | 468721748 ps | ||
T1023 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3463372513 | Jul 15 07:38:00 PM PDT 24 | Jul 15 07:38:06 PM PDT 24 | 289451799 ps | ||
T1024 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3426124954 | Jul 15 07:37:37 PM PDT 24 | Jul 15 07:37:42 PM PDT 24 | 2046940704 ps | ||
T1025 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4158065467 | Jul 15 07:37:24 PM PDT 24 | Jul 15 07:37:25 PM PDT 24 | 15407801 ps | ||
T1026 | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3979682349 | Jul 15 07:38:00 PM PDT 24 | Jul 15 07:38:02 PM PDT 24 | 28319208 ps | ||
T1027 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2753108797 | Jul 15 07:37:46 PM PDT 24 | Jul 15 07:37:51 PM PDT 24 | 152311135 ps | ||
T1028 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.538604923 | Jul 15 07:37:23 PM PDT 24 | Jul 15 07:37:28 PM PDT 24 | 45483292 ps | ||
T1029 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1542169501 | Jul 15 07:37:51 PM PDT 24 | Jul 15 07:37:54 PM PDT 24 | 388855040 ps | ||
T1030 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3780596705 | Jul 15 07:37:52 PM PDT 24 | Jul 15 07:37:53 PM PDT 24 | 12994174 ps | ||
T1031 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1435452931 | Jul 15 07:37:28 PM PDT 24 | Jul 15 07:37:31 PM PDT 24 | 444883750 ps | ||
T1032 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3154287211 | Jul 15 07:37:29 PM PDT 24 | Jul 15 07:37:31 PM PDT 24 | 197274878 ps | ||
T1033 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1512388549 | Jul 15 07:37:23 PM PDT 24 | Jul 15 07:37:29 PM PDT 24 | 2028316959 ps | ||
T1034 | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2948778083 | Jul 15 07:37:53 PM PDT 24 | Jul 15 07:37:56 PM PDT 24 | 31719985 ps | ||
T1035 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2360584518 | Jul 15 07:37:46 PM PDT 24 | Jul 15 07:37:49 PM PDT 24 | 82909815 ps |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1953436125 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 63549083076 ps |
CPU time | 977.25 seconds |
Started | Jul 15 06:16:22 PM PDT 24 |
Finished | Jul 15 06:32:41 PM PDT 24 |
Peak memory | 379676 kb |
Host | smart-8e1964f4-5217-4543-8990-049b92dfcf11 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953436125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.1953436125 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2283173656 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 978618367 ps |
CPU time | 31.91 seconds |
Started | Jul 15 06:18:38 PM PDT 24 |
Finished | Jul 15 06:19:10 PM PDT 24 |
Peak memory | 211320 kb |
Host | smart-bbb7721b-b04e-4fc6-8a70-e842ecee25eb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2283173656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2283173656 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3438614046 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 3189255793 ps |
CPU time | 44.46 seconds |
Started | Jul 15 06:19:13 PM PDT 24 |
Finished | Jul 15 06:19:58 PM PDT 24 |
Peak memory | 241900 kb |
Host | smart-5cd7ae75-72fc-49b1-b2b9-3ee74dab16b2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3438614046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3438614046 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.3233708626 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 146505529240 ps |
CPU time | 5432.96 seconds |
Started | Jul 15 06:16:45 PM PDT 24 |
Finished | Jul 15 07:47:19 PM PDT 24 |
Peak memory | 379656 kb |
Host | smart-139bb873-e0f0-40a5-8429-ce2a6e8b5fb1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233708626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.3233708626 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2270708865 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 156320830 ps |
CPU time | 2.26 seconds |
Started | Jul 15 07:37:23 PM PDT 24 |
Finished | Jul 15 07:37:27 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-c7f8417d-3afe-4c4c-8891-2faae0b20d67 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270708865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.2270708865 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.948636426 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 297158826 ps |
CPU time | 2.42 seconds |
Started | Jul 15 06:15:37 PM PDT 24 |
Finished | Jul 15 06:15:41 PM PDT 24 |
Peak memory | 222124 kb |
Host | smart-4b872bea-f6a6-43c1-b39f-3058d4638329 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948636426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_sec_cm.948636426 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2581539615 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 19473099568 ps |
CPU time | 460.09 seconds |
Started | Jul 15 06:20:25 PM PDT 24 |
Finished | Jul 15 06:28:05 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-e0f86d7e-7280-4736-98b1-46ced7385b58 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581539615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.2581539615 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.2728375923 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 11191701 ps |
CPU time | 0.64 seconds |
Started | Jul 15 06:20:34 PM PDT 24 |
Finished | Jul 15 06:20:35 PM PDT 24 |
Peak memory | 202516 kb |
Host | smart-016085aa-ee9f-43c6-aab4-1a1c50707094 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728375923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.2728375923 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.2324486920 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 122415878135 ps |
CPU time | 5063.49 seconds |
Started | Jul 15 06:17:26 PM PDT 24 |
Finished | Jul 15 07:41:51 PM PDT 24 |
Peak memory | 378620 kb |
Host | smart-0f1546d3-b54d-487e-ae67-4d3d883afdab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324486920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.2324486920 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.386861324 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 12129288609 ps |
CPU time | 181.23 seconds |
Started | Jul 15 06:15:59 PM PDT 24 |
Finished | Jul 15 06:19:01 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-f3e819fb-504c-4589-a1b1-3d114b418c5c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386861324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_stress_pipeline.386861324 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1465552181 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 8934651070 ps |
CPU time | 50.62 seconds |
Started | Jul 15 07:37:51 PM PDT 24 |
Finished | Jul 15 07:38:43 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-36634fcd-8d78-4d51-a33b-de28c9308eea |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465552181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.1465552181 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3598111836 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 2103620927 ps |
CPU time | 27.63 seconds |
Started | Jul 15 06:17:32 PM PDT 24 |
Finished | Jul 15 06:18:00 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-32d7d56e-69d9-434f-a641-7375e98d3364 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3598111836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3598111836 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.3451206184 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 2237225636 ps |
CPU time | 3.35 seconds |
Started | Jul 15 06:15:58 PM PDT 24 |
Finished | Jul 15 06:16:02 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-4df04abc-a970-4aa5-8742-e1b7acc148be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451206184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3451206184 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2891510904 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 252797296 ps |
CPU time | 2.06 seconds |
Started | Jul 15 07:37:35 PM PDT 24 |
Finished | Jul 15 07:37:38 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-af407efd-7eef-4452-80ab-d221b851bcfb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891510904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.2891510904 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.3094129452 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 243974295022 ps |
CPU time | 2608.1 seconds |
Started | Jul 15 06:16:30 PM PDT 24 |
Finished | Jul 15 07:00:00 PM PDT 24 |
Peak memory | 380688 kb |
Host | smart-7ae0af4f-8546-489a-8a1f-ccbefbcca76d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094129452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.3094129452 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2563724068 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 9819130397 ps |
CPU time | 66.36 seconds |
Started | Jul 15 06:16:01 PM PDT 24 |
Finished | Jul 15 06:17:09 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-93d81d51-650b-4124-a051-c937c02a8d1a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2563724068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2563724068 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3693611906 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 873502143 ps |
CPU time | 2.52 seconds |
Started | Jul 15 07:37:51 PM PDT 24 |
Finished | Jul 15 07:37:54 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-ecd5503b-d1fb-4d48-b3c6-207969426a1a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693611906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.3693611906 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3812729280 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 8178797246 ps |
CPU time | 46.86 seconds |
Started | Jul 15 07:37:37 PM PDT 24 |
Finished | Jul 15 07:38:24 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-b003040e-5d30-4b38-90d3-4a259b488978 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812729280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3812729280 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2262942069 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 102066454 ps |
CPU time | 0.65 seconds |
Started | Jul 15 07:37:25 PM PDT 24 |
Finished | Jul 15 07:37:26 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-2a9c074e-cf74-47bf-b9b9-c51d03398111 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262942069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.2262942069 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2387872864 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 381028125 ps |
CPU time | 1.5 seconds |
Started | Jul 15 07:37:23 PM PDT 24 |
Finished | Jul 15 07:37:25 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-e1080683-87e7-4b12-b63a-68e90ebcc4d8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387872864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.2387872864 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.699126489 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 31365878 ps |
CPU time | 0.75 seconds |
Started | Jul 15 07:37:25 PM PDT 24 |
Finished | Jul 15 07:37:26 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-19df7373-4d6c-4408-a2a8-caf741fa101e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699126489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_reset.699126489 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1512388549 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 2028316959 ps |
CPU time | 4.16 seconds |
Started | Jul 15 07:37:23 PM PDT 24 |
Finished | Jul 15 07:37:29 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-bc7fa7d4-c9e0-4c3d-9abe-c6785bef7314 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512388549 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1512388549 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.35685366 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 26090865 ps |
CPU time | 0.63 seconds |
Started | Jul 15 07:37:22 PM PDT 24 |
Finished | Jul 15 07:37:24 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-0d7398b7-1dfe-4a82-98e1-8fc4178a9a7f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35685366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.sram_ctrl_csr_rw.35685366 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.390158083 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 15419808775 ps |
CPU time | 31.56 seconds |
Started | Jul 15 07:37:16 PM PDT 24 |
Finished | Jul 15 07:37:48 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-8155797d-cabb-4f38-b46d-d1bd83568812 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390158083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.390158083 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1356239373 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 15913532 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:37:23 PM PDT 24 |
Finished | Jul 15 07:37:25 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-217bbfba-4398-4f8b-a2d0-c80d03eeebc7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356239373 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1356239373 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3700442026 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 649421338 ps |
CPU time | 4.78 seconds |
Started | Jul 15 07:37:18 PM PDT 24 |
Finished | Jul 15 07:37:24 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-7c5ffbfc-dc7b-4d80-8ac3-87ec8bb40357 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700442026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.3700442026 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.664579458 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 407691839 ps |
CPU time | 1.58 seconds |
Started | Jul 15 07:37:17 PM PDT 24 |
Finished | Jul 15 07:37:19 PM PDT 24 |
Peak memory | 211188 kb |
Host | smart-9246bfc7-75df-46a3-8dba-f1373ca059ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664579458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.sram_ctrl_tl_intg_err.664579458 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4158065467 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 15407801 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:37:24 PM PDT 24 |
Finished | Jul 15 07:37:25 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-f00ed4f1-0e0d-43e6-8b00-cf6cee6bbb56 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158065467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.4158065467 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2008973827 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 41269022 ps |
CPU time | 1.78 seconds |
Started | Jul 15 07:37:24 PM PDT 24 |
Finished | Jul 15 07:37:26 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-8f809562-bedf-4d2a-883d-613911ae994d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008973827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.2008973827 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3233876800 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 15615609 ps |
CPU time | 0.67 seconds |
Started | Jul 15 07:37:26 PM PDT 24 |
Finished | Jul 15 07:37:28 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-58ac9d93-b6f2-40db-9715-b448d363c8e1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233876800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.3233876800 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1543713591 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 366465556 ps |
CPU time | 3.52 seconds |
Started | Jul 15 07:37:22 PM PDT 24 |
Finished | Jul 15 07:37:26 PM PDT 24 |
Peak memory | 219052 kb |
Host | smart-925e7dcc-04e4-4648-8ab3-a4965b4229b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543713591 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1543713591 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2566731338 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 80745129 ps |
CPU time | 0.69 seconds |
Started | Jul 15 07:37:24 PM PDT 24 |
Finished | Jul 15 07:37:25 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-18c859b5-976f-468f-95ca-98144e73ae28 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566731338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2566731338 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.204682081 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 14787040893 ps |
CPU time | 28.42 seconds |
Started | Jul 15 07:37:21 PM PDT 24 |
Finished | Jul 15 07:37:50 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-a95d4b0b-a02c-4672-921b-3298aa160575 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204682081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.204682081 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3270769285 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 23690146 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:37:23 PM PDT 24 |
Finished | Jul 15 07:37:24 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-6d245aff-c6f8-43e6-b5d9-720ed8212513 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270769285 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3270769285 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4039531849 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 135635260 ps |
CPU time | 5.28 seconds |
Started | Jul 15 07:37:24 PM PDT 24 |
Finished | Jul 15 07:37:30 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-589b4659-7496-4b4e-87a2-610dac3aa0c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039531849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.4039531849 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.960001102 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 353774971 ps |
CPU time | 3.89 seconds |
Started | Jul 15 07:37:47 PM PDT 24 |
Finished | Jul 15 07:37:52 PM PDT 24 |
Peak memory | 212508 kb |
Host | smart-1779daff-8320-4bf7-822b-0ed094c203ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960001102 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.960001102 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.183917739 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 17046793 ps |
CPU time | 0.67 seconds |
Started | Jul 15 07:37:45 PM PDT 24 |
Finished | Jul 15 07:37:46 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-693e5fcc-17fc-44ee-bf8c-ecf496aa7d9c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183917739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_csr_rw.183917739 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2864191980 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 14781654928 ps |
CPU time | 28.51 seconds |
Started | Jul 15 07:37:42 PM PDT 24 |
Finished | Jul 15 07:38:11 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-1183bb56-103b-4148-b2a8-b8c83e66aa93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864191980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2864191980 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2035501597 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 34511944 ps |
CPU time | 0.76 seconds |
Started | Jul 15 07:37:49 PM PDT 24 |
Finished | Jul 15 07:37:50 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-6cd87e5e-a5ab-40de-94ad-30244b005bec |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035501597 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2035501597 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2360584518 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 82909815 ps |
CPU time | 2.56 seconds |
Started | Jul 15 07:37:46 PM PDT 24 |
Finished | Jul 15 07:37:49 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-30dcd893-5f23-4c87-b1b8-c6a67ad4e949 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360584518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.2360584518 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1975272084 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 324266930 ps |
CPU time | 2.22 seconds |
Started | Jul 15 07:37:43 PM PDT 24 |
Finished | Jul 15 07:37:46 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-8e33ca98-7e00-4431-a409-52033c85a3da |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975272084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.1975272084 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.640389442 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 703463484 ps |
CPU time | 4.55 seconds |
Started | Jul 15 07:37:52 PM PDT 24 |
Finished | Jul 15 07:37:57 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-d5a2a2ae-efeb-433d-b1cd-86912e0eecd1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640389442 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.640389442 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4272130700 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 13765431 ps |
CPU time | 0.68 seconds |
Started | Jul 15 07:37:53 PM PDT 24 |
Finished | Jul 15 07:37:55 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-84a4ab0c-25ad-4b18-9575-832a58919aec |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272130700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.4272130700 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2995786351 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 3698894923 ps |
CPU time | 28.69 seconds |
Started | Jul 15 07:37:55 PM PDT 24 |
Finished | Jul 15 07:38:24 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-0f318d3e-b075-48c2-b563-a30d54194e36 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995786351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.2995786351 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2238550874 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 18393965 ps |
CPU time | 0.7 seconds |
Started | Jul 15 07:37:51 PM PDT 24 |
Finished | Jul 15 07:37:52 PM PDT 24 |
Peak memory | 202568 kb |
Host | smart-780c5302-5f88-4f12-a2ae-1d497c9d18ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238550874 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2238550874 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1470250039 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 117032339 ps |
CPU time | 4.28 seconds |
Started | Jul 15 07:37:52 PM PDT 24 |
Finished | Jul 15 07:37:57 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-7d72c6d4-a5be-4b86-930b-9398507ddae9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470250039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1470250039 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.66865025 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 210914139 ps |
CPU time | 2.09 seconds |
Started | Jul 15 07:37:52 PM PDT 24 |
Finished | Jul 15 07:37:55 PM PDT 24 |
Peak memory | 211156 kb |
Host | smart-cd1c5f12-bb50-4ed9-b701-67f7354c662b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66865025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 11.sram_ctrl_tl_intg_err.66865025 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3374347317 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 4922774731 ps |
CPU time | 3.46 seconds |
Started | Jul 15 07:37:50 PM PDT 24 |
Finished | Jul 15 07:37:54 PM PDT 24 |
Peak memory | 212180 kb |
Host | smart-5c66756a-4404-4e01-96a4-aec1e587ea12 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374347317 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3374347317 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3780596705 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 12994174 ps |
CPU time | 0.68 seconds |
Started | Jul 15 07:37:52 PM PDT 24 |
Finished | Jul 15 07:37:53 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-5bec380a-d801-49be-b49f-b78993f63513 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780596705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.3780596705 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1557389785 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 64171352176 ps |
CPU time | 72.1 seconds |
Started | Jul 15 07:37:49 PM PDT 24 |
Finished | Jul 15 07:39:02 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-19de7d39-9dd5-4efa-8f8a-136bf089556e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557389785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1557389785 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.428897026 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 17354543 ps |
CPU time | 0.8 seconds |
Started | Jul 15 07:37:56 PM PDT 24 |
Finished | Jul 15 07:37:57 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-8ec2b415-a1a2-40c7-96ff-af21df4de62d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428897026 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.428897026 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4028078767 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 145351744 ps |
CPU time | 2.04 seconds |
Started | Jul 15 07:37:56 PM PDT 24 |
Finished | Jul 15 07:37:59 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-4e2d4595-7fbb-4c28-a1a5-372af729ccf6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028078767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.4028078767 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4229537121 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 357521026 ps |
CPU time | 3.44 seconds |
Started | Jul 15 07:37:50 PM PDT 24 |
Finished | Jul 15 07:37:54 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-b5790b24-e7e1-4dce-8752-c9796aaa0277 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229537121 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.4229537121 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3592004735 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 48403412 ps |
CPU time | 0.69 seconds |
Started | Jul 15 07:37:50 PM PDT 24 |
Finished | Jul 15 07:37:51 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-3736c698-cf02-4398-86cb-8f40986be321 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592004735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.3592004735 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.772844150 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 72421147 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:37:50 PM PDT 24 |
Finished | Jul 15 07:37:51 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-093bfa26-7606-49e3-9125-bf764dd04855 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772844150 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.772844150 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3088843689 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 607439371 ps |
CPU time | 4.84 seconds |
Started | Jul 15 07:37:54 PM PDT 24 |
Finished | Jul 15 07:38:00 PM PDT 24 |
Peak memory | 211196 kb |
Host | smart-dd38054f-8596-403c-9a69-d1dc1bf887dc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088843689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3088843689 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1721050519 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 604869693 ps |
CPU time | 2.44 seconds |
Started | Jul 15 07:37:55 PM PDT 24 |
Finished | Jul 15 07:37:58 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-a7845894-cea7-422f-91b2-8158863ebb6c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721050519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.1721050519 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.545740634 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 388011973 ps |
CPU time | 3.59 seconds |
Started | Jul 15 07:37:54 PM PDT 24 |
Finished | Jul 15 07:37:58 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-a2b7b860-cff1-4776-805d-8fc997982d5f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545740634 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.545740634 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2857274797 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 137831673 ps |
CPU time | 0.67 seconds |
Started | Jul 15 07:37:56 PM PDT 24 |
Finished | Jul 15 07:37:57 PM PDT 24 |
Peak memory | 202592 kb |
Host | smart-9a17ca14-d134-480a-8875-02b36e073759 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857274797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.2857274797 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1512024936 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 14430846610 ps |
CPU time | 54.36 seconds |
Started | Jul 15 07:37:53 PM PDT 24 |
Finished | Jul 15 07:38:48 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-c6331f31-23fc-4620-8fac-faf5a241bb6e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512024936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1512024936 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2948778083 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 31719985 ps |
CPU time | 0.82 seconds |
Started | Jul 15 07:37:53 PM PDT 24 |
Finished | Jul 15 07:37:56 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-29b7257a-58cf-45f0-871f-d7ded8a8068d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948778083 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.2948778083 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3655694246 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 114286000 ps |
CPU time | 2.28 seconds |
Started | Jul 15 07:37:51 PM PDT 24 |
Finished | Jul 15 07:37:54 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-836c6799-97fd-4aa1-b5d8-bfa8891b1c19 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655694246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3655694246 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3655541988 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 205323804 ps |
CPU time | 2.21 seconds |
Started | Jul 15 07:37:53 PM PDT 24 |
Finished | Jul 15 07:37:57 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-62ae65f4-8686-4430-83e9-0602f2abbf62 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655541988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.3655541988 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4014848879 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 375616789 ps |
CPU time | 4.04 seconds |
Started | Jul 15 07:37:58 PM PDT 24 |
Finished | Jul 15 07:38:03 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-50f460a8-3fc1-4000-a0b6-4679861b97b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014848879 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.4014848879 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2870900399 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 16156967 ps |
CPU time | 0.69 seconds |
Started | Jul 15 07:38:00 PM PDT 24 |
Finished | Jul 15 07:38:01 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-6a789f3e-5239-4d18-9bd7-f908ce8b1ad5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870900399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.2870900399 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.987191868 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 7094506488 ps |
CPU time | 28.79 seconds |
Started | Jul 15 07:37:50 PM PDT 24 |
Finished | Jul 15 07:38:20 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-579551e4-a122-404a-9a9f-84ea8ff9c63f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987191868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.987191868 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1581356011 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 25865732 ps |
CPU time | 0.66 seconds |
Started | Jul 15 07:37:58 PM PDT 24 |
Finished | Jul 15 07:37:59 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-32d31ba8-c2e9-4320-9c3f-607d825d5a0d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581356011 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1581356011 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1542169501 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 388855040 ps |
CPU time | 2.41 seconds |
Started | Jul 15 07:37:51 PM PDT 24 |
Finished | Jul 15 07:37:54 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-25ef3f04-b02e-49d0-a8b5-5326743036a6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542169501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.1542169501 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.82683407 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 150147044 ps |
CPU time | 1.71 seconds |
Started | Jul 15 07:37:58 PM PDT 24 |
Finished | Jul 15 07:38:01 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-0d6ce498-d7ef-4122-bcef-2184e64cc7eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82683407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 15.sram_ctrl_tl_intg_err.82683407 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4182363575 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 1449866057 ps |
CPU time | 3.98 seconds |
Started | Jul 15 07:37:59 PM PDT 24 |
Finished | Jul 15 07:38:03 PM PDT 24 |
Peak memory | 211236 kb |
Host | smart-579a7046-e824-4d9f-97f9-327bd3d11d81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182363575 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.4182363575 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3973219830 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 15496454 ps |
CPU time | 0.64 seconds |
Started | Jul 15 07:37:57 PM PDT 24 |
Finished | Jul 15 07:37:59 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-c280917c-1df2-4e0f-b131-812fccb258b8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973219830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.3973219830 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.771344454 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 7396610409 ps |
CPU time | 30.24 seconds |
Started | Jul 15 07:37:58 PM PDT 24 |
Finished | Jul 15 07:38:29 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-821ff0a6-1070-4d18-a2f1-0117defaed25 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771344454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.771344454 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3979682349 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 28319208 ps |
CPU time | 0.76 seconds |
Started | Jul 15 07:38:00 PM PDT 24 |
Finished | Jul 15 07:38:02 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-10577a4d-4943-450f-9f3e-4fd3860475d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979682349 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3979682349 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2787778052 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 468721748 ps |
CPU time | 4.97 seconds |
Started | Jul 15 07:38:00 PM PDT 24 |
Finished | Jul 15 07:38:05 PM PDT 24 |
Peak memory | 211156 kb |
Host | smart-c28e8677-a265-4893-888d-9c73fbde7dc4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787778052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.2787778052 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1684671368 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 331106283 ps |
CPU time | 1.56 seconds |
Started | Jul 15 07:37:57 PM PDT 24 |
Finished | Jul 15 07:37:59 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-97576659-78bf-4399-9f74-396a62ca4a17 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684671368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.1684671368 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2929629097 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 366401098 ps |
CPU time | 3.68 seconds |
Started | Jul 15 07:37:56 PM PDT 24 |
Finished | Jul 15 07:38:01 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-34dcd8fe-50e2-4fa7-8bfd-a765b0104b04 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929629097 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.2929629097 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1947782117 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 104938304 ps |
CPU time | 0.66 seconds |
Started | Jul 15 07:37:58 PM PDT 24 |
Finished | Jul 15 07:38:00 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-14f5c6b0-c341-4f33-a6f3-516d3ad0588a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947782117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.1947782117 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.819371326 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 9118999302 ps |
CPU time | 27.63 seconds |
Started | Jul 15 07:37:58 PM PDT 24 |
Finished | Jul 15 07:38:27 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-bd6ba5bc-b569-48d3-876b-f6f1ba2af17e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819371326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.819371326 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.610610015 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 26376471 ps |
CPU time | 0.79 seconds |
Started | Jul 15 07:37:56 PM PDT 24 |
Finished | Jul 15 07:37:58 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-944f4b24-c32e-48e8-ad6b-beda4de73149 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610610015 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.610610015 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3463372513 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 289451799 ps |
CPU time | 4.95 seconds |
Started | Jul 15 07:38:00 PM PDT 24 |
Finished | Jul 15 07:38:06 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-0d112bc8-fb46-41dd-b5a5-5fb08c105e58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463372513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.3463372513 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3242777866 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 174779708 ps |
CPU time | 2.42 seconds |
Started | Jul 15 07:37:58 PM PDT 24 |
Finished | Jul 15 07:38:01 PM PDT 24 |
Peak memory | 211288 kb |
Host | smart-e21dc6b7-205d-4c5b-983b-3de2a20b9f8f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242777866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.3242777866 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3268186387 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 362484199 ps |
CPU time | 3.7 seconds |
Started | Jul 15 07:38:04 PM PDT 24 |
Finished | Jul 15 07:38:08 PM PDT 24 |
Peak memory | 212396 kb |
Host | smart-2a9d0928-f09a-4240-b952-d9d2aeeb48d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268186387 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3268186387 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.928861431 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 46872933 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:38:06 PM PDT 24 |
Finished | Jul 15 07:38:08 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-1fd1e8e9-7a68-4125-9c60-a0b7158b5b53 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928861431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_csr_rw.928861431 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3765573081 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 4054111082 ps |
CPU time | 26.5 seconds |
Started | Jul 15 07:38:00 PM PDT 24 |
Finished | Jul 15 07:38:28 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-ad423942-045a-4723-a7a0-af0dc156b310 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765573081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3765573081 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.168644154 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 26741222 ps |
CPU time | 0.72 seconds |
Started | Jul 15 07:38:04 PM PDT 24 |
Finished | Jul 15 07:38:06 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-26dd48e3-74ae-4597-a81e-6fd3b1ebe511 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168644154 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.168644154 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1955893552 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 77244670 ps |
CPU time | 3.69 seconds |
Started | Jul 15 07:37:57 PM PDT 24 |
Finished | Jul 15 07:38:01 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-03606bd0-584a-4acd-90be-950a2573489b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955893552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.1955893552 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.899178019 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 774155809 ps |
CPU time | 2.54 seconds |
Started | Jul 15 07:38:04 PM PDT 24 |
Finished | Jul 15 07:38:08 PM PDT 24 |
Peak memory | 211156 kb |
Host | smart-0692ed0c-7d7d-45c7-b2f0-f3100c5b6385 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899178019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.sram_ctrl_tl_intg_err.899178019 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.506034118 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 1443162173 ps |
CPU time | 3.64 seconds |
Started | Jul 15 07:38:06 PM PDT 24 |
Finished | Jul 15 07:38:11 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-0921bafb-708e-4ee5-ae5e-75b7b9a9e790 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506034118 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.506034118 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.223838994 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 15558814 ps |
CPU time | 0.67 seconds |
Started | Jul 15 07:38:06 PM PDT 24 |
Finished | Jul 15 07:38:08 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-8fc16dcd-2176-4642-830b-16cc52f24a35 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223838994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_csr_rw.223838994 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1310134031 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 13185890087 ps |
CPU time | 28.7 seconds |
Started | Jul 15 07:38:05 PM PDT 24 |
Finished | Jul 15 07:38:35 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-ae0be286-d422-4e54-b262-5ec8442eeaee |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310134031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1310134031 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3962426178 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 56005501 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:38:08 PM PDT 24 |
Finished | Jul 15 07:38:10 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-52e75c72-1e44-4eeb-869b-f9f2c5dc4803 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962426178 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3962426178 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1982045696 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 117774462 ps |
CPU time | 3.96 seconds |
Started | Jul 15 07:38:09 PM PDT 24 |
Finished | Jul 15 07:38:14 PM PDT 24 |
Peak memory | 211220 kb |
Host | smart-72257f45-5f52-4a51-b7a6-4e6a4e874d03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982045696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.1982045696 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1858659074 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 152428764 ps |
CPU time | 1.57 seconds |
Started | Jul 15 07:38:09 PM PDT 24 |
Finished | Jul 15 07:38:12 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-592393da-9b02-4daf-ab21-23dc7b663a11 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858659074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.1858659074 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3154287211 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 197274878 ps |
CPU time | 0.76 seconds |
Started | Jul 15 07:37:29 PM PDT 24 |
Finished | Jul 15 07:37:31 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-d5d828c4-42ae-494b-a691-9b1dca2d6b56 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154287211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.3154287211 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3089981031 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 64816775 ps |
CPU time | 1.4 seconds |
Started | Jul 15 07:37:32 PM PDT 24 |
Finished | Jul 15 07:37:34 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-de661587-1617-4e4f-a360-a4858616af25 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089981031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.3089981031 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2407075467 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 17532028 ps |
CPU time | 0.67 seconds |
Started | Jul 15 07:37:31 PM PDT 24 |
Finished | Jul 15 07:37:32 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-3a1e546f-d628-4e7b-976f-dd320baec968 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407075467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.2407075467 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1147676118 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 1453915876 ps |
CPU time | 4.02 seconds |
Started | Jul 15 07:37:31 PM PDT 24 |
Finished | Jul 15 07:37:36 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-5281da31-603a-43c9-8fbb-3b267d0963d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147676118 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1147676118 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3425225354 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 39807427 ps |
CPU time | 0.68 seconds |
Started | Jul 15 07:37:34 PM PDT 24 |
Finished | Jul 15 07:37:36 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-32268137-1b07-440d-9450-6ad4ff5d16d0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425225354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.3425225354 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.228406078 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 7786775733 ps |
CPU time | 27.38 seconds |
Started | Jul 15 07:37:23 PM PDT 24 |
Finished | Jul 15 07:37:52 PM PDT 24 |
Peak memory | 203004 kb |
Host | smart-eeaf868d-5215-49fd-816b-cbe7023a71f5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228406078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.228406078 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.846567899 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 14595492 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:37:29 PM PDT 24 |
Finished | Jul 15 07:37:31 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-80dc3ee2-f1fc-4bad-9833-423e898d42cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846567899 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.846567899 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.538604923 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 45483292 ps |
CPU time | 3.84 seconds |
Started | Jul 15 07:37:23 PM PDT 24 |
Finished | Jul 15 07:37:28 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-01565b96-a7f4-4fb4-a47d-aa1f63bba0b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538604923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.538604923 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.74528837 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 193523418 ps |
CPU time | 2.32 seconds |
Started | Jul 15 07:37:29 PM PDT 24 |
Finished | Jul 15 07:37:32 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-375bfd7d-66c3-437b-836f-d6b018df82fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74528837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.sram_ctrl_tl_intg_err.74528837 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3570108321 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 26443049 ps |
CPU time | 0.68 seconds |
Started | Jul 15 07:37:31 PM PDT 24 |
Finished | Jul 15 07:37:33 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-b92014b7-8cea-49ea-a625-40ff08982b37 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570108321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.3570108321 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1435452931 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 444883750 ps |
CPU time | 1.44 seconds |
Started | Jul 15 07:37:28 PM PDT 24 |
Finished | Jul 15 07:37:31 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-bfcb36e9-c2da-4d0c-a35f-0645b882d063 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435452931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.1435452931 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1956897382 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 14641143 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:37:31 PM PDT 24 |
Finished | Jul 15 07:37:33 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-85910334-a208-4b2b-92c0-f3eeb68fa208 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956897382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1956897382 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2090581495 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 717582874 ps |
CPU time | 3.51 seconds |
Started | Jul 15 07:37:31 PM PDT 24 |
Finished | Jul 15 07:37:36 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-0b3c1143-4f7b-44f3-ad7b-c0f79eca87d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090581495 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2090581495 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3919693525 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 30624797 ps |
CPU time | 0.69 seconds |
Started | Jul 15 07:37:29 PM PDT 24 |
Finished | Jul 15 07:37:30 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-e4559569-f362-4256-bbe0-9839eb7ea434 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919693525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.3919693525 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2188278038 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 29424306838 ps |
CPU time | 57.06 seconds |
Started | Jul 15 07:37:31 PM PDT 24 |
Finished | Jul 15 07:38:28 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-fa1a175b-3f60-4113-83aa-17d6ffdab557 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188278038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2188278038 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4256897583 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 72522407 ps |
CPU time | 0.77 seconds |
Started | Jul 15 07:37:29 PM PDT 24 |
Finished | Jul 15 07:37:30 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-8a9a5725-617e-44d7-b467-27361a9016a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256897583 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.4256897583 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3447844149 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 40901274 ps |
CPU time | 3.57 seconds |
Started | Jul 15 07:37:29 PM PDT 24 |
Finished | Jul 15 07:37:33 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-8202dd34-d85d-4323-aa53-aea1eee10062 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447844149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.3447844149 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1112222281 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 272799120 ps |
CPU time | 2.28 seconds |
Started | Jul 15 07:37:28 PM PDT 24 |
Finished | Jul 15 07:37:30 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-c69da42b-5e04-4a5c-8153-884a00318427 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112222281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.1112222281 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1665591251 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 67800788 ps |
CPU time | 0.75 seconds |
Started | Jul 15 07:37:34 PM PDT 24 |
Finished | Jul 15 07:37:36 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-b227e61e-6a9b-4201-b220-4a8a08d6bdc6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665591251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.1665591251 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1268247682 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 27338477 ps |
CPU time | 1.22 seconds |
Started | Jul 15 07:37:34 PM PDT 24 |
Finished | Jul 15 07:37:37 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-a5891163-0a6a-4928-8690-d38ada42da44 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268247682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.1268247682 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2390933781 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 43044527 ps |
CPU time | 0.67 seconds |
Started | Jul 15 07:37:34 PM PDT 24 |
Finished | Jul 15 07:37:35 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-4c3dccde-85a6-4d6a-8502-0e7167ef361b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390933781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.2390933781 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3426124954 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 2046940704 ps |
CPU time | 4.82 seconds |
Started | Jul 15 07:37:37 PM PDT 24 |
Finished | Jul 15 07:37:42 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-1e5843f9-91fb-4a65-a7da-4647bb523b9f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426124954 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3426124954 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3649512115 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 12372781 ps |
CPU time | 0.66 seconds |
Started | Jul 15 07:37:38 PM PDT 24 |
Finished | Jul 15 07:37:40 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-ace5c936-0fba-4536-a8ca-a2fcfcf0f030 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649512115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.3649512115 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2191654483 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 13616310180 ps |
CPU time | 52.71 seconds |
Started | Jul 15 07:37:29 PM PDT 24 |
Finished | Jul 15 07:38:23 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-28e322bf-3b4d-46be-b146-1f8a2453aae5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191654483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2191654483 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3990675457 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 43994789 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:37:36 PM PDT 24 |
Finished | Jul 15 07:37:37 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-d8b8a0ee-6328-4a37-9da3-03918f114c5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990675457 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3990675457 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.404886455 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 38172504 ps |
CPU time | 3.67 seconds |
Started | Jul 15 07:37:30 PM PDT 24 |
Finished | Jul 15 07:37:34 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-901ab847-d096-43e9-aaa0-07d7d4aa5280 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404886455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.404886455 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4257182936 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 430606772 ps |
CPU time | 1.42 seconds |
Started | Jul 15 07:37:35 PM PDT 24 |
Finished | Jul 15 07:37:37 PM PDT 24 |
Peak memory | 211216 kb |
Host | smart-2f935d97-8628-43a1-ac45-da7bf2ebd7e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257182936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.4257182936 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3647604177 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 355164929 ps |
CPU time | 3.39 seconds |
Started | Jul 15 07:37:35 PM PDT 24 |
Finished | Jul 15 07:37:39 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-28157b93-9715-44af-9a47-32a5adb9a9f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647604177 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3647604177 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.197875442 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 23303011 ps |
CPU time | 0.65 seconds |
Started | Jul 15 07:37:37 PM PDT 24 |
Finished | Jul 15 07:37:38 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-ab0bd309-93ad-4c78-87c2-2cde8769c515 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197875442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_csr_rw.197875442 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2376157473 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 56058581 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:37:36 PM PDT 24 |
Finished | Jul 15 07:37:37 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-29791c78-4be1-47b7-ab45-6fb05ed8fcd2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376157473 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2376157473 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4160947106 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 218303403 ps |
CPU time | 3.86 seconds |
Started | Jul 15 07:37:35 PM PDT 24 |
Finished | Jul 15 07:37:40 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-b98652e4-a390-44a2-bea3-70237fb3ae30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160947106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.4160947106 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.110792966 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 747361423 ps |
CPU time | 2.48 seconds |
Started | Jul 15 07:37:35 PM PDT 24 |
Finished | Jul 15 07:37:39 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-419d2de1-19b8-40eb-8002-99be23144863 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110792966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.sram_ctrl_tl_intg_err.110792966 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.319555412 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 368185473 ps |
CPU time | 3.83 seconds |
Started | Jul 15 07:37:34 PM PDT 24 |
Finished | Jul 15 07:37:39 PM PDT 24 |
Peak memory | 210936 kb |
Host | smart-f94a7a02-8e0d-487c-8b13-6a9678c65a33 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319555412 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.319555412 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3870109587 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 27414413 ps |
CPU time | 0.65 seconds |
Started | Jul 15 07:37:35 PM PDT 24 |
Finished | Jul 15 07:37:37 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-c9766ecf-e0e9-486b-8017-7eb97939c8b2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870109587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.3870109587 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.374134792 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 7177372580 ps |
CPU time | 51.66 seconds |
Started | Jul 15 07:37:35 PM PDT 24 |
Finished | Jul 15 07:38:28 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-df2c0a12-77f5-47d6-af0d-496cf4096e3a |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374134792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.374134792 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3778058095 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 51274980 ps |
CPU time | 0.7 seconds |
Started | Jul 15 07:37:37 PM PDT 24 |
Finished | Jul 15 07:37:39 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-1eef5ffd-c3d5-4acd-ac08-ba38461f4853 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778058095 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3778058095 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2358042586 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 44310943 ps |
CPU time | 3.82 seconds |
Started | Jul 15 07:37:33 PM PDT 24 |
Finished | Jul 15 07:37:38 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-0bb8029e-b4c8-4def-8cfc-fdb6fd0d7322 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358042586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.2358042586 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1469074030 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 1425001924 ps |
CPU time | 3.45 seconds |
Started | Jul 15 07:37:45 PM PDT 24 |
Finished | Jul 15 07:37:49 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-c9c67129-eddc-4abf-a3fe-1763e2913c78 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469074030 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1469074030 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3015018584 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 27211329 ps |
CPU time | 0.72 seconds |
Started | Jul 15 07:37:46 PM PDT 24 |
Finished | Jul 15 07:37:48 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-4e4982fe-e882-4ffc-9c3f-30b393a72c48 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015018584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.3015018584 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2737123464 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 3702641453 ps |
CPU time | 28.92 seconds |
Started | Jul 15 07:37:36 PM PDT 24 |
Finished | Jul 15 07:38:06 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-04c1e31d-f6e6-4054-8163-0094c69bba0d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737123464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2737123464 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1812964877 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 20123224 ps |
CPU time | 0.65 seconds |
Started | Jul 15 07:37:44 PM PDT 24 |
Finished | Jul 15 07:37:45 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-36d27bc9-04e4-4f0f-958f-baf3b72bc990 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812964877 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1812964877 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4078467834 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 310750631 ps |
CPU time | 4.5 seconds |
Started | Jul 15 07:37:35 PM PDT 24 |
Finished | Jul 15 07:37:41 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-118dcbd3-5433-442e-adaf-d928c5cefb82 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078467834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.4078467834 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.612686667 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 988247781 ps |
CPU time | 2.56 seconds |
Started | Jul 15 07:37:37 PM PDT 24 |
Finished | Jul 15 07:37:41 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-54bc2e32-0e96-4860-93bd-1dcc5bf1f455 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612686667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.sram_ctrl_tl_intg_err.612686667 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2459809675 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 350056108 ps |
CPU time | 3.43 seconds |
Started | Jul 15 07:37:45 PM PDT 24 |
Finished | Jul 15 07:37:49 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-90f65a73-db75-4c96-a848-400d7898a9a6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459809675 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2459809675 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.675055792 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 20202737 ps |
CPU time | 0.66 seconds |
Started | Jul 15 07:37:45 PM PDT 24 |
Finished | Jul 15 07:37:46 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-93c316ec-8153-4b9a-a2d5-791252178ad9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675055792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_csr_rw.675055792 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2772964769 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 7076396457 ps |
CPU time | 51.23 seconds |
Started | Jul 15 07:37:46 PM PDT 24 |
Finished | Jul 15 07:38:38 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-ec21a399-a778-44c4-97be-0621eb626e22 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772964769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.2772964769 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1895897493 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 22083487 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:37:47 PM PDT 24 |
Finished | Jul 15 07:37:49 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-d827a1d6-6184-4a72-825c-9a8d7bdd88cc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895897493 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1895897493 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2753108797 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 152311135 ps |
CPU time | 4.05 seconds |
Started | Jul 15 07:37:46 PM PDT 24 |
Finished | Jul 15 07:37:51 PM PDT 24 |
Peak memory | 219292 kb |
Host | smart-25f8d68e-e69d-41ad-bee3-7ba51ca83387 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753108797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.2753108797 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2816935017 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 196298228 ps |
CPU time | 2.32 seconds |
Started | Jul 15 07:37:43 PM PDT 24 |
Finished | Jul 15 07:37:45 PM PDT 24 |
Peak memory | 211208 kb |
Host | smart-21c30b3c-82a8-497c-b5a5-da090aeb5669 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816935017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.2816935017 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3292175415 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 366034666 ps |
CPU time | 4.01 seconds |
Started | Jul 15 07:37:47 PM PDT 24 |
Finished | Jul 15 07:37:52 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-95edc71b-4478-4ade-a01f-0385cb7186e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292175415 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3292175415 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4220434402 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 33817274 ps |
CPU time | 0.63 seconds |
Started | Jul 15 07:37:45 PM PDT 24 |
Finished | Jul 15 07:37:46 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-2535e4b3-87c1-4e3c-b154-ed43d8044315 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220434402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.4220434402 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1190760564 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 3851382465 ps |
CPU time | 28.22 seconds |
Started | Jul 15 07:37:43 PM PDT 24 |
Finished | Jul 15 07:38:12 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-9faf4f0b-d270-472d-ba77-597aac146452 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190760564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1190760564 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2092192595 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 21235942 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:37:44 PM PDT 24 |
Finished | Jul 15 07:37:45 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-f5251606-be43-44ab-a649-e274ff7e3fac |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092192595 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2092192595 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4167013483 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 122672625 ps |
CPU time | 2.6 seconds |
Started | Jul 15 07:37:47 PM PDT 24 |
Finished | Jul 15 07:37:50 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-bf0e3f6c-072f-4081-93ed-81ffe1f9de81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167013483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.4167013483 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1198163821 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 174096532 ps |
CPU time | 2.18 seconds |
Started | Jul 15 07:37:44 PM PDT 24 |
Finished | Jul 15 07:37:47 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-90e0a9f9-db06-4b2b-b283-7b0132318402 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198163821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.1198163821 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1632054833 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 12017661514 ps |
CPU time | 490.11 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:23:38 PM PDT 24 |
Peak memory | 378404 kb |
Host | smart-45903c0f-3e71-4ed1-9047-4c4c72210e4b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632054833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.1632054833 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.3076666249 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 43398487 ps |
CPU time | 0.63 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:15:30 PM PDT 24 |
Peak memory | 202344 kb |
Host | smart-520c0d61-1adb-44ba-9e16-c6759a9b0037 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076666249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3076666249 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.3454260198 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 332015017586 ps |
CPU time | 1985.34 seconds |
Started | Jul 15 06:15:24 PM PDT 24 |
Finished | Jul 15 06:48:31 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-10493d95-8a95-4cd0-9164-2ab65c205ff1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454260198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 3454260198 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.2136084003 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 16262868976 ps |
CPU time | 622.13 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:25:51 PM PDT 24 |
Peak memory | 360948 kb |
Host | smart-b950b10e-1e39-472c-92ec-a74df9badd4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136084003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.2136084003 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.679432845 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 8028762954 ps |
CPU time | 52.73 seconds |
Started | Jul 15 06:15:24 PM PDT 24 |
Finished | Jul 15 06:16:18 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-5d6aafe2-f2d0-4dbe-b705-933a6685da3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679432845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca lation.679432845 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.2305612028 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 791391071 ps |
CPU time | 105.48 seconds |
Started | Jul 15 06:15:20 PM PDT 24 |
Finished | Jul 15 06:17:07 PM PDT 24 |
Peak memory | 370348 kb |
Host | smart-ec6d29da-75cb-4414-8ebf-d3935777110b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305612028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.2305612028 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2782694635 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 9048066079 ps |
CPU time | 151.54 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:17:59 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-53d4c8a7-75af-4d5f-bd41-07fd9886afac |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782694635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.2782694635 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.2015424720 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 55384749703 ps |
CPU time | 354.35 seconds |
Started | Jul 15 06:15:21 PM PDT 24 |
Finished | Jul 15 06:21:17 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-8f2838dc-98f2-4ad5-989e-34d1bbc3717c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015424720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.2015424720 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.1588491646 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 13622007028 ps |
CPU time | 913.51 seconds |
Started | Jul 15 06:15:23 PM PDT 24 |
Finished | Jul 15 06:30:38 PM PDT 24 |
Peak memory | 379700 kb |
Host | smart-a5ffc0ff-cb26-4947-893f-2adf719a36c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588491646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.1588491646 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.1683376623 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 3998386657 ps |
CPU time | 110.25 seconds |
Started | Jul 15 06:15:22 PM PDT 24 |
Finished | Jul 15 06:17:13 PM PDT 24 |
Peak memory | 368136 kb |
Host | smart-4da91dc3-b47e-4070-9e0e-ac3f09552dae |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683376623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.1683376623 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1131284723 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 13969971698 ps |
CPU time | 191.24 seconds |
Started | Jul 15 06:15:25 PM PDT 24 |
Finished | Jul 15 06:18:37 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-9f577a58-0263-4ca6-8ec7-eb3ef3320977 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131284723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.1131284723 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.3377253553 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 361730558 ps |
CPU time | 3.11 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:15:32 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-9fb949eb-6af0-40f6-8420-ba69eaf9854c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377253553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3377253553 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.3110136101 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 9420856384 ps |
CPU time | 577.92 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:25:06 PM PDT 24 |
Peak memory | 369652 kb |
Host | smart-d498fe41-ccfe-484e-9f98-b2efa098d220 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110136101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3110136101 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.2040583542 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 353210769 ps |
CPU time | 2.73 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:15:31 PM PDT 24 |
Peak memory | 222220 kb |
Host | smart-bd65429b-ac2c-4ed6-bd7b-97a3ec2115c7 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040583542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2040583542 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.3001100263 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 5049998721 ps |
CPU time | 134.43 seconds |
Started | Jul 15 06:15:25 PM PDT 24 |
Finished | Jul 15 06:17:40 PM PDT 24 |
Peak memory | 367388 kb |
Host | smart-30fbc983-7e18-42d5-9668-ed8f3c9f1596 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001100263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3001100263 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.3228005331 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 82207991228 ps |
CPU time | 4944.55 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 07:37:54 PM PDT 24 |
Peak memory | 381784 kb |
Host | smart-c188d5eb-117a-4c83-8289-df2e2f0fb5b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228005331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.3228005331 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3843791087 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 3442559209 ps |
CPU time | 63.02 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:16:31 PM PDT 24 |
Peak memory | 258880 kb |
Host | smart-ddbe399a-100b-470e-b8a7-8ee74bae7a69 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3843791087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.3843791087 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.457418340 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 3294145675 ps |
CPU time | 209.01 seconds |
Started | Jul 15 06:15:23 PM PDT 24 |
Finished | Jul 15 06:18:53 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-0b976192-58cd-4b1a-8f49-881c25074e3f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457418340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_stress_pipeline.457418340 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4058640606 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 1874260561 ps |
CPU time | 37.55 seconds |
Started | Jul 15 06:15:22 PM PDT 24 |
Finished | Jul 15 06:16:01 PM PDT 24 |
Peak memory | 290736 kb |
Host | smart-5d8881b2-4011-4ea3-b8aa-2bca8b2418cd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058640606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.4058640606 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.4022796142 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 20723021082 ps |
CPU time | 623.25 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:25:53 PM PDT 24 |
Peak memory | 370844 kb |
Host | smart-58d51e6c-64c0-4ce3-b4d4-0cf9bd06f0c5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022796142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.4022796142 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.1850802393 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 54263729 ps |
CPU time | 0.66 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:15:30 PM PDT 24 |
Peak memory | 202408 kb |
Host | smart-ae13ddbf-34e8-4f6b-bbf5-6b63fd989ceb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850802393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1850802393 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.3338966020 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 279727679271 ps |
CPU time | 1916.96 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:47:25 PM PDT 24 |
Peak memory | 203552 kb |
Host | smart-8f2488fd-3da1-4f70-b0d3-9124c5d0770f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338966020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 3338966020 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.3383621630 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 67895481366 ps |
CPU time | 773.72 seconds |
Started | Jul 15 06:15:30 PM PDT 24 |
Finished | Jul 15 06:28:24 PM PDT 24 |
Peak memory | 379756 kb |
Host | smart-d5a9d920-e04a-4534-a48f-ecd736ef2e0d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383621630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.3383621630 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.2015830032 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 26513424740 ps |
CPU time | 50.06 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:16:27 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-041d42d1-e33f-473a-b38a-eda10a78ff95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015830032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.2015830032 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.3381686917 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 693461327 ps |
CPU time | 10.13 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:15:46 PM PDT 24 |
Peak memory | 228328 kb |
Host | smart-e5397e95-886b-4748-9514-9f5ef6d45f2f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381686917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.3381686917 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1912655233 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 962772490 ps |
CPU time | 63.57 seconds |
Started | Jul 15 06:15:37 PM PDT 24 |
Finished | Jul 15 06:16:41 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-a727e581-7956-4900-a328-23ecb4cd42ba |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912655233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.1912655233 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.388676825 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 3954349113 ps |
CPU time | 127.83 seconds |
Started | Jul 15 06:15:31 PM PDT 24 |
Finished | Jul 15 06:17:39 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-de78ad85-7610-4759-9303-6aeb5d5ef865 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388676825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ mem_walk.388676825 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.3508700526 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 4752951297 ps |
CPU time | 399.67 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:22:08 PM PDT 24 |
Peak memory | 352124 kb |
Host | smart-be64d8a7-fbd2-4597-9b70-09bf6bfb569b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508700526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.3508700526 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.2618235077 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 996398138 ps |
CPU time | 29.71 seconds |
Started | Jul 15 06:15:22 PM PDT 24 |
Finished | Jul 15 06:15:53 PM PDT 24 |
Peak memory | 275444 kb |
Host | smart-1b44f115-eb80-40a4-985b-af1069a45664 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618235077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.2618235077 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1381201939 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 208537543394 ps |
CPU time | 549.44 seconds |
Started | Jul 15 06:15:36 PM PDT 24 |
Finished | Jul 15 06:24:46 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-fd5760f5-eb42-4793-bad1-c87cd9b2e794 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381201939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.1381201939 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.2974009968 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 1343803437 ps |
CPU time | 3.54 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:15:32 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-18915287-c79d-4f02-9acf-788544650178 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974009968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2974009968 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.3036178807 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 6454126088 ps |
CPU time | 542.02 seconds |
Started | Jul 15 06:15:30 PM PDT 24 |
Finished | Jul 15 06:24:32 PM PDT 24 |
Peak memory | 377464 kb |
Host | smart-dfffc80a-7daa-4ae1-9dd0-0876f066133f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036178807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3036178807 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.1723494584 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 508731603 ps |
CPU time | 3.42 seconds |
Started | Jul 15 06:15:29 PM PDT 24 |
Finished | Jul 15 06:15:34 PM PDT 24 |
Peak memory | 222368 kb |
Host | smart-a8e8b372-f6ac-4467-9195-100e4a95e71c |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723494584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1723494584 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.638155746 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 3020593110 ps |
CPU time | 9.76 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:15:37 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-7456b56e-ca51-483d-a883-8d12e10f8694 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638155746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.638155746 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.2447825702 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 80405113812 ps |
CPU time | 5059.99 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 07:39:50 PM PDT 24 |
Peak memory | 380704 kb |
Host | smart-dd5d729b-cd8c-4b1c-8573-a13ef8b80fed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447825702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.2447825702 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1707657716 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 397339845 ps |
CPU time | 10.63 seconds |
Started | Jul 15 06:15:36 PM PDT 24 |
Finished | Jul 15 06:15:48 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-8a854453-315b-4f4e-b892-93d6cdc25b5e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1707657716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.1707657716 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3283920612 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 10941339149 ps |
CPU time | 379.01 seconds |
Started | Jul 15 06:15:25 PM PDT 24 |
Finished | Jul 15 06:21:45 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-7514e831-301a-4d3f-8aee-148e2b3da046 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283920612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.3283920612 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1891105154 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 3611957897 ps |
CPU time | 34.15 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:16:04 PM PDT 24 |
Peak memory | 284580 kb |
Host | smart-0e11f183-6bad-4cb0-b6b3-71d070c79e5b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891105154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1891105154 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1453032916 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 65839482762 ps |
CPU time | 1194.25 seconds |
Started | Jul 15 06:15:56 PM PDT 24 |
Finished | Jul 15 06:35:51 PM PDT 24 |
Peak memory | 377612 kb |
Host | smart-8333b30e-9ad9-48a6-9e6a-a0eb3dd93500 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453032916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.1453032916 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.3927310203 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 16781973 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 06:16:02 PM PDT 24 |
Peak memory | 202368 kb |
Host | smart-e87c6724-4cb4-4770-9033-3ab83a348df3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927310203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3927310203 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.3315832196 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 13920912880 ps |
CPU time | 566.52 seconds |
Started | Jul 15 06:15:59 PM PDT 24 |
Finished | Jul 15 06:25:26 PM PDT 24 |
Peak memory | 203672 kb |
Host | smart-bf586c3e-6405-42e9-b5b8-85e6b50d6382 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315832196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .3315832196 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.2742191250 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 3421852371 ps |
CPU time | 653.85 seconds |
Started | Jul 15 06:15:59 PM PDT 24 |
Finished | Jul 15 06:26:54 PM PDT 24 |
Peak memory | 378616 kb |
Host | smart-9efe0529-d159-4101-a5af-fa21820d328b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742191250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.2742191250 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.892690311 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 10763397534 ps |
CPU time | 66.7 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 06:17:07 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-3a778ddb-642a-4eb9-94f3-3799ddfd17c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892690311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esc alation.892690311 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.3254343733 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 3478734027 ps |
CPU time | 47.71 seconds |
Started | Jul 15 06:15:56 PM PDT 24 |
Finished | Jul 15 06:16:44 PM PDT 24 |
Peak memory | 310336 kb |
Host | smart-f554891a-23bd-419f-ab59-ee370442aaf6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254343733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.3254343733 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3776248629 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 7010487535 ps |
CPU time | 150.52 seconds |
Started | Jul 15 06:15:54 PM PDT 24 |
Finished | Jul 15 06:18:26 PM PDT 24 |
Peak memory | 219112 kb |
Host | smart-0ce8e28e-01f4-4320-948d-f32c0c50386e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776248629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.3776248629 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.1227516495 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 2500772364 ps |
CPU time | 134.18 seconds |
Started | Jul 15 06:15:55 PM PDT 24 |
Finished | Jul 15 06:18:10 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-fa2c1ff3-bbc5-479e-99bc-533d66862ea5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227516495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.1227516495 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.841884090 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 35623392852 ps |
CPU time | 835.05 seconds |
Started | Jul 15 06:15:57 PM PDT 24 |
Finished | Jul 15 06:29:53 PM PDT 24 |
Peak memory | 376800 kb |
Host | smart-0b9a36d5-c423-446c-b3c9-d9c545b6979c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841884090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip le_keys.841884090 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.1538003550 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 715988856 ps |
CPU time | 5.95 seconds |
Started | Jul 15 06:15:55 PM PDT 24 |
Finished | Jul 15 06:16:02 PM PDT 24 |
Peak memory | 202492 kb |
Host | smart-fedc35bb-d8f4-4d4e-b814-a6ade2158da9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538003550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.1538003550 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2811805790 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 13079036091 ps |
CPU time | 330.94 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 06:21:31 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-37e2adb2-0d91-4efd-8f04-f590e811fdc3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811805790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.2811805790 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.3156643839 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 1767563032 ps |
CPU time | 3.88 seconds |
Started | Jul 15 06:15:55 PM PDT 24 |
Finished | Jul 15 06:16:00 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-145b8add-5bd6-491e-b97a-a930c9d4e643 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156643839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3156643839 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.1668172483 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 8570331987 ps |
CPU time | 112.92 seconds |
Started | Jul 15 06:15:55 PM PDT 24 |
Finished | Jul 15 06:17:48 PM PDT 24 |
Peak memory | 307408 kb |
Host | smart-4ee17c79-2180-47d6-822b-a66ad273419a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668172483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1668172483 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.239928886 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 9486044683 ps |
CPU time | 57.9 seconds |
Started | Jul 15 06:15:56 PM PDT 24 |
Finished | Jul 15 06:16:54 PM PDT 24 |
Peak memory | 320436 kb |
Host | smart-4b7bfb4b-8be9-4e3f-b322-dc8dbfbe5827 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239928886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.239928886 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.214960167 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 1558882040497 ps |
CPU time | 8335.53 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 08:34:57 PM PDT 24 |
Peak memory | 382796 kb |
Host | smart-f31f57c2-dd75-491f-bfeb-b6dbfb0308b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214960167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_stress_all.214960167 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.984932013 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 1591801435 ps |
CPU time | 13.91 seconds |
Started | Jul 15 06:15:58 PM PDT 24 |
Finished | Jul 15 06:16:13 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-ffe4cafb-3855-4a35-ab07-01736c61cb23 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=984932013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.984932013 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.473029691 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 24253877693 ps |
CPU time | 256.25 seconds |
Started | Jul 15 06:15:54 PM PDT 24 |
Finished | Jul 15 06:20:11 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-6b7acdfd-411a-4af2-be7b-f884eb28f8c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473029691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_stress_pipeline.473029691 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.780458446 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 1552274000 ps |
CPU time | 86.32 seconds |
Started | Jul 15 06:15:57 PM PDT 24 |
Finished | Jul 15 06:17:25 PM PDT 24 |
Peak memory | 337676 kb |
Host | smart-d73a0f47-b70c-4ccf-b991-29564f4c5cd2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780458446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.780458446 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3041299624 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 18753154360 ps |
CPU time | 826.09 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 06:29:47 PM PDT 24 |
Peak memory | 378640 kb |
Host | smart-7f90d063-e7e9-4f02-a582-6704ef6f6e00 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041299624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3041299624 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.3452099635 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 26611151 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 06:16:02 PM PDT 24 |
Peak memory | 202324 kb |
Host | smart-925808de-8f3d-4b37-af6e-e4a1f6fdfcc0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452099635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3452099635 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.1429988920 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 26529444869 ps |
CPU time | 501.79 seconds |
Started | Jul 15 06:15:56 PM PDT 24 |
Finished | Jul 15 06:24:18 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-57149c6d-09b5-40d9-8eea-fe5301dd0302 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429988920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .1429988920 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.667909965 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 5867944916 ps |
CPU time | 875.61 seconds |
Started | Jul 15 06:15:58 PM PDT 24 |
Finished | Jul 15 06:30:35 PM PDT 24 |
Peak memory | 376624 kb |
Host | smart-a4cb2369-b33a-48bd-a47d-4e78008917e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667909965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executabl e.667909965 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1781506247 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 5747757372 ps |
CPU time | 8.34 seconds |
Started | Jul 15 06:15:58 PM PDT 24 |
Finished | Jul 15 06:16:07 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-1c3d0e85-1bc2-42b7-a4e9-519ca9a34b16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781506247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1781506247 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.1383947403 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 740734487 ps |
CPU time | 20.44 seconds |
Started | Jul 15 06:15:57 PM PDT 24 |
Finished | Jul 15 06:16:18 PM PDT 24 |
Peak memory | 262160 kb |
Host | smart-e62c7acf-0315-4db6-a646-07df9722e21c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383947403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.1383947403 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.156543499 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 3179932406 ps |
CPU time | 120.93 seconds |
Started | Jul 15 06:15:56 PM PDT 24 |
Finished | Jul 15 06:17:57 PM PDT 24 |
Peak memory | 219108 kb |
Host | smart-94f0afd6-fa37-4dcd-b897-f11ae199012b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156543499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sram_ctrl_mem_partial_access.156543499 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.704573121 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 37469788278 ps |
CPU time | 167.9 seconds |
Started | Jul 15 06:15:57 PM PDT 24 |
Finished | Jul 15 06:18:46 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-afd7f2a4-9d2d-48e6-9332-6bd570465ab6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704573121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl _mem_walk.704573121 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.1100476675 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 7526349445 ps |
CPU time | 184.8 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 06:19:06 PM PDT 24 |
Peak memory | 316540 kb |
Host | smart-7af253ae-70ca-4929-9a51-8fe661bf2ab3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100476675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.1100476675 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.2245331593 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 1907592905 ps |
CPU time | 20.99 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 06:16:22 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-39707ec0-a6f1-4ee2-a785-df94b7eacaf2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245331593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.2245331593 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3353920659 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 7474865202 ps |
CPU time | 394 seconds |
Started | Jul 15 06:15:54 PM PDT 24 |
Finished | Jul 15 06:22:29 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-96f20ebc-94cd-427e-8298-f1db79ab2169 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353920659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.3353920659 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.1963793375 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 14323548090 ps |
CPU time | 1259.7 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 06:37:01 PM PDT 24 |
Peak memory | 378696 kb |
Host | smart-88932502-aea3-45a7-9200-3043c73f1790 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963793375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1963793375 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.3612163356 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 882571902 ps |
CPU time | 5.44 seconds |
Started | Jul 15 06:15:54 PM PDT 24 |
Finished | Jul 15 06:16:00 PM PDT 24 |
Peak memory | 208620 kb |
Host | smart-2877abba-f020-4706-bf07-141077d6484b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612163356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3612163356 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.1622674734 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 613731065732 ps |
CPU time | 3989.51 seconds |
Started | Jul 15 06:15:59 PM PDT 24 |
Finished | Jul 15 07:22:30 PM PDT 24 |
Peak memory | 380036 kb |
Host | smart-c7e0f203-b97d-44b7-acd0-2c9eb03643ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622674734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.1622674734 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.365809935 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 1626934813 ps |
CPU time | 44.25 seconds |
Started | Jul 15 06:15:59 PM PDT 24 |
Finished | Jul 15 06:16:44 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-b95588be-6b40-4836-9dcd-48cf684c83a3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=365809935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.365809935 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2998659559 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 3212786751 ps |
CPU time | 208.34 seconds |
Started | Jul 15 06:15:56 PM PDT 24 |
Finished | Jul 15 06:19:25 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-91ff9118-b776-4545-9429-4527f284c383 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998659559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.2998659559 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3265408073 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 3068510419 ps |
CPU time | 37.85 seconds |
Started | Jul 15 06:15:59 PM PDT 24 |
Finished | Jul 15 06:16:37 PM PDT 24 |
Peak memory | 300896 kb |
Host | smart-331043ca-f060-48c1-92fc-18b40b4610f4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265408073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3265408073 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1048003274 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 7535532956 ps |
CPU time | 674.55 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:27:18 PM PDT 24 |
Peak memory | 378656 kb |
Host | smart-4ad5ba59-d1f4-455c-8929-3ba201cb871b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048003274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.1048003274 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.3612490794 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 51361406 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:16:04 PM PDT 24 |
Peak memory | 202332 kb |
Host | smart-029b9a3c-7f8b-490f-b9e4-334f8ce64976 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612490794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3612490794 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.1505855952 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 141211282862 ps |
CPU time | 1152.55 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:35:16 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-195954b2-a858-49f0-a021-98e58aea335c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505855952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .1505855952 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.1728101723 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 47210769461 ps |
CPU time | 1363.14 seconds |
Started | Jul 15 06:16:04 PM PDT 24 |
Finished | Jul 15 06:38:48 PM PDT 24 |
Peak memory | 377684 kb |
Host | smart-77c416d3-16e1-4ea1-a52d-035bc10f6fbd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728101723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.1728101723 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.3454955476 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 41830585549 ps |
CPU time | 26.89 seconds |
Started | Jul 15 06:16:00 PM PDT 24 |
Finished | Jul 15 06:16:28 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-fdd9b642-a827-42d6-b499-827f7cee91fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454955476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.3454955476 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.574189842 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 1057368158 ps |
CPU time | 73.49 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:17:17 PM PDT 24 |
Peak memory | 341708 kb |
Host | smart-1a3b36a2-b0c3-4357-bee2-3ffb68f57830 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574189842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.sram_ctrl_max_throughput.574189842 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.4280444350 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 23135201371 ps |
CPU time | 172.5 seconds |
Started | Jul 15 06:16:03 PM PDT 24 |
Finished | Jul 15 06:18:57 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-8bcbb52c-7b3d-46b6-b57c-c93e2c2e0562 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280444350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.4280444350 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.3849001448 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 5257366718 ps |
CPU time | 285.81 seconds |
Started | Jul 15 06:16:03 PM PDT 24 |
Finished | Jul 15 06:20:50 PM PDT 24 |
Peak memory | 211340 kb |
Host | smart-d94a61c3-0a86-4481-b2db-b4ce245f7d03 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849001448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.3849001448 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.30079507 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 25295762005 ps |
CPU time | 1337.08 seconds |
Started | Jul 15 06:15:58 PM PDT 24 |
Finished | Jul 15 06:38:16 PM PDT 24 |
Peak memory | 373568 kb |
Host | smart-7eb57684-3879-4f47-87fd-ba8b0881e959 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30079507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multipl e_keys.30079507 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.1467984479 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 6041326964 ps |
CPU time | 21.5 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:16:25 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-b07db2e8-e203-46e1-b9a9-7f7abb63919d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467984479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.1467984479 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3454697621 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 83106617178 ps |
CPU time | 365.27 seconds |
Started | Jul 15 06:15:59 PM PDT 24 |
Finished | Jul 15 06:22:05 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-df79674a-219e-45dd-99bb-87fe0057658f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454697621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.3454697621 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.1007270168 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 1411170715 ps |
CPU time | 3.44 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:16:06 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-f15cbf96-5971-4bf3-b76d-b94f3acf2bc1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007270168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1007270168 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.2285076159 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 2587049477 ps |
CPU time | 474.65 seconds |
Started | Jul 15 06:16:01 PM PDT 24 |
Finished | Jul 15 06:23:57 PM PDT 24 |
Peak memory | 372464 kb |
Host | smart-c76f1423-6431-4cad-aa53-980f31294b1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285076159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2285076159 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.1162190849 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 939888003 ps |
CPU time | 20.09 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:16:23 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-d8ae8985-358b-4ce2-b136-e7538f9b1c44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162190849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1162190849 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.1779910248 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 770085462151 ps |
CPU time | 7474.57 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 08:20:42 PM PDT 24 |
Peak memory | 382832 kb |
Host | smart-5e054fda-2f54-4c44-8c35-d9eb65834c73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779910248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.1779910248 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4152759878 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 7504839256 ps |
CPU time | 70.38 seconds |
Started | Jul 15 06:16:03 PM PDT 24 |
Finished | Jul 15 06:17:15 PM PDT 24 |
Peak memory | 323476 kb |
Host | smart-dee43c0c-ea7c-4c69-a345-925d9c9ee1b2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152759878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.4152759878 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.310568348 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 14020168760 ps |
CPU time | 1315.59 seconds |
Started | Jul 15 06:16:03 PM PDT 24 |
Finished | Jul 15 06:38:00 PM PDT 24 |
Peak memory | 377580 kb |
Host | smart-8542c7c1-79e0-4da5-aaa2-49030f936805 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310568348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 13.sram_ctrl_access_during_key_req.310568348 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.1729584750 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 19745300 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:16:01 PM PDT 24 |
Finished | Jul 15 06:16:03 PM PDT 24 |
Peak memory | 202500 kb |
Host | smart-0fd31064-c7ca-496f-8391-410d4bc39f45 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729584750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1729584750 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.916689073 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 28084712778 ps |
CPU time | 2013.57 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:49:37 PM PDT 24 |
Peak memory | 203704 kb |
Host | smart-b68c102f-af38-4779-ab78-3e4f240447c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916689073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection. 916689073 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.1998938218 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 8950317467 ps |
CPU time | 1236.76 seconds |
Started | Jul 15 06:16:04 PM PDT 24 |
Finished | Jul 15 06:36:42 PM PDT 24 |
Peak memory | 379620 kb |
Host | smart-ccc56b1f-b840-4183-9fc4-94043f0c0fa2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998938218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.1998938218 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.17890667 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 9216233971 ps |
CPU time | 59.23 seconds |
Started | Jul 15 06:16:01 PM PDT 24 |
Finished | Jul 15 06:17:01 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-4b07bf7b-164c-4165-bbc1-ec6b47b8577d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17890667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_esca lation.17890667 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.4108868558 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 845597323 ps |
CPU time | 122.33 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 06:18:09 PM PDT 24 |
Peak memory | 369344 kb |
Host | smart-3de4d7c6-ef01-4c0c-8743-3097bc51b560 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108868558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.4108868558 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3363280580 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 1628235529 ps |
CPU time | 123.49 seconds |
Started | Jul 15 06:16:03 PM PDT 24 |
Finished | Jul 15 06:18:08 PM PDT 24 |
Peak memory | 210852 kb |
Host | smart-ae1d5d5b-1fae-423d-9522-771ef214e1a8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363280580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.3363280580 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.2672562224 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 30075618169 ps |
CPU time | 155.43 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 06:18:41 PM PDT 24 |
Peak memory | 210892 kb |
Host | smart-85a2dbcd-5846-4afa-bdd9-d3624dbf5fc9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672562224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.2672562224 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.569176082 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 4482707655 ps |
CPU time | 272.57 seconds |
Started | Jul 15 06:16:01 PM PDT 24 |
Finished | Jul 15 06:20:34 PM PDT 24 |
Peak memory | 336748 kb |
Host | smart-ea300943-9b49-4120-aa6e-4093c1a0e875 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569176082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip le_keys.569176082 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.1651407971 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 745417039 ps |
CPU time | 9.46 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 06:16:16 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-9a6238d3-ca48-4f07-92f1-718983570122 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651407971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.1651407971 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1283172391 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 7195760080 ps |
CPU time | 392.83 seconds |
Started | Jul 15 06:16:04 PM PDT 24 |
Finished | Jul 15 06:22:38 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-f349aaf4-3f1e-4fd8-ab11-2502f87f7da0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283172391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.1283172391 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.1805599298 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 361477620 ps |
CPU time | 3.29 seconds |
Started | Jul 15 06:16:04 PM PDT 24 |
Finished | Jul 15 06:16:09 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-83145dbc-3206-4195-9a23-cbde538279a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805599298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1805599298 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.3539983248 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 27253667352 ps |
CPU time | 848.82 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 06:30:15 PM PDT 24 |
Peak memory | 375572 kb |
Host | smart-ca7d8ccd-8ef4-4cd3-87f9-3a8e3ba81998 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539983248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3539983248 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.2527246623 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 486140750 ps |
CPU time | 13.58 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 06:16:20 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-b4d15c4a-f11c-4480-9eae-db54ceb19cbe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527246623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2527246623 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.2443816811 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 178577939098 ps |
CPU time | 2362.42 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 06:55:29 PM PDT 24 |
Peak memory | 381196 kb |
Host | smart-f0032359-788e-4571-b4cd-32f5bac0f841 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443816811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.2443816811 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1425700114 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 2619115367 ps |
CPU time | 68.36 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:17:18 PM PDT 24 |
Peak memory | 218776 kb |
Host | smart-d0b78349-a6ca-43f4-aa08-ca34717f8b18 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1425700114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1425700114 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3388947759 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 29486667913 ps |
CPU time | 356.97 seconds |
Started | Jul 15 06:16:01 PM PDT 24 |
Finished | Jul 15 06:21:59 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-24ee28d9-6fd9-4037-8c45-c171f16d061d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388947759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.3388947759 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1895504318 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 1466778934 ps |
CPU time | 25.83 seconds |
Started | Jul 15 06:16:03 PM PDT 24 |
Finished | Jul 15 06:16:30 PM PDT 24 |
Peak memory | 278232 kb |
Host | smart-fe488c8c-6e84-45ee-a345-e3ea6f833518 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895504318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1895504318 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.424802670 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 378798270330 ps |
CPU time | 1959.67 seconds |
Started | Jul 15 06:16:04 PM PDT 24 |
Finished | Jul 15 06:48:45 PM PDT 24 |
Peak memory | 379672 kb |
Host | smart-37c6e8d9-fcd6-47d2-8b09-f107ac49fbaa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424802670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_access_during_key_req.424802670 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.3135899981 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 34665208 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:16:11 PM PDT 24 |
Peak memory | 202344 kb |
Host | smart-fba4506c-0dc2-4f7f-bce1-463fbe4e2e05 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135899981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3135899981 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.2526021435 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 74321220261 ps |
CPU time | 1161.75 seconds |
Started | Jul 15 06:16:01 PM PDT 24 |
Finished | Jul 15 06:35:24 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-036ba1e3-02b7-4ef7-ad14-ba7853cb75f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526021435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .2526021435 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.3497737001 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 37894189674 ps |
CPU time | 152.89 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 06:18:39 PM PDT 24 |
Peak memory | 274924 kb |
Host | smart-bd28822e-85f2-425e-98cf-68b39078ff78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497737001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.3497737001 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.368819494 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 51314100732 ps |
CPU time | 75.46 seconds |
Started | Jul 15 06:16:04 PM PDT 24 |
Finished | Jul 15 06:17:21 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-0cb8b6b3-59b8-43b9-9c47-4ad5a7c8a287 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368819494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_esc alation.368819494 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.1698799970 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 2695467361 ps |
CPU time | 6.62 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:16:17 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-8e47510f-7ff3-41bd-92b3-72312ba4523e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698799970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.1698799970 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3684264108 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 5024526316 ps |
CPU time | 168.32 seconds |
Started | Jul 15 06:16:08 PM PDT 24 |
Finished | Jul 15 06:18:57 PM PDT 24 |
Peak memory | 219048 kb |
Host | smart-f5b2362e-de1d-424c-99de-f4ea737e9321 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684264108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3684264108 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.1860448089 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 159045938982 ps |
CPU time | 385.79 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:22:35 PM PDT 24 |
Peak memory | 210884 kb |
Host | smart-523956e5-4828-4337-ba40-b96de0052394 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860448089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.1860448089 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.989083194 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 20301236829 ps |
CPU time | 1417.99 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 06:39:44 PM PDT 24 |
Peak memory | 373624 kb |
Host | smart-02da8f4e-cdf0-4cf0-8248-4eb9b6fdc69a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989083194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multip le_keys.989083194 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.1078348259 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 4421379156 ps |
CPU time | 159.05 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:18:42 PM PDT 24 |
Peak memory | 369364 kb |
Host | smart-4285a716-9060-4926-9af6-0ea5a15f7eb7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078348259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.1078348259 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1904232120 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 73839756811 ps |
CPU time | 479.56 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:24:09 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-9c949e5a-e894-45ba-b2af-027716d0dff7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904232120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.1904232120 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.2588707243 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 346407630 ps |
CPU time | 3.13 seconds |
Started | Jul 15 06:16:06 PM PDT 24 |
Finished | Jul 15 06:16:10 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-6ba89697-5108-4f32-9c4d-2cc08cd179dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588707243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2588707243 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.383152220 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 16044558757 ps |
CPU time | 492.37 seconds |
Started | Jul 15 06:16:01 PM PDT 24 |
Finished | Jul 15 06:24:14 PM PDT 24 |
Peak memory | 380452 kb |
Host | smart-ea665fe1-4f4c-48ee-bcda-75e571b90461 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383152220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.383152220 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.130939340 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 1310322134 ps |
CPU time | 20.06 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:16:23 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-5144f76d-39c2-4aa0-a26d-2b80916c479b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130939340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.130939340 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.3016923634 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 116728638807 ps |
CPU time | 3840.74 seconds |
Started | Jul 15 06:16:07 PM PDT 24 |
Finished | Jul 15 07:20:09 PM PDT 24 |
Peak memory | 379700 kb |
Host | smart-2c40b366-9e4a-4394-a545-66ac37fff211 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016923634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.3016923634 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.453305110 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 1996631452 ps |
CPU time | 91.66 seconds |
Started | Jul 15 06:16:07 PM PDT 24 |
Finished | Jul 15 06:17:39 PM PDT 24 |
Peak memory | 303536 kb |
Host | smart-1ad7d942-98ca-4a81-ab71-6c23ed42d3be |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=453305110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.453305110 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3085126976 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 60486935415 ps |
CPU time | 346.63 seconds |
Started | Jul 15 06:16:05 PM PDT 24 |
Finished | Jul 15 06:21:52 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-b1af19a2-69bf-4229-8c35-b113331697d7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085126976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.3085126976 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3574491616 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 3503849276 ps |
CPU time | 102.84 seconds |
Started | Jul 15 06:16:02 PM PDT 24 |
Finished | Jul 15 06:17:46 PM PDT 24 |
Peak memory | 358168 kb |
Host | smart-95c6d5e5-a7f5-464f-84d5-1ac101d7e030 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574491616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3574491616 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.874325898 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 22959617611 ps |
CPU time | 1100.8 seconds |
Started | Jul 15 06:16:08 PM PDT 24 |
Finished | Jul 15 06:34:30 PM PDT 24 |
Peak memory | 378620 kb |
Host | smart-cb0ada69-b5b9-4b0d-bf31-bd9d2aad2be1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874325898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_access_during_key_req.874325898 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.493836361 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 34545917 ps |
CPU time | 0.68 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:16:11 PM PDT 24 |
Peak memory | 202312 kb |
Host | smart-400fd6a4-f090-45fb-8f10-2cdbe2769641 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493836361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.493836361 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.2290689361 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 19270586506 ps |
CPU time | 1297.33 seconds |
Started | Jul 15 06:16:10 PM PDT 24 |
Finished | Jul 15 06:37:48 PM PDT 24 |
Peak memory | 203552 kb |
Host | smart-841e5955-ffac-47a9-ba66-90703e17c5c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290689361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .2290689361 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.944904107 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 22086458144 ps |
CPU time | 1275.37 seconds |
Started | Jul 15 06:16:11 PM PDT 24 |
Finished | Jul 15 06:37:27 PM PDT 24 |
Peak memory | 375520 kb |
Host | smart-80a451b9-8718-42b3-8844-7fa5a975ba81 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944904107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executabl e.944904107 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.4002014915 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 66837785786 ps |
CPU time | 60.89 seconds |
Started | Jul 15 06:16:08 PM PDT 24 |
Finished | Jul 15 06:17:10 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-5b7382a0-3d81-42f4-bf26-c5be207cb045 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002014915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.4002014915 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.4021501602 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 2770879176 ps |
CPU time | 6.22 seconds |
Started | Jul 15 06:16:10 PM PDT 24 |
Finished | Jul 15 06:16:17 PM PDT 24 |
Peak memory | 202668 kb |
Host | smart-19586d65-f127-4ec5-8853-9042407d5cc1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021501602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.4021501602 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2120258543 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 5789123219 ps |
CPU time | 77.87 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:17:28 PM PDT 24 |
Peak memory | 219108 kb |
Host | smart-036be50b-c691-4023-a994-4e608be10709 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120258543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.2120258543 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.2374148772 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 2713294785 ps |
CPU time | 152.27 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:18:42 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-76dd4723-f476-434b-ba03-4d952e6ed49f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374148772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.2374148772 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.2426743822 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 60418014592 ps |
CPU time | 1008.23 seconds |
Started | Jul 15 06:16:10 PM PDT 24 |
Finished | Jul 15 06:32:59 PM PDT 24 |
Peak memory | 375548 kb |
Host | smart-8fb230ce-d4ff-46ea-8b24-d19cb384f847 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426743822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.2426743822 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.2992938302 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 1256427627 ps |
CPU time | 19.17 seconds |
Started | Jul 15 06:16:08 PM PDT 24 |
Finished | Jul 15 06:16:28 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-6dc1bfaa-3175-4101-b191-72e9963451f0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992938302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.2992938302 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.500950350 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 4122961876 ps |
CPU time | 250.84 seconds |
Started | Jul 15 06:16:07 PM PDT 24 |
Finished | Jul 15 06:20:19 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-c1711261-1089-4e8e-a02b-d82850a9bd2c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500950350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.sram_ctrl_partial_access_b2b.500950350 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.2037433508 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 1405598122 ps |
CPU time | 3.45 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:16:13 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-6a85ca25-041a-4764-b65e-447ccbc618c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037433508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2037433508 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.2223933730 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 19287699274 ps |
CPU time | 985.49 seconds |
Started | Jul 15 06:16:08 PM PDT 24 |
Finished | Jul 15 06:32:34 PM PDT 24 |
Peak memory | 377608 kb |
Host | smart-959b9e2a-7929-4596-b854-192bcd949d7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223933730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2223933730 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.2374486872 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 10739037248 ps |
CPU time | 25.59 seconds |
Started | Jul 15 06:16:07 PM PDT 24 |
Finished | Jul 15 06:16:33 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-8b9cae31-5a0d-49a8-be86-406568f8f323 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374486872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2374486872 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.2840584349 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 160199052382 ps |
CPU time | 3170.59 seconds |
Started | Jul 15 06:16:08 PM PDT 24 |
Finished | Jul 15 07:09:00 PM PDT 24 |
Peak memory | 382016 kb |
Host | smart-2d74c47f-9dab-4a72-b23e-024787ff3a06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840584349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.2840584349 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3704923828 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 1616067654 ps |
CPU time | 27.83 seconds |
Started | Jul 15 06:16:09 PM PDT 24 |
Finished | Jul 15 06:16:37 PM PDT 24 |
Peak memory | 253984 kb |
Host | smart-9887c145-d58b-40e0-8df1-fdd4fbca5e3d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3704923828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3704923828 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2491924360 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 2920299512 ps |
CPU time | 163.65 seconds |
Started | Jul 15 06:16:08 PM PDT 24 |
Finished | Jul 15 06:18:52 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-02171ef5-2625-4098-bf8d-fa10bbc1ed48 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491924360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.2491924360 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.857218590 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 1080430342 ps |
CPU time | 137.21 seconds |
Started | Jul 15 06:16:10 PM PDT 24 |
Finished | Jul 15 06:18:28 PM PDT 24 |
Peak memory | 370344 kb |
Host | smart-076f2284-641b-4171-a279-4a9f62e5fee8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857218590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.857218590 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.310335921 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 10774564387 ps |
CPU time | 496.91 seconds |
Started | Jul 15 06:16:17 PM PDT 24 |
Finished | Jul 15 06:24:34 PM PDT 24 |
Peak memory | 372488 kb |
Host | smart-b1c47312-6c79-4c50-a5aa-9d520e87cab9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310335921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_access_during_key_req.310335921 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.2839713728 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 27749811 ps |
CPU time | 0.63 seconds |
Started | Jul 15 06:16:20 PM PDT 24 |
Finished | Jul 15 06:16:21 PM PDT 24 |
Peak memory | 202136 kb |
Host | smart-8bbd1f06-7661-4297-a202-1a368550968f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839713728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.2839713728 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.2673419626 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 298854213150 ps |
CPU time | 2954.27 seconds |
Started | Jul 15 06:16:08 PM PDT 24 |
Finished | Jul 15 07:05:23 PM PDT 24 |
Peak memory | 203440 kb |
Host | smart-04befc79-ad37-4780-ba6e-78c7ae94d012 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673419626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .2673419626 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.3114847737 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 22940899945 ps |
CPU time | 415.42 seconds |
Started | Jul 15 06:16:18 PM PDT 24 |
Finished | Jul 15 06:23:14 PM PDT 24 |
Peak memory | 361244 kb |
Host | smart-61aca50f-7ae3-42cc-a248-f850328b0295 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114847737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.3114847737 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.2014579303 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 9820495658 ps |
CPU time | 34.59 seconds |
Started | Jul 15 06:16:17 PM PDT 24 |
Finished | Jul 15 06:16:52 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-c745f78d-4c3c-4750-894f-bfc4daac8cb9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014579303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2014579303 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.152575374 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 3156365088 ps |
CPU time | 17.09 seconds |
Started | Jul 15 06:16:16 PM PDT 24 |
Finished | Jul 15 06:16:33 PM PDT 24 |
Peak memory | 251924 kb |
Host | smart-0760962f-59e0-4ee2-960e-416ca5fc99ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152575374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.sram_ctrl_max_throughput.152575374 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.274902697 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 1022529581 ps |
CPU time | 63.49 seconds |
Started | Jul 15 06:16:18 PM PDT 24 |
Finished | Jul 15 06:17:22 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-f073f400-f4b9-45e0-a03e-a6c4bced8a36 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274902697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_mem_partial_access.274902697 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.4003510125 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 28244933867 ps |
CPU time | 302.85 seconds |
Started | Jul 15 06:16:18 PM PDT 24 |
Finished | Jul 15 06:21:21 PM PDT 24 |
Peak memory | 211516 kb |
Host | smart-0d3186f2-4238-4443-acc6-3e4573072485 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003510125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.4003510125 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.3413830206 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 51167917903 ps |
CPU time | 733.7 seconds |
Started | Jul 15 06:16:07 PM PDT 24 |
Finished | Jul 15 06:28:21 PM PDT 24 |
Peak memory | 380432 kb |
Host | smart-af7a7c0a-65c5-4618-a24f-5b428001cf87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413830206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.3413830206 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.1274985687 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 2289882305 ps |
CPU time | 22.2 seconds |
Started | Jul 15 06:16:17 PM PDT 24 |
Finished | Jul 15 06:16:40 PM PDT 24 |
Peak memory | 268276 kb |
Host | smart-6b5dc9b0-a0ee-46be-8685-20a062410d1e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274985687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.1274985687 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3335153566 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 133657549671 ps |
CPU time | 314.4 seconds |
Started | Jul 15 06:16:17 PM PDT 24 |
Finished | Jul 15 06:21:32 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-c3a7b773-ae21-4328-a2d7-14d271f8e80e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335153566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.3335153566 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.540510752 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 741304985 ps |
CPU time | 3.47 seconds |
Started | Jul 15 06:16:19 PM PDT 24 |
Finished | Jul 15 06:16:23 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-57b61f4a-704c-47d4-bf01-c40a458584ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540510752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.540510752 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.1530985692 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 14474160436 ps |
CPU time | 817.68 seconds |
Started | Jul 15 06:16:15 PM PDT 24 |
Finished | Jul 15 06:29:53 PM PDT 24 |
Peak memory | 380756 kb |
Host | smart-54bcf69e-e5e6-477e-a6f4-9b84eb5fb56e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530985692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1530985692 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.837453149 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 2386682117 ps |
CPU time | 102.67 seconds |
Started | Jul 15 06:16:10 PM PDT 24 |
Finished | Jul 15 06:17:54 PM PDT 24 |
Peak memory | 337948 kb |
Host | smart-67904a5c-603a-4b70-ac55-2ef2244af8a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837453149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.837453149 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.2967017189 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 390319022217 ps |
CPU time | 5102.87 seconds |
Started | Jul 15 06:16:15 PM PDT 24 |
Finished | Jul 15 07:41:19 PM PDT 24 |
Peak memory | 380756 kb |
Host | smart-00644d01-0879-44d8-acc7-8ef26d58a0fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967017189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.2967017189 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2356852985 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 1028451113 ps |
CPU time | 70.63 seconds |
Started | Jul 15 06:16:18 PM PDT 24 |
Finished | Jul 15 06:17:29 PM PDT 24 |
Peak memory | 308708 kb |
Host | smart-8d68046c-fa9c-44f4-b8b7-40d2bd355f25 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2356852985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2356852985 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3406417169 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 18857061946 ps |
CPU time | 313.28 seconds |
Started | Jul 15 06:16:10 PM PDT 24 |
Finished | Jul 15 06:21:24 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-18d9f586-3428-422b-8d97-36be5250380d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406417169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.3406417169 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3912604366 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 704318646 ps |
CPU time | 9.01 seconds |
Started | Jul 15 06:16:17 PM PDT 24 |
Finished | Jul 15 06:16:27 PM PDT 24 |
Peak memory | 220660 kb |
Host | smart-765fd059-02f4-44f9-9143-3bb9f3bbb575 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912604366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.3912604366 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.247977014 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 54152048804 ps |
CPU time | 1005.61 seconds |
Started | Jul 15 06:16:22 PM PDT 24 |
Finished | Jul 15 06:33:09 PM PDT 24 |
Peak memory | 379700 kb |
Host | smart-bf130dbe-3941-4da3-82a0-0b193f22af4f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247977014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_access_during_key_req.247977014 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.3317700142 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 37430449 ps |
CPU time | 0.64 seconds |
Started | Jul 15 06:16:23 PM PDT 24 |
Finished | Jul 15 06:16:24 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-4b39f990-8480-44ad-8633-7e7149a68eed |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317700142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.3317700142 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.3100721438 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 194747323116 ps |
CPU time | 2436.45 seconds |
Started | Jul 15 06:16:17 PM PDT 24 |
Finished | Jul 15 06:56:54 PM PDT 24 |
Peak memory | 203460 kb |
Host | smart-554ce0f0-00eb-4d92-9270-a7f12cdb4b85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100721438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .3100721438 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.1821520218 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 147623236431 ps |
CPU time | 1921.28 seconds |
Started | Jul 15 06:16:23 PM PDT 24 |
Finished | Jul 15 06:48:25 PM PDT 24 |
Peak memory | 379744 kb |
Host | smart-620b8ec7-a02e-4656-aeb4-04258f9acfe6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821520218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.1821520218 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.3840968300 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 12563138427 ps |
CPU time | 70.46 seconds |
Started | Jul 15 06:16:26 PM PDT 24 |
Finished | Jul 15 06:17:38 PM PDT 24 |
Peak memory | 215988 kb |
Host | smart-7646938b-804c-4c78-88db-86de4e8d87d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840968300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.3840968300 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.617147259 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 746328419 ps |
CPU time | 17.6 seconds |
Started | Jul 15 06:16:25 PM PDT 24 |
Finished | Jul 15 06:16:43 PM PDT 24 |
Peak memory | 253024 kb |
Host | smart-ec25015b-1d2e-4db6-89b6-5a422d17408d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617147259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.sram_ctrl_max_throughput.617147259 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1091745169 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 3104749939 ps |
CPU time | 83.6 seconds |
Started | Jul 15 06:16:25 PM PDT 24 |
Finished | Jul 15 06:17:49 PM PDT 24 |
Peak memory | 219152 kb |
Host | smart-59cbf682-37ca-4c02-8aeb-474d8254b778 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091745169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.1091745169 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.1973669655 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 8045556404 ps |
CPU time | 267.76 seconds |
Started | Jul 15 06:16:22 PM PDT 24 |
Finished | Jul 15 06:20:50 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-24c0430f-a187-4299-9719-347aaa59bb6f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973669655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.1973669655 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.1563377426 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 69319224012 ps |
CPU time | 902.43 seconds |
Started | Jul 15 06:16:18 PM PDT 24 |
Finished | Jul 15 06:31:22 PM PDT 24 |
Peak memory | 368492 kb |
Host | smart-cca1c9b9-7e6b-400d-ac1b-b78b18d7df65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563377426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1563377426 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.2932744844 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 3145077062 ps |
CPU time | 13.9 seconds |
Started | Jul 15 06:16:20 PM PDT 24 |
Finished | Jul 15 06:16:34 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-56e9785a-b575-4f94-9831-c892fd978a8d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932744844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.2932744844 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1040679403 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 112237322639 ps |
CPU time | 340.71 seconds |
Started | Jul 15 06:16:20 PM PDT 24 |
Finished | Jul 15 06:22:01 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-5fadfa13-8cb6-4305-906c-9b842ffed1c3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040679403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.1040679403 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.863921024 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 343950259 ps |
CPU time | 3.17 seconds |
Started | Jul 15 06:16:20 PM PDT 24 |
Finished | Jul 15 06:16:24 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-9a48e704-e723-4961-8228-667b0b8e340d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863921024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.863921024 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.1930831603 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 38770309360 ps |
CPU time | 555.54 seconds |
Started | Jul 15 06:16:27 PM PDT 24 |
Finished | Jul 15 06:25:43 PM PDT 24 |
Peak memory | 368404 kb |
Host | smart-4d8ae08e-bac4-416a-bdb9-8ec47f190b19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930831603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1930831603 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.2876924951 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 525800204 ps |
CPU time | 14.92 seconds |
Started | Jul 15 06:16:16 PM PDT 24 |
Finished | Jul 15 06:16:31 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-394b637c-632f-4013-8ae4-24580bd3bc98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876924951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2876924951 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.3190507697 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 663985812157 ps |
CPU time | 5482.11 seconds |
Started | Jul 15 06:16:21 PM PDT 24 |
Finished | Jul 15 07:47:44 PM PDT 24 |
Peak memory | 380720 kb |
Host | smart-89fb5625-dffe-4376-878f-60f71a9d3e6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190507697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.3190507697 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4251986063 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 745848254 ps |
CPU time | 19.39 seconds |
Started | Jul 15 06:16:25 PM PDT 24 |
Finished | Jul 15 06:16:45 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-17638703-a955-4805-84d2-c690491ca623 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4251986063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.4251986063 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3614080733 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 34397227986 ps |
CPU time | 154.24 seconds |
Started | Jul 15 06:16:16 PM PDT 24 |
Finished | Jul 15 06:18:51 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-46444f84-97b1-41f5-aa64-8adc6b165788 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614080733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.3614080733 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2280052934 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 1529063010 ps |
CPU time | 53.83 seconds |
Started | Jul 15 06:16:25 PM PDT 24 |
Finished | Jul 15 06:17:19 PM PDT 24 |
Peak memory | 319252 kb |
Host | smart-2073a700-e546-41f1-aa04-88017b3f45f6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280052934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.2280052934 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.2498297608 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 15034903 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:16:28 PM PDT 24 |
Finished | Jul 15 06:16:30 PM PDT 24 |
Peak memory | 202320 kb |
Host | smart-6c5de1c2-69ce-4499-b08b-dcb6fa205b1d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498297608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2498297608 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.1910571458 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 17749484239 ps |
CPU time | 1213.52 seconds |
Started | Jul 15 06:16:24 PM PDT 24 |
Finished | Jul 15 06:36:39 PM PDT 24 |
Peak memory | 203540 kb |
Host | smart-b7dbcd00-f516-42a3-8e0f-aa13e30a2043 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910571458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .1910571458 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.973205392 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 10189754109 ps |
CPU time | 939.71 seconds |
Started | Jul 15 06:16:26 PM PDT 24 |
Finished | Jul 15 06:32:07 PM PDT 24 |
Peak memory | 376596 kb |
Host | smart-cf26b1d1-0843-448c-bcd4-739e3d577e52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973205392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executabl e.973205392 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.3327201172 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 6397663964 ps |
CPU time | 39.82 seconds |
Started | Jul 15 06:16:26 PM PDT 24 |
Finished | Jul 15 06:17:07 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-caebf7b5-03e3-4c82-978d-b30cf1bc70e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327201172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.3327201172 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.1142806392 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 3154403896 ps |
CPU time | 122.57 seconds |
Started | Jul 15 06:16:23 PM PDT 24 |
Finished | Jul 15 06:18:27 PM PDT 24 |
Peak memory | 358024 kb |
Host | smart-37e3a52c-43e3-4aa0-9c25-e43214ae6f97 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142806392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.1142806392 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.812490705 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 5255604581 ps |
CPU time | 159.93 seconds |
Started | Jul 15 06:16:30 PM PDT 24 |
Finished | Jul 15 06:19:11 PM PDT 24 |
Peak memory | 219088 kb |
Host | smart-114c70f8-5580-4aac-8fdd-dc28d6b57048 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812490705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sram_ctrl_mem_partial_access.812490705 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.1716031183 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 18712953362 ps |
CPU time | 331.64 seconds |
Started | Jul 15 06:16:30 PM PDT 24 |
Finished | Jul 15 06:22:03 PM PDT 24 |
Peak memory | 203792 kb |
Host | smart-7383c68b-bb74-405f-9cbc-4389763b960b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716031183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.1716031183 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.2388905404 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 5350023312 ps |
CPU time | 288.57 seconds |
Started | Jul 15 06:16:22 PM PDT 24 |
Finished | Jul 15 06:21:11 PM PDT 24 |
Peak memory | 367356 kb |
Host | smart-8a3cc198-5b17-4de6-ab17-50761bdf40a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388905404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.2388905404 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.2756388893 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 6425403736 ps |
CPU time | 26.09 seconds |
Started | Jul 15 06:16:26 PM PDT 24 |
Finished | Jul 15 06:16:53 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-4d73662f-e306-4a05-a561-faf6e8826f16 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756388893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.2756388893 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1546527030 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 9225850065 ps |
CPU time | 248.01 seconds |
Started | Jul 15 06:16:26 PM PDT 24 |
Finished | Jul 15 06:20:35 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-172c4210-dc29-4d1c-b900-d2eb9d6b5b77 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546527030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.1546527030 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.2935381108 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 678976904 ps |
CPU time | 3.32 seconds |
Started | Jul 15 06:16:31 PM PDT 24 |
Finished | Jul 15 06:16:35 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-bf112a9e-6657-4ef3-8540-dec443d350a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935381108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2935381108 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.4053781288 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 29272115517 ps |
CPU time | 1038.96 seconds |
Started | Jul 15 06:16:24 PM PDT 24 |
Finished | Jul 15 06:33:43 PM PDT 24 |
Peak memory | 359232 kb |
Host | smart-022e9918-9b99-4091-b313-cc6400e895ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053781288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.4053781288 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.2491734778 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 477312020 ps |
CPU time | 7.21 seconds |
Started | Jul 15 06:16:23 PM PDT 24 |
Finished | Jul 15 06:16:31 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-d68b70f2-a826-48fe-b662-9c3366660b0d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491734778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2491734778 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2227263867 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 3212552602 ps |
CPU time | 12.69 seconds |
Started | Jul 15 06:16:30 PM PDT 24 |
Finished | Jul 15 06:16:44 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-268a609e-c5b9-4721-a8b3-989b4cf5213d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2227263867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2227263867 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.690437722 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 3433332902 ps |
CPU time | 201.06 seconds |
Started | Jul 15 06:16:24 PM PDT 24 |
Finished | Jul 15 06:19:46 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-9fd6ae5f-07e6-4cc2-8146-185db67ccc22 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690437722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sram_ctrl_stress_pipeline.690437722 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3083291597 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 926493833 ps |
CPU time | 124.59 seconds |
Started | Jul 15 06:16:23 PM PDT 24 |
Finished | Jul 15 06:18:28 PM PDT 24 |
Peak memory | 370340 kb |
Host | smart-c4a33e21-d159-4c7f-abcd-190259b8f591 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083291597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3083291597 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.2041061283 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 58567057565 ps |
CPU time | 806.19 seconds |
Started | Jul 15 06:16:30 PM PDT 24 |
Finished | Jul 15 06:29:58 PM PDT 24 |
Peak memory | 379668 kb |
Host | smart-9326fdc2-de9b-42d7-bd41-7f9730f0b972 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041061283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.2041061283 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.1658907983 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 39255204 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:16:38 PM PDT 24 |
Finished | Jul 15 06:16:39 PM PDT 24 |
Peak memory | 202252 kb |
Host | smart-7c9e0de7-c0a8-4a7b-ac69-88e23290981e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658907983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1658907983 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.3394187803 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 20014427529 ps |
CPU time | 1374.47 seconds |
Started | Jul 15 06:16:29 PM PDT 24 |
Finished | Jul 15 06:39:25 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-615f2ff7-a623-491b-8043-ed4ce53bed6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394187803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .3394187803 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.239142686 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 11100362736 ps |
CPU time | 463.89 seconds |
Started | Jul 15 06:16:27 PM PDT 24 |
Finished | Jul 15 06:24:12 PM PDT 24 |
Peak memory | 369432 kb |
Host | smart-b3c455de-e5ba-4087-adbe-6d61000a0557 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239142686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl e.239142686 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.1085353300 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 74252273390 ps |
CPU time | 117.85 seconds |
Started | Jul 15 06:16:29 PM PDT 24 |
Finished | Jul 15 06:18:28 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-95deaf7e-2bda-474f-b917-ce01227be189 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085353300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.1085353300 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.1325677756 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 756422529 ps |
CPU time | 61.13 seconds |
Started | Jul 15 06:16:29 PM PDT 24 |
Finished | Jul 15 06:17:31 PM PDT 24 |
Peak memory | 322400 kb |
Host | smart-64c5e090-a048-485a-963c-04c3cc7ddc30 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325677756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.1325677756 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1242357786 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 2995112788 ps |
CPU time | 83.64 seconds |
Started | Jul 15 06:16:35 PM PDT 24 |
Finished | Jul 15 06:17:59 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-bb626344-8993-4bb3-8911-219a713d4ca5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242357786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.1242357786 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.2875399016 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 39039464671 ps |
CPU time | 328.87 seconds |
Started | Jul 15 06:16:36 PM PDT 24 |
Finished | Jul 15 06:22:05 PM PDT 24 |
Peak memory | 210936 kb |
Host | smart-e318abd5-f35e-4471-8bfd-e6a196ef4955 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875399016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.2875399016 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.1040669838 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 40309656459 ps |
CPU time | 1123.16 seconds |
Started | Jul 15 06:16:30 PM PDT 24 |
Finished | Jul 15 06:35:15 PM PDT 24 |
Peak memory | 374460 kb |
Host | smart-d7caa5e4-a312-415c-9bba-ea9c2083e9e2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040669838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.1040669838 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.447189350 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 893013671 ps |
CPU time | 122.35 seconds |
Started | Jul 15 06:16:29 PM PDT 24 |
Finished | Jul 15 06:18:32 PM PDT 24 |
Peak memory | 368228 kb |
Host | smart-6807a4b5-cce4-49cc-a7a7-c088ba9d9cad |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447189350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s ram_ctrl_partial_access.447189350 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3813677248 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 13971095225 ps |
CPU time | 238.44 seconds |
Started | Jul 15 06:16:32 PM PDT 24 |
Finished | Jul 15 06:20:31 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-70d8fdcb-da50-4d99-b0fc-bd04a9a5a1cd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813677248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.3813677248 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.2469979837 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 1356360287 ps |
CPU time | 3.62 seconds |
Started | Jul 15 06:16:31 PM PDT 24 |
Finished | Jul 15 06:16:36 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-ff3f08c3-bb6e-4589-8002-a64559a19cc7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469979837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2469979837 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.750879907 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 835627906 ps |
CPU time | 201.94 seconds |
Started | Jul 15 06:16:29 PM PDT 24 |
Finished | Jul 15 06:19:53 PM PDT 24 |
Peak memory | 369500 kb |
Host | smart-f970d522-a16c-495c-b6bf-1fe1ab677336 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750879907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.750879907 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.86523981 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 10365468635 ps |
CPU time | 16.64 seconds |
Started | Jul 15 06:16:29 PM PDT 24 |
Finished | Jul 15 06:16:47 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-62382ae0-8e2b-4510-88d5-17a197d68bb9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86523981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.86523981 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.1933814332 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 663689081471 ps |
CPU time | 5151.77 seconds |
Started | Jul 15 06:16:36 PM PDT 24 |
Finished | Jul 15 07:42:29 PM PDT 24 |
Peak memory | 381152 kb |
Host | smart-b22716ec-d0d5-47fa-8a24-c7b9fac89d6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933814332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.1933814332 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4173183134 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 3346603571 ps |
CPU time | 47.42 seconds |
Started | Jul 15 06:16:38 PM PDT 24 |
Finished | Jul 15 06:17:25 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-7634e84f-96f4-4381-8195-5ebb53f56919 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4173183134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.4173183134 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3611906780 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 14564721935 ps |
CPU time | 415.1 seconds |
Started | Jul 15 06:16:29 PM PDT 24 |
Finished | Jul 15 06:23:26 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-049d1399-d2f8-4cfd-8471-4f1a46121095 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611906780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.3611906780 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2407162762 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 741454530 ps |
CPU time | 47.67 seconds |
Started | Jul 15 06:16:28 PM PDT 24 |
Finished | Jul 15 06:17:17 PM PDT 24 |
Peak memory | 295384 kb |
Host | smart-38e6932b-62bc-4caf-a112-a9c150664627 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407162762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.2407162762 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3509956009 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 44751348366 ps |
CPU time | 737.76 seconds |
Started | Jul 15 06:15:31 PM PDT 24 |
Finished | Jul 15 06:27:49 PM PDT 24 |
Peak memory | 369384 kb |
Host | smart-cf25fc66-a26b-4f7b-8e38-2c7bf99d3560 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509956009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.3509956009 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.3056360029 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 17246490 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:15:29 PM PDT 24 |
Finished | Jul 15 06:15:31 PM PDT 24 |
Peak memory | 202528 kb |
Host | smart-cbb647f9-fb29-49fe-96d0-61e75b3f53dd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056360029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3056360029 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.869045402 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 127183065982 ps |
CPU time | 2430.21 seconds |
Started | Jul 15 06:15:36 PM PDT 24 |
Finished | Jul 15 06:56:08 PM PDT 24 |
Peak memory | 203660 kb |
Host | smart-80f742d0-c97d-4b4c-a895-001605549509 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869045402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.869045402 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.3322999870 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 16614758655 ps |
CPU time | 240.4 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:19:30 PM PDT 24 |
Peak memory | 354044 kb |
Host | smart-c1922ae0-0a2b-4859-a58a-23e0a6387230 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322999870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.3322999870 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.821532862 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 2557010698 ps |
CPU time | 16.22 seconds |
Started | Jul 15 06:15:29 PM PDT 24 |
Finished | Jul 15 06:15:47 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-bf5d0f18-7e81-4670-a715-2c916d73ca45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821532862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esca lation.821532862 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.2554092501 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 842738951 ps |
CPU time | 107.78 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:17:17 PM PDT 24 |
Peak memory | 370376 kb |
Host | smart-e0eaef34-d24f-4edc-916a-5859da5c5049 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554092501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.2554092501 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.4076135138 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 1842419955 ps |
CPU time | 126.03 seconds |
Started | Jul 15 06:15:29 PM PDT 24 |
Finished | Jul 15 06:17:36 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-eecea61e-100b-46f7-89ac-cb5c61be1a9e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076135138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.4076135138 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.2170890268 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 74870485579 ps |
CPU time | 369.12 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:21:45 PM PDT 24 |
Peak memory | 204108 kb |
Host | smart-fcaddb9f-930a-42f5-83ec-0796ea163349 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170890268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.2170890268 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.259529629 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 17125238572 ps |
CPU time | 588.64 seconds |
Started | Jul 15 06:15:31 PM PDT 24 |
Finished | Jul 15 06:25:21 PM PDT 24 |
Peak memory | 350052 kb |
Host | smart-60718c3c-da47-48f8-9818-50d210443ba5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259529629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multipl e_keys.259529629 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.352034435 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 5023525895 ps |
CPU time | 70.36 seconds |
Started | Jul 15 06:15:39 PM PDT 24 |
Finished | Jul 15 06:16:50 PM PDT 24 |
Peak memory | 331500 kb |
Host | smart-9d7ba4bd-94b2-4ac2-a9bd-f362d8122f7b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352034435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sr am_ctrl_partial_access.352034435 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1541733141 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 8415870980 ps |
CPU time | 446.73 seconds |
Started | Jul 15 06:15:30 PM PDT 24 |
Finished | Jul 15 06:22:57 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-89cffde4-70c0-4673-b68a-49996ea4c453 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541733141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.1541733141 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.3825831467 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 711572735 ps |
CPU time | 3.25 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:15:32 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-390dc8aa-cd79-4f77-8fc3-24962ff1aacc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825831467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3825831467 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.2610216769 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 17403299419 ps |
CPU time | 1076.03 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:33:26 PM PDT 24 |
Peak memory | 372816 kb |
Host | smart-6c7a3064-5363-4b4a-8412-8acac8bc797c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610216769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2610216769 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.1758763232 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 286339359 ps |
CPU time | 1.93 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:15:32 PM PDT 24 |
Peak memory | 222312 kb |
Host | smart-c08c103d-d73a-4a8a-b992-0aa574bdae6d |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758763232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1758763232 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.502481070 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 1410868499 ps |
CPU time | 23.89 seconds |
Started | Jul 15 06:15:36 PM PDT 24 |
Finished | Jul 15 06:16:01 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-fcac6422-d588-4f0a-a538-0c4fd4824393 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502481070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.502481070 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.709395487 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 397911871305 ps |
CPU time | 4697.19 seconds |
Started | Jul 15 06:15:31 PM PDT 24 |
Finished | Jul 15 07:33:50 PM PDT 24 |
Peak memory | 360440 kb |
Host | smart-9981c621-66fb-43e2-9517-06c1c5b49f2b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709395487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_stress_all.709395487 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.865449120 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 204916370 ps |
CPU time | 10.15 seconds |
Started | Jul 15 06:15:29 PM PDT 24 |
Finished | Jul 15 06:15:40 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-e09e82aa-0c62-4cbd-8ffc-4aa17ed9fbb1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=865449120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.865449120 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3302385550 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 4391429232 ps |
CPU time | 188.64 seconds |
Started | Jul 15 06:15:28 PM PDT 24 |
Finished | Jul 15 06:18:38 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-8f159b01-d1e1-4422-845f-4921500fdc5c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302385550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.3302385550 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3703878657 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 704465798 ps |
CPU time | 6.35 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:15:43 PM PDT 24 |
Peak memory | 210916 kb |
Host | smart-dfeff314-d506-47ff-9877-c60581e1b942 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703878657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3703878657 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.4189881195 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 8582352344 ps |
CPU time | 400 seconds |
Started | Jul 15 06:16:44 PM PDT 24 |
Finished | Jul 15 06:23:25 PM PDT 24 |
Peak memory | 356616 kb |
Host | smart-f2209f26-7d43-4582-8a46-9879507b1b52 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189881195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.4189881195 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.291761589 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 22448443 ps |
CPU time | 0.67 seconds |
Started | Jul 15 06:16:43 PM PDT 24 |
Finished | Jul 15 06:16:45 PM PDT 24 |
Peak memory | 202484 kb |
Host | smart-3fbd1d16-ff9c-42c1-bad2-cd284bced151 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291761589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.291761589 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.3227399269 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 216067155201 ps |
CPU time | 1061.72 seconds |
Started | Jul 15 06:16:40 PM PDT 24 |
Finished | Jul 15 06:34:22 PM PDT 24 |
Peak memory | 203456 kb |
Host | smart-51048840-2c1f-48a7-8d05-2f3c136e7e61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227399269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .3227399269 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.697104579 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 25986020249 ps |
CPU time | 598.82 seconds |
Started | Jul 15 06:16:51 PM PDT 24 |
Finished | Jul 15 06:26:51 PM PDT 24 |
Peak memory | 377696 kb |
Host | smart-0f281acf-1d76-4ffe-9120-883155910e90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697104579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executabl e.697104579 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.2124775513 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 18977099608 ps |
CPU time | 60.36 seconds |
Started | Jul 15 06:16:40 PM PDT 24 |
Finished | Jul 15 06:17:41 PM PDT 24 |
Peak memory | 215924 kb |
Host | smart-8e232ed0-bfb8-468b-ba41-aa7e68d5392d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124775513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.2124775513 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.2957012439 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 2917857424 ps |
CPU time | 39.78 seconds |
Started | Jul 15 06:16:42 PM PDT 24 |
Finished | Jul 15 06:17:22 PM PDT 24 |
Peak memory | 309812 kb |
Host | smart-8f77f643-9f65-42e0-b9ba-70b591000ba6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957012439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.2957012439 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3564697664 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 1632083287 ps |
CPU time | 126.04 seconds |
Started | Jul 15 06:16:51 PM PDT 24 |
Finished | Jul 15 06:18:57 PM PDT 24 |
Peak memory | 218980 kb |
Host | smart-904d51cd-0ffc-452f-9ceb-16ae8c0cf664 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564697664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.3564697664 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.2646735227 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 103569719907 ps |
CPU time | 178.67 seconds |
Started | Jul 15 06:16:43 PM PDT 24 |
Finished | Jul 15 06:19:42 PM PDT 24 |
Peak memory | 210868 kb |
Host | smart-081af2db-313e-4c0a-ac9b-540425458bee |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646735227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.2646735227 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.3502802506 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 10289308896 ps |
CPU time | 1210.12 seconds |
Started | Jul 15 06:16:36 PM PDT 24 |
Finished | Jul 15 06:36:47 PM PDT 24 |
Peak memory | 376616 kb |
Host | smart-dca860af-b6a7-4573-a71a-ba2a2f1dc366 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502802506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.3502802506 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.1661726814 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 1353387395 ps |
CPU time | 20.4 seconds |
Started | Jul 15 06:16:37 PM PDT 24 |
Finished | Jul 15 06:16:58 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-5b23ce49-31e2-4501-bb41-25dda9cfe183 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661726814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.1661726814 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3608599389 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 68739889089 ps |
CPU time | 434.06 seconds |
Started | Jul 15 06:16:36 PM PDT 24 |
Finished | Jul 15 06:23:50 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-49a06db8-9827-4dd2-a297-b3f604e3546e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608599389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.3608599389 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.3750390778 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1352099927 ps |
CPU time | 3.18 seconds |
Started | Jul 15 06:16:43 PM PDT 24 |
Finished | Jul 15 06:16:47 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-808b40e7-9142-4a9b-9a58-5ee26a286e25 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750390778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3750390778 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.3789776845 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 4025403865 ps |
CPU time | 153.47 seconds |
Started | Jul 15 06:16:49 PM PDT 24 |
Finished | Jul 15 06:19:23 PM PDT 24 |
Peak memory | 366232 kb |
Host | smart-8dc0ed23-ac8f-4aa2-a971-ab7c10ea7744 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789776845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3789776845 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.4271525519 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 935401333 ps |
CPU time | 8.01 seconds |
Started | Jul 15 06:16:36 PM PDT 24 |
Finished | Jul 15 06:16:45 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-0de8fe33-9114-473a-a800-dd78930e4df4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271525519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4271525519 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.995815276 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 767410601 ps |
CPU time | 21.73 seconds |
Started | Jul 15 06:16:42 PM PDT 24 |
Finished | Jul 15 06:17:04 PM PDT 24 |
Peak memory | 213096 kb |
Host | smart-e4606376-e44e-4f0c-a3a9-e1e866456690 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=995815276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.995815276 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1217502950 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 14495103892 ps |
CPU time | 257.66 seconds |
Started | Jul 15 06:16:38 PM PDT 24 |
Finished | Jul 15 06:20:56 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-3b6cb631-e465-4280-b7c1-1eb5ceb5d9dd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217502950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.1217502950 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3902169046 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 759567196 ps |
CPU time | 25.28 seconds |
Started | Jul 15 06:16:42 PM PDT 24 |
Finished | Jul 15 06:17:08 PM PDT 24 |
Peak memory | 278268 kb |
Host | smart-f60f38ca-896d-4f63-b4fb-f7c254af7957 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902169046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3902169046 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3053866304 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 27146908609 ps |
CPU time | 150.06 seconds |
Started | Jul 15 06:16:44 PM PDT 24 |
Finished | Jul 15 06:19:15 PM PDT 24 |
Peak memory | 339576 kb |
Host | smart-ce2aef13-e8af-4993-bf30-0689b7cfe024 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053866304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.3053866304 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.1001263273 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 14072385 ps |
CPU time | 0.66 seconds |
Started | Jul 15 06:16:53 PM PDT 24 |
Finished | Jul 15 06:16:54 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-23386452-d8b1-40c5-bd32-479f88607957 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001263273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1001263273 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.307373685 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 177855704673 ps |
CPU time | 2983.53 seconds |
Started | Jul 15 06:16:41 PM PDT 24 |
Finished | Jul 15 07:06:25 PM PDT 24 |
Peak memory | 203636 kb |
Host | smart-6e604a81-1443-49ef-9072-3f4b864c9c45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307373685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection. 307373685 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.1910308945 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 14209228811 ps |
CPU time | 1946.6 seconds |
Started | Jul 15 06:16:42 PM PDT 24 |
Finished | Jul 15 06:49:10 PM PDT 24 |
Peak memory | 380776 kb |
Host | smart-33a3d13b-d788-4f19-80d8-9920be9b8308 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910308945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.1910308945 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.3202075728 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 15700300894 ps |
CPU time | 94.03 seconds |
Started | Jul 15 06:16:42 PM PDT 24 |
Finished | Jul 15 06:18:16 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-944da2a2-99c7-48b3-9848-ae7ba867f41d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202075728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.3202075728 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.102564225 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 2995547854 ps |
CPU time | 74.48 seconds |
Started | Jul 15 06:16:51 PM PDT 24 |
Finished | Jul 15 06:18:05 PM PDT 24 |
Peak memory | 345992 kb |
Host | smart-3bc16e27-bff2-4fd7-94e9-2a6cf1c6f412 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102564225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.sram_ctrl_max_throughput.102564225 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3936500193 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 2716608242 ps |
CPU time | 85.52 seconds |
Started | Jul 15 06:16:54 PM PDT 24 |
Finished | Jul 15 06:18:20 PM PDT 24 |
Peak memory | 219084 kb |
Host | smart-614bf84c-f96c-4fdd-8f8e-60dce6ef88be |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936500193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.3936500193 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.1831251930 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 28877527018 ps |
CPU time | 177.36 seconds |
Started | Jul 15 06:16:50 PM PDT 24 |
Finished | Jul 15 06:19:47 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-43968762-1a3d-4096-9c0a-1a54eef54a77 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831251930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.1831251930 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.4274233637 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 77227233481 ps |
CPU time | 1298.1 seconds |
Started | Jul 15 06:16:45 PM PDT 24 |
Finished | Jul 15 06:38:24 PM PDT 24 |
Peak memory | 378752 kb |
Host | smart-863baa00-c3eb-44c7-8818-fee720ae4a3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274233637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.4274233637 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.879323217 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 5895203290 ps |
CPU time | 17.81 seconds |
Started | Jul 15 06:16:51 PM PDT 24 |
Finished | Jul 15 06:17:09 PM PDT 24 |
Peak memory | 239892 kb |
Host | smart-126b6998-46ca-4812-b376-1e903bc4a942 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879323217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.s ram_ctrl_partial_access.879323217 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2046739555 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 9588703869 ps |
CPU time | 512.75 seconds |
Started | Jul 15 06:16:42 PM PDT 24 |
Finished | Jul 15 06:25:16 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-afb63186-5d72-43ac-a549-5951f7a18933 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046739555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.2046739555 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.620913660 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 713254963 ps |
CPU time | 3.29 seconds |
Started | Jul 15 06:16:43 PM PDT 24 |
Finished | Jul 15 06:16:47 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-57b02fb8-2eb1-4abe-9804-e0963f825bab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620913660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.620913660 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.2462167600 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 9289131859 ps |
CPU time | 988.68 seconds |
Started | Jul 15 06:16:43 PM PDT 24 |
Finished | Jul 15 06:33:12 PM PDT 24 |
Peak memory | 380732 kb |
Host | smart-7e99cdf5-6079-4f99-9d7c-49ca8a04f471 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462167600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2462167600 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.904627857 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 1583491162 ps |
CPU time | 141.15 seconds |
Started | Jul 15 06:16:43 PM PDT 24 |
Finished | Jul 15 06:19:05 PM PDT 24 |
Peak memory | 367304 kb |
Host | smart-921dbc36-cf38-4759-a037-9ecbc655d8e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904627857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.904627857 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.4051962703 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 2093204019402 ps |
CPU time | 7140.44 seconds |
Started | Jul 15 06:16:51 PM PDT 24 |
Finished | Jul 15 08:15:53 PM PDT 24 |
Peak memory | 378812 kb |
Host | smart-51d3ed59-cf21-4430-b361-713abfef9067 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051962703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.4051962703 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.14408071 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 1722996555 ps |
CPU time | 12.89 seconds |
Started | Jul 15 06:16:53 PM PDT 24 |
Finished | Jul 15 06:17:06 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-068be879-c83e-4882-9837-03fe12b6773e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=14408071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.14408071 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.678410585 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 10146516317 ps |
CPU time | 349.46 seconds |
Started | Jul 15 06:16:43 PM PDT 24 |
Finished | Jul 15 06:22:33 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-62029d57-bcc4-4899-95e2-787646b94b62 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678410585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_stress_pipeline.678410585 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2297235409 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 710713640 ps |
CPU time | 17.59 seconds |
Started | Jul 15 06:16:43 PM PDT 24 |
Finished | Jul 15 06:17:02 PM PDT 24 |
Peak memory | 256524 kb |
Host | smart-d64268aa-2864-4326-84fd-63cbea542efc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297235409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2297235409 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3327653420 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 38305035564 ps |
CPU time | 832.17 seconds |
Started | Jul 15 06:16:52 PM PDT 24 |
Finished | Jul 15 06:30:45 PM PDT 24 |
Peak memory | 376584 kb |
Host | smart-e363f8bc-34f2-4d84-87c5-f884602ba0fa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327653420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.3327653420 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.48508919 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 37702809 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:16:56 PM PDT 24 |
Finished | Jul 15 06:16:58 PM PDT 24 |
Peak memory | 202312 kb |
Host | smart-a454b023-e8b0-4ab5-89cb-68f9ad7d1702 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48508919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_alert_test.48508919 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.235452333 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 76854055732 ps |
CPU time | 1269.71 seconds |
Started | Jul 15 06:16:52 PM PDT 24 |
Finished | Jul 15 06:38:03 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-df6c8846-8a80-4be2-80ef-57e3a3db60f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235452333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection. 235452333 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.1158816834 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 44248887970 ps |
CPU time | 616 seconds |
Started | Jul 15 06:16:51 PM PDT 24 |
Finished | Jul 15 06:27:08 PM PDT 24 |
Peak memory | 372512 kb |
Host | smart-7456231c-9e96-43ad-96a8-b3aa968510a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158816834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.1158816834 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.2719789406 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 16182291131 ps |
CPU time | 89.59 seconds |
Started | Jul 15 06:16:52 PM PDT 24 |
Finished | Jul 15 06:18:22 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-1fab44e3-1fc7-44a5-b9be-90fc354828da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719789406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.2719789406 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.3748428655 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 1370934155 ps |
CPU time | 12.11 seconds |
Started | Jul 15 06:16:53 PM PDT 24 |
Finished | Jul 15 06:17:06 PM PDT 24 |
Peak memory | 235396 kb |
Host | smart-59928b3f-209d-48e2-ac0c-f8140efd3ffe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748428655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.3748428655 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1712854262 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 2791016795 ps |
CPU time | 75.08 seconds |
Started | Jul 15 06:16:56 PM PDT 24 |
Finished | Jul 15 06:18:12 PM PDT 24 |
Peak memory | 219144 kb |
Host | smart-0b0c8d04-9221-4283-8fa8-d27183dab76b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712854262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.1712854262 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.1961946099 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 10942493148 ps |
CPU time | 297.5 seconds |
Started | Jul 15 06:16:56 PM PDT 24 |
Finished | Jul 15 06:21:54 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-651e337e-0ae3-4c2d-af0d-b4b31cd5c97a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961946099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.1961946099 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.1055963499 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 59715273736 ps |
CPU time | 866.56 seconds |
Started | Jul 15 06:16:52 PM PDT 24 |
Finished | Jul 15 06:31:19 PM PDT 24 |
Peak memory | 373512 kb |
Host | smart-7d4c061d-eca9-435e-b3c6-a4222c58d945 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055963499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.1055963499 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.1650666220 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 1072894316 ps |
CPU time | 17.23 seconds |
Started | Jul 15 06:16:51 PM PDT 24 |
Finished | Jul 15 06:17:09 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-7b639901-7a68-47c7-8bb5-1507c7313923 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650666220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.1650666220 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.366380326 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 49296295183 ps |
CPU time | 293.44 seconds |
Started | Jul 15 06:16:50 PM PDT 24 |
Finished | Jul 15 06:21:44 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-3bc2946c-2b88-40dc-94d1-28d69ceaddec |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366380326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.sram_ctrl_partial_access_b2b.366380326 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.1307232171 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 343499512 ps |
CPU time | 3.21 seconds |
Started | Jul 15 06:16:58 PM PDT 24 |
Finished | Jul 15 06:17:02 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-8232321f-6736-4b14-ba87-f51e80f3f7ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307232171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1307232171 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.711767537 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 19323963432 ps |
CPU time | 490.91 seconds |
Started | Jul 15 06:16:50 PM PDT 24 |
Finished | Jul 15 06:25:02 PM PDT 24 |
Peak memory | 379720 kb |
Host | smart-93edde7f-c56c-468c-82ca-df859f924db1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711767537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.711767537 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.42931804 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 1093109412 ps |
CPU time | 62.8 seconds |
Started | Jul 15 06:16:51 PM PDT 24 |
Finished | Jul 15 06:17:54 PM PDT 24 |
Peak memory | 302904 kb |
Host | smart-a2c0c7f1-5e58-46f3-b7cc-dedb30c33cf5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42931804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.42931804 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.1121376841 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 38196106688 ps |
CPU time | 5086.43 seconds |
Started | Jul 15 06:16:56 PM PDT 24 |
Finished | Jul 15 07:41:43 PM PDT 24 |
Peak memory | 381840 kb |
Host | smart-2a660c21-d0f7-4bc9-b97d-ef670a8f4a2e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121376841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.1121376841 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.112850820 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1123695022 ps |
CPU time | 11.16 seconds |
Started | Jul 15 06:16:57 PM PDT 24 |
Finished | Jul 15 06:17:09 PM PDT 24 |
Peak memory | 212896 kb |
Host | smart-ce5b2508-a4af-4775-bab4-df5bca991bd6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=112850820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.112850820 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2755183677 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 15546328314 ps |
CPU time | 302.11 seconds |
Started | Jul 15 06:16:50 PM PDT 24 |
Finished | Jul 15 06:21:53 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-d2f5500b-02e7-4e8e-b2a2-3a39a22b2108 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755183677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.2755183677 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.934284742 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 770799458 ps |
CPU time | 37.26 seconds |
Started | Jul 15 06:16:54 PM PDT 24 |
Finished | Jul 15 06:17:32 PM PDT 24 |
Peak memory | 295588 kb |
Host | smart-cd36533f-8ec8-43e9-8ddd-6ae62f16e574 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934284742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.934284742 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1993420470 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 6341512181 ps |
CPU time | 199.86 seconds |
Started | Jul 15 06:16:59 PM PDT 24 |
Finished | Jul 15 06:20:20 PM PDT 24 |
Peak memory | 350056 kb |
Host | smart-7007316b-abef-4e70-9663-19dc44ff449e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993420470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.1993420470 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.277511943 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 34888324 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:17:07 PM PDT 24 |
Finished | Jul 15 06:17:08 PM PDT 24 |
Peak memory | 202520 kb |
Host | smart-5379cbf4-f99c-4df9-8c0c-b85625d9398b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277511943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.277511943 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.3003724580 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 106215153408 ps |
CPU time | 1949.17 seconds |
Started | Jul 15 06:16:57 PM PDT 24 |
Finished | Jul 15 06:49:27 PM PDT 24 |
Peak memory | 203404 kb |
Host | smart-e38eb943-4f52-44e7-b3b8-f26d2bab02e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003724580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .3003724580 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.1902562200 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 14856710048 ps |
CPU time | 613.33 seconds |
Started | Jul 15 06:16:58 PM PDT 24 |
Finished | Jul 15 06:27:12 PM PDT 24 |
Peak memory | 375580 kb |
Host | smart-f91d7733-0558-4c8b-9ad0-2be77a580544 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902562200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.1902562200 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.920929043 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 11398790360 ps |
CPU time | 38.19 seconds |
Started | Jul 15 06:16:59 PM PDT 24 |
Finished | Jul 15 06:17:38 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-4ff1757a-767a-4f4a-aaf1-a4078ac689c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920929043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_esc alation.920929043 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.65481040 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 709470223 ps |
CPU time | 19.88 seconds |
Started | Jul 15 06:16:58 PM PDT 24 |
Finished | Jul 15 06:17:18 PM PDT 24 |
Peak memory | 268092 kb |
Host | smart-ebba5c27-872a-49ed-b44c-de0dfdceb968 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65481040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 23.sram_ctrl_max_throughput.65481040 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3601560593 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 1455225742 ps |
CPU time | 75.9 seconds |
Started | Jul 15 06:17:02 PM PDT 24 |
Finished | Jul 15 06:18:18 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-83a11db4-222d-4225-b7b7-d03b68d98ce4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601560593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.3601560593 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.926215327 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 7883416184 ps |
CPU time | 254.39 seconds |
Started | Jul 15 06:17:02 PM PDT 24 |
Finished | Jul 15 06:21:17 PM PDT 24 |
Peak memory | 210896 kb |
Host | smart-24ad5814-80f1-4bbc-ae3f-ef1b11812710 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926215327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl _mem_walk.926215327 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.4257552386 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 5363252099 ps |
CPU time | 486.42 seconds |
Started | Jul 15 06:16:59 PM PDT 24 |
Finished | Jul 15 06:25:06 PM PDT 24 |
Peak memory | 379940 kb |
Host | smart-ca8b354c-f49f-4e7a-b3f6-36e29dba28b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257552386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.4257552386 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.655598969 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 1543266866 ps |
CPU time | 22.34 seconds |
Started | Jul 15 06:16:56 PM PDT 24 |
Finished | Jul 15 06:17:19 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-58bb781d-058a-4798-a5b7-2b428f41af83 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655598969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s ram_ctrl_partial_access.655598969 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3774705681 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 4029042638 ps |
CPU time | 222.07 seconds |
Started | Jul 15 06:16:57 PM PDT 24 |
Finished | Jul 15 06:20:40 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-739e7d84-1e74-44e6-9e01-00e3c3dd5c0f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774705681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.3774705681 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.543538034 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 463743391 ps |
CPU time | 3.45 seconds |
Started | Jul 15 06:17:04 PM PDT 24 |
Finished | Jul 15 06:17:08 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-a4774910-396e-48df-aef4-9d193aef778b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543538034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.543538034 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.312431820 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 11455756863 ps |
CPU time | 1009.31 seconds |
Started | Jul 15 06:16:57 PM PDT 24 |
Finished | Jul 15 06:33:47 PM PDT 24 |
Peak memory | 371468 kb |
Host | smart-df6c7b2c-0d82-4b60-bdbb-bb6754f07097 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312431820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.312431820 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.3769254838 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 3739490814 ps |
CPU time | 18.35 seconds |
Started | Jul 15 06:16:59 PM PDT 24 |
Finished | Jul 15 06:17:18 PM PDT 24 |
Peak memory | 251224 kb |
Host | smart-51024944-9f36-4a9f-b658-2aee4c2b65d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769254838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3769254838 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.4266551516 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 45858714103 ps |
CPU time | 3001.72 seconds |
Started | Jul 15 06:17:05 PM PDT 24 |
Finished | Jul 15 07:07:07 PM PDT 24 |
Peak memory | 380688 kb |
Host | smart-696fbf5e-1509-462b-8bc4-4ea3b1dfc1ca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266551516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.4266551516 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1190260672 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 13884310099 ps |
CPU time | 31.14 seconds |
Started | Jul 15 06:17:04 PM PDT 24 |
Finished | Jul 15 06:17:36 PM PDT 24 |
Peak memory | 212128 kb |
Host | smart-ae17b800-bd17-4f30-98e3-efed8c5dad38 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1190260672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1190260672 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3201263617 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 10277072953 ps |
CPU time | 329.09 seconds |
Started | Jul 15 06:16:58 PM PDT 24 |
Finished | Jul 15 06:22:28 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-bfdbc8da-ed80-4662-bbfb-edfba6e36fc1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201263617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3201263617 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.810834082 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 2291838077 ps |
CPU time | 100.66 seconds |
Started | Jul 15 06:16:56 PM PDT 24 |
Finished | Jul 15 06:18:38 PM PDT 24 |
Peak memory | 334624 kb |
Host | smart-05318fd4-a3ea-406c-b12b-b320de5422ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810834082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.810834082 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1383005181 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 7207680600 ps |
CPU time | 463.74 seconds |
Started | Jul 15 06:17:04 PM PDT 24 |
Finished | Jul 15 06:24:48 PM PDT 24 |
Peak memory | 368416 kb |
Host | smart-8b36d45a-e5bc-4a59-9654-84754393a38a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383005181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.1383005181 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.3249766000 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 15406436 ps |
CPU time | 0.66 seconds |
Started | Jul 15 06:17:10 PM PDT 24 |
Finished | Jul 15 06:17:11 PM PDT 24 |
Peak memory | 202288 kb |
Host | smart-85df426a-f4a8-4f37-bfb9-b86ca3834236 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249766000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3249766000 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.3994035424 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 161302739428 ps |
CPU time | 876.29 seconds |
Started | Jul 15 06:17:03 PM PDT 24 |
Finished | Jul 15 06:31:40 PM PDT 24 |
Peak memory | 203296 kb |
Host | smart-2b398cae-9615-4198-b41e-9ec3e26e6f76 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994035424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .3994035424 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.275011520 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 43850869081 ps |
CPU time | 1438.54 seconds |
Started | Jul 15 06:17:05 PM PDT 24 |
Finished | Jul 15 06:41:04 PM PDT 24 |
Peak memory | 379720 kb |
Host | smart-a3a098d1-6a23-437e-916a-66d74a364ec5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275011520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executabl e.275011520 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.3599074498 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 15533373909 ps |
CPU time | 24.62 seconds |
Started | Jul 15 06:17:04 PM PDT 24 |
Finished | Jul 15 06:17:30 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-dc35a44d-6cfc-4aa7-bb0a-8ddf3d8af2dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599074498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.3599074498 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.3599169764 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 1783398747 ps |
CPU time | 87.73 seconds |
Started | Jul 15 06:17:04 PM PDT 24 |
Finished | Jul 15 06:18:32 PM PDT 24 |
Peak memory | 342664 kb |
Host | smart-12f40557-4a75-49ed-a9fb-ecb4748ef6f3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599169764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.3599169764 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1410158724 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 3027950082 ps |
CPU time | 82.7 seconds |
Started | Jul 15 06:17:08 PM PDT 24 |
Finished | Jul 15 06:18:31 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-61e027a7-6735-498d-bda2-d61b62c61d90 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410158724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1410158724 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.2572549445 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 98367732462 ps |
CPU time | 356.78 seconds |
Started | Jul 15 06:17:08 PM PDT 24 |
Finished | Jul 15 06:23:06 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-28dd1d7e-1a5b-4a82-bcf4-d7763a3dd193 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572549445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2572549445 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.2492951772 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 138933382282 ps |
CPU time | 1998.82 seconds |
Started | Jul 15 06:17:03 PM PDT 24 |
Finished | Jul 15 06:50:23 PM PDT 24 |
Peak memory | 375624 kb |
Host | smart-663f0a95-4b41-41a3-a583-b579fe225707 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492951772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.2492951772 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.998468726 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 840603043 ps |
CPU time | 15.74 seconds |
Started | Jul 15 06:17:03 PM PDT 24 |
Finished | Jul 15 06:17:19 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-aa64eb7f-d0f6-4573-982a-3c1dbb7872ee |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998468726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s ram_ctrl_partial_access.998468726 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1794351689 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 85106327982 ps |
CPU time | 429.04 seconds |
Started | Jul 15 06:17:03 PM PDT 24 |
Finished | Jul 15 06:24:13 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-adc1ba13-b771-4189-ab77-d89dc1bffddb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794351689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.1794351689 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.3701271208 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 354711252 ps |
CPU time | 3.27 seconds |
Started | Jul 15 06:17:05 PM PDT 24 |
Finished | Jul 15 06:17:09 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-d68d2bf2-86ef-4c1d-ac99-08d972edcb48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701271208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3701271208 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.384100931 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 13712771890 ps |
CPU time | 1575.48 seconds |
Started | Jul 15 06:17:04 PM PDT 24 |
Finished | Jul 15 06:43:20 PM PDT 24 |
Peak memory | 380700 kb |
Host | smart-4d10230f-1652-4baa-97f4-3525fd1a968f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384100931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.384100931 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.972978820 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 6719980114 ps |
CPU time | 17.43 seconds |
Started | Jul 15 06:17:03 PM PDT 24 |
Finished | Jul 15 06:17:22 PM PDT 24 |
Peak memory | 245164 kb |
Host | smart-95d00abd-45c9-4ffd-bae0-5fb9f4411c36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972978820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.972978820 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.438804593 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 580346459956 ps |
CPU time | 6007.04 seconds |
Started | Jul 15 06:17:10 PM PDT 24 |
Finished | Jul 15 07:57:18 PM PDT 24 |
Peak memory | 380364 kb |
Host | smart-e860b57a-cfdd-4680-8b25-1c5d312d9328 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438804593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_stress_all.438804593 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.936438745 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 5868820954 ps |
CPU time | 51.46 seconds |
Started | Jul 15 06:17:14 PM PDT 24 |
Finished | Jul 15 06:18:06 PM PDT 24 |
Peak memory | 214520 kb |
Host | smart-4a5265a0-9c16-43f3-89aa-f11ee674233f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=936438745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.936438745 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3477961352 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 6076778544 ps |
CPU time | 217.93 seconds |
Started | Jul 15 06:17:08 PM PDT 24 |
Finished | Jul 15 06:20:47 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-e9e9573b-3edb-4e5c-9ac2-c0d945fd4962 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477961352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.3477961352 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3593413378 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 712524276 ps |
CPU time | 7.2 seconds |
Started | Jul 15 06:17:02 PM PDT 24 |
Finished | Jul 15 06:17:10 PM PDT 24 |
Peak memory | 216748 kb |
Host | smart-28ef239a-e529-4610-ac95-7a0c59988ec0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593413378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3593413378 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1058699875 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 36356476743 ps |
CPU time | 1598.14 seconds |
Started | Jul 15 06:17:10 PM PDT 24 |
Finished | Jul 15 06:43:49 PM PDT 24 |
Peak memory | 379368 kb |
Host | smart-205d91d0-cfc7-4344-8fa1-726408c1e58a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058699875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.1058699875 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.1262870381 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 22882302 ps |
CPU time | 0.67 seconds |
Started | Jul 15 06:17:22 PM PDT 24 |
Finished | Jul 15 06:17:23 PM PDT 24 |
Peak memory | 202512 kb |
Host | smart-168b2617-20b6-4098-8f70-29b4b8c3c20d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262870381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1262870381 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.2663191548 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 56835953468 ps |
CPU time | 667.5 seconds |
Started | Jul 15 06:17:10 PM PDT 24 |
Finished | Jul 15 06:28:18 PM PDT 24 |
Peak memory | 203480 kb |
Host | smart-8d3b0a58-4324-40e7-b641-0737301b8854 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663191548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .2663191548 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.75225515 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 22968745786 ps |
CPU time | 422.3 seconds |
Started | Jul 15 06:17:08 PM PDT 24 |
Finished | Jul 15 06:24:11 PM PDT 24 |
Peak memory | 368340 kb |
Host | smart-6677ab12-71d9-42a9-87db-a46bbac155f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75225515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable .75225515 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.2944170684 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 43293495986 ps |
CPU time | 67.58 seconds |
Started | Jul 15 06:17:10 PM PDT 24 |
Finished | Jul 15 06:18:18 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-aabdb5d2-c968-443e-9ba1-27cee7793d5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944170684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.2944170684 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.3759435954 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 2850498391 ps |
CPU time | 9.69 seconds |
Started | Jul 15 06:17:09 PM PDT 24 |
Finished | Jul 15 06:17:19 PM PDT 24 |
Peak memory | 227160 kb |
Host | smart-9108d9e4-273a-4496-ba20-17627f642215 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759435954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.3759435954 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1894074377 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 13931964494 ps |
CPU time | 172.96 seconds |
Started | Jul 15 06:17:10 PM PDT 24 |
Finished | Jul 15 06:20:03 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-9b04533b-251a-40e2-87b9-24d399a3620e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894074377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.1894074377 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.658814294 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 39174766352 ps |
CPU time | 181.82 seconds |
Started | Jul 15 06:17:13 PM PDT 24 |
Finished | Jul 15 06:20:15 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-dad71828-1f1f-4fb4-b897-4538b4acf6f5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658814294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl _mem_walk.658814294 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.3928350180 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 28076905896 ps |
CPU time | 804.67 seconds |
Started | Jul 15 06:17:10 PM PDT 24 |
Finished | Jul 15 06:30:35 PM PDT 24 |
Peak memory | 379708 kb |
Host | smart-c7892ed9-39be-4d86-9d64-883ecf0409de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928350180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.3928350180 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.3412643079 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 2883710235 ps |
CPU time | 14.63 seconds |
Started | Jul 15 06:17:13 PM PDT 24 |
Finished | Jul 15 06:17:28 PM PDT 24 |
Peak memory | 242232 kb |
Host | smart-857e3df9-80b6-4475-ae89-dc1905cc0e2b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412643079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3412643079 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3701857311 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 13887095242 ps |
CPU time | 372.11 seconds |
Started | Jul 15 06:17:13 PM PDT 24 |
Finished | Jul 15 06:23:26 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-722bfd6a-6d4c-4509-a7b6-8bc913c914fa |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701857311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3701857311 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.1823625729 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 3078898081 ps |
CPU time | 3.38 seconds |
Started | Jul 15 06:17:08 PM PDT 24 |
Finished | Jul 15 06:17:12 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-25984086-de65-4fcf-b6b2-76db3c930558 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823625729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1823625729 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.2646059668 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 3015091146 ps |
CPU time | 724.91 seconds |
Started | Jul 15 06:17:09 PM PDT 24 |
Finished | Jul 15 06:29:14 PM PDT 24 |
Peak memory | 380684 kb |
Host | smart-b24250b2-f633-4f5a-9049-ca418c2eb8ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646059668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2646059668 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.169966306 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 531569174 ps |
CPU time | 16.27 seconds |
Started | Jul 15 06:17:10 PM PDT 24 |
Finished | Jul 15 06:17:27 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-a7fe6e30-dc01-4c42-8f57-804ae946e0de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169966306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.169966306 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.1891569659 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 102171032543 ps |
CPU time | 4245.6 seconds |
Started | Jul 15 06:17:23 PM PDT 24 |
Finished | Jul 15 07:28:10 PM PDT 24 |
Peak memory | 380776 kb |
Host | smart-96dec42f-7b61-4111-9847-1d202c0ce61b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891569659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.1891569659 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4198139066 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1774068371 ps |
CPU time | 237.87 seconds |
Started | Jul 15 06:17:22 PM PDT 24 |
Finished | Jul 15 06:21:20 PM PDT 24 |
Peak memory | 358032 kb |
Host | smart-a7641c16-a314-42c1-b3ef-27037813372b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4198139066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.4198139066 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.568627236 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 13984668814 ps |
CPU time | 227.89 seconds |
Started | Jul 15 06:17:13 PM PDT 24 |
Finished | Jul 15 06:21:01 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-92377986-55da-44c2-965e-9526e3802045 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568627236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_stress_pipeline.568627236 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3742037458 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 703745422 ps |
CPU time | 6.29 seconds |
Started | Jul 15 06:17:10 PM PDT 24 |
Finished | Jul 15 06:17:16 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-84169e01-b623-4081-a7fd-54201c4803f8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742037458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.3742037458 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3636341297 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 13931240538 ps |
CPU time | 1138.01 seconds |
Started | Jul 15 06:17:21 PM PDT 24 |
Finished | Jul 15 06:36:20 PM PDT 24 |
Peak memory | 375552 kb |
Host | smart-3457e388-eac6-4939-a5b6-982a60ef6d76 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636341297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.3636341297 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.3061553163 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 48098482 ps |
CPU time | 0.67 seconds |
Started | Jul 15 06:17:30 PM PDT 24 |
Finished | Jul 15 06:17:31 PM PDT 24 |
Peak memory | 202536 kb |
Host | smart-48558001-d7f8-411c-9de7-5d2ad63174b7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061553163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.3061553163 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.499975358 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 42160109925 ps |
CPU time | 1024.94 seconds |
Started | Jul 15 06:17:23 PM PDT 24 |
Finished | Jul 15 06:34:29 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-bfee6f7c-aa33-411a-813b-7d1b09cda761 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499975358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 499975358 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.511172000 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 10170856532 ps |
CPU time | 137.93 seconds |
Started | Jul 15 06:17:22 PM PDT 24 |
Finished | Jul 15 06:19:41 PM PDT 24 |
Peak memory | 299968 kb |
Host | smart-ebe2d024-4851-4a6b-ae26-17de04b0960a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511172000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl e.511172000 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.1690881612 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 14225837282 ps |
CPU time | 44.28 seconds |
Started | Jul 15 06:17:22 PM PDT 24 |
Finished | Jul 15 06:18:07 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-8e8f216c-a59d-42b0-9d1c-e27f0643eb4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690881612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.1690881612 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.2024411144 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 1024516694 ps |
CPU time | 72.94 seconds |
Started | Jul 15 06:17:23 PM PDT 24 |
Finished | Jul 15 06:18:36 PM PDT 24 |
Peak memory | 343748 kb |
Host | smart-a7d3120f-5d82-4a71-91d0-ccd75331d89f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024411144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.2024411144 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.845838190 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 2420621016 ps |
CPU time | 148.09 seconds |
Started | Jul 15 06:17:28 PM PDT 24 |
Finished | Jul 15 06:19:57 PM PDT 24 |
Peak memory | 219088 kb |
Host | smart-965c0a55-fb78-4c60-a91a-05ab1c13cafa |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845838190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_mem_partial_access.845838190 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.3503498640 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 3946669530 ps |
CPU time | 245.96 seconds |
Started | Jul 15 06:17:27 PM PDT 24 |
Finished | Jul 15 06:21:33 PM PDT 24 |
Peak memory | 210948 kb |
Host | smart-9e465684-c40a-4459-ade8-4b18bdad12bd |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503498640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.3503498640 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.618908138 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 4067986506 ps |
CPU time | 398.78 seconds |
Started | Jul 15 06:17:21 PM PDT 24 |
Finished | Jul 15 06:24:00 PM PDT 24 |
Peak memory | 370164 kb |
Host | smart-d4190d66-540a-4c1c-83f8-1920e97b3d16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618908138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip le_keys.618908138 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.2475364621 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 3615228161 ps |
CPU time | 21.59 seconds |
Started | Jul 15 06:17:22 PM PDT 24 |
Finished | Jul 15 06:17:44 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-026b1729-a506-43d4-b2d0-505202a4adf1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475364621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.2475364621 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1701383757 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 17859093799 ps |
CPU time | 454.28 seconds |
Started | Jul 15 06:17:24 PM PDT 24 |
Finished | Jul 15 06:24:59 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-6f488fea-85eb-41b6-bb43-2f199f19d20a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701383757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.1701383757 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.1513435708 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 694919883 ps |
CPU time | 3.31 seconds |
Started | Jul 15 06:17:28 PM PDT 24 |
Finished | Jul 15 06:17:32 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-85dc84eb-5e7d-47c8-a2a8-3976f9e38427 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513435708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1513435708 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.1914595162 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 5626208621 ps |
CPU time | 845.72 seconds |
Started | Jul 15 06:17:28 PM PDT 24 |
Finished | Jul 15 06:31:34 PM PDT 24 |
Peak memory | 373624 kb |
Host | smart-bcb84c33-9d9f-4e1f-9eb0-137717fb6198 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914595162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1914595162 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.1817060097 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 11678967113 ps |
CPU time | 23.55 seconds |
Started | Jul 15 06:17:21 PM PDT 24 |
Finished | Jul 15 06:17:45 PM PDT 24 |
Peak memory | 268244 kb |
Host | smart-75efc5b1-4590-443e-8c9e-e6173ddc4074 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817060097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1817060097 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3915311443 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 2391907366 ps |
CPU time | 19.81 seconds |
Started | Jul 15 06:17:31 PM PDT 24 |
Finished | Jul 15 06:17:51 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-76dcc8fa-9749-4973-8d50-48d8f348f590 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3915311443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3915311443 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2080391257 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 9688671447 ps |
CPU time | 255.97 seconds |
Started | Jul 15 06:17:22 PM PDT 24 |
Finished | Jul 15 06:21:39 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-f909cfd2-4a04-4956-bec2-dd3a832f22f2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080391257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.2080391257 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1686660054 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 3787499209 ps |
CPU time | 66.13 seconds |
Started | Jul 15 06:17:23 PM PDT 24 |
Finished | Jul 15 06:18:30 PM PDT 24 |
Peak memory | 336632 kb |
Host | smart-887bc2b6-cfef-49a6-9a66-65ec49589276 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686660054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.1686660054 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3363511182 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 55698192685 ps |
CPU time | 1190.28 seconds |
Started | Jul 15 06:17:26 PM PDT 24 |
Finished | Jul 15 06:37:17 PM PDT 24 |
Peak memory | 378740 kb |
Host | smart-f86113b6-730d-4db8-8bf1-f59c73a1caa1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363511182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.3363511182 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.3132547612 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 19552991 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:17:36 PM PDT 24 |
Finished | Jul 15 06:17:38 PM PDT 24 |
Peak memory | 202352 kb |
Host | smart-35f21229-bc0b-4d83-8fa8-7cd8889c4549 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132547612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3132547612 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.3155316374 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 131965422215 ps |
CPU time | 1284.97 seconds |
Started | Jul 15 06:17:29 PM PDT 24 |
Finished | Jul 15 06:38:55 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-aca85910-2f72-408d-b611-be33cdfaea00 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155316374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .3155316374 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.2693084102 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 83250048705 ps |
CPU time | 1127.33 seconds |
Started | Jul 15 06:17:28 PM PDT 24 |
Finished | Jul 15 06:36:16 PM PDT 24 |
Peak memory | 379636 kb |
Host | smart-b924db2f-e38d-456f-86d6-fe54ef253dba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693084102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.2693084102 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.4123095935 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 13050314693 ps |
CPU time | 78.9 seconds |
Started | Jul 15 06:17:26 PM PDT 24 |
Finished | Jul 15 06:18:46 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-42e929c6-078a-48ef-88c0-32faecfd6c56 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123095935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.4123095935 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.915488489 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 5638204487 ps |
CPU time | 9 seconds |
Started | Jul 15 06:17:28 PM PDT 24 |
Finished | Jul 15 06:17:38 PM PDT 24 |
Peak memory | 221776 kb |
Host | smart-1c017840-b731-4d95-a019-0462638f04b2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915488489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.sram_ctrl_max_throughput.915488489 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.385752402 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 1679479077 ps |
CPU time | 131.72 seconds |
Started | Jul 15 06:17:26 PM PDT 24 |
Finished | Jul 15 06:19:38 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-aa70f859-7102-44a6-bac6-b46cce281a71 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385752402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_mem_partial_access.385752402 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.3912435197 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 5364434899 ps |
CPU time | 296.72 seconds |
Started | Jul 15 06:17:28 PM PDT 24 |
Finished | Jul 15 06:22:26 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-c7278aad-3ef7-445a-ab96-a3d9671aa697 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912435197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.3912435197 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.933675946 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 22760798281 ps |
CPU time | 444.44 seconds |
Started | Jul 15 06:17:27 PM PDT 24 |
Finished | Jul 15 06:24:52 PM PDT 24 |
Peak memory | 375728 kb |
Host | smart-b308937f-8b9d-4eab-aae1-5447f89ee990 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933675946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip le_keys.933675946 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.774119650 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 1055731233 ps |
CPU time | 15.81 seconds |
Started | Jul 15 06:17:30 PM PDT 24 |
Finished | Jul 15 06:17:47 PM PDT 24 |
Peak memory | 202624 kb |
Host | smart-682f9d9a-aaf5-4803-b4d8-3443c71bef7b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774119650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.s ram_ctrl_partial_access.774119650 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.4073729214 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 95090377264 ps |
CPU time | 406.94 seconds |
Started | Jul 15 06:17:28 PM PDT 24 |
Finished | Jul 15 06:24:15 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-a2798cb2-39e2-45d1-911b-369256a1bd0c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073729214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.4073729214 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.934239706 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 5554672799 ps |
CPU time | 4.22 seconds |
Started | Jul 15 06:17:27 PM PDT 24 |
Finished | Jul 15 06:17:32 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-4c5d19e2-d1ef-4a9b-b1e1-43995ca561c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934239706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.934239706 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.2667358057 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 5007929823 ps |
CPU time | 796.2 seconds |
Started | Jul 15 06:17:29 PM PDT 24 |
Finished | Jul 15 06:30:46 PM PDT 24 |
Peak memory | 367468 kb |
Host | smart-818d67ab-8a7f-4964-b412-2fadda52ea8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667358057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2667358057 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.646198388 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 3004562307 ps |
CPU time | 10.99 seconds |
Started | Jul 15 06:17:28 PM PDT 24 |
Finished | Jul 15 06:17:39 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-a1a92a84-0ae8-4c2b-bd2b-41d3832435b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646198388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.646198388 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.3713318642 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 68117700546 ps |
CPU time | 5705.13 seconds |
Started | Jul 15 06:17:35 PM PDT 24 |
Finished | Jul 15 07:52:41 PM PDT 24 |
Peak memory | 383716 kb |
Host | smart-a177587f-7b69-4ca0-a1ab-b78ca34c79a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713318642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.3713318642 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.696703102 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 3993908354 ps |
CPU time | 185.78 seconds |
Started | Jul 15 06:17:27 PM PDT 24 |
Finished | Jul 15 06:20:33 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-f951c670-75ad-46d5-b676-ccdc23aee27a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696703102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_stress_pipeline.696703102 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3172257299 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 788948495 ps |
CPU time | 35.62 seconds |
Started | Jul 15 06:17:27 PM PDT 24 |
Finished | Jul 15 06:18:03 PM PDT 24 |
Peak memory | 292048 kb |
Host | smart-f3cb2bbe-54e0-4604-8c74-5c69afeb29ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172257299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3172257299 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1106248632 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 14779918475 ps |
CPU time | 1101.86 seconds |
Started | Jul 15 06:17:34 PM PDT 24 |
Finished | Jul 15 06:35:56 PM PDT 24 |
Peak memory | 375576 kb |
Host | smart-dba7b932-2f4a-4b29-92b8-b02942b2e9a0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106248632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.1106248632 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.2546062759 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 15684387 ps |
CPU time | 0.63 seconds |
Started | Jul 15 06:17:45 PM PDT 24 |
Finished | Jul 15 06:17:46 PM PDT 24 |
Peak memory | 202464 kb |
Host | smart-41f3ecc0-3284-4fd3-bb5e-bfc3453f54e2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546062759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.2546062759 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.3590788455 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 307264468344 ps |
CPU time | 1796.74 seconds |
Started | Jul 15 06:17:32 PM PDT 24 |
Finished | Jul 15 06:47:30 PM PDT 24 |
Peak memory | 203616 kb |
Host | smart-21218c03-98bb-49e1-a35b-0682ec102e5e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590788455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .3590788455 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.1245093007 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 5028255164 ps |
CPU time | 324.55 seconds |
Started | Jul 15 06:17:35 PM PDT 24 |
Finished | Jul 15 06:23:00 PM PDT 24 |
Peak memory | 372468 kb |
Host | smart-1a9fed1d-200e-4150-9c3a-cbfe186881cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245093007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.1245093007 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.2589850680 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 55702539371 ps |
CPU time | 94.56 seconds |
Started | Jul 15 06:17:42 PM PDT 24 |
Finished | Jul 15 06:19:17 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-3b844a73-7bf4-4711-8278-3b625ab0649c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589850680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.2589850680 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.3258959443 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 773798978 ps |
CPU time | 97.97 seconds |
Started | Jul 15 06:17:33 PM PDT 24 |
Finished | Jul 15 06:19:11 PM PDT 24 |
Peak memory | 341664 kb |
Host | smart-49821171-9b43-4d2b-928a-c02d46caa5f1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258959443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.3258959443 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1720339023 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 1401723433 ps |
CPU time | 75.21 seconds |
Started | Jul 15 06:17:36 PM PDT 24 |
Finished | Jul 15 06:18:51 PM PDT 24 |
Peak memory | 210796 kb |
Host | smart-d2b6e80e-102b-499a-9c59-426a7650fe3f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720339023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.1720339023 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.2929307317 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 4078804604 ps |
CPU time | 244.21 seconds |
Started | Jul 15 06:17:34 PM PDT 24 |
Finished | Jul 15 06:21:39 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-bf6ef3f6-b86f-4234-80cf-78e685967a65 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929307317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.2929307317 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.3928436169 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 29996088991 ps |
CPU time | 1156.38 seconds |
Started | Jul 15 06:17:35 PM PDT 24 |
Finished | Jul 15 06:36:52 PM PDT 24 |
Peak memory | 376672 kb |
Host | smart-4378a35a-bc9f-49d5-b1b4-a9a4756d1033 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928436169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.3928436169 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.1632958530 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 900347606 ps |
CPU time | 61.33 seconds |
Started | Jul 15 06:17:35 PM PDT 24 |
Finished | Jul 15 06:18:37 PM PDT 24 |
Peak memory | 324444 kb |
Host | smart-0a752035-d04c-4efe-86d1-6b223fce0fcf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632958530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.1632958530 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1873110182 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 87176862428 ps |
CPU time | 527.41 seconds |
Started | Jul 15 06:17:35 PM PDT 24 |
Finished | Jul 15 06:26:22 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-24f3a26a-7df1-45b4-90ed-9b00e011c6f3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873110182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.1873110182 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.1460563857 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 584548388 ps |
CPU time | 3.24 seconds |
Started | Jul 15 06:17:42 PM PDT 24 |
Finished | Jul 15 06:17:46 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-8b08d67b-b87a-4a79-9217-2629908c3ca7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460563857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1460563857 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.759976856 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 6665498244 ps |
CPU time | 337.02 seconds |
Started | Jul 15 06:17:38 PM PDT 24 |
Finished | Jul 15 06:23:16 PM PDT 24 |
Peak memory | 361784 kb |
Host | smart-795d98de-0c84-4a32-bdff-4fa609569b87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759976856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.759976856 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.4294721595 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 891918768 ps |
CPU time | 79.64 seconds |
Started | Jul 15 06:17:38 PM PDT 24 |
Finished | Jul 15 06:18:58 PM PDT 24 |
Peak memory | 355972 kb |
Host | smart-05226659-785b-4cd4-a681-7d5cf8e74eae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294721595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.4294721595 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.368917133 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 72320591863 ps |
CPU time | 5567.77 seconds |
Started | Jul 15 06:17:35 PM PDT 24 |
Finished | Jul 15 07:50:24 PM PDT 24 |
Peak memory | 379648 kb |
Host | smart-2c481900-dc55-4fea-889b-063bfebc9010 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368917133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_stress_all.368917133 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.870623086 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 11008270438 ps |
CPU time | 162.76 seconds |
Started | Jul 15 06:17:38 PM PDT 24 |
Finished | Jul 15 06:20:22 PM PDT 24 |
Peak memory | 351068 kb |
Host | smart-29594917-2211-4cc8-a7ef-70270c2e9acc |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=870623086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.870623086 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2399393252 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 19099822911 ps |
CPU time | 340.17 seconds |
Started | Jul 15 06:17:37 PM PDT 24 |
Finished | Jul 15 06:23:17 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-073e60a6-2310-4ec8-89d1-c3f8e4770788 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399393252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.2399393252 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3527144789 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 746037741 ps |
CPU time | 18.02 seconds |
Started | Jul 15 06:17:34 PM PDT 24 |
Finished | Jul 15 06:17:52 PM PDT 24 |
Peak memory | 253804 kb |
Host | smart-4b1f6372-ab08-4d4c-968a-a787d0919a6b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527144789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.3527144789 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2295807567 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 11792412653 ps |
CPU time | 821.54 seconds |
Started | Jul 15 06:17:43 PM PDT 24 |
Finished | Jul 15 06:31:25 PM PDT 24 |
Peak memory | 378428 kb |
Host | smart-15fd2fd8-5e76-4a94-9d90-1dabf4ba9fc6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295807567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.2295807567 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.3912270042 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 36531885 ps |
CPU time | 0.68 seconds |
Started | Jul 15 06:17:48 PM PDT 24 |
Finished | Jul 15 06:17:49 PM PDT 24 |
Peak memory | 202280 kb |
Host | smart-53458f12-fffe-4037-aca5-f56bc5638606 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912270042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.3912270042 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.2143989239 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 177154009706 ps |
CPU time | 1994.92 seconds |
Started | Jul 15 06:17:39 PM PDT 24 |
Finished | Jul 15 06:50:55 PM PDT 24 |
Peak memory | 203344 kb |
Host | smart-9544d6db-c34c-4667-86ba-c14c6e417caa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143989239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .2143989239 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.2655201194 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 39182689778 ps |
CPU time | 885.4 seconds |
Started | Jul 15 06:17:45 PM PDT 24 |
Finished | Jul 15 06:32:31 PM PDT 24 |
Peak memory | 378856 kb |
Host | smart-43aba31a-3a5a-42ce-8518-c6794d2d2009 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655201194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.2655201194 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.562324204 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 6201612671 ps |
CPU time | 36.14 seconds |
Started | Jul 15 06:17:45 PM PDT 24 |
Finished | Jul 15 06:18:21 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-47b4cdd8-8fe8-4ae0-b760-dbac3aa632f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562324204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esc alation.562324204 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.3237037213 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 3452398100 ps |
CPU time | 46.86 seconds |
Started | Jul 15 06:17:40 PM PDT 24 |
Finished | Jul 15 06:18:27 PM PDT 24 |
Peak memory | 300968 kb |
Host | smart-03f7e1b5-4af7-4d73-ab83-7d88b7f76d58 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237037213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.3237037213 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1571237486 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 1061492053 ps |
CPU time | 63.46 seconds |
Started | Jul 15 06:17:47 PM PDT 24 |
Finished | Jul 15 06:18:51 PM PDT 24 |
Peak memory | 218980 kb |
Host | smart-e863ce22-7c58-45a5-8817-30100b592575 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571237486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.1571237486 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.3740071036 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 17923046691 ps |
CPU time | 167.53 seconds |
Started | Jul 15 06:17:49 PM PDT 24 |
Finished | Jul 15 06:20:37 PM PDT 24 |
Peak memory | 203688 kb |
Host | smart-2e0a7124-8fe3-48b2-87e0-ec266fa36555 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740071036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.3740071036 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.3948324274 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 7493438047 ps |
CPU time | 449.41 seconds |
Started | Jul 15 06:17:40 PM PDT 24 |
Finished | Jul 15 06:25:10 PM PDT 24 |
Peak memory | 372600 kb |
Host | smart-23f660e9-f17a-400d-a61e-50ba1e13c1cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948324274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.3948324274 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.4096563540 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 1263199890 ps |
CPU time | 95.76 seconds |
Started | Jul 15 06:17:40 PM PDT 24 |
Finished | Jul 15 06:19:16 PM PDT 24 |
Peak memory | 353920 kb |
Host | smart-a4d72b93-ae65-4f9d-aa59-fbf66d6e8340 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096563540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.4096563540 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.804034522 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 8114187734 ps |
CPU time | 398.68 seconds |
Started | Jul 15 06:17:40 PM PDT 24 |
Finished | Jul 15 06:24:19 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-e4d3ce6f-7e41-4b61-b801-f99730f4481f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804034522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.sram_ctrl_partial_access_b2b.804034522 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.3434662805 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 685573283 ps |
CPU time | 3.32 seconds |
Started | Jul 15 06:17:45 PM PDT 24 |
Finished | Jul 15 06:17:49 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-5fb4e606-19ee-425b-8075-fb0edf2e3661 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434662805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3434662805 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.1618324400 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 19491280023 ps |
CPU time | 324.19 seconds |
Started | Jul 15 06:17:43 PM PDT 24 |
Finished | Jul 15 06:23:08 PM PDT 24 |
Peak memory | 309260 kb |
Host | smart-404dd561-3ce0-4161-9f39-dc5022e631fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618324400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1618324400 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.1626632596 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 2891836808 ps |
CPU time | 41.76 seconds |
Started | Jul 15 06:17:39 PM PDT 24 |
Finished | Jul 15 06:18:22 PM PDT 24 |
Peak memory | 307628 kb |
Host | smart-c4905a4c-ddb8-4352-b55b-d528f775ecd5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626632596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1626632596 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.2761929870 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 711041893277 ps |
CPU time | 6441.07 seconds |
Started | Jul 15 06:17:48 PM PDT 24 |
Finished | Jul 15 08:05:11 PM PDT 24 |
Peak memory | 377684 kb |
Host | smart-c4749e94-006c-4ff2-b745-0d98e8a13722 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761929870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.2761929870 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3628504259 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 1086878107 ps |
CPU time | 17.07 seconds |
Started | Jul 15 06:17:47 PM PDT 24 |
Finished | Jul 15 06:18:05 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-d12fa738-1f63-4e16-829a-3e9b0ae484f8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3628504259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3628504259 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3943559109 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 12463881052 ps |
CPU time | 213.01 seconds |
Started | Jul 15 06:17:39 PM PDT 24 |
Finished | Jul 15 06:21:13 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-33526c15-a494-4205-9ec0-d1e6c048aeeb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943559109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3943559109 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1412743034 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 1400435220 ps |
CPU time | 10.36 seconds |
Started | Jul 15 06:17:44 PM PDT 24 |
Finished | Jul 15 06:17:55 PM PDT 24 |
Peak memory | 228048 kb |
Host | smart-15845d57-4b2b-4afb-8ee5-2d5de9204a5a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412743034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1412743034 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1669904181 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 1908089823 ps |
CPU time | 46.86 seconds |
Started | Jul 15 06:15:38 PM PDT 24 |
Finished | Jul 15 06:16:26 PM PDT 24 |
Peak memory | 259792 kb |
Host | smart-8cd72cb3-ede6-4e68-9e20-f1994ebb230f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669904181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.1669904181 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.4123485463 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 24584755 ps |
CPU time | 0.63 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:15:37 PM PDT 24 |
Peak memory | 202360 kb |
Host | smart-85f4a2cf-fca6-4803-a026-b6dfc5d44615 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123485463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.4123485463 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.945816685 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 233586967485 ps |
CPU time | 1332.43 seconds |
Started | Jul 15 06:15:37 PM PDT 24 |
Finished | Jul 15 06:37:50 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-52edc985-a444-45b9-b38b-d02c48b80d8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945816685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.945816685 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.2877756602 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 11924170297 ps |
CPU time | 750.74 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:28:07 PM PDT 24 |
Peak memory | 377656 kb |
Host | smart-f41d0192-f067-41b9-83ac-a4a7edbb7673 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877756602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.2877756602 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.1942991427 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 73945227476 ps |
CPU time | 118.62 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:17:35 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-d8243f0e-6013-4c5a-bffd-0e71ff13066d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942991427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.1942991427 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.4019838468 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 6100937426 ps |
CPU time | 50.41 seconds |
Started | Jul 15 06:15:38 PM PDT 24 |
Finished | Jul 15 06:16:30 PM PDT 24 |
Peak memory | 314192 kb |
Host | smart-ff83f8c6-be4e-4947-8fd2-dacee5e82f22 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019838468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.4019838468 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3951616716 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 1007957555 ps |
CPU time | 61.86 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:16:37 PM PDT 24 |
Peak memory | 210864 kb |
Host | smart-631c8311-c4da-48da-80d0-e247302e05dd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951616716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.3951616716 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.63586304 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 17985758421 ps |
CPU time | 319.37 seconds |
Started | Jul 15 06:15:33 PM PDT 24 |
Finished | Jul 15 06:20:53 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-a152658e-aec2-4507-90e7-b60c76a27cbb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63586304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m em_walk.63586304 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.1614583496 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 63757633811 ps |
CPU time | 236.12 seconds |
Started | Jul 15 06:15:31 PM PDT 24 |
Finished | Jul 15 06:19:28 PM PDT 24 |
Peak memory | 332584 kb |
Host | smart-9c3ee2cd-3c59-4dc3-bee6-ad6d3eee48c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614583496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.1614583496 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.3338868271 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 440631022 ps |
CPU time | 25.76 seconds |
Started | Jul 15 06:15:32 PM PDT 24 |
Finished | Jul 15 06:15:58 PM PDT 24 |
Peak memory | 278144 kb |
Host | smart-d9df02f6-283c-4063-b938-c69dce878fbf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338868271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.3338868271 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2784173232 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 51501749301 ps |
CPU time | 323.7 seconds |
Started | Jul 15 06:15:29 PM PDT 24 |
Finished | Jul 15 06:20:54 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-209bb777-0a3a-421d-8f0d-ab620c6f9a1c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784173232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.2784173232 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.3853142768 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 347829463 ps |
CPU time | 3.64 seconds |
Started | Jul 15 06:15:39 PM PDT 24 |
Finished | Jul 15 06:15:43 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-2ce7c91b-f191-43ba-92f4-ecb3cfa3ee57 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853142768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3853142768 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.3047555532 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 8211423807 ps |
CPU time | 397.21 seconds |
Started | Jul 15 06:15:33 PM PDT 24 |
Finished | Jul 15 06:22:11 PM PDT 24 |
Peak memory | 332628 kb |
Host | smart-385f5c7e-ba91-46e2-832c-39eef26457fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047555532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.3047555532 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.84571331 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 307356293 ps |
CPU time | 1.93 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:15:38 PM PDT 24 |
Peak memory | 222288 kb |
Host | smart-deb38a15-e045-4056-a1e9-dadb6febd06f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84571331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_sec_cm.84571331 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.2634271907 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 13696988754 ps |
CPU time | 17.95 seconds |
Started | Jul 15 06:15:27 PM PDT 24 |
Finished | Jul 15 06:15:46 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-a82be584-73b6-4146-976b-47239c02026d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634271907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2634271907 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.3810141761 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 189029241514 ps |
CPU time | 4132.05 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 07:24:28 PM PDT 24 |
Peak memory | 378668 kb |
Host | smart-c7844eb1-ce0b-4d47-8aa4-f62ebe2754ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810141761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.3810141761 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3986456643 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 5640295366 ps |
CPU time | 40.82 seconds |
Started | Jul 15 06:15:38 PM PDT 24 |
Finished | Jul 15 06:16:19 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-c2ab08fc-0af9-45de-921f-513451abf3ee |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3986456643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3986456643 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2245096622 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 5639011172 ps |
CPU time | 383.09 seconds |
Started | Jul 15 06:15:36 PM PDT 24 |
Finished | Jul 15 06:22:01 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-9155f195-2d0b-4a73-aac3-eaa24e4d4c85 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245096622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.2245096622 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2644454378 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 998573472 ps |
CPU time | 9.87 seconds |
Started | Jul 15 06:15:36 PM PDT 24 |
Finished | Jul 15 06:15:47 PM PDT 24 |
Peak memory | 235404 kb |
Host | smart-5be38a7b-8090-4e9e-bfef-1cb1bc655b27 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644454378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2644454378 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2310034299 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 10500837037 ps |
CPU time | 758.54 seconds |
Started | Jul 15 06:17:48 PM PDT 24 |
Finished | Jul 15 06:30:27 PM PDT 24 |
Peak memory | 373488 kb |
Host | smart-68143fc7-60f7-412b-bfbb-4a6ebff30226 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310034299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.2310034299 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.1791244049 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 14321647 ps |
CPU time | 0.64 seconds |
Started | Jul 15 06:17:54 PM PDT 24 |
Finished | Jul 15 06:17:55 PM PDT 24 |
Peak memory | 202364 kb |
Host | smart-6d7f15de-47c3-47b8-8f11-d65a24cc90cd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791244049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.1791244049 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.1921335178 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 110670133446 ps |
CPU time | 2535.49 seconds |
Started | Jul 15 06:17:50 PM PDT 24 |
Finished | Jul 15 07:00:06 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-54499204-6960-444d-bd6a-71a61a278d46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921335178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .1921335178 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.3053187751 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 30315407714 ps |
CPU time | 415.99 seconds |
Started | Jul 15 06:17:49 PM PDT 24 |
Finished | Jul 15 06:24:46 PM PDT 24 |
Peak memory | 375584 kb |
Host | smart-83e596cb-3b67-48b1-8619-c93a547a2d30 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053187751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.3053187751 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.3098976380 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 6058249903 ps |
CPU time | 39.97 seconds |
Started | Jul 15 06:17:49 PM PDT 24 |
Finished | Jul 15 06:18:29 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-48583c85-e614-4558-b472-3fefb0cff1e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098976380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.3098976380 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.2223857613 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 3060104098 ps |
CPU time | 124.3 seconds |
Started | Jul 15 06:17:49 PM PDT 24 |
Finished | Jul 15 06:19:54 PM PDT 24 |
Peak memory | 372644 kb |
Host | smart-3b51bb6e-d39d-48f0-b3e6-63b6816a6539 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223857613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.2223857613 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.4072833603 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 2913134582 ps |
CPU time | 75.56 seconds |
Started | Jul 15 06:17:54 PM PDT 24 |
Finished | Jul 15 06:19:10 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-06be2141-6dc8-4720-9c64-e1788b2a0388 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072833603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.4072833603 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.1420711686 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 82884443065 ps |
CPU time | 372.97 seconds |
Started | Jul 15 06:17:48 PM PDT 24 |
Finished | Jul 15 06:24:02 PM PDT 24 |
Peak memory | 210896 kb |
Host | smart-8ef26ffb-b6f7-4842-b777-a84a54daaf4a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420711686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.1420711686 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.2866983283 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 8023549730 ps |
CPU time | 925.82 seconds |
Started | Jul 15 06:17:46 PM PDT 24 |
Finished | Jul 15 06:33:13 PM PDT 24 |
Peak memory | 380724 kb |
Host | smart-31400052-034a-4f12-a54d-22cb489a6d4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866983283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.2866983283 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.2188760075 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 463765278 ps |
CPU time | 9.52 seconds |
Started | Jul 15 06:17:47 PM PDT 24 |
Finished | Jul 15 06:17:57 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-1a4774a1-2ba8-493f-b115-9a9d9bb16574 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188760075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.2188760075 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3428457680 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 77147669923 ps |
CPU time | 484.72 seconds |
Started | Jul 15 06:17:49 PM PDT 24 |
Finished | Jul 15 06:25:54 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-80fa3374-85b3-4443-81bd-46608b3aa1b0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428457680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3428457680 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.2124040882 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 1412161934 ps |
CPU time | 3.42 seconds |
Started | Jul 15 06:17:48 PM PDT 24 |
Finished | Jul 15 06:17:52 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-0efa879a-1cfd-40ec-8ffc-84587265c18c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124040882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2124040882 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.3394578450 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 13766273851 ps |
CPU time | 1069.66 seconds |
Started | Jul 15 06:17:48 PM PDT 24 |
Finished | Jul 15 06:35:38 PM PDT 24 |
Peak memory | 374524 kb |
Host | smart-78876d7f-07ed-4c5e-a10c-a29061fa547b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394578450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3394578450 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.1035833238 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 1627120064 ps |
CPU time | 3.82 seconds |
Started | Jul 15 06:17:49 PM PDT 24 |
Finished | Jul 15 06:17:53 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-0bea1194-3dfa-4bff-a009-1d3a860fb6a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035833238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1035833238 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.2345630827 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 254607382733 ps |
CPU time | 4770.12 seconds |
Started | Jul 15 06:17:55 PM PDT 24 |
Finished | Jul 15 07:37:26 PM PDT 24 |
Peak memory | 348992 kb |
Host | smart-721e3071-d6b4-4b46-a529-d2c0bd1f4718 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345630827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.2345630827 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1032234997 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 2239450187 ps |
CPU time | 18.03 seconds |
Started | Jul 15 06:17:57 PM PDT 24 |
Finished | Jul 15 06:18:15 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-347580a0-7bc6-4115-b50c-2a64b2c1dd84 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1032234997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1032234997 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2779757989 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 4089947036 ps |
CPU time | 222.28 seconds |
Started | Jul 15 06:17:51 PM PDT 24 |
Finished | Jul 15 06:21:34 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-57f92c18-16d9-470f-b0d0-97f4fd21b1f8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779757989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.2779757989 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2449298447 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 1577555409 ps |
CPU time | 150.82 seconds |
Started | Jul 15 06:17:48 PM PDT 24 |
Finished | Jul 15 06:20:19 PM PDT 24 |
Peak memory | 372424 kb |
Host | smart-36dd0fa5-02f7-49f0-a69e-b08be94d99f3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449298447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.2449298447 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2421245249 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 31609595811 ps |
CPU time | 1004.67 seconds |
Started | Jul 15 06:17:54 PM PDT 24 |
Finished | Jul 15 06:34:40 PM PDT 24 |
Peak memory | 375580 kb |
Host | smart-31e117fc-e4b8-4b53-a4ab-9344ec4c260a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421245249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.2421245249 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.1481125613 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 11799541 ps |
CPU time | 0.66 seconds |
Started | Jul 15 06:17:55 PM PDT 24 |
Finished | Jul 15 06:17:57 PM PDT 24 |
Peak memory | 202488 kb |
Host | smart-e8224a4b-8ea6-4550-a404-b92c987d6d15 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481125613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.1481125613 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.3955623918 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 116261712073 ps |
CPU time | 1942.91 seconds |
Started | Jul 15 06:17:56 PM PDT 24 |
Finished | Jul 15 06:50:20 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-17f0a78b-37bc-4cf5-a490-88493b6d2361 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955623918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .3955623918 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.9415835 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 6160048287 ps |
CPU time | 193.32 seconds |
Started | Jul 15 06:17:58 PM PDT 24 |
Finished | Jul 15 06:21:12 PM PDT 24 |
Peak memory | 324732 kb |
Host | smart-8b0db3a8-99a5-4236-bb46-41529699623e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9415835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.9415835 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.279711278 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 10776139375 ps |
CPU time | 70.62 seconds |
Started | Jul 15 06:17:56 PM PDT 24 |
Finished | Jul 15 06:19:08 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-13c76a29-8290-4171-87a5-2ecd88626f95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279711278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_esc alation.279711278 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.3612897834 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 1594740567 ps |
CPU time | 102.27 seconds |
Started | Jul 15 06:17:55 PM PDT 24 |
Finished | Jul 15 06:19:38 PM PDT 24 |
Peak memory | 370364 kb |
Host | smart-ebe745b1-7883-4570-b95a-9a19b16dcd50 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612897834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.3612897834 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.606086436 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 4811939859 ps |
CPU time | 76.94 seconds |
Started | Jul 15 06:17:57 PM PDT 24 |
Finished | Jul 15 06:19:14 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-279c57f8-5f4f-4781-b64e-349df47e136f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606086436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .sram_ctrl_mem_partial_access.606086436 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.1022730218 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 21342967494 ps |
CPU time | 361.15 seconds |
Started | Jul 15 06:17:55 PM PDT 24 |
Finished | Jul 15 06:23:57 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-43e9ad21-5381-4954-8b95-2a7f95408c95 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022730218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.1022730218 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.1626195965 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 86904144057 ps |
CPU time | 951.21 seconds |
Started | Jul 15 06:17:59 PM PDT 24 |
Finished | Jul 15 06:33:50 PM PDT 24 |
Peak memory | 378652 kb |
Host | smart-a4cd31cc-f134-4868-9246-633c6f2c3300 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626195965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.1626195965 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.778537884 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 2857323627 ps |
CPU time | 9.65 seconds |
Started | Jul 15 06:17:59 PM PDT 24 |
Finished | Jul 15 06:18:09 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-6301a496-ec94-4b5b-bd2d-203fed1f0a38 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778537884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.s ram_ctrl_partial_access.778537884 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2197703202 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 7562943802 ps |
CPU time | 235.32 seconds |
Started | Jul 15 06:17:55 PM PDT 24 |
Finished | Jul 15 06:21:51 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-9bd8549b-0894-4362-9f54-66541d9af581 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197703202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2197703202 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.3925252028 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 346221510 ps |
CPU time | 3.22 seconds |
Started | Jul 15 06:17:54 PM PDT 24 |
Finished | Jul 15 06:17:58 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-71f4c892-3219-4dbb-b1ab-09c44e7a7243 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925252028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3925252028 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.2255562652 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 17147873450 ps |
CPU time | 1988.77 seconds |
Started | Jul 15 06:17:57 PM PDT 24 |
Finished | Jul 15 06:51:07 PM PDT 24 |
Peak memory | 379748 kb |
Host | smart-9e28d494-4965-4d81-b966-1440ac56273c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255562652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2255562652 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.2692566100 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 751408538 ps |
CPU time | 32.21 seconds |
Started | Jul 15 06:17:57 PM PDT 24 |
Finished | Jul 15 06:18:29 PM PDT 24 |
Peak memory | 285688 kb |
Host | smart-19495857-ad38-4716-8199-9c67e425e080 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692566100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2692566100 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.3391513509 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 94922516685 ps |
CPU time | 1794.59 seconds |
Started | Jul 15 06:17:58 PM PDT 24 |
Finished | Jul 15 06:47:53 PM PDT 24 |
Peak memory | 360288 kb |
Host | smart-a47eb726-959d-46f0-8492-0dac6e158ac8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391513509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.3391513509 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1439703270 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 1438841642 ps |
CPU time | 179.73 seconds |
Started | Jul 15 06:17:54 PM PDT 24 |
Finished | Jul 15 06:20:55 PM PDT 24 |
Peak memory | 380744 kb |
Host | smart-1228914c-302e-4091-ad9d-ae73a81f7ec8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1439703270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.1439703270 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.80390123 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 4769180379 ps |
CPU time | 255.38 seconds |
Started | Jul 15 06:17:55 PM PDT 24 |
Finished | Jul 15 06:22:11 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-358558f5-41bd-4847-83cb-b4d67d8eabe5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80390123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_stress_pipeline.80390123 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1622882217 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 1452973813 ps |
CPU time | 15.2 seconds |
Started | Jul 15 06:17:57 PM PDT 24 |
Finished | Jul 15 06:18:13 PM PDT 24 |
Peak memory | 241072 kb |
Host | smart-b5f527ef-9453-4195-80d9-af8b9c2a04f1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622882217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1622882217 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1225127239 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 50900547251 ps |
CPU time | 1139.03 seconds |
Started | Jul 15 06:18:00 PM PDT 24 |
Finished | Jul 15 06:37:00 PM PDT 24 |
Peak memory | 373580 kb |
Host | smart-05f3e70a-81c0-48c1-a54f-97f517fcd172 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225127239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.1225127239 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.1700431198 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 40147838 ps |
CPU time | 0.66 seconds |
Started | Jul 15 06:18:02 PM PDT 24 |
Finished | Jul 15 06:18:03 PM PDT 24 |
Peak memory | 202332 kb |
Host | smart-f831ae0d-0a6f-4ea0-a346-60baac32cc83 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700431198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1700431198 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.1990107804 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 210285318901 ps |
CPU time | 2443.4 seconds |
Started | Jul 15 06:17:54 PM PDT 24 |
Finished | Jul 15 06:58:39 PM PDT 24 |
Peak memory | 203620 kb |
Host | smart-63cad701-d77f-4d62-8642-15a8fa6a3dc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990107804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .1990107804 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.754373850 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 25088382362 ps |
CPU time | 1758.39 seconds |
Started | Jul 15 06:18:03 PM PDT 24 |
Finished | Jul 15 06:47:23 PM PDT 24 |
Peak memory | 380708 kb |
Host | smart-e3587bb1-995f-4f07-a974-f311a529b48b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754373850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executabl e.754373850 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.553435835 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 11512616342 ps |
CPU time | 69.93 seconds |
Started | Jul 15 06:18:00 PM PDT 24 |
Finished | Jul 15 06:19:11 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-83b48963-8a84-42a9-810a-7c945088ab0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553435835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_esc alation.553435835 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.2798908162 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 5581955088 ps |
CPU time | 8.24 seconds |
Started | Jul 15 06:18:01 PM PDT 24 |
Finished | Jul 15 06:18:10 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-478c9d61-b11f-4953-b9ce-ec78805a3db1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798908162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.2798908162 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3667222463 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 3088453279 ps |
CPU time | 120.02 seconds |
Started | Jul 15 06:18:04 PM PDT 24 |
Finished | Jul 15 06:20:04 PM PDT 24 |
Peak memory | 219128 kb |
Host | smart-58d0383b-76b4-4a26-a06f-ce0ac4234909 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667222463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.3667222463 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.751410176 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 37429393905 ps |
CPU time | 191.68 seconds |
Started | Jul 15 06:18:02 PM PDT 24 |
Finished | Jul 15 06:21:15 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-dd6dce9c-8fc4-45dd-9daf-79eea57401f4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751410176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl _mem_walk.751410176 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.1768396980 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 25758022697 ps |
CPU time | 521.39 seconds |
Started | Jul 15 06:17:56 PM PDT 24 |
Finished | Jul 15 06:26:38 PM PDT 24 |
Peak memory | 373524 kb |
Host | smart-2217e118-8098-4103-bc5d-1d5e84cf8c87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768396980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.1768396980 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.3825679736 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 6469512003 ps |
CPU time | 185.01 seconds |
Started | Jul 15 06:17:59 PM PDT 24 |
Finished | Jul 15 06:21:05 PM PDT 24 |
Peak memory | 367304 kb |
Host | smart-b11de013-b36a-468b-a69b-635a634881a6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825679736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.3825679736 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3517711705 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 15512879279 ps |
CPU time | 416.17 seconds |
Started | Jul 15 06:18:02 PM PDT 24 |
Finished | Jul 15 06:24:59 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-23758137-c4d8-4940-b59a-e60281e009bf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517711705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.3517711705 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.881184082 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 4201965523 ps |
CPU time | 4.76 seconds |
Started | Jul 15 06:18:02 PM PDT 24 |
Finished | Jul 15 06:18:08 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-907c631a-00fe-410a-ad83-0ee46571d6f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881184082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.881184082 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.2872632060 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 61647981737 ps |
CPU time | 510.9 seconds |
Started | Jul 15 06:18:03 PM PDT 24 |
Finished | Jul 15 06:26:35 PM PDT 24 |
Peak memory | 378796 kb |
Host | smart-0a3d1605-2529-41fa-88bc-0419ada47efc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872632060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2872632060 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.381481297 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 8206277377 ps |
CPU time | 21.44 seconds |
Started | Jul 15 06:17:59 PM PDT 24 |
Finished | Jul 15 06:18:21 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-d12c8949-041c-4aed-b68c-8abb0e3a3ed2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381481297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.381481297 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.2266356214 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 207707732943 ps |
CPU time | 2514.86 seconds |
Started | Jul 15 06:18:02 PM PDT 24 |
Finished | Jul 15 06:59:58 PM PDT 24 |
Peak memory | 383804 kb |
Host | smart-9ea2ed21-927b-44a8-918a-601931d3878d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266356214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.2266356214 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1363624623 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 1737310403 ps |
CPU time | 46.89 seconds |
Started | Jul 15 06:18:05 PM PDT 24 |
Finished | Jul 15 06:18:52 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-95cc20a6-99d8-4906-92ed-fc946922be1f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1363624623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1363624623 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1857799572 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 88785229093 ps |
CPU time | 473.52 seconds |
Started | Jul 15 06:17:55 PM PDT 24 |
Finished | Jul 15 06:25:49 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-3a7d62f8-5314-423a-a424-221281305c37 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857799572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.1857799572 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.946714344 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 3307009162 ps |
CPU time | 13.7 seconds |
Started | Jul 15 06:18:02 PM PDT 24 |
Finished | Jul 15 06:18:17 PM PDT 24 |
Peak memory | 240200 kb |
Host | smart-a9a2eec2-8068-4403-997b-ccb807be3da3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946714344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_throughput_w_partial_write.946714344 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2460190151 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 8804921595 ps |
CPU time | 167.91 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:20:59 PM PDT 24 |
Peak memory | 370724 kb |
Host | smart-a34c0349-9d5a-4abb-88b3-af6bf4c98fcd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460190151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.2460190151 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.3761557488 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 13365584 ps |
CPU time | 0.68 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:18:11 PM PDT 24 |
Peak memory | 202484 kb |
Host | smart-588b8c48-c6b1-4503-8d79-e79620edaecc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761557488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3761557488 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.2215347088 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 933301332769 ps |
CPU time | 2791.79 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 07:04:43 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-ecbdb93a-0500-4501-a03a-6ebbddea0b1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215347088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .2215347088 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.3958422942 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 9608865718 ps |
CPU time | 497.11 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:26:28 PM PDT 24 |
Peak memory | 363304 kb |
Host | smart-90268b82-d8a1-4336-be75-adf0279da150 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958422942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.3958422942 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.3406546706 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 3163686872 ps |
CPU time | 10.44 seconds |
Started | Jul 15 06:18:08 PM PDT 24 |
Finished | Jul 15 06:18:19 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-eb74fb37-60df-4e7b-a70f-fa7918c0ce69 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406546706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.3406546706 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.1917533835 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 6653285747 ps |
CPU time | 8.17 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:18:19 PM PDT 24 |
Peak memory | 210900 kb |
Host | smart-5d56d361-0a6f-4b8d-aaa2-8492b4cd1101 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917533835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.1917533835 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2064303834 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 5149719378 ps |
CPU time | 150.43 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:20:41 PM PDT 24 |
Peak memory | 219084 kb |
Host | smart-bd2e095f-d316-4f53-9c86-c68e2800aa22 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064303834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.2064303834 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.2717636249 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 14411791979 ps |
CPU time | 311.29 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:23:23 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-2c771a2d-0978-491a-86db-c1d5b7663a11 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717636249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.2717636249 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.4275643402 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 3494619708 ps |
CPU time | 227.7 seconds |
Started | Jul 15 06:18:08 PM PDT 24 |
Finished | Jul 15 06:21:56 PM PDT 24 |
Peak memory | 374796 kb |
Host | smart-2b750c72-9448-46f4-a138-60ab1569e52d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275643402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.4275643402 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.220064335 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 2703096344 ps |
CPU time | 48.07 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:18:59 PM PDT 24 |
Peak memory | 289624 kb |
Host | smart-0cec547e-3b99-4c79-8020-6514dcc4dbd0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220064335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s ram_ctrl_partial_access.220064335 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.576468704 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 61124778845 ps |
CPU time | 445.81 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:25:37 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-7fa70741-04fb-4311-b855-4e508030e5a4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576468704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.sram_ctrl_partial_access_b2b.576468704 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.763769494 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 1055492924 ps |
CPU time | 3.15 seconds |
Started | Jul 15 06:18:09 PM PDT 24 |
Finished | Jul 15 06:18:13 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-fe6ecb1a-4ebd-4e77-b84e-83646c8f4ee1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763769494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.763769494 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.3613601945 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 28707776899 ps |
CPU time | 1182.79 seconds |
Started | Jul 15 06:18:09 PM PDT 24 |
Finished | Jul 15 06:37:53 PM PDT 24 |
Peak memory | 379684 kb |
Host | smart-dd45bee8-4358-47fc-8c21-f206442ad825 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613601945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3613601945 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.1306632892 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 741644893 ps |
CPU time | 26.85 seconds |
Started | Jul 15 06:18:09 PM PDT 24 |
Finished | Jul 15 06:18:36 PM PDT 24 |
Peak memory | 286384 kb |
Host | smart-5a797243-ed22-45b8-ae73-4ee018998830 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306632892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1306632892 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.1447264697 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 144912266476 ps |
CPU time | 1654.61 seconds |
Started | Jul 15 06:18:09 PM PDT 24 |
Finished | Jul 15 06:45:44 PM PDT 24 |
Peak memory | 378608 kb |
Host | smart-34ca7acc-d5f1-485b-a094-1585310e049c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447264697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.1447264697 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2714150387 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 1837568618 ps |
CPU time | 60.34 seconds |
Started | Jul 15 06:18:09 PM PDT 24 |
Finished | Jul 15 06:19:10 PM PDT 24 |
Peak memory | 211992 kb |
Host | smart-3e77fa5b-6b04-4525-b8e9-c026ab85f1e9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2714150387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2714150387 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3165550140 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 3428403201 ps |
CPU time | 183.41 seconds |
Started | Jul 15 06:18:08 PM PDT 24 |
Finished | Jul 15 06:21:12 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-59db3830-3a63-4880-aacc-fcdbdd75105a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165550140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.3165550140 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3284831281 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 2992466924 ps |
CPU time | 74.95 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:19:25 PM PDT 24 |
Peak memory | 317164 kb |
Host | smart-07ac92d4-8b97-4aa9-a7e4-097b1c7cf770 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284831281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3284831281 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.1585371559 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 30368968275 ps |
CPU time | 1824.75 seconds |
Started | Jul 15 06:18:16 PM PDT 24 |
Finished | Jul 15 06:48:42 PM PDT 24 |
Peak memory | 379112 kb |
Host | smart-dd585236-5c47-4abe-af7c-e5ba74243754 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585371559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.1585371559 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.1599229177 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 21774507 ps |
CPU time | 0.67 seconds |
Started | Jul 15 06:18:16 PM PDT 24 |
Finished | Jul 15 06:18:17 PM PDT 24 |
Peak memory | 202444 kb |
Host | smart-7ebb530e-7cf0-4fc8-b05e-430df3765b89 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599229177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1599229177 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.2037423952 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 46181565630 ps |
CPU time | 1578.11 seconds |
Started | Jul 15 06:18:17 PM PDT 24 |
Finished | Jul 15 06:44:36 PM PDT 24 |
Peak memory | 203528 kb |
Host | smart-f33de1eb-6272-41b5-abc9-6944896a8da3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037423952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .2037423952 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.4088990813 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 24526247464 ps |
CPU time | 813.54 seconds |
Started | Jul 15 06:18:16 PM PDT 24 |
Finished | Jul 15 06:31:50 PM PDT 24 |
Peak memory | 376696 kb |
Host | smart-5eea4d04-9709-420d-9337-79175c636dee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088990813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.4088990813 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.348979978 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 26100609263 ps |
CPU time | 50 seconds |
Started | Jul 15 06:18:16 PM PDT 24 |
Finished | Jul 15 06:19:07 PM PDT 24 |
Peak memory | 215676 kb |
Host | smart-28791761-e203-4e3e-968e-10edf8babe7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348979978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc alation.348979978 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.2934166732 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 2612964743 ps |
CPU time | 23.73 seconds |
Started | Jul 15 06:18:17 PM PDT 24 |
Finished | Jul 15 06:18:41 PM PDT 24 |
Peak memory | 268184 kb |
Host | smart-6225d7e9-0340-4934-ba7a-93a53fe223ae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934166732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.2934166732 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3207768661 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 975672082 ps |
CPU time | 63.28 seconds |
Started | Jul 15 06:18:16 PM PDT 24 |
Finished | Jul 15 06:19:20 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-2c2f75d4-3cd0-491e-91f1-afb815b9c4a2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207768661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.3207768661 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.3038649382 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 8227185750 ps |
CPU time | 132.7 seconds |
Started | Jul 15 06:18:17 PM PDT 24 |
Finished | Jul 15 06:20:30 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-b4ae984e-708e-4171-9660-8a99c51ab67b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038649382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.3038649382 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.2916210088 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 291503346471 ps |
CPU time | 2087.07 seconds |
Started | Jul 15 06:18:14 PM PDT 24 |
Finished | Jul 15 06:53:02 PM PDT 24 |
Peak memory | 380652 kb |
Host | smart-fade9d58-bbc6-46ad-b9c2-2488bacea8b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916210088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.2916210088 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.3425255891 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 543626883 ps |
CPU time | 133.75 seconds |
Started | Jul 15 06:18:18 PM PDT 24 |
Finished | Jul 15 06:20:32 PM PDT 24 |
Peak memory | 355984 kb |
Host | smart-370d659a-c4f8-4edf-8ebc-4e4b3ea71f7d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425255891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.3425255891 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1627103506 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 5537698571 ps |
CPU time | 285.68 seconds |
Started | Jul 15 06:18:15 PM PDT 24 |
Finished | Jul 15 06:23:01 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-1252b487-9ca1-4ba6-a219-16706945aecf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627103506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.1627103506 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.826609702 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 1573729055 ps |
CPU time | 3.07 seconds |
Started | Jul 15 06:18:19 PM PDT 24 |
Finished | Jul 15 06:18:22 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-f8d56ea3-5955-4d32-b48b-441794309aa5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826609702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.826609702 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.3875685049 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 79163198128 ps |
CPU time | 2023.76 seconds |
Started | Jul 15 06:19:12 PM PDT 24 |
Finished | Jul 15 06:52:56 PM PDT 24 |
Peak memory | 381880 kb |
Host | smart-d2ad3c8d-0fb2-488b-8016-d3ac06e0f806 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875685049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3875685049 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.1785754085 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 1869596930 ps |
CPU time | 68.85 seconds |
Started | Jul 15 06:18:10 PM PDT 24 |
Finished | Jul 15 06:19:20 PM PDT 24 |
Peak memory | 320316 kb |
Host | smart-c4681c39-e12f-4dd8-9cc5-597c8bf211af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785754085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1785754085 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.30285031 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 195242800711 ps |
CPU time | 2553.97 seconds |
Started | Jul 15 06:18:15 PM PDT 24 |
Finished | Jul 15 07:00:50 PM PDT 24 |
Peak memory | 368384 kb |
Host | smart-d65e748b-44cd-42ce-bed5-2c41ad1c13fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30285031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.sram_ctrl_stress_all.30285031 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1277334931 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 1007669448 ps |
CPU time | 11.37 seconds |
Started | Jul 15 06:18:19 PM PDT 24 |
Finished | Jul 15 06:18:30 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-e5ee3fc6-880d-4120-a3a7-439fab55591a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1277334931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1277334931 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.504785420 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 5422964323 ps |
CPU time | 331.59 seconds |
Started | Jul 15 06:18:14 PM PDT 24 |
Finished | Jul 15 06:23:46 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-72936ce6-7951-47ff-9d6a-40c7c04156f6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504785420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34 .sram_ctrl_stress_pipeline.504785420 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1225690904 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 2220293968 ps |
CPU time | 61.6 seconds |
Started | Jul 15 06:18:16 PM PDT 24 |
Finished | Jul 15 06:19:19 PM PDT 24 |
Peak memory | 330440 kb |
Host | smart-26b85803-2534-4f2a-be58-8fd22764b626 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225690904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1225690904 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1620861159 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 36123919999 ps |
CPU time | 589.84 seconds |
Started | Jul 15 06:18:23 PM PDT 24 |
Finished | Jul 15 06:28:14 PM PDT 24 |
Peak memory | 378704 kb |
Host | smart-3e4945f7-c279-4701-b9b8-ef2286c6acb4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620861159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.1620861159 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.2217364926 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 30110247 ps |
CPU time | 0.63 seconds |
Started | Jul 15 06:18:30 PM PDT 24 |
Finished | Jul 15 06:18:32 PM PDT 24 |
Peak memory | 202492 kb |
Host | smart-1c876669-2b21-4c25-951b-e3b18d148f20 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217364926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2217364926 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.1458511875 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 46206993955 ps |
CPU time | 1099.89 seconds |
Started | Jul 15 06:18:23 PM PDT 24 |
Finished | Jul 15 06:36:43 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-6edfc5ea-7917-40ad-a741-aa2a438ddb46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458511875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .1458511875 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.2107311493 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 3656342632 ps |
CPU time | 22.21 seconds |
Started | Jul 15 06:18:21 PM PDT 24 |
Finished | Jul 15 06:18:44 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-e3b50b68-140a-41a8-b53e-0e7118cb948e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107311493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.2107311493 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.967099719 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 3980207317 ps |
CPU time | 7.74 seconds |
Started | Jul 15 06:18:23 PM PDT 24 |
Finished | Jul 15 06:18:31 PM PDT 24 |
Peak memory | 210904 kb |
Host | smart-d455932a-36b2-4e95-9886-6f3346e08669 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967099719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esc alation.967099719 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.3605253335 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 763510540 ps |
CPU time | 33.81 seconds |
Started | Jul 15 06:18:22 PM PDT 24 |
Finished | Jul 15 06:18:56 PM PDT 24 |
Peak memory | 288604 kb |
Host | smart-6a6a7431-fa4e-4db5-a308-374913110750 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605253335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.3605253335 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2616018535 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 18816088839 ps |
CPU time | 170.44 seconds |
Started | Jul 15 06:18:34 PM PDT 24 |
Finished | Jul 15 06:21:25 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-235c77f7-bc64-47bb-b379-8779cd339605 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616018535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.2616018535 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.3243044294 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 86534394566 ps |
CPU time | 192.32 seconds |
Started | Jul 15 06:18:30 PM PDT 24 |
Finished | Jul 15 06:21:43 PM PDT 24 |
Peak memory | 210904 kb |
Host | smart-7f0af137-cd46-49f6-a903-78956ed8ee42 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243044294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.3243044294 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.2085336629 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 6294155580 ps |
CPU time | 497.32 seconds |
Started | Jul 15 06:18:23 PM PDT 24 |
Finished | Jul 15 06:26:40 PM PDT 24 |
Peak memory | 379676 kb |
Host | smart-e8ed8d71-d444-4e42-b9b6-00fa219a1e7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085336629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.2085336629 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.3047866918 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 1426529073 ps |
CPU time | 24.14 seconds |
Started | Jul 15 06:18:23 PM PDT 24 |
Finished | Jul 15 06:18:48 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-2d08faf0-d9fb-4e69-b9f5-a71f6dbde335 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047866918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3047866918 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1507822986 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 40749616657 ps |
CPU time | 468.59 seconds |
Started | Jul 15 06:18:23 PM PDT 24 |
Finished | Jul 15 06:26:12 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-18294194-4fea-4e86-8db0-d3352996ff8f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507822986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.1507822986 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.2905831673 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 350716442 ps |
CPU time | 3.38 seconds |
Started | Jul 15 06:18:32 PM PDT 24 |
Finished | Jul 15 06:18:36 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-8aa3f531-8f98-4ee3-a20b-85a382645e82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905831673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2905831673 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.904205909 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 9756596593 ps |
CPU time | 387.59 seconds |
Started | Jul 15 06:18:31 PM PDT 24 |
Finished | Jul 15 06:24:59 PM PDT 24 |
Peak memory | 377660 kb |
Host | smart-e7712d51-12b1-411d-ba07-aae5d00dd1ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904205909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.904205909 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.1499659458 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 950864966 ps |
CPU time | 121.24 seconds |
Started | Jul 15 06:18:16 PM PDT 24 |
Finished | Jul 15 06:20:18 PM PDT 24 |
Peak memory | 369280 kb |
Host | smart-5f4edddd-819b-4758-99c4-cfdbabcd78f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499659458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1499659458 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.1661255366 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 480219901166 ps |
CPU time | 3184.85 seconds |
Started | Jul 15 06:18:30 PM PDT 24 |
Finished | Jul 15 07:11:37 PM PDT 24 |
Peak memory | 379756 kb |
Host | smart-e4220fd0-bf12-4ab9-b560-b8bae741452e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661255366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.1661255366 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.153558351 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 10369198266 ps |
CPU time | 103.83 seconds |
Started | Jul 15 06:18:30 PM PDT 24 |
Finished | Jul 15 06:20:15 PM PDT 24 |
Peak memory | 304084 kb |
Host | smart-ef13b7ce-dd1c-4815-b347-9a38b0f87587 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=153558351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.153558351 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.954313056 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 5095664855 ps |
CPU time | 193.84 seconds |
Started | Jul 15 06:18:23 PM PDT 24 |
Finished | Jul 15 06:21:38 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-55f49c6c-55c4-401f-8845-ea9192d34fd3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954313056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .sram_ctrl_stress_pipeline.954313056 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1777222789 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 2744174322 ps |
CPU time | 39.04 seconds |
Started | Jul 15 06:18:24 PM PDT 24 |
Finished | Jul 15 06:19:03 PM PDT 24 |
Peak memory | 300892 kb |
Host | smart-095c337d-8b1e-49c9-ad82-83ed43201c5e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777222789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.1777222789 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3372231121 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 10538984829 ps |
CPU time | 931.29 seconds |
Started | Jul 15 06:18:39 PM PDT 24 |
Finished | Jul 15 06:34:11 PM PDT 24 |
Peak memory | 357796 kb |
Host | smart-e3e4c8a8-2918-412b-9feb-7da1e2c43129 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372231121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.3372231121 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.725176024 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 43755438 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:18:38 PM PDT 24 |
Finished | Jul 15 06:18:39 PM PDT 24 |
Peak memory | 202528 kb |
Host | smart-4801f40f-894f-4873-8001-3653c76c03a5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725176024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.725176024 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.1171489699 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 28438680522 ps |
CPU time | 1999.07 seconds |
Started | Jul 15 06:18:32 PM PDT 24 |
Finished | Jul 15 06:51:52 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-317805a6-2a02-45e9-8c8b-b8e28730a92b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171489699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .1171489699 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.1366519118 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 21121960441 ps |
CPU time | 1359.06 seconds |
Started | Jul 15 06:18:40 PM PDT 24 |
Finished | Jul 15 06:41:20 PM PDT 24 |
Peak memory | 379796 kb |
Host | smart-84adba41-1f77-4530-8fe6-ee70e323f1e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366519118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.1366519118 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.4261678946 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 7862327479 ps |
CPU time | 51.33 seconds |
Started | Jul 15 06:18:39 PM PDT 24 |
Finished | Jul 15 06:19:31 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-39a38cc7-be65-4594-b76b-5abe16a51d35 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261678946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.4261678946 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.3137473135 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 3530437140 ps |
CPU time | 7.34 seconds |
Started | Jul 15 06:18:30 PM PDT 24 |
Finished | Jul 15 06:18:38 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-6dfdd810-b95b-4981-ac54-7580f1374a01 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137473135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.3137473135 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2048615441 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 23160370250 ps |
CPU time | 170.63 seconds |
Started | Jul 15 06:18:38 PM PDT 24 |
Finished | Jul 15 06:21:29 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-73cefd99-e03a-45ef-a2be-e3b9eceb8889 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048615441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.2048615441 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.2073591381 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 13588139938 ps |
CPU time | 256.46 seconds |
Started | Jul 15 06:18:36 PM PDT 24 |
Finished | Jul 15 06:22:52 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-ed30bc05-0517-4e10-8610-e2a23ebe431b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073591381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.2073591381 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.3488296623 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 18217372150 ps |
CPU time | 645.06 seconds |
Started | Jul 15 06:18:30 PM PDT 24 |
Finished | Jul 15 06:29:15 PM PDT 24 |
Peak memory | 378696 kb |
Host | smart-b3faea06-8c18-4911-8ce0-0b6ffb8a4b6b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488296623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.3488296623 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.2241647239 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 5200408640 ps |
CPU time | 36.73 seconds |
Started | Jul 15 06:18:29 PM PDT 24 |
Finished | Jul 15 06:19:07 PM PDT 24 |
Peak memory | 299940 kb |
Host | smart-810068e7-e340-498f-b215-0fa68f5118c4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241647239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.2241647239 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2868010727 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 15756171883 ps |
CPU time | 285.22 seconds |
Started | Jul 15 06:18:33 PM PDT 24 |
Finished | Jul 15 06:23:19 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-e6f949c9-0752-4c2e-85dd-2f8dd1997038 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868010727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.2868010727 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.2804748155 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 681001074 ps |
CPU time | 3.54 seconds |
Started | Jul 15 06:18:37 PM PDT 24 |
Finished | Jul 15 06:18:42 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-96f1139e-5b64-48e4-9eaf-0f44496af437 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804748155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.2804748155 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.3108012467 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 10765120895 ps |
CPU time | 884.65 seconds |
Started | Jul 15 06:18:38 PM PDT 24 |
Finished | Jul 15 06:33:23 PM PDT 24 |
Peak memory | 380724 kb |
Host | smart-02467071-23b6-4849-902e-48535ee32bfe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108012467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3108012467 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.992386810 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 849808275 ps |
CPU time | 6.72 seconds |
Started | Jul 15 06:18:30 PM PDT 24 |
Finished | Jul 15 06:18:38 PM PDT 24 |
Peak memory | 216496 kb |
Host | smart-d8284af3-296d-499b-9540-1e0720e026fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992386810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.992386810 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.4283170007 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 78709449893 ps |
CPU time | 4458.24 seconds |
Started | Jul 15 06:18:39 PM PDT 24 |
Finished | Jul 15 07:32:58 PM PDT 24 |
Peak memory | 379360 kb |
Host | smart-81f80f43-f2fb-4e3f-b54a-27daf5fd3346 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283170007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.4283170007 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1531031413 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 4639804153 ps |
CPU time | 278.6 seconds |
Started | Jul 15 06:18:33 PM PDT 24 |
Finished | Jul 15 06:23:12 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-d5ae74d3-96ed-4fd9-ba18-cec2fd8e687d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531031413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.1531031413 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2470831499 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 1603684379 ps |
CPU time | 164.8 seconds |
Started | Jul 15 06:18:32 PM PDT 24 |
Finished | Jul 15 06:21:18 PM PDT 24 |
Peak memory | 369220 kb |
Host | smart-c9673942-bd67-4ffb-aaf4-148b60745756 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470831499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2470831499 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3675129092 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 54705342229 ps |
CPU time | 264.16 seconds |
Started | Jul 15 06:18:44 PM PDT 24 |
Finished | Jul 15 06:23:09 PM PDT 24 |
Peak memory | 376488 kb |
Host | smart-acf65dbd-c41c-414f-b7f2-c751a1595ece |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675129092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.3675129092 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.2903309900 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 23840291 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:18:58 PM PDT 24 |
Finished | Jul 15 06:19:00 PM PDT 24 |
Peak memory | 202332 kb |
Host | smart-9917fa89-5f63-4155-b5f3-4399670c0239 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903309900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.2903309900 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.1232458632 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 267443983651 ps |
CPU time | 2228.33 seconds |
Started | Jul 15 06:18:45 PM PDT 24 |
Finished | Jul 15 06:55:54 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-cac40d01-90a9-4ecb-befe-ab9c3ff8ae30 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232458632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .1232458632 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.2143058343 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 9095973196 ps |
CPU time | 1616.43 seconds |
Started | Jul 15 06:18:51 PM PDT 24 |
Finished | Jul 15 06:45:49 PM PDT 24 |
Peak memory | 374532 kb |
Host | smart-8a4b9609-c255-484b-9a88-fc9b416980a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143058343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.2143058343 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.1309273103 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 6658305147 ps |
CPU time | 8.97 seconds |
Started | Jul 15 06:18:44 PM PDT 24 |
Finished | Jul 15 06:18:54 PM PDT 24 |
Peak memory | 210916 kb |
Host | smart-c1064cd3-23c5-4961-b20d-3e16e576ec90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309273103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.1309273103 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.1328390025 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 10841201986 ps |
CPU time | 111.45 seconds |
Started | Jul 15 06:18:46 PM PDT 24 |
Finished | Jul 15 06:20:38 PM PDT 24 |
Peak memory | 366316 kb |
Host | smart-a9899599-030a-4b5b-97ac-ff4f3513bb75 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328390025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.1328390025 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1895403403 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 18634512674 ps |
CPU time | 167.8 seconds |
Started | Jul 15 06:18:58 PM PDT 24 |
Finished | Jul 15 06:21:46 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-9efbed4c-796b-4fbd-8405-90a706dc21d0 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895403403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.1895403403 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.4136011948 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 7060077427 ps |
CPU time | 164.01 seconds |
Started | Jul 15 06:18:58 PM PDT 24 |
Finished | Jul 15 06:21:42 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-82468ed5-0410-4b7b-8168-44ffea75d3ec |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136011948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.4136011948 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.815789871 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 3803699746 ps |
CPU time | 322.21 seconds |
Started | Jul 15 06:18:38 PM PDT 24 |
Finished | Jul 15 06:24:01 PM PDT 24 |
Peak memory | 339808 kb |
Host | smart-14210e62-4d34-466c-9189-d809614f34fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815789871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip le_keys.815789871 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.3761609237 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 948186580 ps |
CPU time | 8.4 seconds |
Started | Jul 15 06:18:50 PM PDT 24 |
Finished | Jul 15 06:18:59 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-75a30480-0048-4db0-a5e5-855ae3134d6a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761609237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.3761609237 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2013931101 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 19229839307 ps |
CPU time | 610.42 seconds |
Started | Jul 15 06:18:50 PM PDT 24 |
Finished | Jul 15 06:29:01 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-43985210-8c92-442a-99a5-060b47d11535 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013931101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.2013931101 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.2330586855 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 349396367 ps |
CPU time | 3.61 seconds |
Started | Jul 15 06:18:52 PM PDT 24 |
Finished | Jul 15 06:18:56 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-fb4fb63c-9550-4616-85ad-17b3c533c402 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330586855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2330586855 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.3186092115 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 8218117006 ps |
CPU time | 1181.88 seconds |
Started | Jul 15 06:18:51 PM PDT 24 |
Finished | Jul 15 06:38:34 PM PDT 24 |
Peak memory | 378676 kb |
Host | smart-999cb5b1-c6d7-4db4-a8e8-f1b103971bcd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186092115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3186092115 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.1046966436 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 1427882805 ps |
CPU time | 12.99 seconds |
Started | Jul 15 06:18:39 PM PDT 24 |
Finished | Jul 15 06:18:52 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-8205fbe3-b4d9-4134-a059-c412811c0d95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046966436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1046966436 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.3045502732 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 66759011102 ps |
CPU time | 3202.99 seconds |
Started | Jul 15 06:19:03 PM PDT 24 |
Finished | Jul 15 07:12:26 PM PDT 24 |
Peak memory | 387924 kb |
Host | smart-ce5190bf-ce99-47a4-ab63-ec663619a9e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045502732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.3045502732 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2441741242 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 1660825575 ps |
CPU time | 20.37 seconds |
Started | Jul 15 06:18:57 PM PDT 24 |
Finished | Jul 15 06:19:18 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-c64818f0-d722-4702-b077-e5602765de73 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2441741242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2441741242 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.436931188 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 44483588348 ps |
CPU time | 360.99 seconds |
Started | Jul 15 06:18:50 PM PDT 24 |
Finished | Jul 15 06:24:52 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-77b06f40-7f3a-4923-8871-db067e58def1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436931188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_stress_pipeline.436931188 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3344407373 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 1381011628 ps |
CPU time | 7.55 seconds |
Started | Jul 15 06:18:45 PM PDT 24 |
Finished | Jul 15 06:18:53 PM PDT 24 |
Peak memory | 219092 kb |
Host | smart-580a539c-3748-4467-baef-734a609e1b3c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344407373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.3344407373 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2016522701 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 36450794193 ps |
CPU time | 487.55 seconds |
Started | Jul 15 06:19:07 PM PDT 24 |
Finished | Jul 15 06:27:16 PM PDT 24 |
Peak memory | 359244 kb |
Host | smart-0732e389-97ce-4eb7-b6e9-95c136af8031 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016522701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.2016522701 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.444325718 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 25962495 ps |
CPU time | 0.66 seconds |
Started | Jul 15 06:19:15 PM PDT 24 |
Finished | Jul 15 06:19:17 PM PDT 24 |
Peak memory | 202360 kb |
Host | smart-88d459d6-e7d2-47b3-b143-8597fc654573 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444325718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.444325718 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.2110027892 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 127226474617 ps |
CPU time | 2327.16 seconds |
Started | Jul 15 06:18:57 PM PDT 24 |
Finished | Jul 15 06:57:45 PM PDT 24 |
Peak memory | 203372 kb |
Host | smart-c4facf28-b863-4b43-9d4a-d190d09b9036 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110027892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2110027892 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.3520440116 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 54149028965 ps |
CPU time | 1119.25 seconds |
Started | Jul 15 06:19:09 PM PDT 24 |
Finished | Jul 15 06:37:50 PM PDT 24 |
Peak memory | 375732 kb |
Host | smart-1a9295d5-9999-4dfa-8721-188054943b97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520440116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.3520440116 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.2831732965 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 6232620333 ps |
CPU time | 35.97 seconds |
Started | Jul 15 06:19:06 PM PDT 24 |
Finished | Jul 15 06:19:44 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-41e90082-d75d-4455-968f-1c559d84a30b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831732965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.2831732965 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.473351499 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 784779977 ps |
CPU time | 148.63 seconds |
Started | Jul 15 06:19:06 PM PDT 24 |
Finished | Jul 15 06:21:37 PM PDT 24 |
Peak memory | 369584 kb |
Host | smart-b3268b43-65bb-45f7-bcef-f3e8816f3230 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473351499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.sram_ctrl_max_throughput.473351499 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3029054797 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 2547163996 ps |
CPU time | 77.21 seconds |
Started | Jul 15 06:19:15 PM PDT 24 |
Finished | Jul 15 06:20:33 PM PDT 24 |
Peak memory | 219148 kb |
Host | smart-b767b842-1f56-469e-90fd-fb9a1599ab34 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029054797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.3029054797 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.2878294956 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 2060642403 ps |
CPU time | 128.31 seconds |
Started | Jul 15 06:19:06 PM PDT 24 |
Finished | Jul 15 06:21:17 PM PDT 24 |
Peak memory | 210832 kb |
Host | smart-44e55177-4d98-47dc-a73a-efe6a8ac7076 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878294956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.2878294956 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.2947997169 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 16080057957 ps |
CPU time | 1154.83 seconds |
Started | Jul 15 06:19:00 PM PDT 24 |
Finished | Jul 15 06:38:15 PM PDT 24 |
Peak memory | 374656 kb |
Host | smart-df1faa6f-0840-42a1-9354-c40c9257abb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947997169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.2947997169 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.3914539010 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 3242791987 ps |
CPU time | 23.5 seconds |
Started | Jul 15 06:19:00 PM PDT 24 |
Finished | Jul 15 06:19:24 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-7486dde9-7bd9-4ef3-b29b-a019ba38cd87 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914539010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.3914539010 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1300271152 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 22843882723 ps |
CPU time | 281.78 seconds |
Started | Jul 15 06:19:07 PM PDT 24 |
Finished | Jul 15 06:23:51 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-b0311c99-4795-4234-bad4-d98ff433f707 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300271152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.1300271152 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.1873040023 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 1527251970 ps |
CPU time | 3.56 seconds |
Started | Jul 15 06:19:06 PM PDT 24 |
Finished | Jul 15 06:19:12 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-df9ad532-e501-437b-be9b-acb0fbb4ea32 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873040023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1873040023 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.3553820684 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 54253407805 ps |
CPU time | 699.19 seconds |
Started | Jul 15 06:19:08 PM PDT 24 |
Finished | Jul 15 06:30:49 PM PDT 24 |
Peak memory | 381384 kb |
Host | smart-50bab0de-fc56-435e-b752-0821b6c74a27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553820684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3553820684 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.2382933322 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 2742341777 ps |
CPU time | 9.96 seconds |
Started | Jul 15 06:18:59 PM PDT 24 |
Finished | Jul 15 06:19:09 PM PDT 24 |
Peak memory | 225512 kb |
Host | smart-80fa4a03-0642-4a8d-afad-70b415633d54 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382933322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2382933322 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.4245524534 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 23650407412 ps |
CPU time | 277.56 seconds |
Started | Jul 15 06:18:59 PM PDT 24 |
Finished | Jul 15 06:23:37 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-139fc8b5-d587-4aab-abbb-8f81ee58cfa4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245524534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.4245524534 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1841962788 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 1704809643 ps |
CPU time | 151.03 seconds |
Started | Jul 15 06:19:06 PM PDT 24 |
Finished | Jul 15 06:21:39 PM PDT 24 |
Peak memory | 370356 kb |
Host | smart-7cde4b11-0b0f-4206-b796-e3b49ba4cc4d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841962788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1841962788 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2916546629 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 21393823675 ps |
CPU time | 467.3 seconds |
Started | Jul 15 06:19:22 PM PDT 24 |
Finished | Jul 15 06:27:10 PM PDT 24 |
Peak memory | 376596 kb |
Host | smart-5f6657b1-b812-40fd-9247-63cb6424d2f3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916546629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.2916546629 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.3488739009 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 23066421 ps |
CPU time | 0.67 seconds |
Started | Jul 15 06:19:22 PM PDT 24 |
Finished | Jul 15 06:19:23 PM PDT 24 |
Peak memory | 202536 kb |
Host | smart-8ecd7c11-74de-46ed-b2b1-3fae3e46e8f3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488739009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3488739009 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.295865055 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 33559516154 ps |
CPU time | 749.93 seconds |
Started | Jul 15 06:19:15 PM PDT 24 |
Finished | Jul 15 06:31:46 PM PDT 24 |
Peak memory | 203340 kb |
Host | smart-b94ae93e-d237-48bd-ae88-0518e92f5a6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295865055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection. 295865055 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.3616773685 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 5272202392 ps |
CPU time | 182.95 seconds |
Started | Jul 15 06:19:22 PM PDT 24 |
Finished | Jul 15 06:22:25 PM PDT 24 |
Peak memory | 347772 kb |
Host | smart-65aafe63-3992-4006-985e-24b76e132e92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616773685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.3616773685 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.2913831820 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 7960198437 ps |
CPU time | 47.36 seconds |
Started | Jul 15 06:19:21 PM PDT 24 |
Finished | Jul 15 06:20:09 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-c36edc4c-d819-44a0-892b-a9a2e7675271 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913831820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.2913831820 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.3401289199 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 1518485427 ps |
CPU time | 57.33 seconds |
Started | Jul 15 06:19:23 PM PDT 24 |
Finished | Jul 15 06:20:21 PM PDT 24 |
Peak memory | 332616 kb |
Host | smart-e869135c-bbc8-48ad-b2f5-70e78d732ea0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401289199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.3401289199 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2124090209 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 2617159084 ps |
CPU time | 83.09 seconds |
Started | Jul 15 06:19:22 PM PDT 24 |
Finished | Jul 15 06:20:46 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-2dbcde59-1b09-42b0-b6d7-fd8af4903089 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124090209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.2124090209 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.3608019478 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 18342575004 ps |
CPU time | 336.31 seconds |
Started | Jul 15 06:19:22 PM PDT 24 |
Finished | Jul 15 06:24:59 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-176b2862-ff32-42ef-870e-f455d54c2fba |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608019478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.3608019478 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.873256627 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 18879893096 ps |
CPU time | 1301.23 seconds |
Started | Jul 15 06:19:16 PM PDT 24 |
Finished | Jul 15 06:40:58 PM PDT 24 |
Peak memory | 377756 kb |
Host | smart-4849680d-f305-4403-b702-c2b4afa8d9e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873256627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multip le_keys.873256627 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.29847083 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 3781806647 ps |
CPU time | 23.75 seconds |
Started | Jul 15 06:19:21 PM PDT 24 |
Finished | Jul 15 06:19:45 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-65f67eaa-a8a4-4241-a76d-3bf00c9442e6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29847083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sr am_ctrl_partial_access.29847083 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.389049878 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 27825149373 ps |
CPU time | 587.21 seconds |
Started | Jul 15 06:19:22 PM PDT 24 |
Finished | Jul 15 06:29:09 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-dd1a8be9-9d2c-4c3e-8a7b-40effd44d5e2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389049878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.sram_ctrl_partial_access_b2b.389049878 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.3968961415 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 1868984548 ps |
CPU time | 4 seconds |
Started | Jul 15 06:19:21 PM PDT 24 |
Finished | Jul 15 06:19:25 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-3aa6431a-0e2b-4604-afb1-0ae141b889e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968961415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3968961415 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.186429281 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 26176552035 ps |
CPU time | 734.17 seconds |
Started | Jul 15 06:19:24 PM PDT 24 |
Finished | Jul 15 06:31:39 PM PDT 24 |
Peak memory | 370512 kb |
Host | smart-cc5dcf82-6c29-49fc-80b7-8f8b0e7ac931 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186429281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.186429281 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.3015348790 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 879180086 ps |
CPU time | 17.5 seconds |
Started | Jul 15 06:19:13 PM PDT 24 |
Finished | Jul 15 06:19:31 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-298dda17-408e-488d-b2a2-2fbfb97c2d86 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015348790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3015348790 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.3935439998 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 324501493719 ps |
CPU time | 5920.81 seconds |
Started | Jul 15 06:19:21 PM PDT 24 |
Finished | Jul 15 07:58:03 PM PDT 24 |
Peak memory | 381812 kb |
Host | smart-5bcb139f-42c2-4a9e-9c04-369fd7328e52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935439998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.3935439998 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3806545310 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 9641963069 ps |
CPU time | 85.49 seconds |
Started | Jul 15 06:19:25 PM PDT 24 |
Finished | Jul 15 06:20:51 PM PDT 24 |
Peak memory | 248624 kb |
Host | smart-e55d6e4b-70f9-4b9f-b772-33db10cecabf |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3806545310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3806545310 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1843998449 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 6135156419 ps |
CPU time | 346.13 seconds |
Started | Jul 15 06:19:22 PM PDT 24 |
Finished | Jul 15 06:25:08 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-8eeebc42-12ae-4dd8-b592-1844f838b5c0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843998449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1843998449 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1176554832 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 1537746379 ps |
CPU time | 59.75 seconds |
Started | Jul 15 06:19:23 PM PDT 24 |
Finished | Jul 15 06:20:23 PM PDT 24 |
Peak memory | 324380 kb |
Host | smart-bf75144a-39cb-4a70-9e8d-fa5d075861d7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176554832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1176554832 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3698323496 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 8104831959 ps |
CPU time | 577.5 seconds |
Started | Jul 15 06:15:37 PM PDT 24 |
Finished | Jul 15 06:25:16 PM PDT 24 |
Peak memory | 373540 kb |
Host | smart-9e4acc35-13f3-4d80-8453-e768a88934ee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698323496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.3698323496 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.1606177662 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 42957869 ps |
CPU time | 0.66 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:15:36 PM PDT 24 |
Peak memory | 202492 kb |
Host | smart-aadf5960-abb9-4f79-a37d-101a56e6645d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606177662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.1606177662 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.4104927961 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 64917001303 ps |
CPU time | 752.53 seconds |
Started | Jul 15 06:15:40 PM PDT 24 |
Finished | Jul 15 06:28:13 PM PDT 24 |
Peak memory | 203360 kb |
Host | smart-1d0fae88-3c79-48ab-affb-5f268b978822 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104927961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 4104927961 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.2302083920 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 27737819554 ps |
CPU time | 832.65 seconds |
Started | Jul 15 06:15:41 PM PDT 24 |
Finished | Jul 15 06:29:34 PM PDT 24 |
Peak memory | 370172 kb |
Host | smart-fab47137-2b8b-4ef2-b156-5159ee49decf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302083920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.2302083920 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.955207057 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 22963559152 ps |
CPU time | 72.61 seconds |
Started | Jul 15 06:15:38 PM PDT 24 |
Finished | Jul 15 06:16:52 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-bdcb20dd-eb1e-4427-bc46-216f372f18de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955207057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca lation.955207057 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.534570786 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 723661393 ps |
CPU time | 9.62 seconds |
Started | Jul 15 06:15:42 PM PDT 24 |
Finished | Jul 15 06:15:53 PM PDT 24 |
Peak memory | 227756 kb |
Host | smart-0cf79e0a-1fb9-4a3b-bfe5-dad25d52c7e1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534570786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.sram_ctrl_max_throughput.534570786 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2020951491 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 10532925019 ps |
CPU time | 78.49 seconds |
Started | Jul 15 06:15:38 PM PDT 24 |
Finished | Jul 15 06:16:57 PM PDT 24 |
Peak memory | 210960 kb |
Host | smart-fed851b0-cb34-4b85-85a5-73bf67cadd20 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020951491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.2020951491 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.1759685639 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 15762641896 ps |
CPU time | 265.4 seconds |
Started | Jul 15 06:15:32 PM PDT 24 |
Finished | Jul 15 06:19:58 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-88d9df15-221b-41e6-bbd3-9dff3aa5dd8e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759685639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.1759685639 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.1463467660 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 74834403727 ps |
CPU time | 1259.83 seconds |
Started | Jul 15 06:15:39 PM PDT 24 |
Finished | Jul 15 06:36:40 PM PDT 24 |
Peak memory | 379588 kb |
Host | smart-b156e33a-db81-4deb-acc1-b9eadaefc751 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463467660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.1463467660 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.2709825164 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 845463147 ps |
CPU time | 15.61 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:15:51 PM PDT 24 |
Peak memory | 256520 kb |
Host | smart-9f51b186-9e7e-49fe-a459-52d4b42b2a5d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709825164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.2709825164 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.668845650 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 86106543126 ps |
CPU time | 222.63 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:19:19 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-ce0e3d61-49c1-4068-bfbc-82a62fb27a8c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668845650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.sram_ctrl_partial_access_b2b.668845650 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.2850079654 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 1299291374 ps |
CPU time | 3.77 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:15:38 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-8f12309d-1a58-44e5-b8d8-b46ee6f56fd5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850079654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2850079654 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.1812169185 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 59549866653 ps |
CPU time | 1034.53 seconds |
Started | Jul 15 06:15:37 PM PDT 24 |
Finished | Jul 15 06:32:52 PM PDT 24 |
Peak memory | 372544 kb |
Host | smart-fb16dfe9-0ce0-44d6-91dc-80163f45f20e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812169185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1812169185 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.4249830876 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 1364476362 ps |
CPU time | 9.64 seconds |
Started | Jul 15 06:15:33 PM PDT 24 |
Finished | Jul 15 06:15:43 PM PDT 24 |
Peak memory | 222412 kb |
Host | smart-7fe4a56a-b02d-48aa-afcc-a4dfc6818324 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249830876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.4249830876 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.3881670136 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 379740122960 ps |
CPU time | 1301.84 seconds |
Started | Jul 15 06:15:39 PM PDT 24 |
Finished | Jul 15 06:37:21 PM PDT 24 |
Peak memory | 375612 kb |
Host | smart-4b8cd67c-63cb-4709-88f6-ede5a6a92f47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881670136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.3881670136 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3857851997 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 434785907 ps |
CPU time | 12.69 seconds |
Started | Jul 15 06:15:36 PM PDT 24 |
Finished | Jul 15 06:15:50 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-e8e97120-933b-4dd1-bd16-850b9f783567 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3857851997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3857851997 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.1488370117 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 3306110351 ps |
CPU time | 215.42 seconds |
Started | Jul 15 06:15:40 PM PDT 24 |
Finished | Jul 15 06:19:16 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-ebf7994c-56bf-4d67-8c1b-374c76ad9dd1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488370117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.1488370117 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1685572665 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 1742882689 ps |
CPU time | 9.02 seconds |
Started | Jul 15 06:15:33 PM PDT 24 |
Finished | Jul 15 06:15:43 PM PDT 24 |
Peak memory | 219052 kb |
Host | smart-c3c616d0-baf0-4c54-b4b9-46e331316a8a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685572665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1685572665 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2573026134 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 48237097480 ps |
CPU time | 867.41 seconds |
Started | Jul 15 06:19:31 PM PDT 24 |
Finished | Jul 15 06:33:59 PM PDT 24 |
Peak memory | 376808 kb |
Host | smart-b74038d3-71a0-48a5-a3c9-c238acff78aa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573026134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.2573026134 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.114002930 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 21754700 ps |
CPU time | 0.68 seconds |
Started | Jul 15 06:19:35 PM PDT 24 |
Finished | Jul 15 06:19:36 PM PDT 24 |
Peak memory | 202336 kb |
Host | smart-ecfa4921-c299-4a03-ac82-e0d603410c15 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114002930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.114002930 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.396005526 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 96264543342 ps |
CPU time | 1137.2 seconds |
Started | Jul 15 06:19:30 PM PDT 24 |
Finished | Jul 15 06:38:28 PM PDT 24 |
Peak memory | 203504 kb |
Host | smart-95889e6f-232b-46b5-aca5-10eda767d9dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396005526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection. 396005526 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.3471228121 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 57045698044 ps |
CPU time | 1870.44 seconds |
Started | Jul 15 06:19:28 PM PDT 24 |
Finished | Jul 15 06:50:39 PM PDT 24 |
Peak memory | 378668 kb |
Host | smart-3a3fb09c-aef7-4114-a3fb-899e0b2da1da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471228121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.3471228121 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.765989593 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 4166192608 ps |
CPU time | 25.79 seconds |
Started | Jul 15 06:19:31 PM PDT 24 |
Finished | Jul 15 06:19:57 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-2bbd06e1-e77f-4b38-bac3-5fabab437217 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765989593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc alation.765989593 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.2916413786 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 710184112 ps |
CPU time | 7.97 seconds |
Started | Jul 15 06:19:30 PM PDT 24 |
Finished | Jul 15 06:19:38 PM PDT 24 |
Peak memory | 219104 kb |
Host | smart-d8be7a80-7251-49b1-bf23-f26c55b8c63c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916413786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.2916413786 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.355667121 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 1456798907 ps |
CPU time | 82.53 seconds |
Started | Jul 15 06:19:33 PM PDT 24 |
Finished | Jul 15 06:20:56 PM PDT 24 |
Peak memory | 210892 kb |
Host | smart-cc94f023-1fe6-4970-8cf8-e007cbb36975 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355667121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sram_ctrl_mem_partial_access.355667121 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.87585569 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 16412711438 ps |
CPU time | 255.71 seconds |
Started | Jul 15 06:19:29 PM PDT 24 |
Finished | Jul 15 06:23:45 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-abcf10eb-06ee-4ed3-8e59-5ceb2f98c470 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87585569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ mem_walk.87585569 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.745261262 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 126798908360 ps |
CPU time | 1373.57 seconds |
Started | Jul 15 06:19:29 PM PDT 24 |
Finished | Jul 15 06:42:23 PM PDT 24 |
Peak memory | 371544 kb |
Host | smart-a7590fea-2b4b-490a-8be0-1cffdc2a44e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745261262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multip le_keys.745261262 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.695123703 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 978233649 ps |
CPU time | 12.68 seconds |
Started | Jul 15 06:19:27 PM PDT 24 |
Finished | Jul 15 06:19:40 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-18146604-a26f-47df-9356-ceee6501c1f3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695123703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s ram_ctrl_partial_access.695123703 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2596026689 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 5297996069 ps |
CPU time | 291.58 seconds |
Started | Jul 15 06:19:29 PM PDT 24 |
Finished | Jul 15 06:24:21 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-d28b7686-86ee-4431-ada3-e005ff65ce9c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596026689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.2596026689 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.3196234071 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 1357350837 ps |
CPU time | 3.5 seconds |
Started | Jul 15 06:19:29 PM PDT 24 |
Finished | Jul 15 06:19:33 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-ef8030e3-bdc8-43f3-a6e2-1219eab08d54 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196234071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3196234071 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.2997175547 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 3934891109 ps |
CPU time | 1286.83 seconds |
Started | Jul 15 06:19:30 PM PDT 24 |
Finished | Jul 15 06:40:57 PM PDT 24 |
Peak memory | 381756 kb |
Host | smart-a37d2fdd-2d84-4169-b741-264fa35ae531 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997175547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2997175547 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.2004562570 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 10603874199 ps |
CPU time | 23.91 seconds |
Started | Jul 15 06:19:27 PM PDT 24 |
Finished | Jul 15 06:19:51 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-b6215ade-65f3-4059-bdf2-dd3a3b334ed4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004562570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2004562570 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1672627583 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 3452807612 ps |
CPU time | 35.94 seconds |
Started | Jul 15 06:19:35 PM PDT 24 |
Finished | Jul 15 06:20:12 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-b00f807b-9273-4d11-b3bb-f939055b57f9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1672627583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1672627583 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.4135031294 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 4745085630 ps |
CPU time | 312.24 seconds |
Started | Jul 15 06:19:31 PM PDT 24 |
Finished | Jul 15 06:24:44 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-f224ce1a-ae5a-452b-a3be-e598615dab74 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135031294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.4135031294 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3043266927 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 1505936921 ps |
CPU time | 52.2 seconds |
Started | Jul 15 06:19:33 PM PDT 24 |
Finished | Jul 15 06:20:26 PM PDT 24 |
Peak memory | 319152 kb |
Host | smart-d55a8438-bb45-47a5-9a32-ddee9766ec48 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043266927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3043266927 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.756657480 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 18652872975 ps |
CPU time | 930.76 seconds |
Started | Jul 15 06:19:41 PM PDT 24 |
Finished | Jul 15 06:35:12 PM PDT 24 |
Peak memory | 370536 kb |
Host | smart-02a29c39-10e3-4585-b4fc-53e071f5d348 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756657480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 41.sram_ctrl_access_during_key_req.756657480 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.3225459764 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 40714768 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:19:43 PM PDT 24 |
Finished | Jul 15 06:19:44 PM PDT 24 |
Peak memory | 202524 kb |
Host | smart-9f1c07af-c878-4024-a0b8-bb4c43ce5a15 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225459764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.3225459764 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.1340164624 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 265059835654 ps |
CPU time | 2406.02 seconds |
Started | Jul 15 06:19:35 PM PDT 24 |
Finished | Jul 15 06:59:42 PM PDT 24 |
Peak memory | 203596 kb |
Host | smart-866037cd-d9b8-462b-9a3d-5c3c4c465ce9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340164624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .1340164624 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.2391931504 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 2418090932 ps |
CPU time | 33.69 seconds |
Started | Jul 15 06:19:37 PM PDT 24 |
Finished | Jul 15 06:20:11 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-b431c4de-8228-4499-8859-170aeedae4cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391931504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.2391931504 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.4067184206 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 73330522372 ps |
CPU time | 89.23 seconds |
Started | Jul 15 06:19:37 PM PDT 24 |
Finished | Jul 15 06:21:06 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-11453d59-6667-44fd-872f-297476da24aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067184206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.4067184206 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.4098448496 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 3015690209 ps |
CPU time | 47.15 seconds |
Started | Jul 15 06:19:36 PM PDT 24 |
Finished | Jul 15 06:20:24 PM PDT 24 |
Peak memory | 300864 kb |
Host | smart-08b913dc-6b40-432d-8648-cfb89082cdb7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098448496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.4098448496 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1618128238 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 64467849418 ps |
CPU time | 185.7 seconds |
Started | Jul 15 06:19:44 PM PDT 24 |
Finished | Jul 15 06:22:50 PM PDT 24 |
Peak memory | 211712 kb |
Host | smart-ec19e2fd-c639-41e4-a68f-7556669ec438 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618128238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.1618128238 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.2560828239 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 57706199259 ps |
CPU time | 331.41 seconds |
Started | Jul 15 06:19:45 PM PDT 24 |
Finished | Jul 15 06:25:17 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-ba0da7ab-e216-4db4-ba66-07b6f3dbd9e5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560828239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.2560828239 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.1201594844 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 8679224355 ps |
CPU time | 1132.8 seconds |
Started | Jul 15 06:19:37 PM PDT 24 |
Finished | Jul 15 06:38:30 PM PDT 24 |
Peak memory | 380660 kb |
Host | smart-7a5dc940-1699-4755-b785-1d38dc54582a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201594844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.1201594844 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.1152466212 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 817096313 ps |
CPU time | 89.47 seconds |
Started | Jul 15 06:19:38 PM PDT 24 |
Finished | Jul 15 06:21:08 PM PDT 24 |
Peak memory | 362308 kb |
Host | smart-7388231a-1a35-4f14-a3fe-97404213c1ec |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152466212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.1152466212 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2395435960 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 12843108513 ps |
CPU time | 305.41 seconds |
Started | Jul 15 06:19:35 PM PDT 24 |
Finished | Jul 15 06:24:40 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-9caad3be-2ca3-4f26-9e90-08fb4fe3c76f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395435960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.2395435960 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.2535702078 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 1411826039 ps |
CPU time | 3.63 seconds |
Started | Jul 15 06:19:50 PM PDT 24 |
Finished | Jul 15 06:19:54 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-275c2368-996e-4b7c-97ad-e5d550443107 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535702078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2535702078 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.2556434412 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 3323077950 ps |
CPU time | 15.36 seconds |
Started | Jul 15 06:19:35 PM PDT 24 |
Finished | Jul 15 06:19:51 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-c2ab3200-c067-4207-806a-e23fc1a75142 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556434412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2556434412 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.3437548070 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 139946190970 ps |
CPU time | 4722.98 seconds |
Started | Jul 15 06:19:45 PM PDT 24 |
Finished | Jul 15 07:38:29 PM PDT 24 |
Peak memory | 386920 kb |
Host | smart-fa86c701-efe1-4c15-b853-fe57720f0490 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437548070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.3437548070 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3616550169 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 248918085 ps |
CPU time | 7.4 seconds |
Started | Jul 15 06:19:42 PM PDT 24 |
Finished | Jul 15 06:19:50 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-1d46b5e3-6c75-4484-9ac7-14618c2a475e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3616550169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3616550169 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.908836776 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 18895134831 ps |
CPU time | 182.88 seconds |
Started | Jul 15 06:19:37 PM PDT 24 |
Finished | Jul 15 06:22:40 PM PDT 24 |
Peak memory | 202328 kb |
Host | smart-e8e701ce-d85c-4e43-9ce8-2340ed074375 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908836776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_stress_pipeline.908836776 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1362507232 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 3304294457 ps |
CPU time | 101.45 seconds |
Started | Jul 15 06:19:36 PM PDT 24 |
Finished | Jul 15 06:21:18 PM PDT 24 |
Peak memory | 338656 kb |
Host | smart-29920c62-5a77-48f8-a496-bf05776e749a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362507232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1362507232 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1540932357 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 39325037486 ps |
CPU time | 644.56 seconds |
Started | Jul 15 06:19:52 PM PDT 24 |
Finished | Jul 15 06:30:38 PM PDT 24 |
Peak memory | 376552 kb |
Host | smart-273c4d92-8595-4933-a6f9-b274ffedf9d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540932357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.1540932357 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.2827485551 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 32763254 ps |
CPU time | 0.63 seconds |
Started | Jul 15 06:20:00 PM PDT 24 |
Finished | Jul 15 06:20:01 PM PDT 24 |
Peak memory | 202544 kb |
Host | smart-8f199b92-9747-41d6-9ddc-0a351094e0a2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827485551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2827485551 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.3943708993 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 110667818223 ps |
CPU time | 1977.97 seconds |
Started | Jul 15 06:19:43 PM PDT 24 |
Finished | Jul 15 06:52:42 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-b5149c86-c167-481b-861e-6afa44de1b78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943708993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .3943708993 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.3122993316 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 28890605278 ps |
CPU time | 838.45 seconds |
Started | Jul 15 06:19:52 PM PDT 24 |
Finished | Jul 15 06:33:51 PM PDT 24 |
Peak memory | 373736 kb |
Host | smart-387683d2-8610-4045-b256-0caa0274e116 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122993316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.3122993316 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.1393809743 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 56282134080 ps |
CPU time | 77.09 seconds |
Started | Jul 15 06:19:44 PM PDT 24 |
Finished | Jul 15 06:21:02 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-b46b7e72-b510-4995-981f-5c5a01732266 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393809743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.1393809743 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.2325205862 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 1890836967 ps |
CPU time | 34.51 seconds |
Started | Jul 15 06:19:44 PM PDT 24 |
Finished | Jul 15 06:20:19 PM PDT 24 |
Peak memory | 287532 kb |
Host | smart-bcdeb8de-6d74-48ad-b79e-0c3f7639c75b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325205862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.2325205862 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3143501209 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 10664221771 ps |
CPU time | 163.67 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 06:22:35 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-e7afcd0c-2587-4f80-b184-96028d7e2bd2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143501209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.3143501209 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.195323139 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 7897783909 ps |
CPU time | 124.87 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 06:21:57 PM PDT 24 |
Peak memory | 211316 kb |
Host | smart-7d13ac9e-8573-4361-a38e-92abe3168699 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195323139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl _mem_walk.195323139 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.1360344675 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 54347213657 ps |
CPU time | 1696.27 seconds |
Started | Jul 15 06:19:45 PM PDT 24 |
Finished | Jul 15 06:48:02 PM PDT 24 |
Peak memory | 379700 kb |
Host | smart-0da82324-cd85-4d7e-af07-175fd7a55f1c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360344675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.1360344675 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.4289607517 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 10124827812 ps |
CPU time | 70.99 seconds |
Started | Jul 15 06:19:44 PM PDT 24 |
Finished | Jul 15 06:20:56 PM PDT 24 |
Peak memory | 337700 kb |
Host | smart-6107a9b5-1274-4cb7-980b-3062c32fed91 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289607517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.4289607517 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1187109214 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 27625641588 ps |
CPU time | 355.31 seconds |
Started | Jul 15 06:19:49 PM PDT 24 |
Finished | Jul 15 06:25:45 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-448cc120-a287-4601-adff-83ce98906b5a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187109214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.1187109214 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.2104982701 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 4206364511 ps |
CPU time | 3.46 seconds |
Started | Jul 15 06:19:54 PM PDT 24 |
Finished | Jul 15 06:19:58 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-10181f1d-c06d-4db2-8129-818fd47a3770 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104982701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2104982701 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.1159195557 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 2496430282 ps |
CPU time | 107.86 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 06:21:40 PM PDT 24 |
Peak memory | 337716 kb |
Host | smart-23dad6c8-60e2-47ac-a110-d2a4c3ef7389 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159195557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1159195557 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.158085846 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 809192743 ps |
CPU time | 13.27 seconds |
Started | Jul 15 06:19:50 PM PDT 24 |
Finished | Jul 15 06:20:03 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-06fa98c1-7552-4f81-bbad-709acd2a7b9a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158085846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.158085846 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.1815949432 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 1138362970174 ps |
CPU time | 7442.06 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 08:23:55 PM PDT 24 |
Peak memory | 398260 kb |
Host | smart-876f92c5-d9b6-40ed-908e-19657043dd1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815949432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1815949432 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.402319159 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 2968360093 ps |
CPU time | 36.37 seconds |
Started | Jul 15 06:19:53 PM PDT 24 |
Finished | Jul 15 06:20:30 PM PDT 24 |
Peak memory | 219272 kb |
Host | smart-c2fc74bd-f7b7-4b14-bd99-b2792c329e3d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=402319159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.402319159 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.507832601 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 2512394759 ps |
CPU time | 152.31 seconds |
Started | Jul 15 06:19:49 PM PDT 24 |
Finished | Jul 15 06:22:21 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-de35f699-d9bb-412e-8ebc-0fbd89a599c5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507832601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_stress_pipeline.507832601 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2511449552 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 720300191 ps |
CPU time | 7.69 seconds |
Started | Jul 15 06:19:44 PM PDT 24 |
Finished | Jul 15 06:19:53 PM PDT 24 |
Peak memory | 220108 kb |
Host | smart-4850bdaf-36dd-4deb-b6d7-5ba55f050bbd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511449552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2511449552 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2952528181 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 3509887153 ps |
CPU time | 378.18 seconds |
Started | Jul 15 06:19:52 PM PDT 24 |
Finished | Jul 15 06:26:11 PM PDT 24 |
Peak memory | 372492 kb |
Host | smart-c0e8b37a-a659-4a18-b73c-efc0159c2712 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952528181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.2952528181 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.116657102 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 30388921 ps |
CPU time | 0.64 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 06:19:52 PM PDT 24 |
Peak memory | 202536 kb |
Host | smart-0b58d6e8-966e-4ddf-b376-c198c85d0cda |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116657102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.116657102 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.2304587909 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 364537618959 ps |
CPU time | 2130.22 seconds |
Started | Jul 15 06:19:53 PM PDT 24 |
Finished | Jul 15 06:55:24 PM PDT 24 |
Peak memory | 203548 kb |
Host | smart-5c4076df-ad55-4a4a-ad51-2c6fe0a163ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304587909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .2304587909 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.1805061858 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 13696270749 ps |
CPU time | 342.58 seconds |
Started | Jul 15 06:19:52 PM PDT 24 |
Finished | Jul 15 06:25:36 PM PDT 24 |
Peak memory | 368428 kb |
Host | smart-e497309e-21a9-4eea-b3b0-c996e5703ce9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805061858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.1805061858 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.2510186043 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 28741488747 ps |
CPU time | 93.72 seconds |
Started | Jul 15 06:19:53 PM PDT 24 |
Finished | Jul 15 06:21:27 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-a4f3beef-fa76-4d9d-8ad0-8f256a73c131 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510186043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.2510186043 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.3014938052 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 2730834813 ps |
CPU time | 141.99 seconds |
Started | Jul 15 06:19:59 PM PDT 24 |
Finished | Jul 15 06:22:22 PM PDT 24 |
Peak memory | 367292 kb |
Host | smart-a73d24ba-2b25-46da-9585-8634153468bf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014938052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.3014938052 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.497949401 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 3451766639 ps |
CPU time | 74.11 seconds |
Started | Jul 15 06:19:53 PM PDT 24 |
Finished | Jul 15 06:21:08 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-fe9050e4-5bc7-450f-8689-c2435268c405 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497949401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43 .sram_ctrl_mem_partial_access.497949401 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.1153605151 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 9877950570 ps |
CPU time | 127.01 seconds |
Started | Jul 15 06:20:00 PM PDT 24 |
Finished | Jul 15 06:22:07 PM PDT 24 |
Peak memory | 210904 kb |
Host | smart-18b738d5-c45a-4f4e-a287-02b4847342f2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153605151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.1153605151 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.2778022022 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 16530577641 ps |
CPU time | 1012.7 seconds |
Started | Jul 15 06:19:52 PM PDT 24 |
Finished | Jul 15 06:36:46 PM PDT 24 |
Peak memory | 378656 kb |
Host | smart-14767998-b235-4f11-bc43-e97bd3fdda0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778022022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2778022022 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.2834313214 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 1366874859 ps |
CPU time | 3.93 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 06:19:56 PM PDT 24 |
Peak memory | 202568 kb |
Host | smart-eccff33d-82fd-4dc6-bf57-5c76e153f7d5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834313214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.2834313214 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1388326308 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 39610349167 ps |
CPU time | 519.92 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 06:28:31 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-c2f1c3f0-1c87-4ecd-a661-38837a208122 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388326308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.1388326308 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.1754612578 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 360231580 ps |
CPU time | 3.25 seconds |
Started | Jul 15 06:19:54 PM PDT 24 |
Finished | Jul 15 06:19:58 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-76bab91c-5f64-498d-acb2-34da47602e48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754612578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1754612578 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.3028587340 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 29524509197 ps |
CPU time | 820.02 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 06:33:32 PM PDT 24 |
Peak memory | 377676 kb |
Host | smart-0d1feeac-018f-4b8c-9555-c22d506eae8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028587340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3028587340 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.1040553596 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 2536565448 ps |
CPU time | 36.5 seconds |
Started | Jul 15 06:19:53 PM PDT 24 |
Finished | Jul 15 06:20:30 PM PDT 24 |
Peak memory | 278472 kb |
Host | smart-7a457e9e-379f-4356-906b-bd1ed448c096 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040553596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1040553596 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.3489562673 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 956154849175 ps |
CPU time | 5552.36 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 07:52:24 PM PDT 24 |
Peak memory | 379696 kb |
Host | smart-d8a2703a-e7e4-47d4-9f39-da590913ed56 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489562673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.3489562673 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3894369617 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 361910729 ps |
CPU time | 18.36 seconds |
Started | Jul 15 06:19:51 PM PDT 24 |
Finished | Jul 15 06:20:10 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-22c5c0c8-3efb-44c8-8380-4ba07a64e434 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3894369617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3894369617 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1884701478 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 6165964006 ps |
CPU time | 165.04 seconds |
Started | Jul 15 06:19:49 PM PDT 24 |
Finished | Jul 15 06:22:34 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-d5224546-5bc9-4595-913d-6d630f24bc8e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884701478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.1884701478 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1212976170 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 12559425455 ps |
CPU time | 52.36 seconds |
Started | Jul 15 06:19:53 PM PDT 24 |
Finished | Jul 15 06:20:46 PM PDT 24 |
Peak memory | 328356 kb |
Host | smart-5cf69749-d0f6-4f80-84b3-e408e7932ae3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212976170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1212976170 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.224420360 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 18208826278 ps |
CPU time | 733.57 seconds |
Started | Jul 15 06:19:56 PM PDT 24 |
Finished | Jul 15 06:32:10 PM PDT 24 |
Peak memory | 368824 kb |
Host | smart-5e016339-7266-463d-bf66-4a083f54fd1a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224420360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 44.sram_ctrl_access_during_key_req.224420360 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.3557867901 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 50271226 ps |
CPU time | 0.72 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 06:20:00 PM PDT 24 |
Peak memory | 202536 kb |
Host | smart-206a4f59-5f78-4014-9196-6f5f590224e1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557867901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.3557867901 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.2198754322 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 111539981678 ps |
CPU time | 1942.61 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 06:52:22 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-d002621a-8841-4443-a620-b5d05946c276 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198754322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .2198754322 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.1250349403 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 5762321489 ps |
CPU time | 146.13 seconds |
Started | Jul 15 06:19:57 PM PDT 24 |
Finished | Jul 15 06:22:24 PM PDT 24 |
Peak memory | 333304 kb |
Host | smart-025905df-4da8-4fe3-9ed5-c546475ee829 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250349403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.1250349403 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.3503744661 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 30208628057 ps |
CPU time | 93.81 seconds |
Started | Jul 15 06:19:59 PM PDT 24 |
Finished | Jul 15 06:21:33 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-59e3280d-fe27-4281-90e5-d43c9f03778c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503744661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.3503744661 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.4055536843 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 757249135 ps |
CPU time | 44.1 seconds |
Started | Jul 15 06:19:57 PM PDT 24 |
Finished | Jul 15 06:20:42 PM PDT 24 |
Peak memory | 294568 kb |
Host | smart-2a08c9d2-af4a-4561-a1ad-37532f0ec073 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055536843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.4055536843 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3734557755 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 2811415310 ps |
CPU time | 75.15 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 06:21:14 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-3bf9c79b-de97-400c-bcf8-a5529e08b447 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734557755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.3734557755 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.1783395704 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 41422262614 ps |
CPU time | 182.8 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 06:23:01 PM PDT 24 |
Peak memory | 211740 kb |
Host | smart-a6745f0c-36da-48eb-952c-5dc5e35d8bf2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783395704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1783395704 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.1168798951 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 25666634443 ps |
CPU time | 1013.58 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 06:36:52 PM PDT 24 |
Peak memory | 378720 kb |
Host | smart-35b33c38-48a1-4542-84e1-ff01076bbf36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168798951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.1168798951 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.157752817 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 1184143594 ps |
CPU time | 22.59 seconds |
Started | Jul 15 06:19:57 PM PDT 24 |
Finished | Jul 15 06:20:20 PM PDT 24 |
Peak memory | 260032 kb |
Host | smart-2a52ac01-c873-4f96-b942-871287e7fc18 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157752817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s ram_ctrl_partial_access.157752817 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2488847144 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 24898875677 ps |
CPU time | 320.37 seconds |
Started | Jul 15 06:19:57 PM PDT 24 |
Finished | Jul 15 06:25:18 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-c1a522c7-1c1d-4a4b-b722-5132da75c0c8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488847144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.2488847144 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.566548875 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1348996910 ps |
CPU time | 3.54 seconds |
Started | Jul 15 06:19:59 PM PDT 24 |
Finished | Jul 15 06:20:03 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-7fee7c26-013e-4b46-89fb-9739169ebd6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566548875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.566548875 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.1738223514 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 10132204710 ps |
CPU time | 212.46 seconds |
Started | Jul 15 06:20:07 PM PDT 24 |
Finished | Jul 15 06:23:40 PM PDT 24 |
Peak memory | 368476 kb |
Host | smart-34252a11-3f33-4c17-8f64-4a824e3fe821 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738223514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1738223514 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.801266156 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 3745633882 ps |
CPU time | 9.51 seconds |
Started | Jul 15 06:19:59 PM PDT 24 |
Finished | Jul 15 06:20:09 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-c1e4f763-056a-4056-887e-701b70602d17 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801266156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.801266156 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.3749339529 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 165645879843 ps |
CPU time | 7296.48 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 08:21:37 PM PDT 24 |
Peak memory | 382808 kb |
Host | smart-cf4bd77e-920a-4e35-bb29-3a9de1bd35f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749339529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.3749339529 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1671430415 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 36479059720 ps |
CPU time | 228.07 seconds |
Started | Jul 15 06:20:07 PM PDT 24 |
Finished | Jul 15 06:23:56 PM PDT 24 |
Peak memory | 375580 kb |
Host | smart-cdfee633-98f7-4b68-8a1c-bada18b22b4a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1671430415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1671430415 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2675932374 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 83226753431 ps |
CPU time | 374.61 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 06:26:13 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-e58115b0-0623-4bb5-b10d-f751c2cf02e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675932374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.2675932374 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3938274762 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 694751458 ps |
CPU time | 8.42 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 06:20:08 PM PDT 24 |
Peak memory | 220576 kb |
Host | smart-d7a35ec0-b6e1-4188-bb03-440d759c8d05 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938274762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3938274762 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1506339986 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 226834501570 ps |
CPU time | 1124.08 seconds |
Started | Jul 15 06:20:05 PM PDT 24 |
Finished | Jul 15 06:38:50 PM PDT 24 |
Peak memory | 377640 kb |
Host | smart-592013ad-f9a8-4562-b639-3ef74d0bb3fe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506339986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.1506339986 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.2288132766 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 16615008 ps |
CPU time | 0.67 seconds |
Started | Jul 15 06:20:05 PM PDT 24 |
Finished | Jul 15 06:20:06 PM PDT 24 |
Peak memory | 202512 kb |
Host | smart-f508ef84-4960-43b5-b929-d724d21ca6a0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288132766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2288132766 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.2012172554 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 76112855000 ps |
CPU time | 1314.48 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 06:41:53 PM PDT 24 |
Peak memory | 203340 kb |
Host | smart-28afd559-99fb-4c40-ad19-bb18bbf34c16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012172554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .2012172554 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.2063627377 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 27582679696 ps |
CPU time | 785.52 seconds |
Started | Jul 15 06:20:07 PM PDT 24 |
Finished | Jul 15 06:33:13 PM PDT 24 |
Peak memory | 370528 kb |
Host | smart-13088fe2-75a4-4636-b0f2-2fda3184fbf4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063627377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.2063627377 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.471361359 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 32927691924 ps |
CPU time | 62.63 seconds |
Started | Jul 15 06:20:06 PM PDT 24 |
Finished | Jul 15 06:21:09 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-fef13535-59ac-43f4-acbf-691a63ff99f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471361359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esc alation.471361359 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.2278573119 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 5032013258 ps |
CPU time | 21.48 seconds |
Started | Jul 15 06:20:04 PM PDT 24 |
Finished | Jul 15 06:20:26 PM PDT 24 |
Peak memory | 268232 kb |
Host | smart-c57b9096-6c6b-470e-923c-5fae972859fa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278573119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.2278573119 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2768694780 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 2711159795 ps |
CPU time | 85.81 seconds |
Started | Jul 15 06:20:05 PM PDT 24 |
Finished | Jul 15 06:21:31 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-7a7d25e9-70fd-4118-948b-ffaa682a5aae |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768694780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.2768694780 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.358246523 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 1977158582 ps |
CPU time | 124.23 seconds |
Started | Jul 15 06:20:05 PM PDT 24 |
Finished | Jul 15 06:22:10 PM PDT 24 |
Peak memory | 210884 kb |
Host | smart-122c6b90-407d-410e-9e63-1a3f2c52b74d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358246523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _mem_walk.358246523 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.21504084 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 5614029242 ps |
CPU time | 265.47 seconds |
Started | Jul 15 06:20:08 PM PDT 24 |
Finished | Jul 15 06:24:34 PM PDT 24 |
Peak memory | 367364 kb |
Host | smart-942489c2-75c9-452c-9b9e-45c3ea3d0e96 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21504084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multipl e_keys.21504084 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.1152929146 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 718749035 ps |
CPU time | 6.56 seconds |
Started | Jul 15 06:20:07 PM PDT 24 |
Finished | Jul 15 06:20:14 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-dac7cdff-7260-4e59-9fb4-13914bc4d003 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152929146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.1152929146 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.904605974 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 21226940875 ps |
CPU time | 196.57 seconds |
Started | Jul 15 06:20:06 PM PDT 24 |
Finished | Jul 15 06:23:24 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-5418fd61-cb1f-4bfa-836b-f5363a1e7f8d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904605974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.sram_ctrl_partial_access_b2b.904605974 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.3380084163 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 2578894496 ps |
CPU time | 3.47 seconds |
Started | Jul 15 06:20:06 PM PDT 24 |
Finished | Jul 15 06:20:11 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-308edd39-85fb-4a6f-9820-5a7dd89c3cad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380084163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3380084163 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.2347682603 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 8356029656 ps |
CPU time | 206.18 seconds |
Started | Jul 15 06:20:05 PM PDT 24 |
Finished | Jul 15 06:23:32 PM PDT 24 |
Peak memory | 336640 kb |
Host | smart-35bd6cb6-1a2a-4d3e-8a29-e49f76da463c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347682603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2347682603 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.3818696110 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 1659679588 ps |
CPU time | 18.58 seconds |
Started | Jul 15 06:19:58 PM PDT 24 |
Finished | Jul 15 06:20:17 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-58795c89-1816-4201-bdfa-fe58e7d662c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818696110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3818696110 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.1802274961 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 97212564667 ps |
CPU time | 1908.34 seconds |
Started | Jul 15 06:20:09 PM PDT 24 |
Finished | Jul 15 06:51:58 PM PDT 24 |
Peak memory | 375616 kb |
Host | smart-da91d164-87de-4918-bb88-565f8a53c049 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802274961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.1802274961 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.342823155 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 1663247531 ps |
CPU time | 41.26 seconds |
Started | Jul 15 06:20:06 PM PDT 24 |
Finished | Jul 15 06:20:48 PM PDT 24 |
Peak memory | 219276 kb |
Host | smart-976af960-2867-4ee4-ae81-1ace990166b2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=342823155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.342823155 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2344835467 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 4175668960 ps |
CPU time | 256.65 seconds |
Started | Jul 15 06:20:07 PM PDT 24 |
Finished | Jul 15 06:24:24 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-7aba71cd-f26d-4c3b-996f-e97b77decebd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344835467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2344835467 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4006547248 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 3086088572 ps |
CPU time | 62.62 seconds |
Started | Jul 15 06:20:05 PM PDT 24 |
Finished | Jul 15 06:21:08 PM PDT 24 |
Peak memory | 305252 kb |
Host | smart-4263367e-5f50-433c-9fca-e05bc1aa5d8e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006547248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.4006547248 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.4217187538 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 9280580759 ps |
CPU time | 654.6 seconds |
Started | Jul 15 06:20:19 PM PDT 24 |
Finished | Jul 15 06:31:14 PM PDT 24 |
Peak memory | 378868 kb |
Host | smart-3b50193e-aff1-448e-b8b0-c7333174a801 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217187538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.4217187538 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.2588335469 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 20874420 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:20:19 PM PDT 24 |
Finished | Jul 15 06:20:20 PM PDT 24 |
Peak memory | 202300 kb |
Host | smart-321dd971-40f4-4a3f-ba9a-b06ca6ea14a5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588335469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2588335469 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.45248983 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 689902217531 ps |
CPU time | 2443.77 seconds |
Started | Jul 15 06:20:14 PM PDT 24 |
Finished | Jul 15 07:00:59 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-51500321-8fb1-47b4-b682-93cd6ff23043 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45248983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.45248983 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.2137253840 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 57363057019 ps |
CPU time | 1344.73 seconds |
Started | Jul 15 06:20:19 PM PDT 24 |
Finished | Jul 15 06:42:45 PM PDT 24 |
Peak memory | 379644 kb |
Host | smart-b27633b3-5161-4f40-bf12-32cad3ef2dc6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137253840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.2137253840 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.1609175047 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 6177873775 ps |
CPU time | 41.84 seconds |
Started | Jul 15 06:20:20 PM PDT 24 |
Finished | Jul 15 06:21:03 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-b34c9aa2-acc1-4d53-9833-c8acbefacfa6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609175047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.1609175047 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.925736809 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 2764221179 ps |
CPU time | 60.37 seconds |
Started | Jul 15 06:20:13 PM PDT 24 |
Finished | Jul 15 06:21:13 PM PDT 24 |
Peak memory | 335588 kb |
Host | smart-4b599c48-d13b-4462-8c69-b9463212a183 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925736809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.sram_ctrl_max_throughput.925736809 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.793576682 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 4576109285 ps |
CPU time | 145.43 seconds |
Started | Jul 15 06:20:19 PM PDT 24 |
Finished | Jul 15 06:22:45 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-8ced7ad1-d08f-4056-984a-0a9f919dd616 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793576682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sram_ctrl_mem_partial_access.793576682 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.1616090369 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 7105954834 ps |
CPU time | 291.52 seconds |
Started | Jul 15 06:20:18 PM PDT 24 |
Finished | Jul 15 06:25:10 PM PDT 24 |
Peak memory | 210912 kb |
Host | smart-bfa3b4c4-d7a6-4818-8884-9820a02a235f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616090369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.1616090369 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.1012609074 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 61650525341 ps |
CPU time | 903.05 seconds |
Started | Jul 15 06:20:12 PM PDT 24 |
Finished | Jul 15 06:35:15 PM PDT 24 |
Peak memory | 376580 kb |
Host | smart-ba363a8e-5b1d-4573-bc0f-d0b22f2fb8b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012609074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.1012609074 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.3684364361 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 3674889558 ps |
CPU time | 18.61 seconds |
Started | Jul 15 06:20:12 PM PDT 24 |
Finished | Jul 15 06:20:31 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-76e61c7d-688a-48a8-91d7-078aaa8398e6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684364361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.3684364361 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3839834492 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 16677752650 ps |
CPU time | 429.64 seconds |
Started | Jul 15 06:20:12 PM PDT 24 |
Finished | Jul 15 06:27:22 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-70ba4058-b208-4528-a82e-48c0b338a978 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839834492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.3839834492 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.2024861356 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 390018402 ps |
CPU time | 3.39 seconds |
Started | Jul 15 06:20:20 PM PDT 24 |
Finished | Jul 15 06:20:24 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-4214a063-9f46-47da-bb23-37e613a8623d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024861356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2024861356 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.2154357689 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 90930714976 ps |
CPU time | 1252.75 seconds |
Started | Jul 15 06:20:20 PM PDT 24 |
Finished | Jul 15 06:41:13 PM PDT 24 |
Peak memory | 380760 kb |
Host | smart-ccf93067-4355-4eb8-85ac-fbe4fddfd4c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154357689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2154357689 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.176671382 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 1116813022 ps |
CPU time | 16.53 seconds |
Started | Jul 15 06:20:16 PM PDT 24 |
Finished | Jul 15 06:20:33 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-eef0ea79-1c2f-4140-a8ab-000652e27705 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176671382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.176671382 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.3351628187 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 71032519930 ps |
CPU time | 5616.37 seconds |
Started | Jul 15 06:20:20 PM PDT 24 |
Finished | Jul 15 07:53:58 PM PDT 24 |
Peak memory | 389500 kb |
Host | smart-fe5f247d-4ca9-4745-96ea-5fda91efedfa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351628187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.3351628187 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3904773821 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 305539220 ps |
CPU time | 13.02 seconds |
Started | Jul 15 06:20:18 PM PDT 24 |
Finished | Jul 15 06:20:32 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-f7251899-ce7e-4812-9ed4-011fff595c85 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3904773821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3904773821 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2407817959 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 39800671377 ps |
CPU time | 277.36 seconds |
Started | Jul 15 06:20:12 PM PDT 24 |
Finished | Jul 15 06:24:50 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-8ccaafae-9a61-42b5-a296-a3c3cf37e127 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407817959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.2407817959 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4079687136 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 1430032144 ps |
CPU time | 32.87 seconds |
Started | Jul 15 06:20:12 PM PDT 24 |
Finished | Jul 15 06:20:46 PM PDT 24 |
Peak memory | 288572 kb |
Host | smart-ab5b96d1-2e52-4b5b-9a59-c0fd5a494972 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079687136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.4079687136 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3442103459 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 14708555925 ps |
CPU time | 384.55 seconds |
Started | Jul 15 06:20:26 PM PDT 24 |
Finished | Jul 15 06:26:51 PM PDT 24 |
Peak memory | 365372 kb |
Host | smart-1c725124-7dc1-4384-a714-2a82f8451613 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442103459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.3442103459 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.3974319519 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 29187655622 ps |
CPU time | 2049.17 seconds |
Started | Jul 15 06:20:20 PM PDT 24 |
Finished | Jul 15 06:54:30 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-7c1adaa0-b478-4649-b991-90039b8f42a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974319519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .3974319519 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.583218394 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 15648758869 ps |
CPU time | 25.56 seconds |
Started | Jul 15 06:20:25 PM PDT 24 |
Finished | Jul 15 06:20:51 PM PDT 24 |
Peak memory | 214532 kb |
Host | smart-086f27a4-6f4d-4b84-84f0-d742c6f32e7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583218394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esc alation.583218394 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.4188170513 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 809599281 ps |
CPU time | 66.93 seconds |
Started | Jul 15 06:20:25 PM PDT 24 |
Finished | Jul 15 06:21:32 PM PDT 24 |
Peak memory | 338704 kb |
Host | smart-ec91cebc-bd6f-41dd-8ccf-2c1c0771b71c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188170513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.4188170513 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.202925625 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 5206249877 ps |
CPU time | 151.87 seconds |
Started | Jul 15 06:20:32 PM PDT 24 |
Finished | Jul 15 06:23:05 PM PDT 24 |
Peak memory | 219144 kb |
Host | smart-5efc2fac-3afa-40b1-8c1b-b7c3d777e3f5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202925625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_mem_partial_access.202925625 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.132644004 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 41379103517 ps |
CPU time | 183.79 seconds |
Started | Jul 15 06:20:33 PM PDT 24 |
Finished | Jul 15 06:23:37 PM PDT 24 |
Peak memory | 211856 kb |
Host | smart-ea2d4c82-a344-4aab-b3f3-1048f58dfe63 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132644004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl _mem_walk.132644004 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.794029291 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 28195359969 ps |
CPU time | 1149.22 seconds |
Started | Jul 15 06:20:19 PM PDT 24 |
Finished | Jul 15 06:39:28 PM PDT 24 |
Peak memory | 379592 kb |
Host | smart-ea3ac92c-dbc2-4562-9d74-2cdad6a4231c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794029291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip le_keys.794029291 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.1147055690 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 1116906867 ps |
CPU time | 14.58 seconds |
Started | Jul 15 06:20:26 PM PDT 24 |
Finished | Jul 15 06:20:41 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-7a3241de-4f5d-4b2b-ae8c-ad99bc3fae77 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147055690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.1147055690 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.858938182 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 1347855882 ps |
CPU time | 3.34 seconds |
Started | Jul 15 06:20:30 PM PDT 24 |
Finished | Jul 15 06:20:34 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-58499370-4f8b-4918-8d9e-fdb383101e07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858938182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.858938182 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.2140044294 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 14091915798 ps |
CPU time | 1558.93 seconds |
Started | Jul 15 06:20:33 PM PDT 24 |
Finished | Jul 15 06:46:33 PM PDT 24 |
Peak memory | 377732 kb |
Host | smart-44e8a8d8-0571-4b7a-939b-61f60aa3d633 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140044294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2140044294 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.2699467354 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 3682957338 ps |
CPU time | 10 seconds |
Started | Jul 15 06:20:21 PM PDT 24 |
Finished | Jul 15 06:20:31 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-591e0492-2636-4aea-853d-58d5c0e21034 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699467354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2699467354 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.1771554647 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 128529230757 ps |
CPU time | 5092.39 seconds |
Started | Jul 15 06:20:32 PM PDT 24 |
Finished | Jul 15 07:45:26 PM PDT 24 |
Peak memory | 380732 kb |
Host | smart-14899f70-e239-48cb-8671-da97056b2ee4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771554647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.1771554647 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1621418727 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 4265290959 ps |
CPU time | 24.29 seconds |
Started | Jul 15 06:20:31 PM PDT 24 |
Finished | Jul 15 06:20:55 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-906e58ba-e3f6-4db5-bdff-53ecc0225282 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1621418727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1621418727 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2196642693 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 46486173015 ps |
CPU time | 379.59 seconds |
Started | Jul 15 06:20:24 PM PDT 24 |
Finished | Jul 15 06:26:44 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-0844f830-1315-4c62-be96-d9538481c8c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196642693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.2196642693 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2258660307 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 685487604 ps |
CPU time | 7.03 seconds |
Started | Jul 15 06:20:25 PM PDT 24 |
Finished | Jul 15 06:20:33 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-c464759a-9bad-4d25-8455-05883c1599e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258660307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.2258660307 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3840627038 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 74565337834 ps |
CPU time | 1302.38 seconds |
Started | Jul 15 06:20:34 PM PDT 24 |
Finished | Jul 15 06:42:17 PM PDT 24 |
Peak memory | 376676 kb |
Host | smart-06542588-d952-41d7-96d8-6ccdb062718c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840627038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.3840627038 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.2577434928 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 19135107 ps |
CPU time | 0.63 seconds |
Started | Jul 15 06:20:42 PM PDT 24 |
Finished | Jul 15 06:20:43 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-f6620fb5-406f-4b12-8bfa-3754b5f91c04 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577434928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.2577434928 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.1243472866 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 202819688299 ps |
CPU time | 2437.51 seconds |
Started | Jul 15 06:20:33 PM PDT 24 |
Finished | Jul 15 07:01:11 PM PDT 24 |
Peak memory | 203388 kb |
Host | smart-0d3a061f-103a-4c9e-ada7-a39fa7451a1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243472866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .1243472866 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.775610370 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 32007638521 ps |
CPU time | 1066.82 seconds |
Started | Jul 15 06:20:36 PM PDT 24 |
Finished | Jul 15 06:38:24 PM PDT 24 |
Peak memory | 379612 kb |
Host | smart-4cd9bd9b-7160-49ee-9d82-5f9872385e83 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775610370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl e.775610370 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.3591756915 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 10210131573 ps |
CPU time | 35.63 seconds |
Started | Jul 15 06:20:37 PM PDT 24 |
Finished | Jul 15 06:21:13 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-8a7360da-ad0e-4a2d-ba3e-4c0300a1f612 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591756915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.3591756915 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.946836505 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 800896172 ps |
CPU time | 6.36 seconds |
Started | Jul 15 06:20:38 PM PDT 24 |
Finished | Jul 15 06:20:45 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-9ca561de-8ac1-486d-a3a3-0fcbf4a5fab8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946836505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.sram_ctrl_max_throughput.946836505 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4256066190 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 5516596803 ps |
CPU time | 170.73 seconds |
Started | Jul 15 06:20:35 PM PDT 24 |
Finished | Jul 15 06:23:26 PM PDT 24 |
Peak memory | 219168 kb |
Host | smart-50a5df9c-bd99-4434-93ff-d28e7d8b83fa |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256066190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.4256066190 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.1597956200 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 138418906634 ps |
CPU time | 204.17 seconds |
Started | Jul 15 06:20:37 PM PDT 24 |
Finished | Jul 15 06:24:01 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-b77882e3-ecc7-485a-ac6a-0523efd501b1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597956200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.1597956200 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.2140148629 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 5725822009 ps |
CPU time | 936.6 seconds |
Started | Jul 15 06:20:33 PM PDT 24 |
Finished | Jul 15 06:36:10 PM PDT 24 |
Peak memory | 378708 kb |
Host | smart-9d21ee10-244d-48d4-b31a-bded5350617a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140148629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.2140148629 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.1553510859 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 1690880632 ps |
CPU time | 101.66 seconds |
Started | Jul 15 06:20:32 PM PDT 24 |
Finished | Jul 15 06:22:14 PM PDT 24 |
Peak memory | 351856 kb |
Host | smart-73ba043f-f420-499b-a34d-bd4ad4efc840 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553510859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1553510859 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.346353103 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 35526955724 ps |
CPU time | 406.78 seconds |
Started | Jul 15 06:20:32 PM PDT 24 |
Finished | Jul 15 06:27:19 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-d7c3429f-faa1-43ae-ab10-747dfda6afb8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346353103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.sram_ctrl_partial_access_b2b.346353103 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.1053990310 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 391063399 ps |
CPU time | 3.42 seconds |
Started | Jul 15 06:20:37 PM PDT 24 |
Finished | Jul 15 06:20:41 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-58ff50a5-b3ea-439a-8f7b-085b87090366 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053990310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1053990310 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.3825385143 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 15877319587 ps |
CPU time | 598.28 seconds |
Started | Jul 15 06:20:37 PM PDT 24 |
Finished | Jul 15 06:30:36 PM PDT 24 |
Peak memory | 369476 kb |
Host | smart-b28ea28d-207e-4e4c-9045-29075ece7441 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825385143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3825385143 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.3162496665 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 671655580 ps |
CPU time | 6.19 seconds |
Started | Jul 15 06:20:31 PM PDT 24 |
Finished | Jul 15 06:20:38 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-3bafcabb-4602-4bc7-9438-9d2cc95b27a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162496665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3162496665 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.1544161751 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 68665182658 ps |
CPU time | 3467.3 seconds |
Started | Jul 15 06:20:42 PM PDT 24 |
Finished | Jul 15 07:18:30 PM PDT 24 |
Peak memory | 380692 kb |
Host | smart-dd2aa56c-3e14-4a6c-b52a-cb6f013e8b30 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544161751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.1544161751 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2598242084 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 4407102113 ps |
CPU time | 102.08 seconds |
Started | Jul 15 06:20:43 PM PDT 24 |
Finished | Jul 15 06:22:26 PM PDT 24 |
Peak memory | 335736 kb |
Host | smart-4cb2e263-5bda-45dc-bdf7-3bacfe9194b9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2598242084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2598242084 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2186247776 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 13339458915 ps |
CPU time | 195.38 seconds |
Started | Jul 15 06:20:32 PM PDT 24 |
Finished | Jul 15 06:23:48 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-76759b5e-789b-43a6-9a94-c6457b2ca30f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186247776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.2186247776 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.430751584 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 765272347 ps |
CPU time | 36.93 seconds |
Started | Jul 15 06:20:36 PM PDT 24 |
Finished | Jul 15 06:21:13 PM PDT 24 |
Peak memory | 290624 kb |
Host | smart-e349546a-0f1d-4127-8d89-bd59a4d1170d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430751584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.430751584 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2095020035 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 11981507219 ps |
CPU time | 970.02 seconds |
Started | Jul 15 06:20:48 PM PDT 24 |
Finished | Jul 15 06:36:59 PM PDT 24 |
Peak memory | 379716 kb |
Host | smart-20d1d127-41a8-4dc1-8c07-81aaefddfe64 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095020035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.2095020035 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.2210967911 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 40153935 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:20:52 PM PDT 24 |
Finished | Jul 15 06:20:53 PM PDT 24 |
Peak memory | 202264 kb |
Host | smart-63b18ef3-e39e-4a12-9cfe-99a9bf5675a3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210967911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2210967911 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.2741330629 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 461510736483 ps |
CPU time | 1768.58 seconds |
Started | Jul 15 06:20:43 PM PDT 24 |
Finished | Jul 15 06:50:12 PM PDT 24 |
Peak memory | 203592 kb |
Host | smart-7d61dda8-b9bd-4ad1-9755-4ec024cb9d49 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741330629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .2741330629 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.1707676876 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 5378083289 ps |
CPU time | 1131.95 seconds |
Started | Jul 15 06:20:52 PM PDT 24 |
Finished | Jul 15 06:39:45 PM PDT 24 |
Peak memory | 374488 kb |
Host | smart-aee7747f-5fa9-4117-87a8-dc89ac99d8f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707676876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.1707676876 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.1871007431 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 17377017249 ps |
CPU time | 26.11 seconds |
Started | Jul 15 06:20:49 PM PDT 24 |
Finished | Jul 15 06:21:16 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-3fc203c7-0fb1-4737-8787-71b28344c64b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871007431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.1871007431 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.879651738 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 1597142855 ps |
CPU time | 149.79 seconds |
Started | Jul 15 06:20:44 PM PDT 24 |
Finished | Jul 15 06:23:14 PM PDT 24 |
Peak memory | 372384 kb |
Host | smart-8089328b-e334-4c1e-b5c2-7bbf61abbfdd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879651738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.sram_ctrl_max_throughput.879651738 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1073214710 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 5801492852 ps |
CPU time | 170.02 seconds |
Started | Jul 15 06:20:50 PM PDT 24 |
Finished | Jul 15 06:23:40 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-b6571fac-13c0-41ed-9b26-13934be1af22 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073214710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.1073214710 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.2257630902 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 2833017558 ps |
CPU time | 147.19 seconds |
Started | Jul 15 06:20:51 PM PDT 24 |
Finished | Jul 15 06:23:19 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-34a4e0ff-d39e-4c1b-9d5d-cf140a0bff43 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257630902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.2257630902 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.589856325 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 11375415725 ps |
CPU time | 790.03 seconds |
Started | Jul 15 06:20:42 PM PDT 24 |
Finished | Jul 15 06:33:53 PM PDT 24 |
Peak memory | 372136 kb |
Host | smart-b97d6796-69fe-4b0c-9439-11832d1ca886 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589856325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip le_keys.589856325 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.3564039331 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 814358362 ps |
CPU time | 8.96 seconds |
Started | Jul 15 06:20:44 PM PDT 24 |
Finished | Jul 15 06:20:53 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-f591e0e9-2ae2-4519-b5ab-3e87c5720967 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564039331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.3564039331 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3229506147 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 18450067403 ps |
CPU time | 463.96 seconds |
Started | Jul 15 06:20:43 PM PDT 24 |
Finished | Jul 15 06:28:27 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-ffc8cc67-8984-4459-99c3-2bc51a803e65 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229506147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.3229506147 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.2769415818 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 1525960401 ps |
CPU time | 3.56 seconds |
Started | Jul 15 06:20:48 PM PDT 24 |
Finished | Jul 15 06:20:52 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-87914cff-0a28-4c0a-a87c-1e4473a0f742 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769415818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.2769415818 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.539786320 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 75526913240 ps |
CPU time | 1567.71 seconds |
Started | Jul 15 06:20:49 PM PDT 24 |
Finished | Jul 15 06:46:58 PM PDT 24 |
Peak memory | 370496 kb |
Host | smart-6b44b1b0-1210-4f80-a4f2-4c1a21d9cf83 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539786320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.539786320 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.3368312590 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 1380480673 ps |
CPU time | 3.6 seconds |
Started | Jul 15 06:20:42 PM PDT 24 |
Finished | Jul 15 06:20:46 PM PDT 24 |
Peak memory | 202604 kb |
Host | smart-75b34a26-d48c-4298-97cd-41b8f477b5df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368312590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3368312590 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.2885502382 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 244349074140 ps |
CPU time | 5054.75 seconds |
Started | Jul 15 06:20:52 PM PDT 24 |
Finished | Jul 15 07:45:08 PM PDT 24 |
Peak memory | 383948 kb |
Host | smart-49189848-839c-40af-b477-6e8dcfb0a49c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885502382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.2885502382 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.335030228 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 7104318932 ps |
CPU time | 56.82 seconds |
Started | Jul 15 06:20:49 PM PDT 24 |
Finished | Jul 15 06:21:47 PM PDT 24 |
Peak memory | 260436 kb |
Host | smart-4fe349a3-fc78-44cf-bd49-3bf6768e90ee |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=335030228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.335030228 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3288425280 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 5495106376 ps |
CPU time | 357.79 seconds |
Started | Jul 15 06:20:43 PM PDT 24 |
Finished | Jul 15 06:26:41 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-395798d9-da5b-45b2-a7c6-7379359f6035 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288425280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.3288425280 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.142997592 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 830404421 ps |
CPU time | 129.26 seconds |
Started | Jul 15 06:20:52 PM PDT 24 |
Finished | Jul 15 06:23:02 PM PDT 24 |
Peak memory | 367736 kb |
Host | smart-74f76f73-204b-4c8a-854a-5b150af38136 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142997592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_throughput_w_partial_write.142997592 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3171284044 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 10058738216 ps |
CPU time | 858.83 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:29:54 PM PDT 24 |
Peak memory | 379684 kb |
Host | smart-7d8f08cf-48f4-415b-8a65-d533cc29596f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171284044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.3171284044 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.3871395369 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 12754783 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:15:41 PM PDT 24 |
Finished | Jul 15 06:15:43 PM PDT 24 |
Peak memory | 202508 kb |
Host | smart-f6f68043-be61-4c1d-8085-e61e3d732f08 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871395369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3871395369 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.1833328484 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 27147089743 ps |
CPU time | 1910.05 seconds |
Started | Jul 15 06:15:38 PM PDT 24 |
Finished | Jul 15 06:47:29 PM PDT 24 |
Peak memory | 203320 kb |
Host | smart-57c1184c-6f14-408d-8358-5302b4f48b4c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833328484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 1833328484 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.165779977 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 5834784523 ps |
CPU time | 186.58 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:18:42 PM PDT 24 |
Peak memory | 361060 kb |
Host | smart-a4f82391-7540-42c6-9d48-b4e6a218ba46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165779977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable .165779977 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.3071254813 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 62632442350 ps |
CPU time | 97.89 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:17:13 PM PDT 24 |
Peak memory | 215652 kb |
Host | smart-b0e0bff0-14b4-4ac6-b444-24601aff4c37 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071254813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.3071254813 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.4146897812 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 12005186522 ps |
CPU time | 36.05 seconds |
Started | Jul 15 06:15:39 PM PDT 24 |
Finished | Jul 15 06:16:16 PM PDT 24 |
Peak memory | 292216 kb |
Host | smart-67a071b9-6bf1-4c7f-881d-a2deb68d3335 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146897812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.4146897812 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3545422316 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 111131433370 ps |
CPU time | 205.1 seconds |
Started | Jul 15 06:15:38 PM PDT 24 |
Finished | Jul 15 06:19:04 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-64131c4e-ffa6-414a-a0e3-69a9ae968cc4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545422316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.3545422316 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.395138767 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 7890084161 ps |
CPU time | 130.87 seconds |
Started | Jul 15 06:15:43 PM PDT 24 |
Finished | Jul 15 06:17:56 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-d1309395-1c40-440c-bda3-14fa8c0edb9c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395138767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ mem_walk.395138767 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.4047574808 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 238479775750 ps |
CPU time | 1629.05 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:42:46 PM PDT 24 |
Peak memory | 379688 kb |
Host | smart-3f9efc5a-0c79-4056-a349-004f90dc7ead |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047574808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.4047574808 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.3089488645 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 2061692767 ps |
CPU time | 117.98 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:17:34 PM PDT 24 |
Peak memory | 370300 kb |
Host | smart-e56fb9c2-bd66-47e4-b6ce-aecb0c40a293 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089488645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.3089488645 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2064665037 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 71054219148 ps |
CPU time | 447.5 seconds |
Started | Jul 15 06:15:42 PM PDT 24 |
Finished | Jul 15 06:23:11 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-f8a6f409-396a-42aa-800f-80014af45ba8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064665037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.2064665037 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.3870424050 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 1461850045 ps |
CPU time | 3.55 seconds |
Started | Jul 15 06:15:37 PM PDT 24 |
Finished | Jul 15 06:15:41 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-b7912f59-0b2f-497c-9199-37cd35500d4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870424050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3870424050 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.1937807022 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 5433034098 ps |
CPU time | 612.56 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:25:48 PM PDT 24 |
Peak memory | 369436 kb |
Host | smart-4b77ff40-e89b-47af-9091-cb8663076cf9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937807022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1937807022 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.2796904811 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 3949989167 ps |
CPU time | 14.14 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:15:49 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-f4295d5f-bf92-474f-acf9-2da37dea1f99 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796904811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2796904811 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.3849071658 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 41534986515 ps |
CPU time | 2846.02 seconds |
Started | Jul 15 06:15:44 PM PDT 24 |
Finished | Jul 15 07:03:13 PM PDT 24 |
Peak memory | 380940 kb |
Host | smart-4edee995-2eb1-48c0-aa7d-7c951d118266 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849071658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.3849071658 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1039887164 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 13136612754 ps |
CPU time | 152.32 seconds |
Started | Jul 15 06:15:38 PM PDT 24 |
Finished | Jul 15 06:18:11 PM PDT 24 |
Peak memory | 372556 kb |
Host | smart-c568cdac-6819-4fb2-a2dd-4a004a512d93 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1039887164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1039887164 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2902690345 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 3173703295 ps |
CPU time | 197.17 seconds |
Started | Jul 15 06:15:34 PM PDT 24 |
Finished | Jul 15 06:18:53 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-76b5fff3-bee0-4cd0-a3e4-8c806579b1c4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902690345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.2902690345 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.229176861 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 4607512871 ps |
CPU time | 102.24 seconds |
Started | Jul 15 06:15:35 PM PDT 24 |
Finished | Jul 15 06:17:18 PM PDT 24 |
Peak memory | 371692 kb |
Host | smart-2b9240c2-d2ee-454f-9e24-9bcdec787fc0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229176861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.229176861 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2102751868 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 88773084884 ps |
CPU time | 734.66 seconds |
Started | Jul 15 06:15:44 PM PDT 24 |
Finished | Jul 15 06:28:00 PM PDT 24 |
Peak memory | 371548 kb |
Host | smart-aa56e0a1-3b54-479e-8c43-a25e592a7c5c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102751868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.2102751868 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.1533280141 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 19936110 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:15:49 PM PDT 24 |
Peak memory | 202316 kb |
Host | smart-005fdecf-dde5-47f3-b04a-d9466ecd204e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533280141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1533280141 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.234476646 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 690242002373 ps |
CPU time | 2656.98 seconds |
Started | Jul 15 06:15:44 PM PDT 24 |
Finished | Jul 15 07:00:03 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-4a49d535-846b-4544-abe9-c76d6c7f5073 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234476646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.234476646 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.3613749474 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 6452511824 ps |
CPU time | 389.21 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:22:18 PM PDT 24 |
Peak memory | 378700 kb |
Host | smart-82f91883-f2a9-411f-8c38-b71b15f3a1ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613749474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.3613749474 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.3155592284 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 70552046824 ps |
CPU time | 95.28 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:17:24 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-9141e8f7-4706-4b82-ae27-3dce6ee97a19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155592284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.3155592284 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.2811499401 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 762137383 ps |
CPU time | 37.84 seconds |
Started | Jul 15 06:15:43 PM PDT 24 |
Finished | Jul 15 06:16:23 PM PDT 24 |
Peak memory | 300608 kb |
Host | smart-4e2138a9-77af-4f05-af32-53fd54f5d418 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811499401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.2811499401 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1324920453 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 3976049548 ps |
CPU time | 66.7 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:16:56 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-3aa01e4e-2ec4-469c-9d33-7525ec9a1a02 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324920453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.1324920453 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.3553982138 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 21588778330 ps |
CPU time | 353.02 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:21:42 PM PDT 24 |
Peak memory | 203704 kb |
Host | smart-bb181fc3-8fb9-404d-8510-eccc240a91da |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553982138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.3553982138 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.2950653380 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 32659264630 ps |
CPU time | 1001.05 seconds |
Started | Jul 15 06:15:42 PM PDT 24 |
Finished | Jul 15 06:32:24 PM PDT 24 |
Peak memory | 379776 kb |
Host | smart-fce70ab4-0d8e-4d5c-a850-8a09682a1f40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950653380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.2950653380 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.2536578212 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 725172018 ps |
CPU time | 15.99 seconds |
Started | Jul 15 06:15:43 PM PDT 24 |
Finished | Jul 15 06:16:01 PM PDT 24 |
Peak memory | 246648 kb |
Host | smart-a9e7bce2-d5b6-4b45-9031-a4e54681e09b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536578212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.2536578212 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.304960569 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 41894013914 ps |
CPU time | 185.3 seconds |
Started | Jul 15 06:15:43 PM PDT 24 |
Finished | Jul 15 06:18:50 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-466e2e4c-3108-499f-ace8-17bd3314c592 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304960569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.sram_ctrl_partial_access_b2b.304960569 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.4083138901 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 1412391123 ps |
CPU time | 3.76 seconds |
Started | Jul 15 06:15:42 PM PDT 24 |
Finished | Jul 15 06:15:47 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-a75ef4f6-d809-4ca8-8c45-56e94ccbc06b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083138901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.4083138901 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2860164597 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 9790963687 ps |
CPU time | 35.65 seconds |
Started | Jul 15 06:15:43 PM PDT 24 |
Finished | Jul 15 06:16:19 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-48f3c1f5-e109-4674-a918-c5222f1d4ee0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860164597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2860164597 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.2888596462 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 700117679 ps |
CPU time | 10.02 seconds |
Started | Jul 15 06:15:44 PM PDT 24 |
Finished | Jul 15 06:15:56 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-c57a7f5c-e01f-4cae-a767-cd08c8797c5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888596462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.2888596462 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.1513804712 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 54780080508 ps |
CPU time | 4697.74 seconds |
Started | Jul 15 06:15:41 PM PDT 24 |
Finished | Jul 15 07:33:59 PM PDT 24 |
Peak memory | 380720 kb |
Host | smart-7a5b95dd-2d21-43cb-83c1-81b62eff5e99 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513804712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.1513804712 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2292300952 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 991362834 ps |
CPU time | 28.66 seconds |
Started | Jul 15 06:15:44 PM PDT 24 |
Finished | Jul 15 06:16:15 PM PDT 24 |
Peak memory | 213928 kb |
Host | smart-9d366ada-3586-409e-ac04-8ceed83d0b2c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2292300952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2292300952 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.4281967755 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 17366448687 ps |
CPU time | 271.84 seconds |
Started | Jul 15 06:15:41 PM PDT 24 |
Finished | Jul 15 06:20:13 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-55b6275e-e9e2-4a87-abba-a57ff0e20a85 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281967755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.4281967755 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2084771975 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 1525870707 ps |
CPU time | 75.58 seconds |
Started | Jul 15 06:15:49 PM PDT 24 |
Finished | Jul 15 06:17:07 PM PDT 24 |
Peak memory | 342728 kb |
Host | smart-269b7954-7dee-4dd5-b97e-8f745276ee04 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084771975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.2084771975 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.4100006827 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 6722164689 ps |
CPU time | 409.13 seconds |
Started | Jul 15 06:15:45 PM PDT 24 |
Finished | Jul 15 06:22:37 PM PDT 24 |
Peak memory | 349104 kb |
Host | smart-59befb91-2d59-40ed-ab41-339bece80d25 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100006827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.4100006827 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.1958910814 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 14330844 ps |
CPU time | 0.65 seconds |
Started | Jul 15 06:15:49 PM PDT 24 |
Finished | Jul 15 06:15:53 PM PDT 24 |
Peak memory | 202312 kb |
Host | smart-62e1f097-273b-43d9-9aa7-4ec13e6dc949 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958910814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.1958910814 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.2519800523 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 44292476699 ps |
CPU time | 676.31 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:27:05 PM PDT 24 |
Peak memory | 203496 kb |
Host | smart-830652f4-7710-48ae-84af-8934bc9337ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519800523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 2519800523 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.4090060006 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 56874339581 ps |
CPU time | 1592.36 seconds |
Started | Jul 15 06:15:45 PM PDT 24 |
Finished | Jul 15 06:42:20 PM PDT 24 |
Peak memory | 379808 kb |
Host | smart-44d33a9a-afe5-4643-b31e-cc004d7cc2ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090060006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.4090060006 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.2572735236 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 13530062320 ps |
CPU time | 87.69 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:17:16 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-24012087-7e4e-49cb-9f74-55c6b47d4844 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572735236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.2572735236 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.1657112922 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 793164983 ps |
CPU time | 102.48 seconds |
Started | Jul 15 06:15:44 PM PDT 24 |
Finished | Jul 15 06:17:29 PM PDT 24 |
Peak memory | 360120 kb |
Host | smart-4900350b-5e8c-4c82-bee7-63040e75f1b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657112922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.1657112922 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.900669524 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 1446806014 ps |
CPU time | 73.44 seconds |
Started | Jul 15 06:15:39 PM PDT 24 |
Finished | Jul 15 06:16:53 PM PDT 24 |
Peak memory | 219024 kb |
Host | smart-56f3da61-71d6-4916-8c37-d424d7b16736 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900669524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. sram_ctrl_mem_partial_access.900669524 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.1537842832 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 82704459269 ps |
CPU time | 371.85 seconds |
Started | Jul 15 06:15:43 PM PDT 24 |
Finished | Jul 15 06:21:57 PM PDT 24 |
Peak memory | 211736 kb |
Host | smart-f96a26d8-8e33-45c5-8674-2e5f7321ccd2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537842832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.1537842832 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.1914574378 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 2705150624 ps |
CPU time | 300.19 seconds |
Started | Jul 15 06:15:49 PM PDT 24 |
Finished | Jul 15 06:20:52 PM PDT 24 |
Peak memory | 370408 kb |
Host | smart-93023f2d-10f5-40d0-b047-3b191eeb1d67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914574378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.1914574378 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.1410240331 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 1216370017 ps |
CPU time | 20.27 seconds |
Started | Jul 15 06:15:42 PM PDT 24 |
Finished | Jul 15 06:16:03 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-cdb7148e-e59c-4d51-a96a-a0d80215fffe |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410240331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.1410240331 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.322381991 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 77584737264 ps |
CPU time | 237.48 seconds |
Started | Jul 15 06:15:43 PM PDT 24 |
Finished | Jul 15 06:19:42 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-06268f50-25c2-4b16-8924-ed0b6f1fa6ac |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322381991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.sram_ctrl_partial_access_b2b.322381991 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.2404593812 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 696382467 ps |
CPU time | 3.53 seconds |
Started | Jul 15 06:15:43 PM PDT 24 |
Finished | Jul 15 06:15:49 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-24e8d30c-e202-4418-91a8-ab96dbf43f4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404593812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2404593812 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.3692819243 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 14388624233 ps |
CPU time | 308.68 seconds |
Started | Jul 15 06:15:43 PM PDT 24 |
Finished | Jul 15 06:20:53 PM PDT 24 |
Peak memory | 332720 kb |
Host | smart-e74a2478-917f-4782-9c77-01ba090fadea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692819243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3692819243 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.3859568491 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 887902858 ps |
CPU time | 21.16 seconds |
Started | Jul 15 06:15:49 PM PDT 24 |
Finished | Jul 15 06:16:13 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-2eb21b55-d7de-4615-95b1-508caa73bb6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859568491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3859568491 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.1609216697 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 229461403399 ps |
CPU time | 5368.46 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 07:45:20 PM PDT 24 |
Peak memory | 383764 kb |
Host | smart-7ffce45d-1995-40d4-b3e7-2cefc731616a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609216697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.1609216697 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.552542260 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 2001663550 ps |
CPU time | 29.82 seconds |
Started | Jul 15 06:15:51 PM PDT 24 |
Finished | Jul 15 06:16:22 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-71480cc7-17ef-416f-8928-ea15e91e759b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=552542260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.552542260 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.4184383294 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 9157000769 ps |
CPU time | 264.14 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:20:13 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-f88d50f6-bb20-45e8-be49-613049be9b09 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184383294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.4184383294 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2041172882 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 5523258003 ps |
CPU time | 27.19 seconds |
Started | Jul 15 06:15:44 PM PDT 24 |
Finished | Jul 15 06:16:13 PM PDT 24 |
Peak memory | 280524 kb |
Host | smart-c2e5e034-d65b-4c75-ad2a-ca95fbde17c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041172882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2041172882 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.265544137 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 12498464913 ps |
CPU time | 101.76 seconds |
Started | Jul 15 06:15:52 PM PDT 24 |
Finished | Jul 15 06:17:35 PM PDT 24 |
Peak memory | 341816 kb |
Host | smart-7de19420-6753-4e72-9b3f-0a5b3006f241 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265544137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_access_during_key_req.265544137 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.113322947 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 46250964 ps |
CPU time | 0.66 seconds |
Started | Jul 15 06:15:51 PM PDT 24 |
Finished | Jul 15 06:15:54 PM PDT 24 |
Peak memory | 202528 kb |
Host | smart-a9e513cf-d9e3-4fa2-a50f-28a9b5990fd6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113322947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.113322947 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.4076083151 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 26832955522 ps |
CPU time | 1899.28 seconds |
Started | Jul 15 06:15:47 PM PDT 24 |
Finished | Jul 15 06:47:30 PM PDT 24 |
Peak memory | 203628 kb |
Host | smart-892cdba5-2f3f-4f91-a1ac-59840197e5b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076083151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 4076083151 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.3746706823 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 34866317583 ps |
CPU time | 719.46 seconds |
Started | Jul 15 06:15:51 PM PDT 24 |
Finished | Jul 15 06:27:52 PM PDT 24 |
Peak memory | 378816 kb |
Host | smart-3a8bf741-efc2-4cef-b7b2-7ed7091bf85a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746706823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.3746706823 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.2775289018 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 11009298634 ps |
CPU time | 65.03 seconds |
Started | Jul 15 06:15:49 PM PDT 24 |
Finished | Jul 15 06:16:57 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-37da6575-773c-416c-bab7-d8db4949be02 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775289018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.2775289018 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.3856520494 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 1424065568 ps |
CPU time | 15.02 seconds |
Started | Jul 15 06:15:54 PM PDT 24 |
Finished | Jul 15 06:16:10 PM PDT 24 |
Peak memory | 241988 kb |
Host | smart-357b75be-5613-490b-96e5-9afb363a41bd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856520494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.3856520494 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2461771441 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 12081685880 ps |
CPU time | 82.64 seconds |
Started | Jul 15 06:15:49 PM PDT 24 |
Finished | Jul 15 06:17:15 PM PDT 24 |
Peak memory | 210948 kb |
Host | smart-13c63cd4-7543-4ec5-ae09-ceb37843e05e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461771441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.2461771441 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.289845807 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 52561752891 ps |
CPU time | 162.04 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 06:18:33 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-c9710d90-3394-4e25-8bc4-6858db1c1068 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289845807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ mem_walk.289845807 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.3566715077 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 7687096465 ps |
CPU time | 1135.69 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:34:45 PM PDT 24 |
Peak memory | 380672 kb |
Host | smart-edad171b-5d0c-44da-aa18-927e10411a5a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566715077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.3566715077 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.911022483 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 3495186537 ps |
CPU time | 15.54 seconds |
Started | Jul 15 06:15:49 PM PDT 24 |
Finished | Jul 15 06:16:07 PM PDT 24 |
Peak memory | 240328 kb |
Host | smart-12cb4e9a-2807-461c-af63-cc9608db8272 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911022483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr am_ctrl_partial_access.911022483 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2116617002 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 21240854646 ps |
CPU time | 506.93 seconds |
Started | Jul 15 06:15:46 PM PDT 24 |
Finished | Jul 15 06:24:16 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-63ddb723-46ed-40f9-9183-fb29cbcec5ec |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116617002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.2116617002 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.1631881752 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 354412086 ps |
CPU time | 3.32 seconds |
Started | Jul 15 06:15:44 PM PDT 24 |
Finished | Jul 15 06:15:49 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-799365ff-3bda-4176-94e6-52af780abf19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631881752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1631881752 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.2666599297 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 18445929616 ps |
CPU time | 1302.58 seconds |
Started | Jul 15 06:15:47 PM PDT 24 |
Finished | Jul 15 06:37:33 PM PDT 24 |
Peak memory | 375784 kb |
Host | smart-dfd37690-e6b6-432a-9472-6d6af71300f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666599297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2666599297 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.1737652396 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 1120550106 ps |
CPU time | 57.67 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 06:16:49 PM PDT 24 |
Peak memory | 305944 kb |
Host | smart-13801753-c379-423e-a47f-9e8378d73a22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737652396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1737652396 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1887531629 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 754775029 ps |
CPU time | 9.96 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 06:16:01 PM PDT 24 |
Peak memory | 212760 kb |
Host | smart-b0bb1507-6405-40c9-a3d8-ad2148525ef5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1887531629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1887531629 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.4292892657 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 4063240997 ps |
CPU time | 251.66 seconds |
Started | Jul 15 06:15:49 PM PDT 24 |
Finished | Jul 15 06:20:04 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-5f779657-6398-49ad-a654-b4fd70e6ad16 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292892657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.4292892657 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3375833343 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 778059368 ps |
CPU time | 92.26 seconds |
Started | Jul 15 06:15:53 PM PDT 24 |
Finished | Jul 15 06:17:26 PM PDT 24 |
Peak memory | 333440 kb |
Host | smart-7e719cd1-7457-4979-81b8-f4e216d5f1d6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375833343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.3375833343 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2759617262 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 24529734903 ps |
CPU time | 1170.75 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 06:35:21 PM PDT 24 |
Peak memory | 372512 kb |
Host | smart-2956eb4a-44e5-4cfe-b620-e2ab89d52068 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759617262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.2759617262 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.4282617854 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 36481364 ps |
CPU time | 0.68 seconds |
Started | Jul 15 06:15:55 PM PDT 24 |
Finished | Jul 15 06:15:57 PM PDT 24 |
Peak memory | 202316 kb |
Host | smart-2fdef644-80f5-40bf-a35a-99b25f94cadd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282617854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.4282617854 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.3015404684 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 168439485036 ps |
CPU time | 2537.38 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 06:58:08 PM PDT 24 |
Peak memory | 203424 kb |
Host | smart-4602be36-1618-4526-97f2-547e99cfb545 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015404684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 3015404684 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.191456077 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 34798915586 ps |
CPU time | 822.34 seconds |
Started | Jul 15 06:15:51 PM PDT 24 |
Finished | Jul 15 06:29:35 PM PDT 24 |
Peak memory | 372536 kb |
Host | smart-9ff1d2dd-9d07-48f8-88db-71d4a9ca5204 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191456077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable .191456077 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.230262283 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 12283860922 ps |
CPU time | 75.84 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 06:17:07 PM PDT 24 |
Peak memory | 215412 kb |
Host | smart-039ed7e7-05da-4f9e-827c-c46f82c8a92a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230262283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca lation.230262283 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.3210170261 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 801709970 ps |
CPU time | 145.48 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 06:18:16 PM PDT 24 |
Peak memory | 370420 kb |
Host | smart-16ff280c-685f-4433-bd08-110d86998781 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210170261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.3210170261 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1176599940 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 20081907033 ps |
CPU time | 180.11 seconds |
Started | Jul 15 06:15:53 PM PDT 24 |
Finished | Jul 15 06:18:54 PM PDT 24 |
Peak memory | 219112 kb |
Host | smart-b0476d51-f77d-491c-be1b-18e257b70ad6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176599940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.1176599940 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.561896772 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 16423110143 ps |
CPU time | 254.06 seconds |
Started | Jul 15 06:15:50 PM PDT 24 |
Finished | Jul 15 06:20:07 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-a299869f-9d3f-4af3-b43c-174ab20b6a87 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561896772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ mem_walk.561896772 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.3560176674 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 25542958694 ps |
CPU time | 943.97 seconds |
Started | Jul 15 06:15:50 PM PDT 24 |
Finished | Jul 15 06:31:36 PM PDT 24 |
Peak memory | 376532 kb |
Host | smart-69a29cc6-acd4-413f-a7d0-6ae09d7de6bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560176674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.3560176674 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.1942242035 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 648850830 ps |
CPU time | 21.11 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 06:16:12 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-66df23b4-0774-40ee-ab5d-c2ab5dbd6d18 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942242035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.1942242035 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1153935813 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 69630988000 ps |
CPU time | 315.23 seconds |
Started | Jul 15 06:15:47 PM PDT 24 |
Finished | Jul 15 06:21:05 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-86de3b9c-dc38-4b7d-a4e1-fc6ef96cec04 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153935813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.1153935813 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.1008341551 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 675829620 ps |
CPU time | 3.27 seconds |
Started | Jul 15 06:15:48 PM PDT 24 |
Finished | Jul 15 06:15:54 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-76c182c6-d9a6-4819-b3df-76db9a84b59c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008341551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.1008341551 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.2904312850 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 50703419885 ps |
CPU time | 814.89 seconds |
Started | Jul 15 06:15:47 PM PDT 24 |
Finished | Jul 15 06:29:25 PM PDT 24 |
Peak memory | 376912 kb |
Host | smart-070e08eb-15ad-453e-973b-bda1b765b2ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904312850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2904312850 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.3296994776 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 1067780915 ps |
CPU time | 107.58 seconds |
Started | Jul 15 06:15:51 PM PDT 24 |
Finished | Jul 15 06:17:41 PM PDT 24 |
Peak memory | 369224 kb |
Host | smart-ddccc181-f095-4cc4-bd31-f5dac593408c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296994776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3296994776 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.2616906251 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 40790608722 ps |
CPU time | 3258.41 seconds |
Started | Jul 15 06:15:57 PM PDT 24 |
Finished | Jul 15 07:10:17 PM PDT 24 |
Peak memory | 382764 kb |
Host | smart-be465c68-3015-416b-87ec-a54c7c5eaa7e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616906251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.2616906251 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4285996931 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 4043589969 ps |
CPU time | 48.83 seconds |
Started | Jul 15 06:15:58 PM PDT 24 |
Finished | Jul 15 06:16:48 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-36c45995-361a-4383-8dc2-53492808d7a6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4285996931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.4285996931 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.673622824 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 14348859144 ps |
CPU time | 223.66 seconds |
Started | Jul 15 06:15:51 PM PDT 24 |
Finished | Jul 15 06:19:36 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-8944ce78-a488-45ec-ad48-b6751fd10ca5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673622824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9. sram_ctrl_stress_pipeline.673622824 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4072657723 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 3463499878 ps |
CPU time | 11.54 seconds |
Started | Jul 15 06:15:50 PM PDT 24 |
Finished | Jul 15 06:16:04 PM PDT 24 |
Peak memory | 235472 kb |
Host | smart-91243f00-576e-48a5-9c11-bf89effb793f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072657723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.4072657723 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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