SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[sram_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[sram_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 173449760 | 0 | T1 | 37406 | T3 | 281947 | T4 | 3819 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 173449584 | 1 | T1 | 37406 | T3 | 281947 | T4 | 3819 | ||||
values[1] | 14 | 1 | T63 | 1 | T64 | 1 | T115 | 1 | ||||
values[2] | 2 | 1 | T64 | 1 | T116 | 1 | - | - | ||||
values[3] | 92 | 1 | T63 | 7 | T64 | 2 | T65 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 173449589 | 1 | T1 | 37406 | T3 | 281947 | T4 | 3819 | ||||
values[1] | 21 | 1 | T63 | 3 | T64 | 4 | T115 | 1 | ||||
values[2] | 2 | 1 | T117 | 1 | T118 | 1 | - | - | ||||
values[3] | 78 | 1 | T63 | 7 | T64 | 2 | T65 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 173449500 | 1 | T1 | 37406 | T3 | 281947 | T4 | 3819 | ||||
auto[TlIntgErrCmd] | 89 | 1 | T63 | 6 | T64 | 4 | T65 | 5 | ||||
auto[TlIntgErrData] | 84 | 1 | T63 | 9 | T64 | 6 | T65 | 3 | ||||
auto[TlIntgErrBoth] | 87 | 1 | T63 | 5 | T65 | 2 | T115 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 443952 | 0 | T1 | 14 | T2 | 15 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 443791 | 1 | T1 | 14 | T2 | 15 | T3 | 3 | ||||
values[1] | 18 | 1 | T64 | 2 | T119 | 3 | T120 | 1 | ||||
values[2] | 3 | 1 | T63 | 1 | T117 | 2 | - | - | ||||
values[3] | 81 | 1 | T63 | 5 | T64 | 1 | T65 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 443769 | 1 | T1 | 14 | T2 | 15 | T3 | 3 | ||||
values[1] | 11 | 1 | T63 | 1 | T64 | 1 | T119 | 2 | ||||
values[2] | 4 | 1 | T64 | 1 | T119 | 1 | T121 | 1 | ||||
values[3] | 103 | 1 | T63 | 11 | T64 | 3 | T65 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 443692 | 1 | T1 | 14 | T2 | 15 | T3 | 3 | ||||
auto[TlIntgErrCmd] | 77 | 1 | T63 | 3 | T64 | 3 | T65 | 5 | ||||
auto[TlIntgErrData] | 99 | 1 | T63 | 9 | T64 | 7 | T65 | 3 | ||||
auto[TlIntgErrBoth] | 84 | 1 | T63 | 8 | T65 | 2 | T115 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |