Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15746880	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

160542530

1

T1

40164

T3

51446

T4

3465

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86826035	1			T1	22043		T3	141081		T4	1882
values[0x0]	43168403	1			T1	10631		T3	47485		T4	952
values[0x1]	46294972	1			T1	11390		T3	93381		T4	985

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8011641	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

168277769

1

T1

42118

T3

166842

T4

3653

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	619788	1			T1	178		T3	1020		T4	14
valid_sources[0x01]	583546	1			T1	160		T3	1072		T4	7
valid_sources[0x02]	587492	1			T1	175		T3	1103		T4	26
valid_sources[0x03]	632623	1			T1	159		T3	911		T4	8
valid_sources[0x04]	582974	1			T1	155		T3	866		T4	15
valid_sources[0x05]	591899	1			T1	160		T3	994		T4	5
valid_sources[0x06]	593969	1			T1	174		T3	1152		T4	10
valid_sources[0x07]	812254	1			T1	165		T3	1002		T4	17
valid_sources[0x08]	608558	1			T1	167		T3	1123		T4	1
valid_sources[0x09]	554213	1			T1	171		T3	975		T4	8
valid_sources[0x0a]	571099	1			T1	169		T3	1246		T4	28
valid_sources[0x0b]	584609	1			T1	171		T3	991		T4	8
valid_sources[0x0c]	1804262	1			T1	174		T3	994		T4	8
valid_sources[0x0d]	669477	1			T1	173		T3	863		T4	23
valid_sources[0x0e]	570557	1			T1	170		T3	998		T4	10
valid_sources[0x0f]	549545	1			T1	165		T3	1480		T4	10
valid_sources[0x10]	600033	1			T1	191		T3	929		T4	9
valid_sources[0x11]	653698	1			T1	191		T3	901		T4	11
valid_sources[0x12]	565565	1			T1	172		T3	1435		T4	9
valid_sources[0x13]	552114	1			T1	208		T3	1010		T4	18
valid_sources[0x14]	613274	1			T1	197		T3	1165		T4	12
valid_sources[0x15]	600736	1			T1	156		T3	1347		T4	22
valid_sources[0x16]	595700	1			T1	165		T3	1157		T4	11
valid_sources[0x17]	624280	1			T1	154		T3	1116		T4	20
valid_sources[0x18]	568493	1			T1	151		T3	1256		T4	14
valid_sources[0x19]	576339	1			T1	182		T3	1162		T4	3
valid_sources[0x1a]	568788	1			T1	189		T3	1282		T4	12
valid_sources[0x1b]	688935	1			T1	169		T3	1052		T4	10
valid_sources[0x1c]	572038	1			T1	161		T3	923		T4	17
valid_sources[0x1d]	569592	1			T1	165		T3	1057		T4	19
valid_sources[0x1e]	631294	1			T1	186		T3	1123		T4	13
valid_sources[0x1f]	577069	1			T1	176		T3	1026		T4	15
valid_sources[0x20]	546761	1			T1	181		T3	1010		T4	31
valid_sources[0x21]	602038	1			T1	180		T3	1140		T4	27
valid_sources[0x22]	1190749	1			T1	160		T3	1156		T4	9
valid_sources[0x23]	637331	1			T1	165		T3	1159		T4	5
valid_sources[0x24]	545268	1			T1	192		T3	1081		T4	26
valid_sources[0x25]	562269	1			T1	183		T3	864		T4	23
valid_sources[0x26]	556383	1			T1	130		T3	1175		T4	16
valid_sources[0x27]	566836	1			T1	155		T3	1152		T4	8
valid_sources[0x28]	688254	1			T1	221		T3	1138		T4	10
valid_sources[0x29]	2137249	1			T1	169		T3	1165		T4	6
valid_sources[0x2a]	628222	1			T1	187		T3	1229		T4	7
valid_sources[0x2b]	1348777	1			T1	194		T3	1093		T4	16
valid_sources[0x2c]	662880	1			T1	166		T3	1096		T4	8
valid_sources[0x2d]	773128	1			T1	159		T3	1243		T4	14
valid_sources[0x2e]	696894	1			T1	173		T3	854		T4	13
valid_sources[0x2f]	544538	1			T1	193		T3	805		T4	16
valid_sources[0x30]	556787	1			T1	145		T3	927		T4	33
valid_sources[0x31]	615589	1			T1	173		T3	1081		T4	36
valid_sources[0x32]	563746	1			T1	178		T3	1131		T4	27
valid_sources[0x33]	748797	1			T1	166		T3	1161		T4	25
valid_sources[0x34]	698639	1			T1	149		T3	1109		T4	7
valid_sources[0x35]	677214	1			T1	170		T3	1041		T4	14
valid_sources[0x36]	1121520	1			T1	144		T3	1153		T4	6
valid_sources[0x37]	593121	1			T1	184		T3	934		T4	14
valid_sources[0x38]	564399	1			T1	181		T3	1046		T4	13
valid_sources[0x39]	587265	1			T1	193		T3	715		T4	20
valid_sources[0x3a]	564843	1			T1	178		T3	1161		T4	37
valid_sources[0x3b]	585585	1			T1	195		T3	907		T4	10
valid_sources[0x3c]	2007736	1			T1	191		T3	952		T4	19
valid_sources[0x3d]	562371	1			T1	179		T3	1048		T4	20
valid_sources[0x3e]	625278	1			T1	210		T3	1274		T4	9
valid_sources[0x3f]	571902	1			T1	151		T3	887		T4	20
valid_sources[0x40]	557947	1			T1	178		T3	1059		T4	7
valid_sources[0x41]	1191814	1			T1	175		T3	1140		T4	22
valid_sources[0x42]	572722	1			T1	205		T3	1224		T4	41
valid_sources[0x43]	585047	1			T1	171		T3	885		T4	15
valid_sources[0x44]	561560	1			T1	155		T3	1030		T4	6
valid_sources[0x45]	1362289	1			T1	170		T3	1203		T4	16
valid_sources[0x46]	649779	1			T1	187		T3	1066		T4	11
valid_sources[0x47]	549936	1			T1	167		T3	1178		T4	9
valid_sources[0x48]	614687	1			T1	138		T3	1296		T4	28
valid_sources[0x49]	597300	1			T1	220		T3	1198		T4	6
valid_sources[0x4a]	576532	1			T1	151		T3	996		T4	10
valid_sources[0x4b]	568711	1			T1	171		T3	1006		T4	6
valid_sources[0x4c]	2813855	1			T1	189		T3	1071		T4	23
valid_sources[0x4d]	594159	1			T1	160		T3	877		T4	14
valid_sources[0x4e]	608286	1			T1	162		T3	935		T4	22
valid_sources[0x4f]	2058776	1			T1	146		T3	1363		T4	7
valid_sources[0x50]	629169	1			T1	176		T3	1141		T4	10
valid_sources[0x51]	563092	1			T1	157		T3	1125		T4	10
valid_sources[0x52]	589110	1			T1	166		T3	1058		T4	17
valid_sources[0x53]	566644	1			T1	181		T3	1051		T4	24
valid_sources[0x54]	571198	1			T1	169		T3	1103		T4	8
valid_sources[0x55]	578293	1			T1	147		T3	1223		T4	11
valid_sources[0x56]	603156	1			T1	173		T3	1022		T4	4
valid_sources[0x57]	700050	1			T1	146		T3	1079		T4	4
valid_sources[0x58]	632371	1			T1	196		T3	932		T4	13
valid_sources[0x59]	589907	1			T1	176		T3	1056		T4	23
valid_sources[0x5a]	564383	1			T1	172		T3	1337		T4	8
valid_sources[0x5b]	553337	1			T1	160		T3	990		T4	4
valid_sources[0x5c]	550824	1			T1	176		T3	1387		T4	5
valid_sources[0x5d]	583612	1			T1	198		T3	1076		T4	49
valid_sources[0x5e]	607888	1			T1	155		T3	1148		T4	3
valid_sources[0x5f]	648652	1			T1	180		T3	1004		T4	4
valid_sources[0x60]	575860	1			T1	197		T3	1198		T4	13
valid_sources[0x61]	628226	1			T1	179		T3	928		T4	23
valid_sources[0x62]	604288	1			T1	168		T3	982		T4	9
valid_sources[0x63]	579135	1			T1	187		T3	1401		T4	32
valid_sources[0x64]	547717	1			T1	178		T3	1183		T4	12
valid_sources[0x65]	1471622	1			T1	193		T3	1084		T4	8
valid_sources[0x66]	546143	1			T1	173		T3	921		T4	27
valid_sources[0x67]	579600	1			T1	157		T3	1244		T4	15
valid_sources[0x68]	638423	1			T1	162		T3	1055		T4	19
valid_sources[0x69]	587224	1			T1	189		T3	1034		T4	14
valid_sources[0x6a]	559744	1			T1	146		T3	1065		T4	15
valid_sources[0x6b]	558167	1			T1	202		T3	1206		T4	7
valid_sources[0x6c]	958716	1			T1	157		T3	1178		T4	6
valid_sources[0x6d]	555926	1			T1	155		T3	849		T4	4
valid_sources[0x6e]	555120	1			T1	164		T3	1022		T4	15
valid_sources[0x6f]	572083	1			T1	165		T3	996		T4	3
valid_sources[0x70]	610890	1			T1	173		T3	1157		T4	18
valid_sources[0x71]	555648	1			T1	154		T3	1066		T4	24
valid_sources[0x72]	625251	1			T1	180		T3	1031		T4	20
valid_sources[0x73]	592214	1			T1	157		T3	1301		T4	26
valid_sources[0x74]	567147	1			T1	162		T3	1178		T4	22
valid_sources[0x75]	586206	1			T1	175		T3	1230		T4	5
valid_sources[0x76]	669304	1			T1	137		T3	1161		T4	18
valid_sources[0x77]	550924	1			T1	188		T3	1428		T4	8
valid_sources[0x78]	1759421	1			T1	167		T3	1047		T4	23
valid_sources[0x79]	575367	1			T1	181		T3	1138		T4	19
valid_sources[0x7a]	805665	1			T1	164		T3	1132		T4	11
valid_sources[0x7b]	590947	1			T1	173		T3	1219		T4	23
valid_sources[0x7c]	611457	1			T1	163		T3	925		T4	14
valid_sources[0x7d]	653787	1			T1	138		T3	1475		T4	25
valid_sources[0x7e]	599576	1			T1	156		T3	1177		T4	24
valid_sources[0x7f]	1184300	1			T1	181		T3	1215		T4	14
valid_sources[0x80]	1929024	1			T1	177		T3	1134		T4	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78906054

1

T1

20125

T3

25766

T4

1707

values[0x0]

all_enables

biggest_size

40821101

1

T1

10025

T3

12858

T4

899

values[0x1]

all_enables

biggest_size

40815375

1

T1

10014

T3

12822

T4

859

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43720	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156652

1

T1

5

T2

1

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54727	1			T1	3		T18	15		T19	14
values[0x0]	70560	1			T1	6		T2	7		T3	1
values[0x1]	75085	1			T1	5		T2	8		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166586

1

T1

7

T2

1

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	691	1			T28	1		T24	25		T25	5
valid_sources[0x01]	753	1			T42	3		T25	6		T26	16
valid_sources[0x02]	1149	1			T42	2		T24	74		T25	9
valid_sources[0x03]	1331	1			T9	2		T24	49		T25	3
valid_sources[0x04]	787	1			T24	16		T25	5		T26	29
valid_sources[0x05]	504	1			T42	1		T18	4		T25	10
valid_sources[0x06]	959	1			T42	1		T24	2		T25	9
valid_sources[0x07]	706	1			T24	1		T25	6		T26	19
valid_sources[0x08]	653	1			T24	3		T25	8		T26	19
valid_sources[0x09]	648	1			T9	1		T25	4		T26	22
valid_sources[0x0a]	974	1			T24	2		T25	6		T26	17
valid_sources[0x0b]	757	1			T24	1		T25	7		T26	22
valid_sources[0x0c]	759	1			T25	7		T26	14		T55	35
valid_sources[0x0d]	742	1			T24	7		T25	7		T26	16
valid_sources[0x0e]	841	1			T9	1		T25	6		T26	16
valid_sources[0x0f]	751	1			T42	1		T25	1		T26	14
valid_sources[0x10]	991	1			T24	1		T14	10		T25	7
valid_sources[0x11]	545	1			T28	1		T25	3		T26	5
valid_sources[0x12]	1162	1			T24	4		T25	7		T26	23
valid_sources[0x13]	602	1			T24	1		T25	4		T26	16
valid_sources[0x14]	830	1			T18	1		T19	6		T25	11
valid_sources[0x15]	815	1			T18	4		T24	181		T25	12
valid_sources[0x16]	592	1			T25	7		T26	23		T55	31
valid_sources[0x17]	933	1			T25	5		T26	11		T55	26
valid_sources[0x18]	984	1			T24	339		T25	9		T26	16
valid_sources[0x19]	688	1			T24	69		T25	5		T26	17
valid_sources[0x1a]	706	1			T42	1		T24	1		T25	9
valid_sources[0x1b]	532	1			T42	3		T19	1		T24	15
valid_sources[0x1c]	665	1			T19	2		T24	2		T25	3
valid_sources[0x1d]	587	1			T24	5		T25	9		T26	21
valid_sources[0x1e]	713	1			T42	1		T19	2		T24	72
valid_sources[0x1f]	1091	1			T24	388		T25	6		T26	10
valid_sources[0x20]	861	1			T24	2		T25	4		T26	14
valid_sources[0x21]	584	1			T24	1		T25	5		T26	18
valid_sources[0x22]	968	1			T2	2		T46	3		T19	4
valid_sources[0x23]	1070	1			T24	42		T25	4		T26	15
valid_sources[0x24]	739	1			T25	6		T26	15		T55	28
valid_sources[0x25]	1185	1			T24	282		T25	6		T26	20
valid_sources[0x26]	767	1			T2	1		T42	4		T19	1
valid_sources[0x27]	686	1			T25	5		T26	13		T55	26
valid_sources[0x28]	1046	1			T42	1		T18	1		T24	1
valid_sources[0x29]	769	1			T25	7		T26	12		T55	20
valid_sources[0x2a]	870	1			T24	7		T25	3		T26	20
valid_sources[0x2b]	833	1			T9	1		T25	7		T26	18
valid_sources[0x2c]	1070	1			T19	1		T24	2		T25	6
valid_sources[0x2d]	619	1			T24	8		T25	4		T26	16
valid_sources[0x2e]	727	1			T24	3		T25	6		T26	10
valid_sources[0x2f]	1063	1			T9	1		T18	1		T25	5
valid_sources[0x30]	698	1			T42	2		T25	9		T26	14
valid_sources[0x31]	906	1			T24	186		T25	4		T26	21
valid_sources[0x32]	622	1			T42	3		T24	1		T25	6
valid_sources[0x33]	753	1			T25	10		T26	19		T55	33
valid_sources[0x34]	612	1			T2	1		T24	58		T25	6
valid_sources[0x35]	767	1			T13	3		T66	2		T25	7
valid_sources[0x36]	770	1			T24	115		T25	9		T26	11
valid_sources[0x37]	892	1			T42	2		T25	6		T26	15
valid_sources[0x38]	543	1			T29	3		T24	2		T76	1
valid_sources[0x39]	954	1			T18	2		T24	67		T25	3
valid_sources[0x3a]	1112	1			T42	1		T18	1		T24	136
valid_sources[0x3b]	661	1			T24	1		T25	4		T26	7
valid_sources[0x3c]	866	1			T9	1		T42	1		T24	5
valid_sources[0x3d]	839	1			T42	1		T25	9		T26	22
valid_sources[0x3e]	723	1			T25	5		T26	17		T55	29
valid_sources[0x3f]	864	1			T19	2		T24	186		T25	5
valid_sources[0x40]	585	1			T1	1		T42	1		T24	9
valid_sources[0x41]	568	1			T25	5		T26	17		T55	21
valid_sources[0x42]	701	1			T18	6		T24	1		T25	5
valid_sources[0x43]	706	1			T24	3		T25	11		T26	19
valid_sources[0x44]	606	1			T1	1		T24	20		T43	56
valid_sources[0x45]	1053	1			T24	1		T25	4		T26	20
valid_sources[0x46]	685	1			T19	1		T25	8		T26	10
valid_sources[0x47]	879	1			T24	8		T25	4		T26	12
valid_sources[0x48]	590	1			T19	2		T25	7		T26	10
valid_sources[0x49]	761	1			T42	1		T24	23		T25	10
valid_sources[0x4a]	626	1			T24	1		T25	5		T26	6
valid_sources[0x4b]	695	1			T24	3		T25	4		T26	20
valid_sources[0x4c]	490	1			T19	1		T24	7		T78	1
valid_sources[0x4d]	895	1			T18	1		T25	5		T26	19
valid_sources[0x4e]	840	1			T42	1		T24	21		T25	6
valid_sources[0x4f]	1290	1			T9	1		T42	2		T18	1
valid_sources[0x50]	674	1			T25	4		T26	15		T55	19
valid_sources[0x51]	633	1			T42	2		T24	2		T25	8
valid_sources[0x52]	627	1			T24	3		T25	8		T26	21
valid_sources[0x53]	1268	1			T24	57		T25	5		T26	20
valid_sources[0x54]	1112	1			T9	1		T19	1		T25	6
valid_sources[0x55]	585	1			T24	5		T25	1		T26	15
valid_sources[0x56]	514	1			T77	5		T25	9		T26	20
valid_sources[0x57]	970	1			T9	1		T20	21		T25	6
valid_sources[0x58]	847	1			T19	3		T25	1		T26	19
valid_sources[0x59]	577	1			T42	1		T24	7		T25	5
valid_sources[0x5a]	619	1			T42	2		T25	4		T26	21
valid_sources[0x5b]	699	1			T25	9		T26	17		T55	38
valid_sources[0x5c]	947	1			T8	1		T59	2		T24	1
valid_sources[0x5d]	684	1			T24	2		T25	9		T26	13
valid_sources[0x5e]	747	1			T42	2		T25	4		T26	13
valid_sources[0x5f]	848	1			T42	3		T25	4		T26	20
valid_sources[0x60]	552	1			T24	1		T25	10		T26	8
valid_sources[0x61]	898	1			T42	2		T21	3		T25	8
valid_sources[0x62]	724	1			T1	1		T114	2		T25	6
valid_sources[0x63]	868	1			T9	1		T42	1		T18	2
valid_sources[0x64]	910	1			T24	92		T25	2		T26	11
valid_sources[0x65]	592	1			T25	6		T26	10		T55	28
valid_sources[0x66]	577	1			T24	1		T25	9		T26	16
valid_sources[0x67]	701	1			T3	1		T42	1		T18	4
valid_sources[0x68]	956	1			T24	2		T25	4		T26	17
valid_sources[0x69]	467	1			T18	1		T19	1		T24	2
valid_sources[0x6a]	1127	1			T3	1		T24	94		T25	6
valid_sources[0x6b]	866	1			T24	141		T25	5		T26	16
valid_sources[0x6c]	800	1			T24	2		T25	10		T135	2
valid_sources[0x6d]	711	1			T19	2		T24	1		T25	5
valid_sources[0x6e]	742	1			T24	6		T25	3		T26	18
valid_sources[0x6f]	581	1			T19	2		T25	8		T26	14
valid_sources[0x70]	876	1			T42	1		T18	7		T24	1
valid_sources[0x71]	614	1			T25	9		T26	11		T55	30
valid_sources[0x72]	660	1			T9	1		T19	1		T24	3
valid_sources[0x73]	606	1			T1	1		T2	1		T24	1
valid_sources[0x74]	669	1			T42	1		T19	1		T24	1
valid_sources[0x75]	681	1			T42	4		T25	5		T26	12
valid_sources[0x76]	548	1			T24	1		T25	7		T26	13
valid_sources[0x77]	552	1			T25	9		T26	18		T55	34
valid_sources[0x78]	842	1			T42	2		T24	3		T25	5
valid_sources[0x79]	947	1			T18	1		T24	1		T25	9
valid_sources[0x7a]	1014	1			T24	2		T25	7		T26	23
valid_sources[0x7b]	869	1			T24	6		T25	8		T26	22
valid_sources[0x7c]	1015	1			T42	1		T18	2		T24	6
valid_sources[0x7d]	641	1			T25	8		T26	10		T55	29
valid_sources[0x7e]	582	1			T18	1		T19	1		T25	4
valid_sources[0x7f]	664	1			T2	1		T24	59		T25	9
valid_sources[0x80]	722	1			T19	2		T24	1		T25	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42073

1

T1

2

T18

8

T19

6

values[0x0]

all_enables

biggest_size

58976

1

T1

1

T3

1

T9

2

values[0x1]

all_enables

biggest_size

55603

1

T1

2

T2

1

T3

1