Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15687565

1

T1

3291

T3

230501

T4

354

full_word

157762195

1

T1

34115

T3

51446

T4

3465

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	173449500	1			T1	37406		T3	281947		T4	3819
auto[TlIntgErrCmd]	89	1			T63	6		T64	4		T65	5
auto[TlIntgErrData]	84	1			T63	9		T64	6		T65	3
auto[TlIntgErrBoth]	87	1			T63	5		T65	2		T115	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83892170

1

T1

15385

T3

141081

T4

1882

auto[1]

89557590

1

T1

22021

T3

140866

T4

1937

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7693066	1			T1	1309		T3	115315		T4	175
auto[TlIntgErrNone]	partial	auto[1]	7994258	1			T1	1982		T3	115186		T4	179
auto[TlIntgErrNone]	full_word	auto[0]	76198987	1			T1	14076		T3	25766		T4	1707
auto[TlIntgErrNone]	full_word	auto[1]	81563189	1			T1	20039		T3	25680		T4	1758
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T65	3		T115	1		T120	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T63	6		T64	3		T65	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T120	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T64	1		T117	2		T118	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T63	4		T64	1		T115	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T63	4		T64	5		T65	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T120	1		T122	2		T118	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T63	1		T116	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T63	5		T115	3		T119	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T65	1		T115	2		T119	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T65	1		T118	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T124	1		T125	2		-	-