Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	736004	1			T1	602		T18	43		T19	54
auto[1]	11271489	1			T1	144		T3	118436		T4	3
auto[2]	573171	1			T1	557		T4	1		T18	34
auto[3]	11004389	1			T1	86		T3	118436		T10	1068

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15401004	1			T1	1090		T3	7779		T4	4
auto[1]	2173670	1			T1	145		T3	35514		T10	153
auto[2]	2217778	1			T1	129		T3	35357		T10	183
auto[3]	3792601	1			T1	25		T3	158222		T10	8

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10463275

1

T1

1389

T4

4

T10

2195

auto[1]

13121778

1

T3

236872

T11

1

T28

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	304948	1			T1	515		T18	37		T19	41
auto[0]	auto[0]	auto[1]	31682	1			T1	35		T18	2		T19	7
auto[0]	auto[0]	auto[2]	31638	1			T1	42		T18	3		T19	5
auto[0]	auto[0]	auto[3]	43702	1			T1	10		T18	1		T19	1
auto[0]	auto[1]	auto[0]	3900235	1			T1	78		T4	3		T10	943
auto[0]	auto[1]	auto[1]	396482	1			T1	57		T10	75		T11	2476
auto[0]	auto[1]	auto[2]	411019	1			T1	6		T10	105		T11	2636
auto[0]	auto[1]	auto[3]	273711	1			T1	3		T10	4		T11	241
auto[0]	auto[2]	auto[0]	222756	1			T1	467		T4	1		T43	2546
auto[0]	auto[2]	auto[1]	24360	1			T1	52		T43	252		T133	56
auto[0]	auto[2]	auto[2]	25712	1			T1	35		T18	31		T19	31
auto[0]	auto[2]	auto[3]	32160	1			T1	3		T18	3		T19	3
auto[0]	auto[3]	auto[0]	3727391	1			T1	30		T10	908		T11	26781
auto[0]	auto[3]	auto[1]	390212	1			T1	1		T10	78		T11	2678
auto[0]	auto[3]	auto[2]	396542	1			T1	46		T10	78		T11	2408
auto[0]	auto[3]	auto[3]	250725	1			T1	9		T10	4		T11	306
auto[1]	auto[0]	auto[0]	10626	1			T27	268		T77	797		T87	123
auto[1]	auto[0]	auto[1]	48123	1			T27	1174		T77	3551		T87	551
auto[1]	auto[0]	auto[2]	48412	1			T27	1209		T77	3619		T87	534
auto[1]	auto[0]	auto[3]	216873	1			T27	5223		T77	16358		T87	2470
auto[1]	auto[1]	auto[0]	3614837	1			T3	3884		T11	1		T28	1
auto[1]	auto[1]	auto[1]	642386	1			T3	17775		T29	4924		T27	1387
auto[1]	auto[1]	auto[2]	625176	1			T3	17677		T29	4888		T27	751
auto[1]	auto[1]	auto[3]	1407643	1			T3	79100		T29	519		T27	6115
auto[1]	auto[2]	auto[0]	6854	1			T27	152		T77	729		T104	942
auto[1]	auto[2]	auto[1]	31594	1			T27	717		T77	3414		T104	4534
auto[1]	auto[2]	auto[2]	41498	1			T27	1282		T77	2389		T87	515
auto[1]	auto[2]	auto[3]	188237	1			T27	5782		T77	10984		T87	2151
auto[1]	auto[3]	auto[0]	3613357	1			T3	3895		T29	49254		T27	58
auto[1]	auto[3]	auto[1]	608831	1			T3	17739		T29	4941		T27	287
auto[1]	auto[3]	auto[2]	637781	1			T3	17680		T29	4928		T27	1448
auto[1]	auto[3]	auto[3]	1379550	1			T3	79122		T29	479		T27	6684