Line Coverage for Module :
prim_mubi8_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Module :
prim_mubi8_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
898 |
898 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1036390775 |
1036282920 |
0 |
0 |
T1 |
397640 |
397582 |
0 |
0 |
T2 |
805 |
749 |
0 |
0 |
T3 |
634834 |
634780 |
0 |
0 |
T4 |
101429 |
101379 |
0 |
0 |
T8 |
33837 |
33784 |
0 |
0 |
T9 |
2000 |
1938 |
0 |
0 |
T10 |
68645 |
68562 |
0 |
0 |
T11 |
105702 |
105697 |
0 |
0 |
T12 |
33865 |
33811 |
0 |
0 |
T13 |
245157 |
245095 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1036390775 |
1036268775 |
0 |
2694 |
T1 |
397640 |
397579 |
0 |
3 |
T2 |
805 |
746 |
0 |
3 |
T3 |
634834 |
634777 |
0 |
3 |
T4 |
101429 |
101376 |
0 |
3 |
T8 |
33837 |
33781 |
0 |
3 |
T9 |
2000 |
1935 |
0 |
3 |
T10 |
68645 |
68559 |
0 |
3 |
T11 |
105702 |
105696 |
0 |
3 |
T12 |
33865 |
33808 |
0 |
3 |
T13 |
245157 |
245092 |
0 |
3 |