Module Definition
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Module : sram_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sram_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1049090989 225910 0 0
ctrl_regwen_rd_A 1049090989 4259 0 0
exec_rd_A 1049090989 3471 0 0
exec_regwen_rd_A 1049090989 3990 0 0
readback_rd_A 1049090989 2943 0 0
readback_regwen_rd_A 1049090989 2499 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1049090989 225910 0 0
T14 959 0 0 0
T20 144932 0 0 0
T21 107006 0 0 0
T24 327273 7692 0 0
T25 25173 2432 0 0
T26 0 6193 0 0
T43 100609 0 0 0
T55 0 11724 0 0
T61 0 3787 0 0
T66 160744 0 0 0
T71 0 5730 0 0
T72 0 4540 0 0
T73 0 1730 0 0
T74 0 3819 0 0
T75 0 1777 0 0
T76 35208 0 0 0
T77 180353 0 0 0
T78 41286 0 0 0

ctrl_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1049090989 4259 0 0
T14 959 0 0 0
T20 144932 0 0 0
T21 107006 0 0 0
T24 327273 654 0 0
T25 25173 0 0 0
T43 100609 0 0 0
T47 0 182 0 0
T51 0 325 0 0
T66 160744 0 0 0
T73 0 160 0 0
T76 35208 0 0 0
T77 180353 0 0 0
T78 41286 0 0 0
T108 0 480 0 0
T109 0 352 0 0
T110 0 217 0 0
T111 0 105 0 0
T112 0 213 0 0
T113 0 54 0 0

exec_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1049090989 3471 0 0
T14 959 0 0 0
T20 144932 0 0 0
T21 107006 0 0 0
T24 327273 496 0 0
T25 25173 0 0 0
T43 100609 0 0 0
T47 0 204 0 0
T51 0 216 0 0
T66 160744 0 0 0
T73 0 93 0 0
T76 35208 0 0 0
T77 180353 0 0 0
T78 41286 0 0 0
T108 0 278 0 0
T109 0 300 0 0
T110 0 195 0 0
T111 0 101 0 0
T112 0 199 0 0
T113 0 29 0 0

exec_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1049090989 3990 0 0
T14 959 0 0 0
T20 144932 0 0 0
T21 107006 0 0 0
T24 327273 570 0 0
T25 25173 0 0 0
T43 100609 0 0 0
T47 0 206 0 0
T51 0 304 0 0
T66 160744 0 0 0
T73 0 120 0 0
T76 35208 0 0 0
T77 180353 0 0 0
T78 41286 0 0 0
T108 0 278 0 0
T109 0 282 0 0
T110 0 369 0 0
T111 0 187 0 0
T112 0 176 0 0
T113 0 46 0 0

readback_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1049090989 2943 0 0
T14 959 0 0 0
T20 144932 0 0 0
T21 107006 0 0 0
T24 327273 621 0 0
T25 25173 0 0 0
T43 100609 0 0 0
T47 0 176 0 0
T51 0 204 0 0
T66 160744 0 0 0
T73 0 154 0 0
T76 35208 0 0 0
T77 180353 0 0 0
T78 41286 0 0 0
T108 0 304 0 0
T109 0 353 0 0
T110 0 177 0 0
T111 0 104 0 0
T112 0 222 0 0
T113 0 73 0 0

readback_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1049090989 2499 0 0
T14 959 0 0 0
T20 144932 0 0 0
T21 107006 0 0 0
T24 327273 487 0 0
T25 25173 0 0 0
T43 100609 0 0 0
T47 0 143 0 0
T51 0 206 0 0
T66 160744 0 0 0
T73 0 87 0 0
T76 35208 0 0 0
T77 180353 0 0 0
T78 41286 0 0 0
T108 0 307 0 0
T109 0 278 0 0
T110 0 201 0 0
T111 0 116 0 0
T112 0 150 0 0
T113 0 54 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%