Module Definition
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Module : tlul_adapter_reg
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.91 100.00 95.65 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_regs.u_reg_if 99.44 100.00 97.78 100.00 100.00



Module Instance : tb.dut.u_reg_regs.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.44 100.00 97.78 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.69 100.00 98.75 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.58 100.00 98.31 100.00 100.00 u_reg_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00

Line Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Module : tlul_adapter_reg
TotalCoveredPercent
Conditions464495.65
Logical464495.65
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T18,T19
11CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T3,T8
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T3,T8
10CoveredT1,T2,T3
11CoveredT1,T18,T19

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T8

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT1,T2,T3

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT1,T18,T19

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T18,T19

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T18,T19
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT1,T18,T19
001CoveredT1,T2,T3
010CoveredT24,T25,T26
100CoveredT24,T25,T26

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT24,T25,T26

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Unreachable
00010Not Covered
00100CoveredT1,T3,T8
01000Not Covered
10000CoveredT24,T25,T26

Branch Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T18,T19
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T18,T19
0 0 - Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 1032 1032 0 0
MatchedWidthAssert 1032 1032 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1032 1032 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 1032 1032 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN9111100.00
ALWAYS9566100.00
ALWAYS10188100.00
ALWAYS14166100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN21111100.00
ALWAYS21833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 1 1
86 1 1
91 1 1
95 2 2
96 2 2
97 2 2
MISSING_ELSE
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
109 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
MISSING_ELSE
149 1 1
150 1 1
154 1 1
204 1 1
208 1 1
211 1 1
218 1 1
220 1 1
223 1 1


Cond Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
TotalCoveredPercent
Conditions454497.78
Logical454497.78
Non-Logical00
Event00

 LINE       77
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
             --1--   ----------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T18,T19
11CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT1,T3,T8
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       80
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       81
 EXPRESSION (a_ack & (tl_i.a_opcode == Get))
             --1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T3,T8
10CoveredT1,T2,T3
11CoveredT1,T18,T19

 LINE       81
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T8

 LINE       83
 EXPRESSION (wr_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT1,T2,T3

 LINE       84
 EXPRESSION (rd_req & ((~err_internal)))
             ---1--   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T26
11CoveredT1,T18,T19

 LINE       109
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T18,T19

 LINE       145
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T18,T19
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT1,T18,T19
001CoveredT1,T2,T3
010CoveredT24,T25,T26
100CoveredT24,T25,T26

 LINE       146
 EXPRESSION (error_i || err_internal)
             ---1---    ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT24,T25,T26

 LINE       154
 SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
                 ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       154
 SUB-EXPRESSION (tl_i.a_valid & busy_i)
                 ------1-----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       208
 EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
             -------1------   ---------2--------   ---3--   -----4-----   -----5----
-1--2--3--4--5-StatusTestsExclude Annotation
00000CoveredT1,T2,T3
00001Unreachable
00010Not Covered
00100CoveredT1,T3,T8
01000Excluded VC_COV_UNR
10000CoveredT24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 95 4 4 100.00
IF 101 4 4 100.00
IF 218 2 2 100.00
IF 141 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 96 if (a_ack) -3-: 97 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 105 if (a_ack) -3-: 109 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T18,T19
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 218 if (wr_req)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (a_ack) -3-: 145 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T18,T19
0 0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg_regs.u_reg_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllowedLatency_A 1032 1032 0 0
MatchedWidthAssert 1032 1032 0 0


AllowedLatency_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1032 1032 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 1032 1032 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%