| T797 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3115628298 |
|
|
Jul 25 06:51:22 PM PDT 24 |
Jul 25 06:51:23 PM PDT 24 |
43956444 ps |
| T798 |
/workspace/coverage/default/24.sram_ctrl_regwen.1358372089 |
|
|
Jul 25 06:49:21 PM PDT 24 |
Jul 25 06:57:11 PM PDT 24 |
2451699473 ps |
| T799 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4133966272 |
|
|
Jul 25 06:48:09 PM PDT 24 |
Jul 25 06:53:27 PM PDT 24 |
24256945691 ps |
| T800 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2900402099 |
|
|
Jul 25 06:47:51 PM PDT 24 |
Jul 25 06:57:07 PM PDT 24 |
6022674187 ps |
| T801 |
/workspace/coverage/default/36.sram_ctrl_stress_all.2507522557 |
|
|
Jul 25 06:51:23 PM PDT 24 |
Jul 25 08:19:40 PM PDT 24 |
134354996621 ps |
| T802 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.162205279 |
|
|
Jul 25 06:52:29 PM PDT 24 |
Jul 25 06:53:11 PM PDT 24 |
7272988501 ps |
| T803 |
/workspace/coverage/default/1.sram_ctrl_bijection.2748635083 |
|
|
Jul 25 06:45:33 PM PDT 24 |
Jul 25 06:59:39 PM PDT 24 |
50585912642 ps |
| T804 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.4245320626 |
|
|
Jul 25 06:50:40 PM PDT 24 |
Jul 25 07:16:58 PM PDT 24 |
28637608171 ps |
| T805 |
/workspace/coverage/default/34.sram_ctrl_partial_access.4032925308 |
|
|
Jul 25 06:50:50 PM PDT 24 |
Jul 25 06:51:05 PM PDT 24 |
1078631991 ps |
| T806 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3442934098 |
|
|
Jul 25 06:45:34 PM PDT 24 |
Jul 25 06:53:33 PM PDT 24 |
22403938468 ps |
| T807 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3632378514 |
|
|
Jul 25 06:53:15 PM PDT 24 |
Jul 25 07:15:18 PM PDT 24 |
24934950720 ps |
| T808 |
/workspace/coverage/default/38.sram_ctrl_smoke.1767309224 |
|
|
Jul 25 06:51:31 PM PDT 24 |
Jul 25 06:53:58 PM PDT 24 |
1302235356 ps |
| T809 |
/workspace/coverage/default/45.sram_ctrl_executable.1713607053 |
|
|
Jul 25 06:52:52 PM PDT 24 |
Jul 25 06:57:11 PM PDT 24 |
14638131013 ps |
| T810 |
/workspace/coverage/default/9.sram_ctrl_bijection.519788773 |
|
|
Jul 25 06:46:58 PM PDT 24 |
Jul 25 07:26:04 PM PDT 24 |
546107775118 ps |
| T811 |
/workspace/coverage/default/37.sram_ctrl_smoke.1363623715 |
|
|
Jul 25 06:51:23 PM PDT 24 |
Jul 25 06:51:57 PM PDT 24 |
12075245147 ps |
| T812 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.332805690 |
|
|
Jul 25 06:45:28 PM PDT 24 |
Jul 25 06:47:58 PM PDT 24 |
18766139755 ps |
| T813 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3092578248 |
|
|
Jul 25 06:51:07 PM PDT 24 |
Jul 25 06:58:02 PM PDT 24 |
10615205912 ps |
| T814 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1324966623 |
|
|
Jul 25 06:48:24 PM PDT 24 |
Jul 25 06:53:16 PM PDT 24 |
31365915455 ps |
| T815 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.652741083 |
|
|
Jul 25 06:53:13 PM PDT 24 |
Jul 25 06:55:45 PM PDT 24 |
10148158207 ps |
| T816 |
/workspace/coverage/default/4.sram_ctrl_bijection.1972879156 |
|
|
Jul 25 06:46:13 PM PDT 24 |
Jul 25 07:26:08 PM PDT 24 |
106067435794 ps |
| T817 |
/workspace/coverage/default/12.sram_ctrl_stress_all.820364420 |
|
|
Jul 25 06:47:28 PM PDT 24 |
Jul 25 07:59:40 PM PDT 24 |
279042780170 ps |
| T818 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3599655472 |
|
|
Jul 25 06:53:23 PM PDT 24 |
Jul 25 08:39:19 PM PDT 24 |
44812496264 ps |
| T819 |
/workspace/coverage/default/22.sram_ctrl_bijection.2221144507 |
|
|
Jul 25 06:49:05 PM PDT 24 |
Jul 25 07:15:55 PM PDT 24 |
48135097074 ps |
| T820 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3764512278 |
|
|
Jul 25 06:47:07 PM PDT 24 |
Jul 25 06:49:41 PM PDT 24 |
16440306038 ps |
| T821 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1417611679 |
|
|
Jul 25 06:47:21 PM PDT 24 |
Jul 25 07:01:20 PM PDT 24 |
147550131959 ps |
| T822 |
/workspace/coverage/default/8.sram_ctrl_smoke.484165928 |
|
|
Jul 25 06:46:46 PM PDT 24 |
Jul 25 06:47:04 PM PDT 24 |
2072670105 ps |
| T823 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.311464991 |
|
|
Jul 25 06:52:00 PM PDT 24 |
Jul 25 06:52:04 PM PDT 24 |
723370312 ps |
| T824 |
/workspace/coverage/default/42.sram_ctrl_smoke.1536861084 |
|
|
Jul 25 06:52:03 PM PDT 24 |
Jul 25 06:52:19 PM PDT 24 |
896102986 ps |
| T825 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.37963723 |
|
|
Jul 25 06:47:12 PM PDT 24 |
Jul 25 06:47:16 PM PDT 24 |
363903070 ps |
| T826 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2942859511 |
|
|
Jul 25 06:50:52 PM PDT 24 |
Jul 25 07:00:01 PM PDT 24 |
41225370814 ps |
| T827 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3722801895 |
|
|
Jul 25 06:48:09 PM PDT 24 |
Jul 25 06:48:10 PM PDT 24 |
15666159 ps |
| T828 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2921719889 |
|
|
Jul 25 06:52:21 PM PDT 24 |
Jul 25 06:58:06 PM PDT 24 |
18939866587 ps |
| T829 |
/workspace/coverage/default/35.sram_ctrl_regwen.2957257922 |
|
|
Jul 25 06:51:09 PM PDT 24 |
Jul 25 07:11:15 PM PDT 24 |
12096100851 ps |
| T830 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1001955438 |
|
|
Jul 25 06:49:39 PM PDT 24 |
Jul 25 06:51:07 PM PDT 24 |
3225348208 ps |
| T831 |
/workspace/coverage/default/40.sram_ctrl_executable.4022121120 |
|
|
Jul 25 06:51:58 PM PDT 24 |
Jul 25 07:10:09 PM PDT 24 |
7856036669 ps |
| T832 |
/workspace/coverage/default/19.sram_ctrl_stress_all.4014621003 |
|
|
Jul 25 06:48:33 PM PDT 24 |
Jul 25 08:35:48 PM PDT 24 |
1045422828318 ps |
| T833 |
/workspace/coverage/default/49.sram_ctrl_executable.3574375848 |
|
|
Jul 25 06:53:33 PM PDT 24 |
Jul 25 07:10:45 PM PDT 24 |
29329105836 ps |
| T834 |
/workspace/coverage/default/34.sram_ctrl_stress_all.963946949 |
|
|
Jul 25 06:50:57 PM PDT 24 |
Jul 25 08:21:15 PM PDT 24 |
333847261998 ps |
| T835 |
/workspace/coverage/default/2.sram_ctrl_stress_all.2146543714 |
|
|
Jul 25 06:45:54 PM PDT 24 |
Jul 25 07:47:25 PM PDT 24 |
536105611382 ps |
| T836 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3549302967 |
|
|
Jul 25 06:46:29 PM PDT 24 |
Jul 25 06:51:52 PM PDT 24 |
81042299049 ps |
| T837 |
/workspace/coverage/default/11.sram_ctrl_stress_all.866710118 |
|
|
Jul 25 06:47:21 PM PDT 24 |
Jul 25 08:09:28 PM PDT 24 |
359232747173 ps |
| T838 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1470136147 |
|
|
Jul 25 06:46:12 PM PDT 24 |
Jul 25 07:03:35 PM PDT 24 |
70682227257 ps |
| T839 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2113625905 |
|
|
Jul 25 06:53:24 PM PDT 24 |
Jul 25 06:59:03 PM PDT 24 |
5017746406 ps |
| T840 |
/workspace/coverage/default/17.sram_ctrl_regwen.3791063978 |
|
|
Jul 25 06:48:10 PM PDT 24 |
Jul 25 07:09:25 PM PDT 24 |
3678170617 ps |
| T841 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3505682894 |
|
|
Jul 25 06:46:21 PM PDT 24 |
Jul 25 06:46:44 PM PDT 24 |
1860848066 ps |
| T842 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.2144240564 |
|
|
Jul 25 06:48:03 PM PDT 24 |
Jul 25 06:48:09 PM PDT 24 |
1364991712 ps |
| T843 |
/workspace/coverage/default/29.sram_ctrl_bijection.3689868824 |
|
|
Jul 25 06:50:02 PM PDT 24 |
Jul 25 06:59:13 PM PDT 24 |
86206498353 ps |
| T844 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1802350652 |
|
|
Jul 25 06:45:14 PM PDT 24 |
Jul 25 06:51:03 PM PDT 24 |
21705657394 ps |
| T845 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1199483465 |
|
|
Jul 25 06:51:14 PM PDT 24 |
Jul 25 07:16:25 PM PDT 24 |
121431166000 ps |
| T846 |
/workspace/coverage/default/19.sram_ctrl_partial_access.801230372 |
|
|
Jul 25 06:48:25 PM PDT 24 |
Jul 25 06:48:38 PM PDT 24 |
1646641337 ps |
| T847 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1656875668 |
|
|
Jul 25 06:47:37 PM PDT 24 |
Jul 25 07:01:27 PM PDT 24 |
55851976687 ps |
| T848 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2083570954 |
|
|
Jul 25 06:47:21 PM PDT 24 |
Jul 25 06:47:40 PM PDT 24 |
635483409 ps |
| T849 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.846577895 |
|
|
Jul 25 06:47:52 PM PDT 24 |
Jul 25 06:49:06 PM PDT 24 |
2804457150 ps |
| T850 |
/workspace/coverage/default/8.sram_ctrl_bijection.74028154 |
|
|
Jul 25 06:46:47 PM PDT 24 |
Jul 25 07:23:07 PM PDT 24 |
231862608988 ps |
| T851 |
/workspace/coverage/default/28.sram_ctrl_regwen.3964660622 |
|
|
Jul 25 06:49:55 PM PDT 24 |
Jul 25 06:59:38 PM PDT 24 |
8331537837 ps |
| T852 |
/workspace/coverage/default/43.sram_ctrl_alert_test.1511473886 |
|
|
Jul 25 06:52:37 PM PDT 24 |
Jul 25 06:52:37 PM PDT 24 |
21032098 ps |
| T853 |
/workspace/coverage/default/35.sram_ctrl_smoke.2566316907 |
|
|
Jul 25 06:50:59 PM PDT 24 |
Jul 25 06:51:19 PM PDT 24 |
912105981 ps |
| T854 |
/workspace/coverage/default/37.sram_ctrl_regwen.3238927098 |
|
|
Jul 25 06:51:30 PM PDT 24 |
Jul 25 06:57:18 PM PDT 24 |
6200171089 ps |
| T855 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.829261785 |
|
|
Jul 25 06:48:09 PM PDT 24 |
Jul 25 06:52:31 PM PDT 24 |
3844464292 ps |
| T856 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.212474940 |
|
|
Jul 25 06:51:16 PM PDT 24 |
Jul 25 07:13:43 PM PDT 24 |
61891475550 ps |
| T857 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1461264011 |
|
|
Jul 25 06:49:51 PM PDT 24 |
Jul 25 06:56:41 PM PDT 24 |
33053489771 ps |
| T858 |
/workspace/coverage/default/21.sram_ctrl_smoke.3791524569 |
|
|
Jul 25 06:48:41 PM PDT 24 |
Jul 25 06:48:46 PM PDT 24 |
960113251 ps |
| T859 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.1800215702 |
|
|
Jul 25 06:47:53 PM PDT 24 |
Jul 25 06:49:10 PM PDT 24 |
5788955025 ps |
| T860 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1164023094 |
|
|
Jul 25 06:46:52 PM PDT 24 |
Jul 25 09:20:38 PM PDT 24 |
1361544252399 ps |
| T861 |
/workspace/coverage/default/0.sram_ctrl_smoke.3614133064 |
|
|
Jul 25 06:45:15 PM PDT 24 |
Jul 25 06:45:29 PM PDT 24 |
1454432622 ps |
| T862 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1435369803 |
|
|
Jul 25 06:46:27 PM PDT 24 |
Jul 25 06:46:31 PM PDT 24 |
1407751341 ps |
| T863 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1731290477 |
|
|
Jul 25 06:51:45 PM PDT 24 |
Jul 25 07:03:35 PM PDT 24 |
10533286476 ps |
| T28 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3127677662 |
|
|
Jul 25 06:45:41 PM PDT 24 |
Jul 25 06:45:45 PM PDT 24 |
1508627549 ps |
| T864 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.377463063 |
|
|
Jul 25 06:53:11 PM PDT 24 |
Jul 25 06:53:41 PM PDT 24 |
3245220926 ps |
| T865 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3339064437 |
|
|
Jul 25 06:50:02 PM PDT 24 |
Jul 25 06:51:21 PM PDT 24 |
10302979725 ps |
| T866 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.4188736624 |
|
|
Jul 25 06:49:02 PM PDT 24 |
Jul 25 06:54:32 PM PDT 24 |
58354024738 ps |
| T867 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1378307986 |
|
|
Jul 25 06:51:40 PM PDT 24 |
Jul 25 07:07:09 PM PDT 24 |
87159758472 ps |
| T868 |
/workspace/coverage/default/18.sram_ctrl_regwen.1626916764 |
|
|
Jul 25 06:48:26 PM PDT 24 |
Jul 25 06:48:33 PM PDT 24 |
2861302670 ps |
| T869 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1277599659 |
|
|
Jul 25 06:46:35 PM PDT 24 |
Jul 25 06:50:26 PM PDT 24 |
20615136912 ps |
| T870 |
/workspace/coverage/default/48.sram_ctrl_bijection.2970431688 |
|
|
Jul 25 06:53:24 PM PDT 24 |
Jul 25 07:02:39 PM PDT 24 |
16448637345 ps |
| T871 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3336079916 |
|
|
Jul 25 06:46:37 PM PDT 24 |
Jul 25 06:46:37 PM PDT 24 |
142125866 ps |
| T872 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2761668047 |
|
|
Jul 25 06:50:09 PM PDT 24 |
Jul 25 06:52:32 PM PDT 24 |
10188540073 ps |
| T29 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3134807683 |
|
|
Jul 25 06:46:18 PM PDT 24 |
Jul 25 06:46:22 PM PDT 24 |
789685716 ps |
| T873 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.881125818 |
|
|
Jul 25 06:50:24 PM PDT 24 |
Jul 25 07:11:52 PM PDT 24 |
17170582555 ps |
| T874 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.583130054 |
|
|
Jul 25 06:48:42 PM PDT 24 |
Jul 25 06:49:44 PM PDT 24 |
1291133132 ps |
| T875 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3786734343 |
|
|
Jul 25 06:49:04 PM PDT 24 |
Jul 25 06:49:42 PM PDT 24 |
1444553569 ps |
| T876 |
/workspace/coverage/default/1.sram_ctrl_regwen.1197987678 |
|
|
Jul 25 06:45:35 PM PDT 24 |
Jul 25 06:47:12 PM PDT 24 |
1767575632 ps |
| T877 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3513951545 |
|
|
Jul 25 06:52:47 PM PDT 24 |
Jul 25 06:59:13 PM PDT 24 |
20454688752 ps |
| T878 |
/workspace/coverage/default/4.sram_ctrl_stress_all.2146278180 |
|
|
Jul 25 06:46:24 PM PDT 24 |
Jul 25 08:18:45 PM PDT 24 |
198424551667 ps |
| T879 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3243476511 |
|
|
Jul 25 06:51:22 PM PDT 24 |
Jul 25 06:51:25 PM PDT 24 |
1350568637 ps |
| T880 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1751682898 |
|
|
Jul 25 06:48:25 PM PDT 24 |
Jul 25 07:06:16 PM PDT 24 |
57714089814 ps |
| T881 |
/workspace/coverage/default/12.sram_ctrl_smoke.3440548877 |
|
|
Jul 25 06:47:20 PM PDT 24 |
Jul 25 06:48:18 PM PDT 24 |
2272798029 ps |
| T882 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2255486541 |
|
|
Jul 25 06:46:23 PM PDT 24 |
Jul 25 06:47:28 PM PDT 24 |
10047686339 ps |
| T883 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3349037854 |
|
|
Jul 25 06:49:12 PM PDT 24 |
Jul 25 06:50:57 PM PDT 24 |
18730877911 ps |
| T884 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2355607872 |
|
|
Jul 25 06:49:33 PM PDT 24 |
Jul 25 07:01:29 PM PDT 24 |
28146499599 ps |
| T885 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.177524553 |
|
|
Jul 25 06:47:30 PM PDT 24 |
Jul 25 07:04:21 PM PDT 24 |
10801022244 ps |
| T886 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.4097104122 |
|
|
Jul 25 06:48:26 PM PDT 24 |
Jul 25 06:50:22 PM PDT 24 |
64528588065 ps |
| T887 |
/workspace/coverage/default/7.sram_ctrl_regwen.2356855838 |
|
|
Jul 25 06:46:45 PM PDT 24 |
Jul 25 06:52:50 PM PDT 24 |
8228864609 ps |
| T888 |
/workspace/coverage/default/12.sram_ctrl_alert_test.1126492339 |
|
|
Jul 25 06:47:29 PM PDT 24 |
Jul 25 06:47:29 PM PDT 24 |
53599550 ps |
| T889 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.264334122 |
|
|
Jul 25 06:47:53 PM PDT 24 |
Jul 25 06:47:59 PM PDT 24 |
351503753 ps |
| T890 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.4239511368 |
|
|
Jul 25 06:50:17 PM PDT 24 |
Jul 25 06:51:19 PM PDT 24 |
47088643715 ps |
| T891 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1146836796 |
|
|
Jul 25 06:51:16 PM PDT 24 |
Jul 25 06:58:31 PM PDT 24 |
17636012137 ps |
| T892 |
/workspace/coverage/default/31.sram_ctrl_bijection.4017363983 |
|
|
Jul 25 06:50:26 PM PDT 24 |
Jul 25 07:25:00 PM PDT 24 |
309575223278 ps |
| T893 |
/workspace/coverage/default/20.sram_ctrl_stress_all.4167777948 |
|
|
Jul 25 06:48:42 PM PDT 24 |
Jul 25 08:47:53 PM PDT 24 |
412453240117 ps |
| T894 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1501828307 |
|
|
Jul 25 06:48:02 PM PDT 24 |
Jul 25 06:50:17 PM PDT 24 |
820021607 ps |
| T895 |
/workspace/coverage/default/27.sram_ctrl_bijection.1690585472 |
|
|
Jul 25 06:49:46 PM PDT 24 |
Jul 25 07:08:12 PM PDT 24 |
56755805735 ps |
| T896 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3885673621 |
|
|
Jul 25 06:45:40 PM PDT 24 |
Jul 25 06:46:56 PM PDT 24 |
5243184562 ps |
| T897 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4052552788 |
|
|
Jul 25 06:49:54 PM PDT 24 |
Jul 25 06:50:04 PM PDT 24 |
689232008 ps |
| T898 |
/workspace/coverage/default/9.sram_ctrl_smoke.1879211905 |
|
|
Jul 25 06:46:58 PM PDT 24 |
Jul 25 06:47:14 PM PDT 24 |
9247817055 ps |
| T899 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2450091702 |
|
|
Jul 25 06:52:36 PM PDT 24 |
Jul 25 06:55:12 PM PDT 24 |
9806284085 ps |
| T900 |
/workspace/coverage/default/2.sram_ctrl_alert_test.1230035818 |
|
|
Jul 25 06:45:48 PM PDT 24 |
Jul 25 06:45:48 PM PDT 24 |
48645758 ps |
| T901 |
/workspace/coverage/default/47.sram_ctrl_bijection.2167629927 |
|
|
Jul 25 06:53:13 PM PDT 24 |
Jul 25 07:15:10 PM PDT 24 |
39217983745 ps |
| T902 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1596161710 |
|
|
Jul 25 06:46:11 PM PDT 24 |
Jul 25 06:46:15 PM PDT 24 |
1467558021 ps |
| T903 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2145979213 |
|
|
Jul 25 06:46:27 PM PDT 24 |
Jul 25 06:51:21 PM PDT 24 |
21875579968 ps |
| T904 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.115777580 |
|
|
Jul 25 06:49:23 PM PDT 24 |
Jul 25 06:52:34 PM PDT 24 |
7451645597 ps |
| T905 |
/workspace/coverage/default/5.sram_ctrl_partial_access.205322785 |
|
|
Jul 25 06:46:19 PM PDT 24 |
Jul 25 06:46:53 PM PDT 24 |
737761655 ps |
| T906 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.232868708 |
|
|
Jul 25 06:51:17 PM PDT 24 |
Jul 25 06:54:08 PM PDT 24 |
10385847163 ps |
| T907 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3357597796 |
|
|
Jul 25 06:51:49 PM PDT 24 |
Jul 25 06:52:36 PM PDT 24 |
781707859 ps |
| T908 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3191938378 |
|
|
Jul 25 06:48:42 PM PDT 24 |
Jul 25 06:48:43 PM PDT 24 |
16151771 ps |
| T909 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1567254051 |
|
|
Jul 25 06:50:34 PM PDT 24 |
Jul 25 06:51:00 PM PDT 24 |
1013949786 ps |
| T910 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3258513488 |
|
|
Jul 25 06:50:26 PM PDT 24 |
Jul 25 06:57:38 PM PDT 24 |
6096155181 ps |
| T911 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.646255168 |
|
|
Jul 25 06:46:11 PM PDT 24 |
Jul 25 06:46:24 PM PDT 24 |
949124982 ps |
| T912 |
/workspace/coverage/default/48.sram_ctrl_regwen.2009506553 |
|
|
Jul 25 06:53:22 PM PDT 24 |
Jul 25 07:01:04 PM PDT 24 |
16146598247 ps |
| T913 |
/workspace/coverage/default/22.sram_ctrl_smoke.2886756050 |
|
|
Jul 25 06:48:48 PM PDT 24 |
Jul 25 06:49:04 PM PDT 24 |
511166730 ps |
| T914 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1181451171 |
|
|
Jul 25 06:52:37 PM PDT 24 |
Jul 25 06:58:36 PM PDT 24 |
15782685746 ps |
| T915 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.2747063395 |
|
|
Jul 25 06:47:52 PM PDT 24 |
Jul 25 06:49:11 PM PDT 24 |
46744009204 ps |
| T916 |
/workspace/coverage/default/45.sram_ctrl_regwen.3457658338 |
|
|
Jul 25 06:52:52 PM PDT 24 |
Jul 25 06:57:21 PM PDT 24 |
6350213338 ps |
| T917 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2018571825 |
|
|
Jul 25 06:50:42 PM PDT 24 |
Jul 25 06:56:46 PM PDT 24 |
21916512663 ps |
| T918 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.577667893 |
|
|
Jul 25 06:47:19 PM PDT 24 |
Jul 25 06:47:23 PM PDT 24 |
354598315 ps |
| T919 |
/workspace/coverage/default/11.sram_ctrl_alert_test.155992735 |
|
|
Jul 25 06:47:20 PM PDT 24 |
Jul 25 06:47:21 PM PDT 24 |
38269374 ps |
| T920 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1839643350 |
|
|
Jul 25 06:47:14 PM PDT 24 |
Jul 25 06:47:45 PM PDT 24 |
7898169324 ps |
| T921 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1427053414 |
|
|
Jul 25 06:49:13 PM PDT 24 |
Jul 25 07:25:20 PM PDT 24 |
208983464589 ps |
| T922 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.850191781 |
|
|
Jul 25 06:53:13 PM PDT 24 |
Jul 25 07:01:37 PM PDT 24 |
59355858794 ps |
| T923 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3244133629 |
|
|
Jul 25 06:47:37 PM PDT 24 |
Jul 25 06:49:02 PM PDT 24 |
4594446302 ps |
| T924 |
/workspace/coverage/default/35.sram_ctrl_executable.1457109086 |
|
|
Jul 25 06:51:10 PM PDT 24 |
Jul 25 06:56:28 PM PDT 24 |
8230314226 ps |
| T925 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.410533667 |
|
|
Jul 25 06:50:03 PM PDT 24 |
Jul 25 06:55:47 PM PDT 24 |
20697299491 ps |
| T926 |
/workspace/coverage/default/30.sram_ctrl_bijection.711193565 |
|
|
Jul 25 06:50:19 PM PDT 24 |
Jul 25 07:26:57 PM PDT 24 |
524124892797 ps |
| T927 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.554636871 |
|
|
Jul 25 06:47:29 PM PDT 24 |
Jul 25 06:48:38 PM PDT 24 |
53410159265 ps |
| T928 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.1106537722 |
|
|
Jul 25 06:45:58 PM PDT 24 |
Jul 25 06:46:14 PM PDT 24 |
2113199087 ps |
| T929 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3453593375 |
|
|
Jul 25 06:48:00 PM PDT 24 |
Jul 25 06:48:04 PM PDT 24 |
1413838890 ps |
| T930 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.1262805013 |
|
|
Jul 25 06:46:45 PM PDT 24 |
Jul 25 06:49:18 PM PDT 24 |
10954127883 ps |
| T931 |
/workspace/coverage/default/44.sram_ctrl_regwen.1985413343 |
|
|
Jul 25 06:52:38 PM PDT 24 |
Jul 25 06:55:14 PM PDT 24 |
3781163537 ps |
| T932 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.1662549887 |
|
|
Jul 25 06:50:27 PM PDT 24 |
Jul 25 06:50:58 PM PDT 24 |
3009089331 ps |
| T933 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1439359125 |
|
|
Jul 25 06:53:02 PM PDT 24 |
Jul 25 06:57:48 PM PDT 24 |
112157321148 ps |
| T934 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.515310606 |
|
|
Jul 25 06:51:32 PM PDT 24 |
Jul 25 06:52:58 PM PDT 24 |
15494355086 ps |
| T935 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.991820582 |
|
|
Jul 25 06:49:29 PM PDT 24 |
Jul 25 06:50:01 PM PDT 24 |
2861845494 ps |
| T936 |
/workspace/coverage/default/33.sram_ctrl_regwen.2154745307 |
|
|
Jul 25 06:50:50 PM PDT 24 |
Jul 25 07:18:12 PM PDT 24 |
8081613624 ps |
| T937 |
/workspace/coverage/default/33.sram_ctrl_smoke.2622179380 |
|
|
Jul 25 06:50:41 PM PDT 24 |
Jul 25 06:52:31 PM PDT 24 |
1556032988 ps |
| T938 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.636419208 |
|
|
Jul 25 06:48:18 PM PDT 24 |
Jul 25 06:53:39 PM PDT 24 |
10586612025 ps |
| T939 |
/workspace/coverage/default/24.sram_ctrl_executable.19069265 |
|
|
Jul 25 06:49:21 PM PDT 24 |
Jul 25 07:03:25 PM PDT 24 |
7405079989 ps |
| T940 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2690604793 |
|
|
Jul 25 06:46:45 PM PDT 24 |
Jul 25 06:46:46 PM PDT 24 |
29786624 ps |
| T941 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1616623889 |
|
|
Jul 25 06:46:00 PM PDT 24 |
Jul 25 06:46:07 PM PDT 24 |
723374931 ps |
| T942 |
/workspace/coverage/default/28.sram_ctrl_smoke.2988536778 |
|
|
Jul 25 06:49:58 PM PDT 24 |
Jul 25 06:50:04 PM PDT 24 |
820427797 ps |
| T943 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.703596427 |
|
|
Jul 25 06:52:22 PM PDT 24 |
Jul 25 06:52:32 PM PDT 24 |
215607634 ps |
| T944 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1942746836 |
|
|
Jul 25 06:47:53 PM PDT 24 |
Jul 25 06:47:57 PM PDT 24 |
1401870367 ps |
| T945 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.605479974 |
|
|
Jul 25 06:40:20 PM PDT 24 |
Jul 25 06:40:22 PM PDT 24 |
55977926 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1100676445 |
|
|
Jul 25 06:41:14 PM PDT 24 |
Jul 25 06:41:19 PM PDT 24 |
1428115114 ps |
| T65 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2645877541 |
|
|
Jul 25 06:40:18 PM PDT 24 |
Jul 25 06:40:18 PM PDT 24 |
17163861 ps |
| T66 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4240683404 |
|
|
Jul 25 06:40:40 PM PDT 24 |
Jul 25 06:40:41 PM PDT 24 |
14906545 ps |
| T67 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3347189401 |
|
|
Jul 25 06:40:08 PM PDT 24 |
Jul 25 06:40:09 PM PDT 24 |
73802947 ps |
| T947 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2957146611 |
|
|
Jul 25 06:40:27 PM PDT 24 |
Jul 25 06:40:32 PM PDT 24 |
757096922 ps |
| T82 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.986984579 |
|
|
Jul 25 06:40:27 PM PDT 24 |
Jul 25 06:40:28 PM PDT 24 |
17515523 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3481202622 |
|
|
Jul 25 06:40:35 PM PDT 24 |
Jul 25 06:40:37 PM PDT 24 |
99826940 ps |
| T83 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.672757515 |
|
|
Jul 25 06:40:36 PM PDT 24 |
Jul 25 06:41:05 PM PDT 24 |
14834153887 ps |
| T949 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4041346820 |
|
|
Jul 25 06:40:20 PM PDT 24 |
Jul 25 06:40:24 PM PDT 24 |
65509203 ps |
| T106 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1011623644 |
|
|
Jul 25 06:40:29 PM PDT 24 |
Jul 25 06:40:30 PM PDT 24 |
25968378 ps |
| T107 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4032940521 |
|
|
Jul 25 06:40:19 PM PDT 24 |
Jul 25 06:40:20 PM PDT 24 |
20350405 ps |
| T108 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1746226537 |
|
|
Jul 25 06:40:34 PM PDT 24 |
Jul 25 06:41:34 PM PDT 24 |
50438921597 ps |
| T118 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1328956970 |
|
|
Jul 25 06:40:12 PM PDT 24 |
Jul 25 06:40:13 PM PDT 24 |
33302915 ps |
| T62 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.810826198 |
|
|
Jul 25 06:40:44 PM PDT 24 |
Jul 25 06:40:47 PM PDT 24 |
282618024 ps |
| T109 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2553492731 |
|
|
Jul 25 06:40:21 PM PDT 24 |
Jul 25 06:40:22 PM PDT 24 |
61896456 ps |
| T950 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2020701846 |
|
|
Jul 25 06:40:35 PM PDT 24 |
Jul 25 06:40:39 PM PDT 24 |
1583053105 ps |
| T63 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1107578106 |
|
|
Jul 25 06:40:35 PM PDT 24 |
Jul 25 06:40:37 PM PDT 24 |
224338789 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2347254193 |
|
|
Jul 25 06:40:28 PM PDT 24 |
Jul 25 06:40:33 PM PDT 24 |
1154632177 ps |
| T952 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2713524822 |
|
|
Jul 25 06:40:33 PM PDT 24 |
Jul 25 06:40:37 PM PDT 24 |
4211776542 ps |
| T953 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2569999989 |
|
|
Jul 25 06:40:11 PM PDT 24 |
Jul 25 06:40:15 PM PDT 24 |
1366537070 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1105131604 |
|
|
Jul 25 06:40:12 PM PDT 24 |
Jul 25 06:40:17 PM PDT 24 |
161660986 ps |
| T110 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2774932445 |
|
|
Jul 25 06:40:43 PM PDT 24 |
Jul 25 06:40:44 PM PDT 24 |
192860543 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1084810945 |
|
|
Jul 25 06:40:13 PM PDT 24 |
Jul 25 06:40:14 PM PDT 24 |
393344559 ps |
| T111 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1900200879 |
|
|
Jul 25 06:40:27 PM PDT 24 |
Jul 25 06:40:27 PM PDT 24 |
33893235 ps |
| T956 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2154785634 |
|
|
Jul 25 06:40:20 PM PDT 24 |
Jul 25 06:40:24 PM PDT 24 |
1910884550 ps |
| T957 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1052565338 |
|
|
Jul 25 06:40:12 PM PDT 24 |
Jul 25 06:40:17 PM PDT 24 |
816911912 ps |
| T112 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3398462027 |
|
|
Jul 25 06:40:43 PM PDT 24 |
Jul 25 06:40:44 PM PDT 24 |
64741906 ps |
| T958 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1347198017 |
|
|
Jul 25 06:40:28 PM PDT 24 |
Jul 25 06:40:29 PM PDT 24 |
42757420 ps |
| T959 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3544512570 |
|
|
Jul 25 06:40:04 PM PDT 24 |
Jul 25 06:40:32 PM PDT 24 |
15376971690 ps |
| T84 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1005002762 |
|
|
Jul 25 06:40:43 PM PDT 24 |
Jul 25 06:41:17 PM PDT 24 |
74067629118 ps |
| T85 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1783958135 |
|
|
Jul 25 06:40:34 PM PDT 24 |
Jul 25 06:41:06 PM PDT 24 |
13701414596 ps |
| T960 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2514917088 |
|
|
Jul 25 06:40:42 PM PDT 24 |
Jul 25 06:40:47 PM PDT 24 |
412448086 ps |
| T86 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2289786280 |
|
|
Jul 25 06:40:36 PM PDT 24 |
Jul 25 06:40:36 PM PDT 24 |
40159828 ps |
| T87 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.502859367 |
|
|
Jul 25 06:40:19 PM PDT 24 |
Jul 25 06:41:17 PM PDT 24 |
25182123608 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3995322439 |
|
|
Jul 25 06:40:19 PM PDT 24 |
Jul 25 06:40:23 PM PDT 24 |
4261705428 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2171260739 |
|
|
Jul 25 06:40:43 PM PDT 24 |
Jul 25 06:40:48 PM PDT 24 |
110147647 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3856129044 |
|
|
Jul 25 06:40:19 PM PDT 24 |
Jul 25 06:40:22 PM PDT 24 |
358835679 ps |
| T88 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1704601159 |
|
|
Jul 25 06:40:33 PM PDT 24 |
Jul 25 06:40:34 PM PDT 24 |
101863405 ps |
| T89 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1135099262 |
|
|
Jul 25 06:40:06 PM PDT 24 |
Jul 25 06:40:59 PM PDT 24 |
7074433259 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.222217238 |
|
|
Jul 25 06:40:05 PM PDT 24 |
Jul 25 06:40:06 PM PDT 24 |
51513778 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1840427756 |
|
|
Jul 25 06:40:04 PM PDT 24 |
Jul 25 06:40:07 PM PDT 24 |
172581105 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3273765626 |
|
|
Jul 25 06:40:16 PM PDT 24 |
Jul 25 06:40:18 PM PDT 24 |
1122267141 ps |
| T965 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1535986878 |
|
|
Jul 25 06:40:35 PM PDT 24 |
Jul 25 06:40:39 PM PDT 24 |
367863351 ps |
| T128 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2168105722 |
|
|
Jul 25 06:40:27 PM PDT 24 |
Jul 25 06:40:29 PM PDT 24 |
465962006 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3350987473 |
|
|
Jul 25 06:40:26 PM PDT 24 |
Jul 25 06:40:27 PM PDT 24 |
16461523 ps |
| T967 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.133830553 |
|
|
Jul 25 06:40:34 PM PDT 24 |
Jul 25 06:40:38 PM PDT 24 |
3821001145 ps |
| T91 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.559968475 |
|
|
Jul 25 06:40:21 PM PDT 24 |
Jul 25 06:40:48 PM PDT 24 |
3728200965 ps |
| T125 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2838380477 |
|
|
Jul 25 06:40:19 PM PDT 24 |
Jul 25 06:40:22 PM PDT 24 |
426667188 ps |
| T968 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.783011668 |
|
|
Jul 25 06:40:19 PM PDT 24 |
Jul 25 06:40:21 PM PDT 24 |
22984728 ps |
| T126 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.911359716 |
|
|
Jul 25 06:40:13 PM PDT 24 |
Jul 25 06:40:16 PM PDT 24 |
669566680 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1554412819 |
|
|
Jul 25 06:40:06 PM PDT 24 |
Jul 25 06:40:07 PM PDT 24 |
20439767 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4118107468 |
|
|
Jul 25 06:40:41 PM PDT 24 |
Jul 25 06:40:42 PM PDT 24 |
69257706 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3943397453 |
|
|
Jul 25 06:40:12 PM PDT 24 |
Jul 25 06:40:16 PM PDT 24 |
121804842 ps |
| T92 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1421692379 |
|
|
Jul 25 06:40:43 PM PDT 24 |
Jul 25 06:41:10 PM PDT 24 |
5671711113 ps |
| T93 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4103102773 |
|
|
Jul 25 06:40:35 PM PDT 24 |
Jul 25 06:41:02 PM PDT 24 |
14773750047 ps |
| T127 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3980826066 |
|
|
Jul 25 06:40:06 PM PDT 24 |
Jul 25 06:40:07 PM PDT 24 |
861064067 ps |
| T972 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3313649290 |
|
|
Jul 25 06:40:28 PM PDT 24 |
Jul 25 06:40:31 PM PDT 24 |
28197393 ps |
| T94 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1015752633 |
|
|
Jul 25 06:40:07 PM PDT 24 |
Jul 25 06:40:08 PM PDT 24 |
16947261 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1837471241 |
|
|
Jul 25 06:40:12 PM PDT 24 |
Jul 25 06:40:13 PM PDT 24 |
22064565 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2438016700 |
|
|
Jul 25 06:40:06 PM PDT 24 |
Jul 25 06:40:06 PM PDT 24 |
48376607 ps |
| T975 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1657016467 |
|
|
Jul 25 06:40:34 PM PDT 24 |
Jul 25 06:40:36 PM PDT 24 |
1388348726 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1458430136 |
|
|
Jul 25 06:40:05 PM PDT 24 |
Jul 25 06:40:09 PM PDT 24 |
365355731 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2097978368 |
|
|
Jul 25 06:40:14 PM PDT 24 |
Jul 25 06:40:15 PM PDT 24 |
82692858 ps |
| T978 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1222739018 |
|
|
Jul 25 06:40:13 PM PDT 24 |
Jul 25 06:40:14 PM PDT 24 |
20636315 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3601024369 |
|
|
Jul 25 06:40:06 PM PDT 24 |
Jul 25 06:40:08 PM PDT 24 |
90142685 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1787610203 |
|
|
Jul 25 06:40:34 PM PDT 24 |
Jul 25 06:40:35 PM PDT 24 |
31180960 ps |
| T981 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2184711225 |
|
|
Jul 25 06:40:43 PM PDT 24 |
Jul 25 06:40:47 PM PDT 24 |
374298053 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3801741878 |
|
|
Jul 25 06:40:27 PM PDT 24 |
Jul 25 06:40:54 PM PDT 24 |
3722022006 ps |
| T982 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2483331533 |
|
|
Jul 25 06:40:26 PM PDT 24 |
Jul 25 06:40:29 PM PDT 24 |
38630847 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.381871975 |
|
|
Jul 25 06:41:14 PM PDT 24 |
Jul 25 06:41:16 PM PDT 24 |
191267640 ps |
| T984 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.929535293 |
|
|
Jul 25 06:40:42 PM PDT 24 |
Jul 25 06:40:43 PM PDT 24 |
37197696 ps |
| T98 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3373166222 |
|
|
Jul 25 06:40:20 PM PDT 24 |
Jul 25 06:41:13 PM PDT 24 |
29450593310 ps |
| T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2247132222 |
|
|
Jul 25 06:40:08 PM PDT 24 |
Jul 25 06:40:09 PM PDT 24 |
14442297 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2702783806 |
|
|
Jul 25 06:40:34 PM PDT 24 |
Jul 25 06:40:35 PM PDT 24 |
93559477 ps |
| T987 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.764662403 |
|
|
Jul 25 06:40:20 PM PDT 24 |
Jul 25 06:40:21 PM PDT 24 |
46955500 ps |
| T988 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1133381011 |
|
|
Jul 25 06:40:41 PM PDT 24 |
Jul 25 06:40:42 PM PDT 24 |
83742344 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.148314592 |
|
|
Jul 25 06:40:21 PM PDT 24 |
Jul 25 06:41:22 PM PDT 24 |
33576012439 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3793243783 |
|
|
Jul 25 06:40:07 PM PDT 24 |
Jul 25 06:40:08 PM PDT 24 |
18351354 ps |
| T991 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3179391264 |
|
|
Jul 25 06:40:06 PM PDT 24 |
Jul 25 06:40:08 PM PDT 24 |
27816657 ps |
| T992 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.889305656 |
|
|
Jul 25 06:40:42 PM PDT 24 |
Jul 25 06:40:44 PM PDT 24 |
21226992 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1769866669 |
|
|
Jul 25 06:40:33 PM PDT 24 |
Jul 25 06:40:34 PM PDT 24 |
12516790 ps |
| T994 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2193779826 |
|
|
Jul 25 06:40:28 PM PDT 24 |
Jul 25 06:40:32 PM PDT 24 |
865806022 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2605610077 |
|
|
Jul 25 06:40:06 PM PDT 24 |
Jul 25 06:40:07 PM PDT 24 |
21080707 ps |
| T104 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.459453228 |
|
|
Jul 25 06:40:07 PM PDT 24 |
Jul 25 06:40:08 PM PDT 24 |
11148044 ps |
| T996 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1629462121 |
|
|
Jul 25 06:40:20 PM PDT 24 |
Jul 25 06:40:21 PM PDT 24 |
52696596 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3031632443 |
|
|
Jul 25 06:40:35 PM PDT 24 |
Jul 25 06:40:39 PM PDT 24 |
99412041 ps |
| T998 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3155729551 |
|
|
Jul 25 06:40:19 PM PDT 24 |
Jul 25 06:40:20 PM PDT 24 |
83779672 ps |
| T124 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1628294111 |
|
|
Jul 25 06:40:18 PM PDT 24 |
Jul 25 06:40:21 PM PDT 24 |
221427584 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1069847827 |
|
|
Jul 25 06:40:11 PM PDT 24 |
Jul 25 06:40:15 PM PDT 24 |
1430106444 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2731763360 |
|
|
Jul 25 06:40:28 PM PDT 24 |
Jul 25 06:40:32 PM PDT 24 |
373087008 ps |
| T99 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.411018957 |
|
|
Jul 25 06:40:27 PM PDT 24 |
Jul 25 06:40:55 PM PDT 24 |
11215236625 ps |
| T129 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1923350804 |
|
|
Jul 25 06:40:20 PM PDT 24 |
Jul 25 06:40:22 PM PDT 24 |
193314673 ps |
| T100 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4238075184 |
|
|
Jul 25 06:40:42 PM PDT 24 |
Jul 25 06:40:43 PM PDT 24 |
14258373 ps |
| T1001 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3278598806 |
|
|
Jul 25 06:40:27 PM PDT 24 |
Jul 25 06:40:31 PM PDT 24 |
116008301 ps |
| T1002 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1268558134 |
|
|
Jul 25 06:40:27 PM PDT 24 |
Jul 25 06:40:30 PM PDT 24 |
300914810 ps |
| T1003 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.945153916 |
|
|
Jul 25 06:40:19 PM PDT 24 |
Jul 25 06:40:20 PM PDT 24 |
33854392 ps |
| T130 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.31963023 |
|
|
Jul 25 06:40:34 PM PDT 24 |
Jul 25 06:40:37 PM PDT 24 |
328310120 ps |
| T1004 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4235986844 |
|
|
Jul 25 06:40:06 PM PDT 24 |
Jul 25 06:40:10 PM PDT 24 |
42429715 ps |
| T101 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1458286693 |
|
|
Jul 25 06:40:33 PM PDT 24 |
Jul 25 06:40:34 PM PDT 24 |
14772037 ps |