SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.99 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.62 |
T1005 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2035611031 | Jul 25 06:40:34 PM PDT 24 | Jul 25 06:40:38 PM PDT 24 | 365076425 ps | ||
T102 | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2999300125 | Jul 25 06:40:35 PM PDT 24 | Jul 25 06:41:02 PM PDT 24 | 6078752552 ps | ||
T1006 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2825672459 | Jul 25 06:40:11 PM PDT 24 | Jul 25 06:40:11 PM PDT 24 | 12208588 ps | ||
T1007 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2522974000 | Jul 25 06:40:07 PM PDT 24 | Jul 25 06:40:09 PM PDT 24 | 67365805 ps | ||
T1008 | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2580751739 | Jul 25 06:40:16 PM PDT 24 | Jul 25 06:40:44 PM PDT 24 | 7667430612 ps | ||
T1009 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4132411232 | Jul 25 06:40:19 PM PDT 24 | Jul 25 06:40:20 PM PDT 24 | 12944892 ps | ||
T1010 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2054552507 | Jul 25 06:40:40 PM PDT 24 | Jul 25 06:40:43 PM PDT 24 | 37427491 ps | ||
T1011 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1952980410 | Jul 25 06:40:35 PM PDT 24 | Jul 25 06:40:36 PM PDT 24 | 15961296 ps | ||
T1012 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2874297038 | Jul 25 06:40:12 PM PDT 24 | Jul 25 06:40:13 PM PDT 24 | 16366881 ps | ||
T1013 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2377985655 | Jul 25 06:40:28 PM PDT 24 | Jul 25 06:40:30 PM PDT 24 | 181217800 ps | ||
T1014 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2585187059 | Jul 25 06:40:14 PM PDT 24 | Jul 25 06:40:15 PM PDT 24 | 25056025 ps | ||
T1015 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3783853498 | Jul 25 06:40:35 PM PDT 24 | Jul 25 06:40:40 PM PDT 24 | 519069093 ps | ||
T1016 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2416045180 | Jul 25 06:40:10 PM PDT 24 | Jul 25 06:40:12 PM PDT 24 | 319553337 ps | ||
T1017 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.877729376 | Jul 25 06:41:25 PM PDT 24 | Jul 25 06:41:26 PM PDT 24 | 58057622 ps | ||
T1018 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2071309142 | Jul 25 06:40:06 PM PDT 24 | Jul 25 06:40:10 PM PDT 24 | 366250360 ps | ||
T131 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2164038450 | Jul 25 06:40:41 PM PDT 24 | Jul 25 06:40:44 PM PDT 24 | 177527922 ps | ||
T1019 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1806579491 | Jul 25 06:40:11 PM PDT 24 | Jul 25 06:40:13 PM PDT 24 | 124208881 ps | ||
T1020 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1858249134 | Jul 25 06:40:35 PM PDT 24 | Jul 25 06:40:38 PM PDT 24 | 282296413 ps | ||
T1021 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2729882688 | Jul 25 06:40:28 PM PDT 24 | Jul 25 06:40:29 PM PDT 24 | 124877874 ps | ||
T1022 | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3013914292 | Jul 25 06:40:06 PM PDT 24 | Jul 25 06:40:07 PM PDT 24 | 18038681 ps | ||
T1023 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2934646450 | Jul 25 06:40:35 PM PDT 24 | Jul 25 06:40:38 PM PDT 24 | 1047899778 ps | ||
T1024 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1829397244 | Jul 25 06:40:43 PM PDT 24 | Jul 25 06:40:47 PM PDT 24 | 354765096 ps | ||
T1025 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3716653510 | Jul 25 06:40:40 PM PDT 24 | Jul 25 06:40:41 PM PDT 24 | 460354177 ps | ||
T1026 | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3469985351 | Jul 25 06:40:33 PM PDT 24 | Jul 25 06:40:34 PM PDT 24 | 50345139 ps | ||
T1027 | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2748883404 | Jul 25 06:40:28 PM PDT 24 | Jul 25 06:40:30 PM PDT 24 | 21655038 ps | ||
T132 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2202520112 | Jul 25 06:40:10 PM PDT 24 | Jul 25 06:40:13 PM PDT 24 | 1896820288 ps | ||
T1028 | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.280091451 | Jul 25 06:40:26 PM PDT 24 | Jul 25 06:40:27 PM PDT 24 | 26168852 ps | ||
T1029 | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1984478281 | Jul 25 06:40:04 PM PDT 24 | Jul 25 06:41:02 PM PDT 24 | 26108710136 ps | ||
T1030 | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.651297827 | Jul 25 06:40:14 PM PDT 24 | Jul 25 06:40:15 PM PDT 24 | 17045685 ps | ||
T1031 | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1540286429 | Jul 25 06:40:29 PM PDT 24 | Jul 25 06:41:34 PM PDT 24 | 35284423781 ps | ||
T133 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.345046305 | Jul 25 06:40:20 PM PDT 24 | Jul 25 06:40:22 PM PDT 24 | 78005629 ps | ||
T1032 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2976521416 | Jul 25 06:41:14 PM PDT 24 | Jul 25 06:41:42 PM PDT 24 | 3870442771 ps | ||
T1033 | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1143279754 | Jul 25 06:40:20 PM PDT 24 | Jul 25 06:40:21 PM PDT 24 | 40585695 ps | ||
T1034 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2604904549 | Jul 25 06:40:25 PM PDT 24 | Jul 25 06:40:30 PM PDT 24 | 1565295356 ps | ||
T1035 | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1819323725 | Jul 25 06:41:14 PM PDT 24 | Jul 25 06:42:02 PM PDT 24 | 14369953075 ps |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.1962519842 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 11993993451 ps |
CPU time | 65.97 seconds |
Started | Jul 25 06:49:37 PM PDT 24 |
Finished | Jul 25 06:50:43 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-c1e3c15e-df83-4bc4-b8c6-30387dd538c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962519842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.1962519842 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.1869637937 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 2999354194 ps |
CPU time | 83.74 seconds |
Started | Jul 25 06:50:35 PM PDT 24 |
Finished | Jul 25 06:51:59 PM PDT 24 |
Peak memory | 219576 kb |
Host | smart-02b0c7a2-7ec0-434d-a96f-c7a39725eb52 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869637937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.1869637937 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3639553272 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 2297028012 ps |
CPU time | 9.95 seconds |
Started | Jul 25 06:46:46 PM PDT 24 |
Finished | Jul 25 06:46:56 PM PDT 24 |
Peak memory | 211468 kb |
Host | smart-eb1a5faa-f23d-4161-b550-899477deec53 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3639553272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3639553272 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.3475584276 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 61498649088 ps |
CPU time | 993 seconds |
Started | Jul 25 06:48:32 PM PDT 24 |
Finished | Jul 25 07:05:05 PM PDT 24 |
Peak memory | 380100 kb |
Host | smart-2ea6c558-fc33-4da9-aa2d-6cd77b532154 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475584276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3475584276 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.810826198 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 282618024 ps |
CPU time | 2.73 seconds |
Started | Jul 25 06:40:44 PM PDT 24 |
Finished | Jul 25 06:40:47 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-88b5e905-a029-4e88-8394-507b55e8ac6e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810826198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.sram_ctrl_tl_intg_err.810826198 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.1435994997 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 1232183919 ps |
CPU time | 3.35 seconds |
Started | Jul 25 06:45:28 PM PDT 24 |
Finished | Jul 25 06:45:31 PM PDT 24 |
Peak memory | 222260 kb |
Host | smart-a78caaa8-e908-41a5-b767-ed047b74d31a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435994997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1435994997 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.688075466 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 29070223515 ps |
CPU time | 170.49 seconds |
Started | Jul 25 06:46:01 PM PDT 24 |
Finished | Jul 25 06:48:52 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-40911365-ee9b-436b-952f-34ab2214260f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688075466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 3.sram_ctrl_partial_access_b2b.688075466 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.2979677780 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 1049935360406 ps |
CPU time | 7861.57 seconds |
Started | Jul 25 06:50:19 PM PDT 24 |
Finished | Jul 25 09:01:21 PM PDT 24 |
Peak memory | 381184 kb |
Host | smart-ade72341-0dc0-437f-959e-649d7bfaf117 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979677780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.2979677780 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.986984579 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 17515523 ps |
CPU time | 0.69 seconds |
Started | Jul 25 06:40:27 PM PDT 24 |
Finished | Jul 25 06:40:28 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-162f58a0-1ce5-4bc7-90b3-607613a189c0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986984579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_csr_rw.986984579 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.336615777 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 370179501 ps |
CPU time | 11.63 seconds |
Started | Jul 25 06:51:53 PM PDT 24 |
Finished | Jul 25 06:52:05 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-023ca4c6-30ba-4bc8-a784-70f6a3196812 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=336615777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.336615777 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.698457087 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 22578444777 ps |
CPU time | 1673.15 seconds |
Started | Jul 25 06:47:55 PM PDT 24 |
Finished | Jul 25 07:15:48 PM PDT 24 |
Peak memory | 383416 kb |
Host | smart-90f99e06-6fb2-4a89-b8c5-412904f41c6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698457087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_stress_all.698457087 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.3191193253 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 706946759 ps |
CPU time | 3.4 seconds |
Started | Jul 25 06:45:19 PM PDT 24 |
Finished | Jul 25 06:45:22 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-c12c4f18-eed0-4346-b132-782006c12691 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191193253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3191193253 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1199297840 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 5802729605 ps |
CPU time | 49.36 seconds |
Started | Jul 25 06:48:27 PM PDT 24 |
Finished | Jul 25 06:49:17 PM PDT 24 |
Peak memory | 212548 kb |
Host | smart-6c33d395-082a-48b4-8685-f799a72a88d9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1199297840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1199297840 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2838380477 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 426667188 ps |
CPU time | 2.44 seconds |
Started | Jul 25 06:40:19 PM PDT 24 |
Finished | Jul 25 06:40:22 PM PDT 24 |
Peak memory | 211232 kb |
Host | smart-73fc3d9f-fe71-43cc-84bc-aa42fc2b714e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838380477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.2838380477 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.2711937739 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 148164145 ps |
CPU time | 0.68 seconds |
Started | Jul 25 06:47:47 PM PDT 24 |
Finished | Jul 25 06:47:48 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-e02199d6-84ba-43aa-b2b3-06106e6c9b66 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711937739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2711937739 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2168105722 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 465962006 ps |
CPU time | 2.24 seconds |
Started | Jul 25 06:40:27 PM PDT 24 |
Finished | Jul 25 06:40:29 PM PDT 24 |
Peak memory | 211244 kb |
Host | smart-a6a703b8-5efc-4a66-810b-690cf1d9286f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168105722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.2168105722 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2768950887 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 17384813034 ps |
CPU time | 366.04 seconds |
Started | Jul 25 06:47:14 PM PDT 24 |
Finished | Jul 25 06:53:20 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-b3d78ce0-6c15-4734-80ca-57b0bcf22e1c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768950887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.2768950887 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.3367240557 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 4033155463 ps |
CPU time | 931.78 seconds |
Started | Jul 25 06:52:30 PM PDT 24 |
Finished | Jul 25 07:08:02 PM PDT 24 |
Peak memory | 377828 kb |
Host | smart-9a31df1d-c903-4137-8677-4db464eb18e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367240557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3367240557 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1746226537 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 50438921597 ps |
CPU time | 59.84 seconds |
Started | Jul 25 06:40:34 PM PDT 24 |
Finished | Jul 25 06:41:34 PM PDT 24 |
Peak memory | 203348 kb |
Host | smart-54c77307-959e-43bd-b3e6-b04d2a385aba |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746226537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1746226537 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1107578106 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 224338789 ps |
CPU time | 1.73 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:40:37 PM PDT 24 |
Peak memory | 211264 kb |
Host | smart-caf10895-dba2-4869-805b-42be8dc6e20e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107578106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.1107578106 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1923350804 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 193314673 ps |
CPU time | 2.35 seconds |
Started | Jul 25 06:40:20 PM PDT 24 |
Finished | Jul 25 06:40:22 PM PDT 24 |
Peak memory | 211248 kb |
Host | smart-34157204-9344-427b-8dfa-c3b9de32118c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923350804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1923350804 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1015752633 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 16947261 ps |
CPU time | 0.71 seconds |
Started | Jul 25 06:40:07 PM PDT 24 |
Finished | Jul 25 06:40:08 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-3dba519d-ba5f-44a9-8888-da95de723715 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015752633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.1015752633 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3179391264 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 27816657 ps |
CPU time | 1.21 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:08 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-cc97a150-1477-44aa-a8e5-b438612f06a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179391264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.3179391264 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2247132222 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 14442297 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:40:08 PM PDT 24 |
Finished | Jul 25 06:40:09 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-f839c143-bf9d-4382-8bf6-3e7ce6f5626d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247132222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.2247132222 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1458430136 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 365355731 ps |
CPU time | 4.11 seconds |
Started | Jul 25 06:40:05 PM PDT 24 |
Finished | Jul 25 06:40:09 PM PDT 24 |
Peak memory | 211244 kb |
Host | smart-cf609850-f13c-4f13-8014-171014b1de29 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458430136 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1458430136 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3347189401 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 73802947 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:40:08 PM PDT 24 |
Finished | Jul 25 06:40:09 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-2262c3c0-a111-40c1-a84d-0994b7feef33 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347189401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.3347189401 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1135099262 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 7074433259 ps |
CPU time | 52.41 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:59 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-8555ff97-df22-4f48-b08c-fad442f7bd77 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135099262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1135099262 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2438016700 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 48376607 ps |
CPU time | 0.8 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:06 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-9859c31e-d632-4984-b028-dcfd4c59bf36 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438016700 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2438016700 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1840427756 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 172581105 ps |
CPU time | 2.72 seconds |
Started | Jul 25 06:40:04 PM PDT 24 |
Finished | Jul 25 06:40:07 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-89eb5271-90e2-4dee-bfc9-e9fdb6dbf4fd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840427756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.1840427756 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3980826066 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 861064067 ps |
CPU time | 1.62 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:07 PM PDT 24 |
Peak memory | 211268 kb |
Host | smart-392428cd-3021-4595-9c1f-db4b62cc6824 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980826066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.3980826066 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.222217238 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 51513778 ps |
CPU time | 0.7 seconds |
Started | Jul 25 06:40:05 PM PDT 24 |
Finished | Jul 25 06:40:06 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-6b4e51a4-056d-4fc3-b5ab-091c06734819 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222217238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_aliasing.222217238 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3601024369 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 90142685 ps |
CPU time | 1.96 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:08 PM PDT 24 |
Peak memory | 203004 kb |
Host | smart-780ae5f1-f3fa-4489-b455-a111ec09456c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601024369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.3601024369 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2605610077 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 21080707 ps |
CPU time | 0.7 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:07 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-04639b45-661f-4682-908e-5bf96e480de9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605610077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2605610077 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2071309142 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 366250360 ps |
CPU time | 4.67 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:10 PM PDT 24 |
Peak memory | 211192 kb |
Host | smart-6aaf4df9-dd4d-49d4-b2b3-fb8164ec5188 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071309142 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2071309142 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1554412819 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 20439767 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:07 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-0206e245-62e4-41c2-a31e-5ac052412f7c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554412819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.1554412819 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1984478281 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 26108710136 ps |
CPU time | 57.14 seconds |
Started | Jul 25 06:40:04 PM PDT 24 |
Finished | Jul 25 06:41:02 PM PDT 24 |
Peak memory | 203352 kb |
Host | smart-1c211aec-dec3-46bc-a555-1ec67646d0a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984478281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1984478281 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3013914292 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 18038681 ps |
CPU time | 0.74 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:07 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-bc5548ec-c443-49d3-a8f0-0795f8db8800 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013914292 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3013914292 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2522974000 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 67365805 ps |
CPU time | 2.05 seconds |
Started | Jul 25 06:40:07 PM PDT 24 |
Finished | Jul 25 06:40:09 PM PDT 24 |
Peak memory | 211288 kb |
Host | smart-9cd89b15-397f-4d3d-af6a-9ce8a4471fb6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522974000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2522974000 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2416045180 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 319553337 ps |
CPU time | 1.56 seconds |
Started | Jul 25 06:40:10 PM PDT 24 |
Finished | Jul 25 06:40:12 PM PDT 24 |
Peak memory | 211256 kb |
Host | smart-746fdc2b-382c-4482-bea1-cbdb6507f8b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416045180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.2416045180 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2731763360 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 373087008 ps |
CPU time | 3.97 seconds |
Started | Jul 25 06:40:28 PM PDT 24 |
Finished | Jul 25 06:40:32 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-dd12ec7f-875f-4fe0-88c1-eff37bd855c3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731763360 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2731763360 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3350987473 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 16461523 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:40:26 PM PDT 24 |
Finished | Jul 25 06:40:27 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-59911eff-af08-4e46-9026-5c3fb81cc9a5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350987473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.3350987473 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.411018957 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 11215236625 ps |
CPU time | 27.84 seconds |
Started | Jul 25 06:40:27 PM PDT 24 |
Finished | Jul 25 06:40:55 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-291bc438-2e7e-4440-888a-a1918772bf60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411018957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.411018957 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.280091451 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 26168852 ps |
CPU time | 0.78 seconds |
Started | Jul 25 06:40:26 PM PDT 24 |
Finished | Jul 25 06:40:27 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-5d8ea451-f9da-46d5-97aa-c90fcdfbd968 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280091451 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.280091451 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3313649290 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 28197393 ps |
CPU time | 2.28 seconds |
Started | Jul 25 06:40:28 PM PDT 24 |
Finished | Jul 25 06:40:31 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-44629dbe-be94-4c39-af19-ab95982e97ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313649290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.3313649290 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2193779826 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 865806022 ps |
CPU time | 3.71 seconds |
Started | Jul 25 06:40:28 PM PDT 24 |
Finished | Jul 25 06:40:32 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-5de11595-9ff6-483b-9fee-59c1f6de9993 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193779826 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2193779826 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1347198017 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 42757420 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:40:28 PM PDT 24 |
Finished | Jul 25 06:40:29 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-042427f8-5c3c-4498-9375-0ef61a62117d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347198017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.1347198017 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3801741878 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 3722022006 ps |
CPU time | 27.12 seconds |
Started | Jul 25 06:40:27 PM PDT 24 |
Finished | Jul 25 06:40:54 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-95862a44-336b-4588-9de6-7013a642320e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801741878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.3801741878 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2748883404 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 21655038 ps |
CPU time | 0.81 seconds |
Started | Jul 25 06:40:28 PM PDT 24 |
Finished | Jul 25 06:40:30 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-88d640e0-00a9-445d-99e1-4a024f9d8b37 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748883404 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2748883404 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2347254193 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 1154632177 ps |
CPU time | 4.62 seconds |
Started | Jul 25 06:40:28 PM PDT 24 |
Finished | Jul 25 06:40:33 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-3ba7506a-5638-479f-9cfc-96646dc1d294 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347254193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.2347254193 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2729882688 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 124877874 ps |
CPU time | 1.5 seconds |
Started | Jul 25 06:40:28 PM PDT 24 |
Finished | Jul 25 06:40:29 PM PDT 24 |
Peak memory | 211276 kb |
Host | smart-2ed43cfe-361f-422a-b3f8-2b74217455f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729882688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.2729882688 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.133830553 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 3821001145 ps |
CPU time | 4.01 seconds |
Started | Jul 25 06:40:34 PM PDT 24 |
Finished | Jul 25 06:40:38 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-755d9523-1f7c-4cba-a5dd-7d72c5263d85 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133830553 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.133830553 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1540286429 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 35284423781 ps |
CPU time | 65.15 seconds |
Started | Jul 25 06:40:29 PM PDT 24 |
Finished | Jul 25 06:41:34 PM PDT 24 |
Peak memory | 203292 kb |
Host | smart-0ec9d25b-ebe2-4d83-ba60-0e3f0d5d0f27 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540286429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1540286429 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1787610203 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 31180960 ps |
CPU time | 0.72 seconds |
Started | Jul 25 06:40:34 PM PDT 24 |
Finished | Jul 25 06:40:35 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-5c4b8376-c384-4c7c-b33e-0782296e1972 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787610203 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1787610203 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2483331533 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 38630847 ps |
CPU time | 3.4 seconds |
Started | Jul 25 06:40:26 PM PDT 24 |
Finished | Jul 25 06:40:29 PM PDT 24 |
Peak memory | 203052 kb |
Host | smart-256be4f0-1fe1-45d1-916d-5a2fee8e966d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483331533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.2483331533 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2377985655 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 181217800 ps |
CPU time | 1.62 seconds |
Started | Jul 25 06:40:28 PM PDT 24 |
Finished | Jul 25 06:40:30 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-f90ef078-0775-46ad-b1af-4100f1d58d14 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377985655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.2377985655 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2713524822 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 4211776542 ps |
CPU time | 4.04 seconds |
Started | Jul 25 06:40:33 PM PDT 24 |
Finished | Jul 25 06:40:37 PM PDT 24 |
Peak memory | 211188 kb |
Host | smart-e7413194-68fb-440a-9441-8a91b5640ea8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713524822 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2713524822 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1769866669 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 12516790 ps |
CPU time | 0.68 seconds |
Started | Jul 25 06:40:33 PM PDT 24 |
Finished | Jul 25 06:40:34 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-2e4c8cae-3983-4fd6-9fa7-369a642e8404 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769866669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.1769866669 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4103102773 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 14773750047 ps |
CPU time | 27.02 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:41:02 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-72a69feb-0bc2-49ba-9eb2-74adf8b730de |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103102773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.4103102773 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3469985351 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 50345139 ps |
CPU time | 0.83 seconds |
Started | Jul 25 06:40:33 PM PDT 24 |
Finished | Jul 25 06:40:34 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-fd8785a6-cd80-4606-b968-9058aef90c8f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469985351 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3469985351 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3783853498 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 519069093 ps |
CPU time | 4.3 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:40:40 PM PDT 24 |
Peak memory | 212624 kb |
Host | smart-e5abda0d-207f-45db-8f6e-95a68720cf77 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783853498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3783853498 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2020701846 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 1583053105 ps |
CPU time | 4.12 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:40:39 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-609b1a2a-f013-4bff-b64b-2f79b380b675 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020701846 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2020701846 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4240683404 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 14906545 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:40:40 PM PDT 24 |
Finished | Jul 25 06:40:41 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-794e4b5a-831e-45d2-a48d-c29e6ac39b22 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240683404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.4240683404 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2999300125 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 6078752552 ps |
CPU time | 26.99 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:41:02 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-bcfc115a-bc73-4a35-a2ac-254c11f5097e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999300125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2999300125 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1704601159 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 101863405 ps |
CPU time | 0.83 seconds |
Started | Jul 25 06:40:33 PM PDT 24 |
Finished | Jul 25 06:40:34 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-d14c009d-8230-4e29-a8fc-52c65dce341e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704601159 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1704601159 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3031632443 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 99412041 ps |
CPU time | 3.6 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:40:39 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-d8a5fa45-f0cc-4ce7-a81b-8bf2afc39f23 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031632443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3031632443 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1657016467 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 1388348726 ps |
CPU time | 1.92 seconds |
Started | Jul 25 06:40:34 PM PDT 24 |
Finished | Jul 25 06:40:36 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-bf568dfa-089c-4458-9fe8-8647ac569dff |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657016467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.1657016467 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2035611031 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 365076425 ps |
CPU time | 3.22 seconds |
Started | Jul 25 06:40:34 PM PDT 24 |
Finished | Jul 25 06:40:38 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-9f8db91f-6093-4968-8511-eff431710402 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035611031 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2035611031 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1458286693 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 14772037 ps |
CPU time | 0.7 seconds |
Started | Jul 25 06:40:33 PM PDT 24 |
Finished | Jul 25 06:40:34 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-51846cb5-f573-4d14-a7bf-d1be20d29beb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458286693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.1458286693 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2702783806 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 93559477 ps |
CPU time | 0.74 seconds |
Started | Jul 25 06:40:34 PM PDT 24 |
Finished | Jul 25 06:40:35 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-131f958e-6581-439b-83ed-8f0020b66578 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702783806 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2702783806 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2054552507 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 37427491 ps |
CPU time | 3.09 seconds |
Started | Jul 25 06:40:40 PM PDT 24 |
Finished | Jul 25 06:40:43 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-01b3d3fa-d97b-4ede-951d-af92ee2dc7f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054552507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.2054552507 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.31963023 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 328310120 ps |
CPU time | 2.23 seconds |
Started | Jul 25 06:40:34 PM PDT 24 |
Finished | Jul 25 06:40:37 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-a7bda252-a39a-474c-82ca-5a7bf4583730 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31963023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 15.sram_ctrl_tl_intg_err.31963023 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1535986878 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 367863351 ps |
CPU time | 3.93 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:40:39 PM PDT 24 |
Peak memory | 211244 kb |
Host | smart-c5a4d67d-3668-4a5b-8a6f-628aa004399f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535986878 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1535986878 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1952980410 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 15961296 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:40:36 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-415f7cb4-f6aa-417e-8f1d-3fd84250d6a1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952980410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.1952980410 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1783958135 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 13701414596 ps |
CPU time | 31.94 seconds |
Started | Jul 25 06:40:34 PM PDT 24 |
Finished | Jul 25 06:41:06 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-8ebbeecc-cd6d-4e1e-b29b-47ed05846b44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783958135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1783958135 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2289786280 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 40159828 ps |
CPU time | 0.74 seconds |
Started | Jul 25 06:40:36 PM PDT 24 |
Finished | Jul 25 06:40:36 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-3ac49fa2-73cd-4c7d-acad-9e91c2a7418b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289786280 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2289786280 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3481202622 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 99826940 ps |
CPU time | 2.08 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:40:37 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-fbe0a5fe-56f1-4e2e-a601-cd14e8690908 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481202622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.3481202622 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2934646450 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 1047899778 ps |
CPU time | 2.35 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:40:38 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-8edf887d-0019-45e0-8612-acf998ecbbb6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934646450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.2934646450 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2184711225 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 374298053 ps |
CPU time | 3.66 seconds |
Started | Jul 25 06:40:43 PM PDT 24 |
Finished | Jul 25 06:40:47 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-e4f0827e-dc5d-46b4-b0f9-dfe58b8a86ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184711225 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.2184711225 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1133381011 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 83742344 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:40:41 PM PDT 24 |
Finished | Jul 25 06:40:42 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-2d9bc3a2-b814-43f4-b75f-bc4fa499f84f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133381011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.1133381011 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.672757515 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 14834153887 ps |
CPU time | 29.2 seconds |
Started | Jul 25 06:40:36 PM PDT 24 |
Finished | Jul 25 06:41:05 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-194f5b48-b54f-45de-9f16-430fb6d9bd5b |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672757515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.672757515 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4118107468 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 69257706 ps |
CPU time | 0.71 seconds |
Started | Jul 25 06:40:41 PM PDT 24 |
Finished | Jul 25 06:40:42 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-f7f81390-0b48-4ef6-92fc-407ca1ec45d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118107468 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.4118107468 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1858249134 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 282296413 ps |
CPU time | 3.51 seconds |
Started | Jul 25 06:40:35 PM PDT 24 |
Finished | Jul 25 06:40:38 PM PDT 24 |
Peak memory | 211196 kb |
Host | smart-d74d7c20-96dc-40c2-a33b-6016c59bd220 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858249134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.1858249134 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3716653510 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 460354177 ps |
CPU time | 1.64 seconds |
Started | Jul 25 06:40:40 PM PDT 24 |
Finished | Jul 25 06:40:41 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-19d36b0b-f1dc-4d92-a115-e515e8a1304b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716653510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.3716653510 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2514917088 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 412448086 ps |
CPU time | 4.25 seconds |
Started | Jul 25 06:40:42 PM PDT 24 |
Finished | Jul 25 06:40:47 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-d5a438ed-2f90-436d-ba3e-97e06e44140a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514917088 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2514917088 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3398462027 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 64741906 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:40:43 PM PDT 24 |
Finished | Jul 25 06:40:44 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-39378958-63ed-45dc-ad3c-3525f09fd4f5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398462027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.3398462027 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1005002762 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 74067629118 ps |
CPU time | 33.64 seconds |
Started | Jul 25 06:40:43 PM PDT 24 |
Finished | Jul 25 06:41:17 PM PDT 24 |
Peak memory | 203352 kb |
Host | smart-614579d3-6a7c-4496-9b78-ebb802e37e1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005002762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1005002762 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2774932445 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 192860543 ps |
CPU time | 0.76 seconds |
Started | Jul 25 06:40:43 PM PDT 24 |
Finished | Jul 25 06:40:44 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-0624d69d-a93c-4c67-85cc-ed44db80a4a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774932445 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.2774932445 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.889305656 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 21226992 ps |
CPU time | 1.93 seconds |
Started | Jul 25 06:40:42 PM PDT 24 |
Finished | Jul 25 06:40:44 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-2c92e929-69d8-417b-b4af-98515748905f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889305656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.889305656 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2164038450 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 177527922 ps |
CPU time | 2.42 seconds |
Started | Jul 25 06:40:41 PM PDT 24 |
Finished | Jul 25 06:40:44 PM PDT 24 |
Peak memory | 211224 kb |
Host | smart-4f8d552d-13cd-4fb4-97d5-4a5a4d7bbba1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164038450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.2164038450 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1829397244 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 354765096 ps |
CPU time | 3.59 seconds |
Started | Jul 25 06:40:43 PM PDT 24 |
Finished | Jul 25 06:40:47 PM PDT 24 |
Peak memory | 211236 kb |
Host | smart-905d3993-8ce5-4b1d-9c45-0d14cbd2d9a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829397244 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1829397244 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4238075184 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 14258373 ps |
CPU time | 0.69 seconds |
Started | Jul 25 06:40:42 PM PDT 24 |
Finished | Jul 25 06:40:43 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-e4bef2c1-7aca-4592-a94a-777b3ad1d92e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238075184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.4238075184 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1421692379 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 5671711113 ps |
CPU time | 27.54 seconds |
Started | Jul 25 06:40:43 PM PDT 24 |
Finished | Jul 25 06:41:10 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-bbe0e253-82db-4c6f-bfac-2d5ae24cd8ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421692379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1421692379 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.929535293 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 37197696 ps |
CPU time | 0.7 seconds |
Started | Jul 25 06:40:42 PM PDT 24 |
Finished | Jul 25 06:40:43 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-b147ac03-09ce-4539-8442-ad330e9f49ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929535293 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.929535293 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2171260739 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 110147647 ps |
CPU time | 4.5 seconds |
Started | Jul 25 06:40:43 PM PDT 24 |
Finished | Jul 25 06:40:48 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-bfbde282-a1cd-459b-978a-fc6a045d7198 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171260739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.2171260739 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.877729376 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 58057622 ps |
CPU time | 0.69 seconds |
Started | Jul 25 06:41:25 PM PDT 24 |
Finished | Jul 25 06:41:26 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-31a166e5-24c7-4a7e-a1c1-4fb065a90d5d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877729376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_aliasing.877729376 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.381871975 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 191267640 ps |
CPU time | 1.78 seconds |
Started | Jul 25 06:41:14 PM PDT 24 |
Finished | Jul 25 06:41:16 PM PDT 24 |
Peak memory | 200992 kb |
Host | smart-8caf8e4f-4646-47d6-9331-edeed6aca15d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381871975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.381871975 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3793243783 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 18351354 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:40:07 PM PDT 24 |
Finished | Jul 25 06:40:08 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-d5ee1269-b965-4510-ab59-84cf4961cec9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793243783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.3793243783 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1069847827 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 1430106444 ps |
CPU time | 3.65 seconds |
Started | Jul 25 06:40:11 PM PDT 24 |
Finished | Jul 25 06:40:15 PM PDT 24 |
Peak memory | 211212 kb |
Host | smart-4755cfde-bf6b-4e07-834f-bcd5465a60db |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069847827 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1069847827 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.459453228 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 11148044 ps |
CPU time | 0.63 seconds |
Started | Jul 25 06:40:07 PM PDT 24 |
Finished | Jul 25 06:40:08 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-e318846d-0df3-4704-b106-3ca81089ba8e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459453228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_csr_rw.459453228 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3544512570 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 15376971690 ps |
CPU time | 27.9 seconds |
Started | Jul 25 06:40:04 PM PDT 24 |
Finished | Jul 25 06:40:32 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-4667b100-720d-49b4-b24f-cf6718d28777 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544512570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3544512570 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1222739018 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 20636315 ps |
CPU time | 0.78 seconds |
Started | Jul 25 06:40:13 PM PDT 24 |
Finished | Jul 25 06:40:14 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-d37d1bf5-2d2f-4caa-9804-5ff9608b3e0c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222739018 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1222739018 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4235986844 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 42429715 ps |
CPU time | 3.94 seconds |
Started | Jul 25 06:40:06 PM PDT 24 |
Finished | Jul 25 06:40:10 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-408face9-6664-44ff-8c2a-2f623316dcdd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235986844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.4235986844 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2202520112 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 1896820288 ps |
CPU time | 2.97 seconds |
Started | Jul 25 06:40:10 PM PDT 24 |
Finished | Jul 25 06:40:13 PM PDT 24 |
Peak memory | 211300 kb |
Host | smart-8f5a5a2c-a9a7-47af-a4ec-1c5998e856a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202520112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.2202520112 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1837471241 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 22064565 ps |
CPU time | 0.73 seconds |
Started | Jul 25 06:40:12 PM PDT 24 |
Finished | Jul 25 06:40:13 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-74fa42f1-1b89-47aa-a010-dc65c280c7f2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837471241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.1837471241 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1806579491 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 124208881 ps |
CPU time | 2.27 seconds |
Started | Jul 25 06:40:11 PM PDT 24 |
Finished | Jul 25 06:40:13 PM PDT 24 |
Peak memory | 203008 kb |
Host | smart-81767f76-0b7c-4c95-9abc-9d5a578e0d21 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806579491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.1806579491 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2585187059 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 25056025 ps |
CPU time | 0.7 seconds |
Started | Jul 25 06:40:14 PM PDT 24 |
Finished | Jul 25 06:40:15 PM PDT 24 |
Peak memory | 202120 kb |
Host | smart-074fd11d-db71-484c-9b98-094a8ecf5e72 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585187059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.2585187059 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1100676445 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 1428115114 ps |
CPU time | 3.91 seconds |
Started | Jul 25 06:41:14 PM PDT 24 |
Finished | Jul 25 06:41:19 PM PDT 24 |
Peak memory | 208832 kb |
Host | smart-6e559a17-878a-45d7-8116-ba4bf6edb15d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100676445 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.1100676445 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2645877541 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 17163861 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:40:18 PM PDT 24 |
Finished | Jul 25 06:40:18 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-4d1e801d-c17e-411e-b385-1fa3dc1addca |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645877541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.2645877541 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2976521416 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 3870442771 ps |
CPU time | 27.55 seconds |
Started | Jul 25 06:41:14 PM PDT 24 |
Finished | Jul 25 06:41:42 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-17441320-1b02-423d-9c2b-4ed31ff71568 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976521416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2976521416 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.651297827 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 17045685 ps |
CPU time | 0.78 seconds |
Started | Jul 25 06:40:14 PM PDT 24 |
Finished | Jul 25 06:40:15 PM PDT 24 |
Peak memory | 202228 kb |
Host | smart-5d543dbb-fd0d-4f82-b692-2cdcc0c75a52 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651297827 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.651297827 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3943397453 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 121804842 ps |
CPU time | 4.21 seconds |
Started | Jul 25 06:40:12 PM PDT 24 |
Finished | Jul 25 06:40:16 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-bbc69242-78c3-48e5-9c9e-f18731b94875 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943397453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.3943397453 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.911359716 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 669566680 ps |
CPU time | 2.14 seconds |
Started | Jul 25 06:40:13 PM PDT 24 |
Finished | Jul 25 06:40:16 PM PDT 24 |
Peak memory | 211280 kb |
Host | smart-1a66e3ea-789c-47ec-9072-f4f0048fbeec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911359716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.sram_ctrl_tl_intg_err.911359716 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1328956970 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 33302915 ps |
CPU time | 0.75 seconds |
Started | Jul 25 06:40:12 PM PDT 24 |
Finished | Jul 25 06:40:13 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-19ad32de-0a19-4e5d-b7f1-e86577cffe9c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328956970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.1328956970 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1084810945 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 393344559 ps |
CPU time | 1.49 seconds |
Started | Jul 25 06:40:13 PM PDT 24 |
Finished | Jul 25 06:40:14 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-b647b029-a0d7-42d8-8cda-63c337237dac |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084810945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.1084810945 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2874297038 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 16366881 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:40:12 PM PDT 24 |
Finished | Jul 25 06:40:13 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-e28ebb76-f316-4f9f-88d6-e027bd451252 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874297038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.2874297038 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2569999989 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 1366537070 ps |
CPU time | 3.97 seconds |
Started | Jul 25 06:40:11 PM PDT 24 |
Finished | Jul 25 06:40:15 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-880ad36b-6696-4c84-a05f-717caca30d0b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569999989 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2569999989 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2825672459 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 12208588 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:40:11 PM PDT 24 |
Finished | Jul 25 06:40:11 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-8e889281-a960-45bf-8339-478fe2a74028 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825672459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.2825672459 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1819323725 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 14369953075 ps |
CPU time | 47.35 seconds |
Started | Jul 25 06:41:14 PM PDT 24 |
Finished | Jul 25 06:42:02 PM PDT 24 |
Peak memory | 201040 kb |
Host | smart-0ba70261-1da9-44d1-99f5-1d7958a1aaec |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819323725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1819323725 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2097978368 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 82692858 ps |
CPU time | 0.81 seconds |
Started | Jul 25 06:40:14 PM PDT 24 |
Finished | Jul 25 06:40:15 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-229b7360-4535-48f3-986f-eeeb324ce811 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097978368 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2097978368 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1105131604 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 161660986 ps |
CPU time | 4.89 seconds |
Started | Jul 25 06:40:12 PM PDT 24 |
Finished | Jul 25 06:40:17 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-51525edb-e81c-419f-ac82-7990a9851279 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105131604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.1105131604 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3273765626 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 1122267141 ps |
CPU time | 2.57 seconds |
Started | Jul 25 06:40:16 PM PDT 24 |
Finished | Jul 25 06:40:18 PM PDT 24 |
Peak memory | 203048 kb |
Host | smart-c7498ff4-b58f-40a3-a863-83799ef646bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273765626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.3273765626 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2604904549 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 1565295356 ps |
CPU time | 4.09 seconds |
Started | Jul 25 06:40:25 PM PDT 24 |
Finished | Jul 25 06:40:30 PM PDT 24 |
Peak memory | 212264 kb |
Host | smart-8708497a-e2b4-4a45-98fb-c906d3e196a6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604904549 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2604904549 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4132411232 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 12944892 ps |
CPU time | 0.71 seconds |
Started | Jul 25 06:40:19 PM PDT 24 |
Finished | Jul 25 06:40:20 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-48c3d65f-db5a-4a94-864f-fa1d784a10b8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132411232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.4132411232 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2580751739 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 7667430612 ps |
CPU time | 27.87 seconds |
Started | Jul 25 06:40:16 PM PDT 24 |
Finished | Jul 25 06:40:44 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-62dd31e9-5adc-4fb0-a573-51d19f2cbf7a |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580751739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.2580751739 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2553492731 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 61896456 ps |
CPU time | 0.73 seconds |
Started | Jul 25 06:40:21 PM PDT 24 |
Finished | Jul 25 06:40:22 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-b1af7aa6-769a-476f-aad9-78cdfeb28b65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553492731 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2553492731 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1052565338 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 816911912 ps |
CPU time | 4.45 seconds |
Started | Jul 25 06:40:12 PM PDT 24 |
Finished | Jul 25 06:40:17 PM PDT 24 |
Peak memory | 211168 kb |
Host | smart-06b30d38-b3a2-49c7-b412-d021b7024c21 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052565338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.1052565338 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.345046305 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 78005629 ps |
CPU time | 1.45 seconds |
Started | Jul 25 06:40:20 PM PDT 24 |
Finished | Jul 25 06:40:22 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-35287a82-83d5-4d9b-8904-dbfb1e8b3109 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345046305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.sram_ctrl_tl_intg_err.345046305 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3995322439 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 4261705428 ps |
CPU time | 3.87 seconds |
Started | Jul 25 06:40:19 PM PDT 24 |
Finished | Jul 25 06:40:23 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-9554fb4f-cf54-4cec-b134-a9bfc64fe34b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995322439 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3995322439 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1629462121 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 52696596 ps |
CPU time | 0.68 seconds |
Started | Jul 25 06:40:20 PM PDT 24 |
Finished | Jul 25 06:40:21 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-00852c97-3ef6-4cb3-9c9f-d474e3b67158 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629462121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.1629462121 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.502859367 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 25182123608 ps |
CPU time | 57.58 seconds |
Started | Jul 25 06:40:19 PM PDT 24 |
Finished | Jul 25 06:41:17 PM PDT 24 |
Peak memory | 203320 kb |
Host | smart-b1e23861-cf60-4700-8319-d4e5b134de8d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502859367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.502859367 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4032940521 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 20350405 ps |
CPU time | 0.74 seconds |
Started | Jul 25 06:40:19 PM PDT 24 |
Finished | Jul 25 06:40:20 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-f71c0edd-cfb9-4159-bd82-f6cd43fb393d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032940521 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.4032940521 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.605479974 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 55977926 ps |
CPU time | 2.13 seconds |
Started | Jul 25 06:40:20 PM PDT 24 |
Finished | Jul 25 06:40:22 PM PDT 24 |
Peak memory | 211304 kb |
Host | smart-25f5426e-b59c-43ad-9cc3-419d5ded2280 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605479974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.605479974 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2154785634 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 1910884550 ps |
CPU time | 3.38 seconds |
Started | Jul 25 06:40:20 PM PDT 24 |
Finished | Jul 25 06:40:24 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-64132461-e194-47d4-90ba-134f90a9f824 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154785634 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2154785634 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.945153916 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 33854392 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:40:19 PM PDT 24 |
Finished | Jul 25 06:40:20 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-68e17204-e2d2-4820-92d0-7a1ca8644e37 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945153916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_csr_rw.945153916 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3373166222 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 29450593310 ps |
CPU time | 53.1 seconds |
Started | Jul 25 06:40:20 PM PDT 24 |
Finished | Jul 25 06:41:13 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-c16efc1f-b057-4044-b4dd-c997cc9c2935 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373166222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3373166222 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3155729551 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 83779672 ps |
CPU time | 0.82 seconds |
Started | Jul 25 06:40:19 PM PDT 24 |
Finished | Jul 25 06:40:20 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-ff3cd844-3c05-4860-aa06-2462c8d0db1f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155729551 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3155729551 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4041346820 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 65509203 ps |
CPU time | 3.55 seconds |
Started | Jul 25 06:40:20 PM PDT 24 |
Finished | Jul 25 06:40:24 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-84c74e21-756f-4cd2-a04c-bef8d8c1e4fd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041346820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.4041346820 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1628294111 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 221427584 ps |
CPU time | 2.57 seconds |
Started | Jul 25 06:40:18 PM PDT 24 |
Finished | Jul 25 06:40:21 PM PDT 24 |
Peak memory | 212404 kb |
Host | smart-c4f37e6c-8782-4409-8916-cae5926df412 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628294111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.1628294111 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3856129044 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 358835679 ps |
CPU time | 3.37 seconds |
Started | Jul 25 06:40:19 PM PDT 24 |
Finished | Jul 25 06:40:22 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-78890876-8f16-483b-a1e4-06af05b2fa43 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856129044 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3856129044 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.764662403 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 46955500 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:40:20 PM PDT 24 |
Finished | Jul 25 06:40:21 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-3e0707b9-f207-499b-b8a8-bd1dd5ee64e0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764662403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_csr_rw.764662403 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.559968475 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 3728200965 ps |
CPU time | 26.97 seconds |
Started | Jul 25 06:40:21 PM PDT 24 |
Finished | Jul 25 06:40:48 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-c9912b15-72e7-4ac7-85a7-b890af69d233 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559968475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.559968475 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1143279754 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 40585695 ps |
CPU time | 0.73 seconds |
Started | Jul 25 06:40:20 PM PDT 24 |
Finished | Jul 25 06:40:21 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-244155d9-83b2-4d4e-baf5-e7cb7767abe7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143279754 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1143279754 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.783011668 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 22984728 ps |
CPU time | 1.86 seconds |
Started | Jul 25 06:40:19 PM PDT 24 |
Finished | Jul 25 06:40:21 PM PDT 24 |
Peak memory | 203008 kb |
Host | smart-e5f56ba5-3882-4852-90bf-4b1060f08ca9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783011668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.783011668 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2957146611 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 757096922 ps |
CPU time | 3.74 seconds |
Started | Jul 25 06:40:27 PM PDT 24 |
Finished | Jul 25 06:40:32 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-2c264584-e51a-4a07-840b-e81531f8cc92 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957146611 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2957146611 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1900200879 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 33893235 ps |
CPU time | 0.7 seconds |
Started | Jul 25 06:40:27 PM PDT 24 |
Finished | Jul 25 06:40:27 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-5b34c513-fc0e-4713-94d8-3baa47991908 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900200879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.1900200879 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.148314592 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 33576012439 ps |
CPU time | 60.33 seconds |
Started | Jul 25 06:40:21 PM PDT 24 |
Finished | Jul 25 06:41:22 PM PDT 24 |
Peak memory | 203308 kb |
Host | smart-77865890-2cd3-4669-bc04-905e63b7502e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148314592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.148314592 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1011623644 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 25968378 ps |
CPU time | 0.89 seconds |
Started | Jul 25 06:40:29 PM PDT 24 |
Finished | Jul 25 06:40:30 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-b0dd54c6-9684-413d-9fe2-53a1a2ef240e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011623644 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1011623644 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3278598806 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 116008301 ps |
CPU time | 4.18 seconds |
Started | Jul 25 06:40:27 PM PDT 24 |
Finished | Jul 25 06:40:31 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-478303c6-22f0-40bc-a69e-eb3561591a9d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278598806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.3278598806 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1268558134 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 300914810 ps |
CPU time | 2.65 seconds |
Started | Jul 25 06:40:27 PM PDT 24 |
Finished | Jul 25 06:40:30 PM PDT 24 |
Peak memory | 211172 kb |
Host | smart-8c943177-d53e-4fb8-a2f0-8529e7df31a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268558134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.1268558134 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1048353992 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 19050233581 ps |
CPU time | 1047.04 seconds |
Started | Jul 25 06:45:18 PM PDT 24 |
Finished | Jul 25 07:02:46 PM PDT 24 |
Peak memory | 378060 kb |
Host | smart-85271b54-6205-4e19-adec-951054ac882a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048353992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.1048353992 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.3207597280 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 46873054 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:45:27 PM PDT 24 |
Finished | Jul 25 06:45:28 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-3875e604-d9ac-4779-a7d9-63e0ea73afdf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207597280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3207597280 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.3696014618 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 69662326803 ps |
CPU time | 655.15 seconds |
Started | Jul 25 06:45:19 PM PDT 24 |
Finished | Jul 25 06:56:14 PM PDT 24 |
Peak memory | 203824 kb |
Host | smart-6b5a814b-71a5-4107-af70-e65b774e42e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696014618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 3696014618 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.2778612593 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 53502935298 ps |
CPU time | 831.31 seconds |
Started | Jul 25 06:45:21 PM PDT 24 |
Finished | Jul 25 06:59:12 PM PDT 24 |
Peak memory | 375396 kb |
Host | smart-0cd4f098-9243-4e8a-ab01-56d983ac4f8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778612593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.2778612593 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.3515388476 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 10986230952 ps |
CPU time | 19.76 seconds |
Started | Jul 25 06:45:20 PM PDT 24 |
Finished | Jul 25 06:45:40 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-2d2a91d1-c750-4486-b5a3-528eda6be604 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515388476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.3515388476 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.3426576000 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 768268937 ps |
CPU time | 39.94 seconds |
Started | Jul 25 06:45:22 PM PDT 24 |
Finished | Jul 25 06:46:02 PM PDT 24 |
Peak memory | 310580 kb |
Host | smart-247c8ab8-fe25-4095-a0b8-f0ea77ff8c22 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426576000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.3426576000 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3520996365 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 2667273627 ps |
CPU time | 74.06 seconds |
Started | Jul 25 06:45:28 PM PDT 24 |
Finished | Jul 25 06:46:42 PM PDT 24 |
Peak memory | 219552 kb |
Host | smart-78696c8a-b578-4254-9ea2-562dba788325 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520996365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.3520996365 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.612914460 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 16425197218 ps |
CPU time | 263.66 seconds |
Started | Jul 25 06:45:28 PM PDT 24 |
Finished | Jul 25 06:49:52 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-2a972d86-d215-4e28-a626-e4e83f7cd598 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612914460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ mem_walk.612914460 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.1802350652 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 21705657394 ps |
CPU time | 348.89 seconds |
Started | Jul 25 06:45:14 PM PDT 24 |
Finished | Jul 25 06:51:03 PM PDT 24 |
Peak memory | 366692 kb |
Host | smart-dc3b1573-1b81-407b-a5bd-e2cab674f6b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802350652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.1802350652 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.3971122562 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 4215017722 ps |
CPU time | 8.29 seconds |
Started | Jul 25 06:45:21 PM PDT 24 |
Finished | Jul 25 06:45:29 PM PDT 24 |
Peak memory | 209100 kb |
Host | smart-54f80eb6-f517-4aff-aca7-1048cc9361ef |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971122562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.3971122562 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1443049493 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 64459521842 ps |
CPU time | 363.36 seconds |
Started | Jul 25 06:45:17 PM PDT 24 |
Finished | Jul 25 06:51:21 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-1df90f6c-6c71-4274-ae88-2876c6807d3a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443049493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.1443049493 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.3253926103 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 16268253225 ps |
CPU time | 1047.87 seconds |
Started | Jul 25 06:45:20 PM PDT 24 |
Finished | Jul 25 07:02:48 PM PDT 24 |
Peak memory | 380124 kb |
Host | smart-e1e801eb-6f0e-40be-9867-824664cc426b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253926103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3253926103 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.3614133064 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 1454432622 ps |
CPU time | 13.82 seconds |
Started | Jul 25 06:45:15 PM PDT 24 |
Finished | Jul 25 06:45:29 PM PDT 24 |
Peak memory | 242060 kb |
Host | smart-723d44da-2004-4385-b003-9a8d8c1a50e2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614133064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3614133064 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.2499598225 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 600915673848 ps |
CPU time | 5120.12 seconds |
Started | Jul 25 06:45:28 PM PDT 24 |
Finished | Jul 25 08:10:49 PM PDT 24 |
Peak memory | 383164 kb |
Host | smart-6934be89-a9bb-4a29-af94-299cb998b07e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499598225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.2499598225 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2299660701 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 3816300603 ps |
CPU time | 33.92 seconds |
Started | Jul 25 06:45:28 PM PDT 24 |
Finished | Jul 25 06:46:02 PM PDT 24 |
Peak memory | 250928 kb |
Host | smart-f44c217b-c2e5-449c-b487-3a545feac28e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2299660701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.2299660701 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1819767191 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 5867323989 ps |
CPU time | 174.17 seconds |
Started | Jul 25 06:45:19 PM PDT 24 |
Finished | Jul 25 06:48:13 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-b88c85ec-d7c1-4f86-ac10-24d2ce1810b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819767191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.1819767191 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2664058322 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 6438234184 ps |
CPU time | 16.94 seconds |
Started | Jul 25 06:45:24 PM PDT 24 |
Finished | Jul 25 06:45:41 PM PDT 24 |
Peak memory | 256600 kb |
Host | smart-7dbcb8f5-e7a7-40a7-9f95-4e6f793990f9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664058322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.2664058322 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2584196552 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 16999102885 ps |
CPU time | 1659.47 seconds |
Started | Jul 25 06:45:33 PM PDT 24 |
Finished | Jul 25 07:13:13 PM PDT 24 |
Peak memory | 379924 kb |
Host | smart-8f681637-a8f2-484d-b9d0-4b4804cfd207 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584196552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.2584196552 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.4179298403 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 72396644 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:45:42 PM PDT 24 |
Finished | Jul 25 06:45:43 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-1681639b-6dbf-4b42-8308-c53b67265c7c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179298403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.4179298403 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.2748635083 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 50585912642 ps |
CPU time | 845.76 seconds |
Started | Jul 25 06:45:33 PM PDT 24 |
Finished | Jul 25 06:59:39 PM PDT 24 |
Peak memory | 204176 kb |
Host | smart-544bac63-e3dc-4e4e-a0f0-d44cfba1e6da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748635083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 2748635083 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.4288763837 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 47749975962 ps |
CPU time | 1269.41 seconds |
Started | Jul 25 06:45:34 PM PDT 24 |
Finished | Jul 25 07:06:44 PM PDT 24 |
Peak memory | 378052 kb |
Host | smart-83e68ec4-6205-4b8c-90cf-759d25ad6a5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288763837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.4288763837 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.3964677594 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 1768481478 ps |
CPU time | 11.32 seconds |
Started | Jul 25 06:45:34 PM PDT 24 |
Finished | Jul 25 06:45:46 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-4eec3638-ad6f-4566-ae7a-bd77ba1ee972 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964677594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.3964677594 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.3698604289 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 1541143106 ps |
CPU time | 58.28 seconds |
Started | Jul 25 06:45:34 PM PDT 24 |
Finished | Jul 25 06:46:33 PM PDT 24 |
Peak memory | 328956 kb |
Host | smart-c1fa6979-338e-41ab-b3f7-75a450a38c34 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698604289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.3698604289 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3885673621 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 5243184562 ps |
CPU time | 75.35 seconds |
Started | Jul 25 06:45:40 PM PDT 24 |
Finished | Jul 25 06:46:56 PM PDT 24 |
Peak memory | 219540 kb |
Host | smart-b4549367-23e5-42b9-8cc9-676064795941 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885673621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.3885673621 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.1493012162 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 30027664616 ps |
CPU time | 165.21 seconds |
Started | Jul 25 06:45:42 PM PDT 24 |
Finished | Jul 25 06:48:27 PM PDT 24 |
Peak memory | 211408 kb |
Host | smart-999e75d9-c7ab-4af1-bfff-1c8b8fc62b41 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493012162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.1493012162 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.2104694383 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 14579326474 ps |
CPU time | 601.85 seconds |
Started | Jul 25 06:45:27 PM PDT 24 |
Finished | Jul 25 06:55:29 PM PDT 24 |
Peak memory | 371912 kb |
Host | smart-5b6c6fb6-be90-4405-82d2-de34c346fadf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104694383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.2104694383 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.1963457228 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 4460117608 ps |
CPU time | 54.59 seconds |
Started | Jul 25 06:45:33 PM PDT 24 |
Finished | Jul 25 06:46:28 PM PDT 24 |
Peak memory | 330988 kb |
Host | smart-106c1109-17a3-48d7-9c2a-3d2c72b671d0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963457228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.1963457228 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3442934098 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 22403938468 ps |
CPU time | 478.89 seconds |
Started | Jul 25 06:45:34 PM PDT 24 |
Finished | Jul 25 06:53:33 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-9229ff77-8bfe-4bbd-8ab0-b343ef07f5d9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442934098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.3442934098 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.693738704 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 1400481086 ps |
CPU time | 3.54 seconds |
Started | Jul 25 06:45:35 PM PDT 24 |
Finished | Jul 25 06:45:39 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-6a001512-0078-4224-938f-c2c7a902e43d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693738704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.693738704 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.1197987678 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 1767575632 ps |
CPU time | 96.57 seconds |
Started | Jul 25 06:45:35 PM PDT 24 |
Finished | Jul 25 06:47:12 PM PDT 24 |
Peak memory | 316704 kb |
Host | smart-9fcfad54-43f1-40ad-aeaa-a3c6ac74d1fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197987678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1197987678 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.3127677662 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1508627549 ps |
CPU time | 3.4 seconds |
Started | Jul 25 06:45:41 PM PDT 24 |
Finished | Jul 25 06:45:45 PM PDT 24 |
Peak memory | 222412 kb |
Host | smart-9de1f126-9837-47f4-9669-d2c8c462fa41 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127677662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3127677662 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.813303646 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 4806241349 ps |
CPU time | 71.88 seconds |
Started | Jul 25 06:45:27 PM PDT 24 |
Finished | Jul 25 06:46:39 PM PDT 24 |
Peak memory | 338160 kb |
Host | smart-a6620443-6083-41f3-8fbc-559f3dc30252 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813303646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.813303646 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.2265178428 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 140108287982 ps |
CPU time | 3425.69 seconds |
Started | Jul 25 06:45:42 PM PDT 24 |
Finished | Jul 25 07:42:48 PM PDT 24 |
Peak memory | 383208 kb |
Host | smart-68b5ae60-6558-4ffb-bf1e-fc42a8ee491d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265178428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.2265178428 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.887146230 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 503316538 ps |
CPU time | 16.37 seconds |
Started | Jul 25 06:45:41 PM PDT 24 |
Finished | Jul 25 06:45:58 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-59f8faeb-d2a4-4f97-a8f1-b3cc4790fbf3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=887146230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.887146230 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.332805690 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 18766139755 ps |
CPU time | 149.8 seconds |
Started | Jul 25 06:45:28 PM PDT 24 |
Finished | Jul 25 06:47:58 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-d21fddf5-7d09-4da9-8f84-6b13f21a6079 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332805690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. sram_ctrl_stress_pipeline.332805690 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3453633263 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 2922843845 ps |
CPU time | 34.66 seconds |
Started | Jul 25 06:45:33 PM PDT 24 |
Finished | Jul 25 06:46:08 PM PDT 24 |
Peak memory | 293036 kb |
Host | smart-17165e45-82f2-4d24-baaf-3dcfc52e04e8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453633263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3453633263 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1171550784 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 35361258442 ps |
CPU time | 448.86 seconds |
Started | Jul 25 06:47:03 PM PDT 24 |
Finished | Jul 25 06:54:32 PM PDT 24 |
Peak memory | 373844 kb |
Host | smart-94c219d1-3792-4661-b9a2-9d8cc84c24e2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171550784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.1171550784 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.843443937 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 92437896 ps |
CPU time | 0.65 seconds |
Started | Jul 25 06:47:16 PM PDT 24 |
Finished | Jul 25 06:47:16 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-692839c5-a6d9-4192-89fd-2829e36f4f0b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843443937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.843443937 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.3539884206 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 508046301167 ps |
CPU time | 2387.63 seconds |
Started | Jul 25 06:47:04 PM PDT 24 |
Finished | Jul 25 07:26:52 PM PDT 24 |
Peak memory | 203864 kb |
Host | smart-0f33e166-b4ad-4cfa-a998-21b9035ce980 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539884206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .3539884206 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.1050700056 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 20207351794 ps |
CPU time | 1165.14 seconds |
Started | Jul 25 06:47:05 PM PDT 24 |
Finished | Jul 25 07:06:30 PM PDT 24 |
Peak memory | 376044 kb |
Host | smart-985bf85d-1dc9-41d3-b4dd-eec5bfc776ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050700056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.1050700056 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.47547392 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 16286206193 ps |
CPU time | 49.49 seconds |
Started | Jul 25 06:47:04 PM PDT 24 |
Finished | Jul 25 06:47:53 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-ca22069f-3f79-47af-b9cc-98986a1124b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47547392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esca lation.47547392 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.3304397207 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 1414412719 ps |
CPU time | 10.83 seconds |
Started | Jul 25 06:47:04 PM PDT 24 |
Finished | Jul 25 06:47:15 PM PDT 24 |
Peak memory | 235884 kb |
Host | smart-ed56e59e-755f-4508-8e3b-56eed40f4aec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304397207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.3304397207 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2741542689 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 5820131834 ps |
CPU time | 84.93 seconds |
Started | Jul 25 06:47:14 PM PDT 24 |
Finished | Jul 25 06:48:39 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-5fb1dcbf-93e5-4215-8d34-8189cd1f3f7d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741542689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.2741542689 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.3082215933 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 30728072276 ps |
CPU time | 333.98 seconds |
Started | Jul 25 06:47:13 PM PDT 24 |
Finished | Jul 25 06:52:47 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-cd036c46-ac2a-42bd-8753-c0999a1860a7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082215933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.3082215933 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.2903566938 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 28170216131 ps |
CPU time | 1754.66 seconds |
Started | Jul 25 06:47:03 PM PDT 24 |
Finished | Jul 25 07:16:18 PM PDT 24 |
Peak memory | 380096 kb |
Host | smart-485b4caf-438f-41d8-99e1-6a3a3f51d96f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903566938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2903566938 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.3814484741 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 537474491 ps |
CPU time | 7 seconds |
Started | Jul 25 06:47:04 PM PDT 24 |
Finished | Jul 25 06:47:11 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-f3d6f9a5-d105-439f-bd75-1e281da59b87 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814484741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.3814484741 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3947406941 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 4671824100 ps |
CPU time | 255.4 seconds |
Started | Jul 25 06:47:04 PM PDT 24 |
Finished | Jul 25 06:51:20 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-92a9dec1-2778-4467-85cb-a0b3b282b1f3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947406941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.3947406941 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.37963723 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 363903070 ps |
CPU time | 3.38 seconds |
Started | Jul 25 06:47:12 PM PDT 24 |
Finished | Jul 25 06:47:16 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-2f15f7e1-bce0-4072-a706-efa3453b63ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37963723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.37963723 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.619296160 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 13913659462 ps |
CPU time | 1662.3 seconds |
Started | Jul 25 06:47:07 PM PDT 24 |
Finished | Jul 25 07:14:49 PM PDT 24 |
Peak memory | 382172 kb |
Host | smart-f245ab7e-c8a2-4a80-9396-590245f95c58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619296160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.619296160 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.4117620037 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 2272588597 ps |
CPU time | 18.47 seconds |
Started | Jul 25 06:47:03 PM PDT 24 |
Finished | Jul 25 06:47:21 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-2318e6b8-54d2-4526-96a6-66ace1473577 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117620037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.4117620037 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.3419537502 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 11335225430 ps |
CPU time | 3975.16 seconds |
Started | Jul 25 06:47:12 PM PDT 24 |
Finished | Jul 25 07:53:27 PM PDT 24 |
Peak memory | 380180 kb |
Host | smart-56778fe1-5d80-4b4f-937a-6e27826526ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419537502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.3419537502 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3273804204 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 3336583568 ps |
CPU time | 33.25 seconds |
Started | Jul 25 06:47:15 PM PDT 24 |
Finished | Jul 25 06:47:48 PM PDT 24 |
Peak memory | 211612 kb |
Host | smart-ab233ced-a2d5-4752-a2b7-7bbe79bbf020 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3273804204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3273804204 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1330071252 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 4063847472 ps |
CPU time | 256.34 seconds |
Started | Jul 25 06:47:04 PM PDT 24 |
Finished | Jul 25 06:51:20 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-97d42277-3110-4b59-b705-d17899012ce7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330071252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.1330071252 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3862702656 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 1391177830 ps |
CPU time | 5.9 seconds |
Started | Jul 25 06:47:05 PM PDT 24 |
Finished | Jul 25 06:47:11 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-303b0318-757c-409c-9c4c-4b36738656f3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862702656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.3862702656 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1417611679 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 147550131959 ps |
CPU time | 838.61 seconds |
Started | Jul 25 06:47:21 PM PDT 24 |
Finished | Jul 25 07:01:20 PM PDT 24 |
Peak memory | 379340 kb |
Host | smart-e4566511-dd0c-4152-9344-58e5a3e6627f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417611679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.1417611679 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.155992735 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 38269374 ps |
CPU time | 0.72 seconds |
Started | Jul 25 06:47:20 PM PDT 24 |
Finished | Jul 25 06:47:21 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-0e9e6ee2-7a5c-44a1-a835-1256a0247d08 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155992735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.155992735 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.288655237 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 234127398163 ps |
CPU time | 2007.03 seconds |
Started | Jul 25 06:47:14 PM PDT 24 |
Finished | Jul 25 07:20:41 PM PDT 24 |
Peak memory | 203364 kb |
Host | smart-0c58363e-14d4-4e10-b9f3-46d28d5253bd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288655237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection. 288655237 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.3806166176 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 32491246495 ps |
CPU time | 401.8 seconds |
Started | Jul 25 06:47:20 PM PDT 24 |
Finished | Jul 25 06:54:02 PM PDT 24 |
Peak memory | 380088 kb |
Host | smart-ed4aae38-73ca-4ad0-81d9-547d764e164a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806166176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.3806166176 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1839643350 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 7898169324 ps |
CPU time | 31.14 seconds |
Started | Jul 25 06:47:14 PM PDT 24 |
Finished | Jul 25 06:47:45 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-331f69ba-22d0-4301-a93e-87e06512aff5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839643350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1839643350 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.661721799 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 2772958736 ps |
CPU time | 48.45 seconds |
Started | Jul 25 06:47:15 PM PDT 24 |
Finished | Jul 25 06:48:04 PM PDT 24 |
Peak memory | 320792 kb |
Host | smart-56380f4a-4561-4a72-b588-ec487a2a58ee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661721799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.sram_ctrl_max_throughput.661721799 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.4218417790 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 2444590365 ps |
CPU time | 77.78 seconds |
Started | Jul 25 06:47:20 PM PDT 24 |
Finished | Jul 25 06:48:38 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-b851b64f-bb6f-40ee-8054-5071ccf619ea |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218417790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.4218417790 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.361108758 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 24102087202 ps |
CPU time | 358.36 seconds |
Started | Jul 25 06:47:22 PM PDT 24 |
Finished | Jul 25 06:53:21 PM PDT 24 |
Peak memory | 212304 kb |
Host | smart-8cb205d2-ce68-4a4c-9961-976fb956eae8 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361108758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl _mem_walk.361108758 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.3345454263 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 80035248860 ps |
CPU time | 1256.35 seconds |
Started | Jul 25 06:47:35 PM PDT 24 |
Finished | Jul 25 07:08:32 PM PDT 24 |
Peak memory | 379128 kb |
Host | smart-98937833-9281-4dd1-970a-3265d1550d26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345454263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.3345454263 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.1279935462 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 4670958321 ps |
CPU time | 95.81 seconds |
Started | Jul 25 06:47:14 PM PDT 24 |
Finished | Jul 25 06:48:50 PM PDT 24 |
Peak memory | 358588 kb |
Host | smart-4f5d310d-409f-46ff-b1dc-f45f9e7c0c43 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279935462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.1279935462 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.577667893 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 354598315 ps |
CPU time | 3.18 seconds |
Started | Jul 25 06:47:19 PM PDT 24 |
Finished | Jul 25 06:47:23 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-e59de98f-a5ef-4ac8-a22b-8ace28c4e953 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577667893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.577667893 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.4045161337 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 66175585828 ps |
CPU time | 938.79 seconds |
Started | Jul 25 06:47:20 PM PDT 24 |
Finished | Jul 25 07:02:59 PM PDT 24 |
Peak memory | 380124 kb |
Host | smart-6018cd7c-3efd-473c-b621-72cd050964a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045161337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.4045161337 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.866023637 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 1967192677 ps |
CPU time | 12.08 seconds |
Started | Jul 25 06:47:14 PM PDT 24 |
Finished | Jul 25 06:47:26 PM PDT 24 |
Peak memory | 239092 kb |
Host | smart-0f7302a9-85e5-429d-906d-be8ecc91b835 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866023637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.866023637 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.866710118 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 359232747173 ps |
CPU time | 4926.49 seconds |
Started | Jul 25 06:47:21 PM PDT 24 |
Finished | Jul 25 08:09:28 PM PDT 24 |
Peak memory | 389344 kb |
Host | smart-baf3270c-0f10-4f3d-a783-be7336d6afbb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866710118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_stress_all.866710118 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2008114339 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 381339695 ps |
CPU time | 13.46 seconds |
Started | Jul 25 06:47:21 PM PDT 24 |
Finished | Jul 25 06:47:34 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-76be9730-7e61-42d4-a831-870f9091c7ef |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2008114339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2008114339 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1228015299 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 4275627679 ps |
CPU time | 269.15 seconds |
Started | Jul 25 06:47:14 PM PDT 24 |
Finished | Jul 25 06:51:43 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-b63aa437-1ec2-489c-b96a-e6e0aac5df5e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228015299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.1228015299 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2786246155 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 804669439 ps |
CPU time | 63.15 seconds |
Started | Jul 25 06:47:13 PM PDT 24 |
Finished | Jul 25 06:48:16 PM PDT 24 |
Peak memory | 342156 kb |
Host | smart-7da89ca9-2157-455e-93cd-700b120b9287 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786246155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.2786246155 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3170177128 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 19558086460 ps |
CPU time | 302.28 seconds |
Started | Jul 25 06:47:29 PM PDT 24 |
Finished | Jul 25 06:52:32 PM PDT 24 |
Peak memory | 373940 kb |
Host | smart-daf6147e-42c2-4f27-81db-2fd3ce461198 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170177128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.3170177128 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.1126492339 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 53599550 ps |
CPU time | 0.62 seconds |
Started | Jul 25 06:47:29 PM PDT 24 |
Finished | Jul 25 06:47:29 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-d8e0b128-e89d-40df-a543-b986117af253 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126492339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1126492339 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.3768855847 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 187278076388 ps |
CPU time | 1725.29 seconds |
Started | Jul 25 06:47:38 PM PDT 24 |
Finished | Jul 25 07:16:24 PM PDT 24 |
Peak memory | 203812 kb |
Host | smart-9189059f-9b5a-49aa-93fd-7b38faabb3f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768855847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .3768855847 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.3922648443 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 37227798675 ps |
CPU time | 992.04 seconds |
Started | Jul 25 06:47:29 PM PDT 24 |
Finished | Jul 25 07:04:02 PM PDT 24 |
Peak memory | 376968 kb |
Host | smart-e9be88ef-4819-4358-8db4-3e8db8fac482 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922648443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.3922648443 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.554636871 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 53410159265 ps |
CPU time | 68.87 seconds |
Started | Jul 25 06:47:29 PM PDT 24 |
Finished | Jul 25 06:48:38 PM PDT 24 |
Peak memory | 203316 kb |
Host | smart-5932ad10-6ebc-4f0b-accd-ff7121b10064 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554636871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_esc alation.554636871 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.701107163 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 714141905 ps |
CPU time | 10.73 seconds |
Started | Jul 25 06:47:30 PM PDT 24 |
Finished | Jul 25 06:47:41 PM PDT 24 |
Peak memory | 235896 kb |
Host | smart-837dc89c-bd46-45cd-9ee2-4250ad76c5d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701107163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.sram_ctrl_max_throughput.701107163 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1358659191 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 3025397352 ps |
CPU time | 75.21 seconds |
Started | Jul 25 06:47:30 PM PDT 24 |
Finished | Jul 25 06:48:46 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-a6d98c88-19ff-42d3-bfc3-e7c5a7ca523a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358659191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.1358659191 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.1519634459 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 5307983152 ps |
CPU time | 297.85 seconds |
Started | Jul 25 06:47:27 PM PDT 24 |
Finished | Jul 25 06:52:25 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-1cb42d2f-adfd-466e-a487-13dd32a3cdd8 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519634459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.1519634459 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.2884075175 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 9163397621 ps |
CPU time | 639.92 seconds |
Started | Jul 25 06:47:19 PM PDT 24 |
Finished | Jul 25 06:57:59 PM PDT 24 |
Peak memory | 375492 kb |
Host | smart-84bfc945-24ba-4acb-905b-31887ad6113a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884075175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.2884075175 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.2083570954 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 635483409 ps |
CPU time | 19.16 seconds |
Started | Jul 25 06:47:21 PM PDT 24 |
Finished | Jul 25 06:47:40 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-22683542-9670-4962-aae6-85f5ba9ce960 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083570954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.2083570954 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2204284022 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 38425845935 ps |
CPU time | 204.1 seconds |
Started | Jul 25 06:47:21 PM PDT 24 |
Finished | Jul 25 06:50:45 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-100c57e8-7113-464f-a828-b67e2f663b26 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204284022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.2204284022 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.447548307 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 362032838 ps |
CPU time | 3.18 seconds |
Started | Jul 25 06:47:28 PM PDT 24 |
Finished | Jul 25 06:47:31 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-42de91fd-ac66-40c4-8fa0-efd3cea30e0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447548307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.447548307 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.3295251 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 1646317732 ps |
CPU time | 22.28 seconds |
Started | Jul 25 06:47:28 PM PDT 24 |
Finished | Jul 25 06:47:51 PM PDT 24 |
Peak memory | 253900 kb |
Host | smart-81022722-cb6a-4633-938d-2983e4c92693 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3295251 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.3440548877 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 2272798029 ps |
CPU time | 57.56 seconds |
Started | Jul 25 06:47:20 PM PDT 24 |
Finished | Jul 25 06:48:18 PM PDT 24 |
Peak memory | 335132 kb |
Host | smart-6a08e95d-b909-437e-a0cb-3813e9f47dca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440548877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3440548877 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.820364420 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 279042780170 ps |
CPU time | 4332.02 seconds |
Started | Jul 25 06:47:28 PM PDT 24 |
Finished | Jul 25 07:59:40 PM PDT 24 |
Peak memory | 379196 kb |
Host | smart-8f0a470f-3723-49f0-b4ad-1389afff224a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820364420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_stress_all.820364420 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1982550251 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 4332412087 ps |
CPU time | 31.38 seconds |
Started | Jul 25 06:47:28 PM PDT 24 |
Finished | Jul 25 06:47:59 PM PDT 24 |
Peak memory | 212816 kb |
Host | smart-e737f99f-b96d-4245-859f-3e78267b2f75 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1982550251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1982550251 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3937671482 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 11927345145 ps |
CPU time | 166.29 seconds |
Started | Jul 25 06:47:22 PM PDT 24 |
Finished | Jul 25 06:50:08 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-d7848315-cb65-4ad2-a705-2da3fc6203f6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937671482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.3937671482 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2200899966 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 2968358902 ps |
CPU time | 57.53 seconds |
Started | Jul 25 06:47:30 PM PDT 24 |
Finished | Jul 25 06:48:28 PM PDT 24 |
Peak memory | 305444 kb |
Host | smart-877eb43c-87b7-4ac0-8031-376d7d213c0e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200899966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.2200899966 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1656875668 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 55851976687 ps |
CPU time | 829.69 seconds |
Started | Jul 25 06:47:37 PM PDT 24 |
Finished | Jul 25 07:01:27 PM PDT 24 |
Peak memory | 381120 kb |
Host | smart-b3b9d144-6c1d-42f1-9741-ece579c99aea |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656875668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.1656875668 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.1832126642 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 27402216475 ps |
CPU time | 1886.3 seconds |
Started | Jul 25 06:47:28 PM PDT 24 |
Finished | Jul 25 07:18:54 PM PDT 24 |
Peak memory | 203988 kb |
Host | smart-cc877e4e-b40e-4a98-bb03-92311fae76e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832126642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .1832126642 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.177800874 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 106979274145 ps |
CPU time | 1568.7 seconds |
Started | Jul 25 06:47:37 PM PDT 24 |
Finished | Jul 25 07:13:46 PM PDT 24 |
Peak memory | 380144 kb |
Host | smart-d170ecc4-8282-46aa-9c6a-bfb5fc5fc4ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177800874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executabl e.177800874 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.4169260650 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 3355134539 ps |
CPU time | 19.66 seconds |
Started | Jul 25 06:47:38 PM PDT 24 |
Finished | Jul 25 06:47:57 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-fed37722-dda3-41e8-b786-ba9439372bb2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169260650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.4169260650 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.1398179599 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 3175663776 ps |
CPU time | 124.08 seconds |
Started | Jul 25 06:47:40 PM PDT 24 |
Finished | Jul 25 06:49:45 PM PDT 24 |
Peak memory | 370848 kb |
Host | smart-2dda1aba-15a3-48bb-b2f7-4a477f62c06d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398179599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.1398179599 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2115630268 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 9770508427 ps |
CPU time | 147.94 seconds |
Started | Jul 25 06:47:39 PM PDT 24 |
Finished | Jul 25 06:50:07 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-ce8b905d-9ee3-4299-9a53-9108be125503 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115630268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.2115630268 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.577821418 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 20710087018 ps |
CPU time | 348.09 seconds |
Started | Jul 25 06:47:36 PM PDT 24 |
Finished | Jul 25 06:53:25 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-21a39875-6b6d-4e8d-a9eb-8d5368e2aa26 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577821418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _mem_walk.577821418 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.177524553 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 10801022244 ps |
CPU time | 1010.38 seconds |
Started | Jul 25 06:47:30 PM PDT 24 |
Finished | Jul 25 07:04:21 PM PDT 24 |
Peak memory | 378036 kb |
Host | smart-095ba42b-3273-483e-834e-66feb37a904f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177524553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip le_keys.177524553 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.4132976486 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 1903139727 ps |
CPU time | 45.31 seconds |
Started | Jul 25 06:47:37 PM PDT 24 |
Finished | Jul 25 06:48:23 PM PDT 24 |
Peak memory | 307460 kb |
Host | smart-ff4ea381-b04b-4022-b1ef-6b924b11b678 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132976486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.4132976486 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.884465674 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 4334128603 ps |
CPU time | 232.22 seconds |
Started | Jul 25 06:47:36 PM PDT 24 |
Finished | Jul 25 06:51:28 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-e2dafa1e-41e1-4537-b6d7-be88d96af3fb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884465674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.sram_ctrl_partial_access_b2b.884465674 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.2795020226 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 367613223 ps |
CPU time | 3.11 seconds |
Started | Jul 25 06:47:37 PM PDT 24 |
Finished | Jul 25 06:47:40 PM PDT 24 |
Peak memory | 203064 kb |
Host | smart-6f3c59ab-1ae9-4f7c-8af4-ef0d20ca4eda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795020226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2795020226 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.2222472165 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 72595398978 ps |
CPU time | 970.14 seconds |
Started | Jul 25 06:47:37 PM PDT 24 |
Finished | Jul 25 07:03:47 PM PDT 24 |
Peak memory | 374084 kb |
Host | smart-adce1b76-208d-4e27-9fb1-2f08afca4fa3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222472165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2222472165 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.3356987534 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 979738766 ps |
CPU time | 135.06 seconds |
Started | Jul 25 06:47:29 PM PDT 24 |
Finished | Jul 25 06:49:44 PM PDT 24 |
Peak memory | 369736 kb |
Host | smart-d7dae178-7616-4974-bc86-be79635c1430 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356987534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3356987534 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.1422217904 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 228339349827 ps |
CPU time | 4191.4 seconds |
Started | Jul 25 06:47:37 PM PDT 24 |
Finished | Jul 25 07:57:29 PM PDT 24 |
Peak memory | 381248 kb |
Host | smart-f3ccc7dd-56d0-40fa-aa73-3d5db49b6c38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422217904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.1422217904 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2337543268 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 2814950439 ps |
CPU time | 18.25 seconds |
Started | Jul 25 06:47:37 PM PDT 24 |
Finished | Jul 25 06:47:56 PM PDT 24 |
Peak memory | 211696 kb |
Host | smart-bfb047ff-964c-424c-add4-cad5511333c7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2337543268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2337543268 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1562668489 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 10312516286 ps |
CPU time | 327.22 seconds |
Started | Jul 25 06:47:36 PM PDT 24 |
Finished | Jul 25 06:53:03 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-11be0edd-c90a-47a2-a2cd-90ade747e9b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562668489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.1562668489 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3244133629 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 4594446302 ps |
CPU time | 84.29 seconds |
Started | Jul 25 06:47:37 PM PDT 24 |
Finished | Jul 25 06:49:02 PM PDT 24 |
Peak memory | 371340 kb |
Host | smart-8ca0dc2b-ada6-4b3e-9fcc-50289391b413 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244133629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3244133629 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.639519524 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 13833983164 ps |
CPU time | 987.12 seconds |
Started | Jul 25 06:47:45 PM PDT 24 |
Finished | Jul 25 07:04:13 PM PDT 24 |
Peak memory | 380104 kb |
Host | smart-2b98097e-f88f-409e-b87b-8cefbdf55bba |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639519524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_access_during_key_req.639519524 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.753722976 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 14760158 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:47:53 PM PDT 24 |
Finished | Jul 25 06:47:54 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-c2fea738-eb69-430c-935b-81d8b450c2a6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753722976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.753722976 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.268220614 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 442298464799 ps |
CPU time | 2655.27 seconds |
Started | Jul 25 06:47:46 PM PDT 24 |
Finished | Jul 25 07:32:02 PM PDT 24 |
Peak memory | 203764 kb |
Host | smart-d8a6fe1e-10c0-4ee8-a742-3db45b22cf72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268220614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection. 268220614 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.901286232 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 17272513275 ps |
CPU time | 972 seconds |
Started | Jul 25 06:47:45 PM PDT 24 |
Finished | Jul 25 07:03:58 PM PDT 24 |
Peak memory | 353508 kb |
Host | smart-eb828c86-8388-4c88-8f0f-52df8b0ce6a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901286232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executabl e.901286232 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.172265248 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 12270718599 ps |
CPU time | 21.27 seconds |
Started | Jul 25 06:47:47 PM PDT 24 |
Finished | Jul 25 06:48:08 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-bc91b978-3ec4-48ec-b83e-272054a3c08a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172265248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_esc alation.172265248 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.485512651 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 2675803284 ps |
CPU time | 32.93 seconds |
Started | Jul 25 06:47:47 PM PDT 24 |
Finished | Jul 25 06:48:20 PM PDT 24 |
Peak memory | 291916 kb |
Host | smart-7d7b1c1f-7fdd-4a92-a52a-b1f688297793 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485512651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.sram_ctrl_max_throughput.485512651 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.846577895 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 2804457150 ps |
CPU time | 74.04 seconds |
Started | Jul 25 06:47:52 PM PDT 24 |
Finished | Jul 25 06:49:06 PM PDT 24 |
Peak memory | 219508 kb |
Host | smart-5ab7e928-afd5-43e1-9631-7f0ed1d0b5bf |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846577895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14 .sram_ctrl_mem_partial_access.846577895 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.4162967913 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 10304891681 ps |
CPU time | 291.66 seconds |
Started | Jul 25 06:47:54 PM PDT 24 |
Finished | Jul 25 06:52:46 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-bc1fe51d-adc7-424a-a681-870e3f923036 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162967913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.4162967913 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.3766067411 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 54272146958 ps |
CPU time | 1357.7 seconds |
Started | Jul 25 06:47:44 PM PDT 24 |
Finished | Jul 25 07:10:22 PM PDT 24 |
Peak memory | 380360 kb |
Host | smart-b5f641f7-7ce6-4366-a401-99a5ee9f5d42 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766067411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3766067411 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.1006481779 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 3986719499 ps |
CPU time | 33.22 seconds |
Started | Jul 25 06:47:47 PM PDT 24 |
Finished | Jul 25 06:48:20 PM PDT 24 |
Peak memory | 285132 kb |
Host | smart-a8c8f553-daaa-40d9-bd9a-f77e36cc2bcc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006481779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.1006481779 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.948118010 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 82205129401 ps |
CPU time | 461.56 seconds |
Started | Jul 25 06:47:46 PM PDT 24 |
Finished | Jul 25 06:55:27 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-cfdf3cf2-c4e0-4001-bfb7-2fb56dc09d37 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948118010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.sram_ctrl_partial_access_b2b.948118010 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.1942746836 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 1401870367 ps |
CPU time | 3.53 seconds |
Started | Jul 25 06:47:53 PM PDT 24 |
Finished | Jul 25 06:47:57 PM PDT 24 |
Peak memory | 203324 kb |
Host | smart-a5c48b3a-9afc-484a-83d6-89df928a1055 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942746836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1942746836 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.1195732632 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 18939909006 ps |
CPU time | 202.5 seconds |
Started | Jul 25 06:47:45 PM PDT 24 |
Finished | Jul 25 06:51:07 PM PDT 24 |
Peak memory | 318712 kb |
Host | smart-cf54680e-91e0-4d3d-af04-d3ac36fb0199 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195732632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1195732632 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.520644342 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 1544154644 ps |
CPU time | 13.25 seconds |
Started | Jul 25 06:47:46 PM PDT 24 |
Finished | Jul 25 06:47:59 PM PDT 24 |
Peak memory | 249148 kb |
Host | smart-8e61ee2e-7da9-4483-8917-a61ad69f1f0e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520644342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.520644342 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.264334122 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 351503753 ps |
CPU time | 5.92 seconds |
Started | Jul 25 06:47:53 PM PDT 24 |
Finished | Jul 25 06:47:59 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-4abd3d15-1d77-45f3-8649-106b85f0359a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=264334122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.264334122 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3204684204 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 9017702254 ps |
CPU time | 302.53 seconds |
Started | Jul 25 06:47:46 PM PDT 24 |
Finished | Jul 25 06:52:49 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-78b59be3-d0b9-4820-a2da-6340da5588e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204684204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.3204684204 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1972507723 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 9792664723 ps |
CPU time | 84.29 seconds |
Started | Jul 25 06:47:43 PM PDT 24 |
Finished | Jul 25 06:49:08 PM PDT 24 |
Peak memory | 371784 kb |
Host | smart-f0f09704-97f1-422d-a64f-2e3037dbae2d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972507723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1972507723 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2900402099 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 6022674187 ps |
CPU time | 555.42 seconds |
Started | Jul 25 06:47:51 PM PDT 24 |
Finished | Jul 25 06:57:07 PM PDT 24 |
Peak memory | 378116 kb |
Host | smart-84728693-d4b5-4159-87a0-b5d9d5aa0121 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900402099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.2900402099 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.153099449 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 43392301 ps |
CPU time | 0.74 seconds |
Started | Jul 25 06:48:02 PM PDT 24 |
Finished | Jul 25 06:48:03 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-64c9a68a-d2e7-410b-8250-37be06ef9fa3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153099449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.153099449 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.3533562650 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 424436704610 ps |
CPU time | 3007.06 seconds |
Started | Jul 25 06:47:54 PM PDT 24 |
Finished | Jul 25 07:38:02 PM PDT 24 |
Peak memory | 203896 kb |
Host | smart-d7018335-7a2d-4cf8-92ac-a7117c34f4d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533562650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .3533562650 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.3256317500 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 6059528970 ps |
CPU time | 414.9 seconds |
Started | Jul 25 06:47:52 PM PDT 24 |
Finished | Jul 25 06:54:47 PM PDT 24 |
Peak memory | 375960 kb |
Host | smart-fecc5436-74f2-4848-8364-cbd92a81fb7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256317500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.3256317500 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.2747063395 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 46744009204 ps |
CPU time | 78.78 seconds |
Started | Jul 25 06:47:52 PM PDT 24 |
Finished | Jul 25 06:49:11 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-22b838fa-47e2-4536-b89a-1970e400cdd7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747063395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.2747063395 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.1920238034 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 716457166 ps |
CPU time | 20.19 seconds |
Started | Jul 25 06:47:53 PM PDT 24 |
Finished | Jul 25 06:48:13 PM PDT 24 |
Peak memory | 268548 kb |
Host | smart-67cd4aab-ac5a-491b-8702-77f3642c51dd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920238034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.1920238034 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1800215702 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 5788955025 ps |
CPU time | 77.39 seconds |
Started | Jul 25 06:47:53 PM PDT 24 |
Finished | Jul 25 06:49:10 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-3fcbf3aa-28e1-44a5-9244-8d81b8155cf8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800215702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.1800215702 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.3948751902 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 23865189121 ps |
CPU time | 293.03 seconds |
Started | Jul 25 06:47:52 PM PDT 24 |
Finished | Jul 25 06:52:45 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-03fa35d5-8bab-41ae-b4d6-82c91aaae7f3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948751902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.3948751902 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.344404032 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 54569854359 ps |
CPU time | 631.24 seconds |
Started | Jul 25 06:47:54 PM PDT 24 |
Finished | Jul 25 06:58:26 PM PDT 24 |
Peak memory | 376436 kb |
Host | smart-93fd6443-6bfc-4875-ba5c-97734f42625a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344404032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip le_keys.344404032 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.2643702072 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 3284979319 ps |
CPU time | 6.78 seconds |
Started | Jul 25 06:47:53 PM PDT 24 |
Finished | Jul 25 06:48:00 PM PDT 24 |
Peak memory | 215260 kb |
Host | smart-2564b304-2fb5-428e-b36a-99a36d9623af |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643702072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.2643702072 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.661903367 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 95073551683 ps |
CPU time | 597.96 seconds |
Started | Jul 25 06:47:52 PM PDT 24 |
Finished | Jul 25 06:57:50 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-156fe0e5-32a6-43bf-a447-9eba88674128 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661903367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.sram_ctrl_partial_access_b2b.661903367 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.556982250 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 350302445 ps |
CPU time | 3.5 seconds |
Started | Jul 25 06:47:54 PM PDT 24 |
Finished | Jul 25 06:47:58 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-e4a25dad-2dc0-4798-8b61-f7a93cbf4570 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556982250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.556982250 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.690414186 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 1784381184 ps |
CPU time | 584.14 seconds |
Started | Jul 25 06:47:52 PM PDT 24 |
Finished | Jul 25 06:57:36 PM PDT 24 |
Peak memory | 376004 kb |
Host | smart-46ff676a-75c4-4c92-b9d0-9f623c9b540f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690414186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.690414186 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.620625823 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 452274450 ps |
CPU time | 134.42 seconds |
Started | Jul 25 06:47:56 PM PDT 24 |
Finished | Jul 25 06:50:10 PM PDT 24 |
Peak memory | 369728 kb |
Host | smart-81a14d1b-16c0-4587-9c24-25160381e6d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620625823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.620625823 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.1703894557 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 148398318886 ps |
CPU time | 4361.4 seconds |
Started | Jul 25 06:48:02 PM PDT 24 |
Finished | Jul 25 08:00:44 PM PDT 24 |
Peak memory | 382204 kb |
Host | smart-7d86677f-f339-4b0a-88ef-d8d41b41b54a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703894557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.1703894557 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2839432687 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 1062259915 ps |
CPU time | 21.96 seconds |
Started | Jul 25 06:48:01 PM PDT 24 |
Finished | Jul 25 06:48:23 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-eb3cc3ef-ae37-47d3-8d3e-064a2561f270 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2839432687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2839432687 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2585186204 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 2988427297 ps |
CPU time | 204.78 seconds |
Started | Jul 25 06:47:52 PM PDT 24 |
Finished | Jul 25 06:51:17 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-2a4a420a-cfec-42f9-a3ce-0318b78c03aa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585186204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.2585186204 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3704447749 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 713669780 ps |
CPU time | 13.89 seconds |
Started | Jul 25 06:47:56 PM PDT 24 |
Finished | Jul 25 06:48:10 PM PDT 24 |
Peak memory | 242180 kb |
Host | smart-16a4891f-6ecc-4930-a132-24ae37b66eea |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704447749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.3704447749 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.106059631 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 27548171740 ps |
CPU time | 732.59 seconds |
Started | Jul 25 06:48:00 PM PDT 24 |
Finished | Jul 25 07:00:13 PM PDT 24 |
Peak memory | 380140 kb |
Host | smart-978cfd97-a6a6-4ab3-a020-a3df7b577206 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106059631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_access_during_key_req.106059631 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.3722801895 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 15666159 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:48:09 PM PDT 24 |
Finished | Jul 25 06:48:10 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-9ec091f2-181d-4f50-8275-82364c59c1d6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722801895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3722801895 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.1367271671 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 26625641044 ps |
CPU time | 1947.46 seconds |
Started | Jul 25 06:47:59 PM PDT 24 |
Finished | Jul 25 07:20:27 PM PDT 24 |
Peak memory | 204108 kb |
Host | smart-80898d34-a513-47bf-9ff7-f72db9c30b9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367271671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .1367271671 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.650720827 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 63353689751 ps |
CPU time | 899.86 seconds |
Started | Jul 25 06:48:02 PM PDT 24 |
Finished | Jul 25 07:03:02 PM PDT 24 |
Peak memory | 365792 kb |
Host | smart-88c3fa1d-3609-4f4a-a57b-2e256e999871 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650720827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executabl e.650720827 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.398179226 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 55057918324 ps |
CPU time | 89.71 seconds |
Started | Jul 25 06:48:01 PM PDT 24 |
Finished | Jul 25 06:49:31 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-b14d62ba-6908-4ce4-b936-dd3da051267e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398179226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_esc alation.398179226 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.2144240564 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 1364991712 ps |
CPU time | 5.82 seconds |
Started | Jul 25 06:48:03 PM PDT 24 |
Finished | Jul 25 06:48:09 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-5b33a3ee-dd34-4bf9-b676-603a5944cef2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144240564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.2144240564 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3517244154 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 5985769676 ps |
CPU time | 167.68 seconds |
Started | Jul 25 06:48:07 PM PDT 24 |
Finished | Jul 25 06:50:55 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-471035d7-dcfd-412a-b2f1-a24760d67423 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517244154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.3517244154 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.1848456068 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 55301593700 ps |
CPU time | 326.26 seconds |
Started | Jul 25 06:48:08 PM PDT 24 |
Finished | Jul 25 06:53:35 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-a77ea085-a390-444a-96d0-339206464aef |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848456068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.1848456068 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.3215248576 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 5100373155 ps |
CPU time | 581.03 seconds |
Started | Jul 25 06:48:01 PM PDT 24 |
Finished | Jul 25 06:57:42 PM PDT 24 |
Peak memory | 379056 kb |
Host | smart-cfea476e-c8f2-47ef-a7af-3ce04aaacc40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215248576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.3215248576 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.550310644 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 1072993510 ps |
CPU time | 14.95 seconds |
Started | Jul 25 06:48:01 PM PDT 24 |
Finished | Jul 25 06:48:16 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-b20a114d-6417-4643-8f8b-c467881a090a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550310644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_partial_access.550310644 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.694220964 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 17611001214 ps |
CPU time | 359.62 seconds |
Started | Jul 25 06:48:00 PM PDT 24 |
Finished | Jul 25 06:54:00 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-1ca9657b-2191-4b53-a773-fe8e3b4ea82b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694220964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.sram_ctrl_partial_access_b2b.694220964 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.3453593375 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 1413838890 ps |
CPU time | 3.49 seconds |
Started | Jul 25 06:48:00 PM PDT 24 |
Finished | Jul 25 06:48:04 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-f490cebb-b08b-4ac8-a975-b0e2ea034609 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453593375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3453593375 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.391487443 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 11963006969 ps |
CPU time | 283.65 seconds |
Started | Jul 25 06:48:01 PM PDT 24 |
Finished | Jul 25 06:52:45 PM PDT 24 |
Peak memory | 328328 kb |
Host | smart-2a779242-e6e2-470c-9c3a-aabfde0afe21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391487443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.391487443 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.2784275974 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 1164121039 ps |
CPU time | 6.77 seconds |
Started | Jul 25 06:48:03 PM PDT 24 |
Finished | Jul 25 06:48:10 PM PDT 24 |
Peak memory | 219848 kb |
Host | smart-7686e2e6-01b0-4cef-9679-64b76fca73a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784275974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2784275974 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.531630251 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 86533023915 ps |
CPU time | 1530.1 seconds |
Started | Jul 25 06:48:08 PM PDT 24 |
Finished | Jul 25 07:13:38 PM PDT 24 |
Peak memory | 381120 kb |
Host | smart-736c4678-bb2d-41f9-b751-5fd8a0f97693 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531630251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_stress_all.531630251 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2241042884 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 2649813242 ps |
CPU time | 21.1 seconds |
Started | Jul 25 06:48:10 PM PDT 24 |
Finished | Jul 25 06:48:31 PM PDT 24 |
Peak memory | 211516 kb |
Host | smart-c2b2db6a-2580-48b8-861d-e451cf11f978 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2241042884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2241042884 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1492559497 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 13529376784 ps |
CPU time | 272.31 seconds |
Started | Jul 25 06:48:02 PM PDT 24 |
Finished | Jul 25 06:52:34 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-bf133d37-964b-4738-ba5a-1ac9de70fa60 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492559497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.1492559497 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1501828307 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 820021607 ps |
CPU time | 135.04 seconds |
Started | Jul 25 06:48:02 PM PDT 24 |
Finished | Jul 25 06:50:17 PM PDT 24 |
Peak memory | 370712 kb |
Host | smart-ffaa1078-5570-4558-b513-d674d0be65ac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501828307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.1501828307 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1572323796 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 152756524377 ps |
CPU time | 530.93 seconds |
Started | Jul 25 06:48:09 PM PDT 24 |
Finished | Jul 25 06:57:00 PM PDT 24 |
Peak memory | 369780 kb |
Host | smart-e14263df-2432-432b-b867-7c0890a28d34 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572323796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.1572323796 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.920523555 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 39180702 ps |
CPU time | 0.72 seconds |
Started | Jul 25 06:48:29 PM PDT 24 |
Finished | Jul 25 06:48:30 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-e9643cde-2f5f-460d-8094-ee53fa8fa459 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920523555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.920523555 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.792353275 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 473324658505 ps |
CPU time | 2195.92 seconds |
Started | Jul 25 06:48:11 PM PDT 24 |
Finished | Jul 25 07:24:47 PM PDT 24 |
Peak memory | 203860 kb |
Host | smart-14c6a67f-a11b-4fb9-b0bb-9c099eb8f335 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792353275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection. 792353275 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.990840626 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 56370063451 ps |
CPU time | 1426.13 seconds |
Started | Jul 25 06:48:10 PM PDT 24 |
Finished | Jul 25 07:11:56 PM PDT 24 |
Peak memory | 378008 kb |
Host | smart-bd0f1901-1be5-48d5-a1a4-5453ea882bb4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990840626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl e.990840626 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.2576293665 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 46339673673 ps |
CPU time | 87.26 seconds |
Started | Jul 25 06:48:12 PM PDT 24 |
Finished | Jul 25 06:49:40 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-6527c43b-2727-400f-bd5e-9d327aa3cbb9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576293665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.2576293665 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.1296609889 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 1680601235 ps |
CPU time | 7.37 seconds |
Started | Jul 25 06:48:15 PM PDT 24 |
Finished | Jul 25 06:48:22 PM PDT 24 |
Peak memory | 212260 kb |
Host | smart-9b5a3f40-fe67-43fa-87cf-2984a6c78eb5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296609889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.1296609889 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.340313623 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 2809845012 ps |
CPU time | 125.08 seconds |
Started | Jul 25 06:48:17 PM PDT 24 |
Finished | Jul 25 06:50:22 PM PDT 24 |
Peak memory | 211428 kb |
Host | smart-a8b7475b-499d-4e69-9d0f-913c2a4fb538 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340313623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17 .sram_ctrl_mem_partial_access.340313623 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.683461844 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 230647990900 ps |
CPU time | 384.77 seconds |
Started | Jul 25 06:48:20 PM PDT 24 |
Finished | Jul 25 06:54:45 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-2e6caa50-8088-42f5-8cdc-d612e63857d3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683461844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _mem_walk.683461844 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.1999489800 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 2951430669 ps |
CPU time | 146.77 seconds |
Started | Jul 25 06:48:12 PM PDT 24 |
Finished | Jul 25 06:50:39 PM PDT 24 |
Peak memory | 306528 kb |
Host | smart-11afb442-7f3a-454d-a45a-19a7693e1a0c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999489800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1999489800 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.3019274432 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 6392418868 ps |
CPU time | 101.3 seconds |
Started | Jul 25 06:48:09 PM PDT 24 |
Finished | Jul 25 06:49:50 PM PDT 24 |
Peak memory | 336132 kb |
Host | smart-5bbfce08-85f3-457d-9ea1-d23fab04cad6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019274432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.3019274432 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4133966272 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 24256945691 ps |
CPU time | 317.93 seconds |
Started | Jul 25 06:48:09 PM PDT 24 |
Finished | Jul 25 06:53:27 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-f04ebee2-93f4-40de-9e28-999997fe7fc6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133966272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.4133966272 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.3127732825 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 360135437 ps |
CPU time | 3.14 seconds |
Started | Jul 25 06:48:25 PM PDT 24 |
Finished | Jul 25 06:48:29 PM PDT 24 |
Peak memory | 203084 kb |
Host | smart-9a79aba2-d885-4e28-bacb-838cfcac4065 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127732825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3127732825 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.3791063978 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 3678170617 ps |
CPU time | 1275.31 seconds |
Started | Jul 25 06:48:10 PM PDT 24 |
Finished | Jul 25 07:09:25 PM PDT 24 |
Peak memory | 380068 kb |
Host | smart-e67bf280-08c4-45f5-a120-3c28a63170c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791063978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3791063978 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.2794689180 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 4493972968 ps |
CPU time | 16.81 seconds |
Started | Jul 25 06:48:09 PM PDT 24 |
Finished | Jul 25 06:48:26 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-f595a3a7-8ed2-46a0-a79d-04e42a5943dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794689180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2794689180 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.1426061177 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 78615250997 ps |
CPU time | 3759.16 seconds |
Started | Jul 25 06:48:27 PM PDT 24 |
Finished | Jul 25 07:51:07 PM PDT 24 |
Peak memory | 380104 kb |
Host | smart-75b53648-99cc-41da-b51a-dc78ccdd4997 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426061177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.1426061177 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3777500112 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 1640585621 ps |
CPU time | 137.9 seconds |
Started | Jul 25 06:48:25 PM PDT 24 |
Finished | Jul 25 06:50:43 PM PDT 24 |
Peak memory | 306508 kb |
Host | smart-9d924056-ffb6-49dc-9cf3-8fabcf29c06f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3777500112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.3777500112 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.829261785 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 3844464292 ps |
CPU time | 261.35 seconds |
Started | Jul 25 06:48:09 PM PDT 24 |
Finished | Jul 25 06:52:31 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-55135164-2e7c-4017-bb43-6dcf822dfbcf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829261785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17 .sram_ctrl_stress_pipeline.829261785 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4102732995 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 3262718570 ps |
CPU time | 98.91 seconds |
Started | Jul 25 06:48:10 PM PDT 24 |
Finished | Jul 25 06:49:49 PM PDT 24 |
Peak memory | 371928 kb |
Host | smart-f934078d-f49d-4e5c-83ab-7fda26470b96 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102732995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.4102732995 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1751682898 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 57714089814 ps |
CPU time | 1070.5 seconds |
Started | Jul 25 06:48:25 PM PDT 24 |
Finished | Jul 25 07:06:16 PM PDT 24 |
Peak memory | 379084 kb |
Host | smart-326a413e-5e27-4c49-b648-49c6350ce455 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751682898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.1751682898 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.445473326 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 50307112 ps |
CPU time | 0.69 seconds |
Started | Jul 25 06:48:26 PM PDT 24 |
Finished | Jul 25 06:48:27 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-d08a6ec5-4776-4a16-9375-a13c7a51b3f5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445473326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.445473326 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.2999254881 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 536552670860 ps |
CPU time | 2683.58 seconds |
Started | Jul 25 06:48:24 PM PDT 24 |
Finished | Jul 25 07:33:08 PM PDT 24 |
Peak memory | 203968 kb |
Host | smart-8f56dce2-cad9-4520-9830-27b901df147a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999254881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .2999254881 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.1846464986 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 12942936939 ps |
CPU time | 659.64 seconds |
Started | Jul 25 06:48:33 PM PDT 24 |
Finished | Jul 25 06:59:33 PM PDT 24 |
Peak memory | 372964 kb |
Host | smart-2ab1c644-8023-4f96-98d6-39dc063c5e35 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846464986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.1846464986 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.4097104122 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 64528588065 ps |
CPU time | 115.47 seconds |
Started | Jul 25 06:48:26 PM PDT 24 |
Finished | Jul 25 06:50:22 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-7c8e800a-32d1-479e-a565-c18800ec771d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097104122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.4097104122 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.1801864245 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 2928553370 ps |
CPU time | 21.15 seconds |
Started | Jul 25 06:48:24 PM PDT 24 |
Finished | Jul 25 06:48:45 PM PDT 24 |
Peak memory | 261792 kb |
Host | smart-28c645f6-e93b-4f84-b55b-ec907d849b21 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801864245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.1801864245 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1895361903 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 1916925594 ps |
CPU time | 65.63 seconds |
Started | Jul 25 06:48:25 PM PDT 24 |
Finished | Jul 25 06:49:31 PM PDT 24 |
Peak memory | 211332 kb |
Host | smart-49b317af-712a-46b7-8226-d8ef3a1ac57f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895361903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.1895361903 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.3817601116 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 5369851303 ps |
CPU time | 151.47 seconds |
Started | Jul 25 06:48:24 PM PDT 24 |
Finished | Jul 25 06:50:56 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-6f206241-f727-4ebc-88f0-7a70a68404a1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817601116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3817601116 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.4193980755 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 23582908090 ps |
CPU time | 1142.94 seconds |
Started | Jul 25 06:48:24 PM PDT 24 |
Finished | Jul 25 07:07:27 PM PDT 24 |
Peak memory | 381216 kb |
Host | smart-fdb39f7b-83ab-48bc-b07b-820dbde4b339 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193980755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.4193980755 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.3053170318 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 1385702776 ps |
CPU time | 17.72 seconds |
Started | Jul 25 06:48:26 PM PDT 24 |
Finished | Jul 25 06:48:44 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-8e380ea8-f0ed-40aa-b75c-913d4393d21c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053170318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.3053170318 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1324966623 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 31365915455 ps |
CPU time | 292 seconds |
Started | Jul 25 06:48:24 PM PDT 24 |
Finished | Jul 25 06:53:16 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-5e5d6414-40a4-4700-8f4e-fa5a063a7770 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324966623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.1324966623 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.2087321122 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 2246384059 ps |
CPU time | 3.52 seconds |
Started | Jul 25 06:48:26 PM PDT 24 |
Finished | Jul 25 06:48:29 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-99499dcb-3233-45a2-b1ac-4160c10048cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087321122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2087321122 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.1626916764 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 2861302670 ps |
CPU time | 7.14 seconds |
Started | Jul 25 06:48:26 PM PDT 24 |
Finished | Jul 25 06:48:33 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-20462ec2-05e4-4839-acc7-a4e9368cd351 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626916764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1626916764 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.1540194394 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 8195487155 ps |
CPU time | 79.36 seconds |
Started | Jul 25 06:48:25 PM PDT 24 |
Finished | Jul 25 06:49:44 PM PDT 24 |
Peak memory | 339100 kb |
Host | smart-57e54eb6-68e0-4d84-bd93-cda03d629c40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540194394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1540194394 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.1843372481 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 126246335285 ps |
CPU time | 3342.74 seconds |
Started | Jul 25 06:48:32 PM PDT 24 |
Finished | Jul 25 07:44:15 PM PDT 24 |
Peak memory | 378996 kb |
Host | smart-696a052d-9c45-42cb-b2fe-078c232df716 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843372481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.1843372481 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.636419208 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 10586612025 ps |
CPU time | 320.06 seconds |
Started | Jul 25 06:48:18 PM PDT 24 |
Finished | Jul 25 06:53:39 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-728985aa-48af-4aaa-93b1-734e4bf76f83 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636419208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sram_ctrl_stress_pipeline.636419208 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2134070587 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 772091137 ps |
CPU time | 51.43 seconds |
Started | Jul 25 06:48:25 PM PDT 24 |
Finished | Jul 25 06:49:17 PM PDT 24 |
Peak memory | 317664 kb |
Host | smart-1456b054-2d0b-4fe8-8f95-5eb78504a2eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134070587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.2134070587 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.338674312 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 12129075296 ps |
CPU time | 656.72 seconds |
Started | Jul 25 06:48:33 PM PDT 24 |
Finished | Jul 25 06:59:30 PM PDT 24 |
Peak memory | 371936 kb |
Host | smart-3a4a9fcd-ef0b-4aec-8e32-0b0ab5607d73 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338674312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_access_during_key_req.338674312 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.247577937 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 18712679 ps |
CPU time | 0.62 seconds |
Started | Jul 25 06:48:32 PM PDT 24 |
Finished | Jul 25 06:48:33 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-da454958-5f9d-4144-88b9-2f4c5e548153 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247577937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.247577937 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.1978417152 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 316853656734 ps |
CPU time | 1262.52 seconds |
Started | Jul 25 06:48:27 PM PDT 24 |
Finished | Jul 25 07:09:30 PM PDT 24 |
Peak memory | 203408 kb |
Host | smart-e0ad0657-3a5a-4437-a660-10bcee66984e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978417152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .1978417152 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.1233538967 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 53519765002 ps |
CPU time | 1132.12 seconds |
Started | Jul 25 06:48:31 PM PDT 24 |
Finished | Jul 25 07:07:24 PM PDT 24 |
Peak memory | 380100 kb |
Host | smart-89379dc2-1b8f-4872-b169-14635bbaf3de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233538967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.1233538967 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.1094398155 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 37733262599 ps |
CPU time | 117.69 seconds |
Started | Jul 25 06:48:34 PM PDT 24 |
Finished | Jul 25 06:50:32 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-035e5fe2-c36a-4139-b02f-3b1e267a01a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094398155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.1094398155 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.3765190797 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 784021958 ps |
CPU time | 91.51 seconds |
Started | Jul 25 06:48:26 PM PDT 24 |
Finished | Jul 25 06:49:57 PM PDT 24 |
Peak memory | 351320 kb |
Host | smart-15fe9ca9-07bf-44bb-9236-0e8222846ae2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765190797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.3765190797 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.95751401 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 5690008757 ps |
CPU time | 125.56 seconds |
Started | Jul 25 06:48:32 PM PDT 24 |
Finished | Jul 25 06:50:38 PM PDT 24 |
Peak memory | 219484 kb |
Host | smart-e9c51dc9-4841-4b75-af32-430ae8bead1a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95751401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_mem_partial_access.95751401 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.1022961467 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 8434697694 ps |
CPU time | 152.21 seconds |
Started | Jul 25 06:48:34 PM PDT 24 |
Finished | Jul 25 06:51:06 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-7611711d-519d-4d12-a28d-7c2c9aa60e79 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022961467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.1022961467 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.2446145458 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 18352197244 ps |
CPU time | 363.68 seconds |
Started | Jul 25 06:48:25 PM PDT 24 |
Finished | Jul 25 06:54:29 PM PDT 24 |
Peak memory | 351240 kb |
Host | smart-b3a18743-eb32-43ae-9019-1d7676417058 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446145458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.2446145458 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.801230372 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 1646641337 ps |
CPU time | 12.46 seconds |
Started | Jul 25 06:48:25 PM PDT 24 |
Finished | Jul 25 06:48:38 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-86f1ec08-be8c-4f79-93da-fc62dd36985b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801230372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s ram_ctrl_partial_access.801230372 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.906405462 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 19233721354 ps |
CPU time | 289.81 seconds |
Started | Jul 25 06:48:27 PM PDT 24 |
Finished | Jul 25 06:53:17 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-4ee1e4ff-e2ae-48b4-8710-4a9b5845111a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906405462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.sram_ctrl_partial_access_b2b.906405462 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.3643013846 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 1408119162 ps |
CPU time | 3.55 seconds |
Started | Jul 25 06:48:31 PM PDT 24 |
Finished | Jul 25 06:48:34 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-cd70bef0-389d-46c5-a27a-4392531f7eef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643013846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3643013846 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.131523829 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 2215950581 ps |
CPU time | 15.42 seconds |
Started | Jul 25 06:48:24 PM PDT 24 |
Finished | Jul 25 06:48:40 PM PDT 24 |
Peak memory | 252244 kb |
Host | smart-3a45eeeb-3c43-4308-b5e0-e861f25114bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131523829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.131523829 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.4014621003 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 1045422828318 ps |
CPU time | 6433.76 seconds |
Started | Jul 25 06:48:33 PM PDT 24 |
Finished | Jul 25 08:35:48 PM PDT 24 |
Peak memory | 388316 kb |
Host | smart-5410e5f8-d052-4eb4-a53b-a892ee6b0118 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014621003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.4014621003 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3804432741 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 426325613 ps |
CPU time | 8.53 seconds |
Started | Jul 25 06:48:33 PM PDT 24 |
Finished | Jul 25 06:48:42 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-6665a52b-d38d-4400-b631-9b88e4b7948e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3804432741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3804432741 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2058964632 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 2988924902 ps |
CPU time | 170.12 seconds |
Started | Jul 25 06:48:25 PM PDT 24 |
Finished | Jul 25 06:51:15 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-8a5f69fb-b0cd-435a-bf43-187d6c8ca99b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058964632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.2058964632 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3332761848 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 3073706673 ps |
CPU time | 72.43 seconds |
Started | Jul 25 06:48:33 PM PDT 24 |
Finished | Jul 25 06:49:46 PM PDT 24 |
Peak memory | 352312 kb |
Host | smart-88aecc57-8eb6-48b0-afa9-d58662564f1e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332761848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3332761848 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.93524520 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 41957909099 ps |
CPU time | 1279.84 seconds |
Started | Jul 25 06:45:58 PM PDT 24 |
Finished | Jul 25 07:07:19 PM PDT 24 |
Peak memory | 378128 kb |
Host | smart-db38dafa-2fb1-4937-98d7-59008f91d5d2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93524520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.sram_ctrl_access_during_key_req.93524520 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.1230035818 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 48645758 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:45:48 PM PDT 24 |
Finished | Jul 25 06:45:48 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-3cef08af-8902-4e3e-b4fe-75224643abcf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230035818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.1230035818 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.2427545161 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 119985531890 ps |
CPU time | 2673.5 seconds |
Started | Jul 25 06:45:42 PM PDT 24 |
Finished | Jul 25 07:30:16 PM PDT 24 |
Peak memory | 203524 kb |
Host | smart-d733b136-35f7-4756-a664-4c5f5ebbb9fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427545161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 2427545161 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.1597048634 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 82488524213 ps |
CPU time | 903.19 seconds |
Started | Jul 25 06:45:47 PM PDT 24 |
Finished | Jul 25 07:00:51 PM PDT 24 |
Peak memory | 380100 kb |
Host | smart-0563d925-75eb-4711-90e6-899bdc62c0e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597048634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.1597048634 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.1216186305 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 9087023612 ps |
CPU time | 46.6 seconds |
Started | Jul 25 06:45:48 PM PDT 24 |
Finished | Jul 25 06:46:35 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-b50293fc-cef9-43ac-a416-f9345a3b228a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216186305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.1216186305 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.3329481554 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 3120108762 ps |
CPU time | 85.35 seconds |
Started | Jul 25 06:45:48 PM PDT 24 |
Finished | Jul 25 06:47:14 PM PDT 24 |
Peak memory | 342356 kb |
Host | smart-c9a480b7-da3e-4ca6-82d3-ac03dd59adc7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329481554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.3329481554 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3307348655 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 1634609179 ps |
CPU time | 121.91 seconds |
Started | Jul 25 06:45:48 PM PDT 24 |
Finished | Jul 25 06:47:50 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-049c58b0-106f-49e7-b1c0-f2b5dbb41894 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307348655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.3307348655 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.4118715452 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 2017555421 ps |
CPU time | 124.04 seconds |
Started | Jul 25 06:45:46 PM PDT 24 |
Finished | Jul 25 06:47:51 PM PDT 24 |
Peak memory | 211316 kb |
Host | smart-3f560f83-1c78-4e9a-aef1-f855d1e967f4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118715452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.4118715452 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.1865706835 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 38418068548 ps |
CPU time | 1481.58 seconds |
Started | Jul 25 06:45:41 PM PDT 24 |
Finished | Jul 25 07:10:23 PM PDT 24 |
Peak memory | 381496 kb |
Host | smart-3900cac9-23e7-46a3-8f02-4572a39ce631 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865706835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.1865706835 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.3597055632 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 9390886299 ps |
CPU time | 15.27 seconds |
Started | Jul 25 06:45:41 PM PDT 24 |
Finished | Jul 25 06:45:56 PM PDT 24 |
Peak memory | 237764 kb |
Host | smart-9ac1d524-0763-42bc-a70d-5cf67513452e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597055632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.3597055632 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2191563732 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 75081463057 ps |
CPU time | 414.96 seconds |
Started | Jul 25 06:45:48 PM PDT 24 |
Finished | Jul 25 06:52:43 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-ce88c397-287b-4f13-9e38-f06df5fc7149 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191563732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.2191563732 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.2035522078 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 697865821 ps |
CPU time | 3.27 seconds |
Started | Jul 25 06:45:47 PM PDT 24 |
Finished | Jul 25 06:45:50 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-4a1d5361-3dfb-4442-9690-420f955d9653 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035522078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2035522078 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.343713925 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 1891517562 ps |
CPU time | 124.55 seconds |
Started | Jul 25 06:45:50 PM PDT 24 |
Finished | Jul 25 06:47:54 PM PDT 24 |
Peak memory | 356448 kb |
Host | smart-2ec903ba-81bb-44a9-ae1e-3d8082ab48d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343713925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.343713925 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.4096173533 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 345995196 ps |
CPU time | 3.29 seconds |
Started | Jul 25 06:45:48 PM PDT 24 |
Finished | Jul 25 06:45:52 PM PDT 24 |
Peak memory | 222564 kb |
Host | smart-65b70319-dc82-40cc-ae00-ce1386fc077f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096173533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.4096173533 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.285476281 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 2953434020 ps |
CPU time | 7.49 seconds |
Started | Jul 25 06:45:43 PM PDT 24 |
Finished | Jul 25 06:45:50 PM PDT 24 |
Peak memory | 207172 kb |
Host | smart-fd8df5f2-0046-4c85-a455-7545ab1c0aab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285476281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.285476281 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.2146543714 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 536105611382 ps |
CPU time | 3690.74 seconds |
Started | Jul 25 06:45:54 PM PDT 24 |
Finished | Jul 25 07:47:25 PM PDT 24 |
Peak memory | 382152 kb |
Host | smart-0228a6fe-2bfa-4169-92ec-a91434c5859f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146543714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.2146543714 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3864321754 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 1696822775 ps |
CPU time | 22.07 seconds |
Started | Jul 25 06:45:50 PM PDT 24 |
Finished | Jul 25 06:46:12 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-c4eb8cf1-ce29-4c98-972c-ef0c26d15601 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3864321754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3864321754 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2412075837 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 20970492509 ps |
CPU time | 128.11 seconds |
Started | Jul 25 06:45:42 PM PDT 24 |
Finished | Jul 25 06:47:51 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-0a9bd1a6-134c-4d49-8be3-0eee9109bd44 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412075837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.2412075837 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1111184690 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 1595498011 ps |
CPU time | 146.71 seconds |
Started | Jul 25 06:45:47 PM PDT 24 |
Finished | Jul 25 06:48:14 PM PDT 24 |
Peak memory | 370836 kb |
Host | smart-fde7da1a-0e5f-4e00-8b75-cea71262e29e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111184690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1111184690 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.4266609595 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 31473356426 ps |
CPU time | 364.4 seconds |
Started | Jul 25 06:48:42 PM PDT 24 |
Finished | Jul 25 06:54:47 PM PDT 24 |
Peak memory | 362700 kb |
Host | smart-9f3c02e8-3330-484a-ae89-fd75aaeb4bd7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266609595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.4266609595 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.3191938378 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 16151771 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:48:42 PM PDT 24 |
Finished | Jul 25 06:48:43 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-49a5eabe-4650-48b6-8a50-d52450446a3f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191938378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.3191938378 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.3068859809 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 423866184222 ps |
CPU time | 1991.84 seconds |
Started | Jul 25 06:48:34 PM PDT 24 |
Finished | Jul 25 07:21:46 PM PDT 24 |
Peak memory | 204144 kb |
Host | smart-0e23b921-66d6-42a0-86c3-76c4aa490ff8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068859809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .3068859809 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.4052812164 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 39443828826 ps |
CPU time | 757.4 seconds |
Started | Jul 25 06:48:41 PM PDT 24 |
Finished | Jul 25 07:01:19 PM PDT 24 |
Peak memory | 380040 kb |
Host | smart-ec8851e0-cb98-4862-8938-8fbf22dfca34 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052812164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.4052812164 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.3524181947 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 35536468056 ps |
CPU time | 27.84 seconds |
Started | Jul 25 06:48:41 PM PDT 24 |
Finished | Jul 25 06:49:09 PM PDT 24 |
Peak memory | 212580 kb |
Host | smart-899dc031-b828-4eb3-868c-5a914fed5564 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524181947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.3524181947 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.198498650 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 2765555104 ps |
CPU time | 15.2 seconds |
Started | Jul 25 06:48:43 PM PDT 24 |
Finished | Jul 25 06:48:58 PM PDT 24 |
Peak memory | 252268 kb |
Host | smart-5256c42e-80cd-47fa-877c-585488c98bdc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198498650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.sram_ctrl_max_throughput.198498650 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.798990009 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 3860232687 ps |
CPU time | 63.93 seconds |
Started | Jul 25 06:48:41 PM PDT 24 |
Finished | Jul 25 06:49:45 PM PDT 24 |
Peak memory | 219528 kb |
Host | smart-bfa5df0f-6b6f-4987-9473-9b437cd88016 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798990009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20 .sram_ctrl_mem_partial_access.798990009 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.2671503622 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 10944316960 ps |
CPU time | 294.33 seconds |
Started | Jul 25 06:48:42 PM PDT 24 |
Finished | Jul 25 06:53:36 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-7fcfeb2c-25e1-4779-b5d1-c6ff2519da45 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671503622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.2671503622 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.1226986858 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 14065491836 ps |
CPU time | 2037.33 seconds |
Started | Jul 25 06:48:32 PM PDT 24 |
Finished | Jul 25 07:22:30 PM PDT 24 |
Peak memory | 381932 kb |
Host | smart-bc1d57c4-2585-4596-8534-15e5a3835209 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226986858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.1226986858 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.316522546 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 4132384433 ps |
CPU time | 17.45 seconds |
Started | Jul 25 06:48:48 PM PDT 24 |
Finished | Jul 25 06:49:06 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-79b7d5c4-23fc-461a-8e26-bea95574a77c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316522546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.s ram_ctrl_partial_access.316522546 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3148198807 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 95370044036 ps |
CPU time | 364.25 seconds |
Started | Jul 25 06:48:42 PM PDT 24 |
Finished | Jul 25 06:54:47 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-4a4ff168-5b66-4318-9a01-974334ad5673 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148198807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.3148198807 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.3280252432 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 684056688 ps |
CPU time | 3.26 seconds |
Started | Jul 25 06:48:41 PM PDT 24 |
Finished | Jul 25 06:48:45 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-4c3a8210-bd4e-4396-a923-047c08f6ae70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280252432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3280252432 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.3935191463 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 27644969304 ps |
CPU time | 957.26 seconds |
Started | Jul 25 06:48:41 PM PDT 24 |
Finished | Jul 25 07:04:38 PM PDT 24 |
Peak memory | 380116 kb |
Host | smart-06b9d055-aef5-4aad-858c-0d81dc89a47f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935191463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3935191463 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.2516397685 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 3027071395 ps |
CPU time | 85.63 seconds |
Started | Jul 25 06:48:33 PM PDT 24 |
Finished | Jul 25 06:49:59 PM PDT 24 |
Peak memory | 343220 kb |
Host | smart-c3b76ebc-722c-4668-9e09-1686e3b0cd97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516397685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2516397685 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.4167777948 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 412453240117 ps |
CPU time | 7150.71 seconds |
Started | Jul 25 06:48:42 PM PDT 24 |
Finished | Jul 25 08:47:53 PM PDT 24 |
Peak memory | 334424 kb |
Host | smart-897b826a-8580-4c16-b790-e7d15ee6e082 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167777948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.4167777948 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.681726596 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 955702858 ps |
CPU time | 11.23 seconds |
Started | Jul 25 06:48:41 PM PDT 24 |
Finished | Jul 25 06:48:52 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-7f14a2f1-8c8c-44c0-9cdd-cdd1e957c39a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=681726596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.681726596 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.4098271635 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 9216257671 ps |
CPU time | 293.15 seconds |
Started | Jul 25 06:48:34 PM PDT 24 |
Finished | Jul 25 06:53:27 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-ad58c35f-2a57-4e2b-b767-e74abd153967 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098271635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.4098271635 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.583130054 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 1291133132 ps |
CPU time | 61.92 seconds |
Started | Jul 25 06:48:42 PM PDT 24 |
Finished | Jul 25 06:49:44 PM PDT 24 |
Peak memory | 341140 kb |
Host | smart-37acccb1-f8bd-412e-b8e5-14692079c998 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583130054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.583130054 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3123899408 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 13234567170 ps |
CPU time | 828.61 seconds |
Started | Jul 25 06:48:53 PM PDT 24 |
Finished | Jul 25 07:02:42 PM PDT 24 |
Peak memory | 364780 kb |
Host | smart-6185df54-255f-4e32-9289-917c11227bee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123899408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.3123899408 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.3478605007 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 41464553 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:48:51 PM PDT 24 |
Finished | Jul 25 06:48:51 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-f62a247c-0b76-4778-a7a5-3a00ed1688d6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478605007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.3478605007 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.3249614705 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 23983144776 ps |
CPU time | 1501.03 seconds |
Started | Jul 25 06:48:49 PM PDT 24 |
Finished | Jul 25 07:13:51 PM PDT 24 |
Peak memory | 203500 kb |
Host | smart-c6784550-0434-4cc8-80ca-4618dc1702ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249614705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .3249614705 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.3789125542 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 24485680280 ps |
CPU time | 182.15 seconds |
Started | Jul 25 06:48:48 PM PDT 24 |
Finished | Jul 25 06:51:50 PM PDT 24 |
Peak memory | 231768 kb |
Host | smart-2940d648-0f7b-4134-b460-956ea5102d53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789125542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.3789125542 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.2532094407 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 51088243845 ps |
CPU time | 67.68 seconds |
Started | Jul 25 06:48:49 PM PDT 24 |
Finished | Jul 25 06:49:57 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-49c8693f-9d56-400e-a8ef-d8a1796ca8f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532094407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.2532094407 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.2635146755 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 688661730 ps |
CPU time | 9.72 seconds |
Started | Jul 25 06:48:53 PM PDT 24 |
Finished | Jul 25 06:49:03 PM PDT 24 |
Peak memory | 226924 kb |
Host | smart-da2c7556-4b0b-498b-b881-60623ede0314 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635146755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.2635146755 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.794813547 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 2549714088 ps |
CPU time | 144.73 seconds |
Started | Jul 25 06:48:48 PM PDT 24 |
Finished | Jul 25 06:51:13 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-df5aa896-7811-4b49-b27e-f89b478627df |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794813547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_mem_partial_access.794813547 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.2304701988 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 6804967236 ps |
CPU time | 126.45 seconds |
Started | Jul 25 06:48:49 PM PDT 24 |
Finished | Jul 25 06:50:55 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-62791839-3e69-4200-913d-e1432d5158fd |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304701988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.2304701988 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.1920010456 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 10058971313 ps |
CPU time | 1243.58 seconds |
Started | Jul 25 06:48:43 PM PDT 24 |
Finished | Jul 25 07:09:27 PM PDT 24 |
Peak memory | 379040 kb |
Host | smart-ed9b7a4a-cd0c-4806-9522-c0c920c9a311 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920010456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.1920010456 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.1742568815 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 420102823 ps |
CPU time | 7.29 seconds |
Started | Jul 25 06:48:50 PM PDT 24 |
Finished | Jul 25 06:48:58 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-967627c3-c236-4c20-b18a-5c51ffad7476 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742568815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.1742568815 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.103647215 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 27350562923 ps |
CPU time | 305.3 seconds |
Started | Jul 25 06:48:50 PM PDT 24 |
Finished | Jul 25 06:53:56 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-bf2bec6c-b94a-4d04-b951-9a38fca36a8a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103647215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 21.sram_ctrl_partial_access_b2b.103647215 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.2267144069 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 1416547221 ps |
CPU time | 3.59 seconds |
Started | Jul 25 06:48:50 PM PDT 24 |
Finished | Jul 25 06:48:54 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-23ba874f-298e-46d0-85ac-3926ce2234bd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267144069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2267144069 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.1321445107 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 18568961516 ps |
CPU time | 1475.42 seconds |
Started | Jul 25 06:48:50 PM PDT 24 |
Finished | Jul 25 07:13:26 PM PDT 24 |
Peak memory | 376016 kb |
Host | smart-89e23fab-5ecc-4e0f-82d3-6f37ebefc0c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321445107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1321445107 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.3791524569 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 960113251 ps |
CPU time | 4.3 seconds |
Started | Jul 25 06:48:41 PM PDT 24 |
Finished | Jul 25 06:48:46 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-33ad399d-f5eb-4fb6-8486-fd0ddc6b0074 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791524569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3791524569 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.456293406 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 403179125157 ps |
CPU time | 4875.57 seconds |
Started | Jul 25 06:48:50 PM PDT 24 |
Finished | Jul 25 08:10:06 PM PDT 24 |
Peak memory | 382204 kb |
Host | smart-ccb0db3e-1b7c-4285-a6f6-658801420a6b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456293406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_stress_all.456293406 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3556471581 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 5150913292 ps |
CPU time | 31.07 seconds |
Started | Jul 25 06:48:51 PM PDT 24 |
Finished | Jul 25 06:49:22 PM PDT 24 |
Peak memory | 211492 kb |
Host | smart-577cb008-4277-4114-96e7-3b39101a7f0c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3556471581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3556471581 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3115610509 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 15858188704 ps |
CPU time | 157.73 seconds |
Started | Jul 25 06:48:49 PM PDT 24 |
Finished | Jul 25 06:51:27 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-7dd23579-3bc0-4175-b6d2-5a38c6c74b26 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115610509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.3115610509 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.910831443 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 3228575703 ps |
CPU time | 95.17 seconds |
Started | Jul 25 06:48:54 PM PDT 24 |
Finished | Jul 25 06:50:29 PM PDT 24 |
Peak memory | 361664 kb |
Host | smart-eea90e50-b5ec-4d2c-b668-5dcbfce27675 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910831443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.910831443 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3285852351 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 4233689640 ps |
CPU time | 153.56 seconds |
Started | Jul 25 06:49:05 PM PDT 24 |
Finished | Jul 25 06:51:39 PM PDT 24 |
Peak memory | 324908 kb |
Host | smart-d91a8e7a-51eb-4db8-a026-043e0dbc5570 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285852351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.3285852351 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.214401497 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 39455688 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:49:06 PM PDT 24 |
Finished | Jul 25 06:49:07 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-2a31e69d-8a19-45b8-a604-d8264de1fe4b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214401497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.214401497 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.2221144507 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 48135097074 ps |
CPU time | 1609.49 seconds |
Started | Jul 25 06:49:05 PM PDT 24 |
Finished | Jul 25 07:15:55 PM PDT 24 |
Peak memory | 203904 kb |
Host | smart-c7589000-e46d-41fc-8165-68ded1c1f82e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221144507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .2221144507 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.1071928398 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 110072225260 ps |
CPU time | 1256.39 seconds |
Started | Jul 25 06:49:02 PM PDT 24 |
Finished | Jul 25 07:09:58 PM PDT 24 |
Peak memory | 374948 kb |
Host | smart-e0b77825-1841-4c26-9281-c93d70834287 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071928398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.1071928398 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.1852209799 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 40774919927 ps |
CPU time | 55.42 seconds |
Started | Jul 25 06:49:05 PM PDT 24 |
Finished | Jul 25 06:50:01 PM PDT 24 |
Peak memory | 216144 kb |
Host | smart-729cc321-e099-4229-9c9b-8eb4a04f1d7a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852209799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.1852209799 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.3786734343 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 1444553569 ps |
CPU time | 38.76 seconds |
Started | Jul 25 06:49:04 PM PDT 24 |
Finished | Jul 25 06:49:42 PM PDT 24 |
Peak memory | 291052 kb |
Host | smart-3dc638ce-7209-4c13-a27d-9dd274790ae3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786734343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.3786734343 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.565346391 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 1014223117 ps |
CPU time | 64.3 seconds |
Started | Jul 25 06:49:01 PM PDT 24 |
Finished | Jul 25 06:50:06 PM PDT 24 |
Peak memory | 219456 kb |
Host | smart-8f77b3f0-1056-47c2-b9ed-e31c208d371b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565346391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_mem_partial_access.565346391 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.4188736624 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 58354024738 ps |
CPU time | 329.46 seconds |
Started | Jul 25 06:49:02 PM PDT 24 |
Finished | Jul 25 06:54:32 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-3005b969-5d09-4fa4-a1e2-86f05395f7d7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188736624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.4188736624 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.1562625015 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 9341340368 ps |
CPU time | 1052.1 seconds |
Started | Jul 25 06:49:01 PM PDT 24 |
Finished | Jul 25 07:06:33 PM PDT 24 |
Peak memory | 380072 kb |
Host | smart-31861fff-4fa9-4c6c-a406-eb8bf78200d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562625015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.1562625015 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.1541683561 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 1283913720 ps |
CPU time | 16.56 seconds |
Started | Jul 25 06:49:02 PM PDT 24 |
Finished | Jul 25 06:49:19 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-686bc893-0abd-48d9-9ce3-c9c4b18091ce |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541683561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.1541683561 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2868897954 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 20312218836 ps |
CPU time | 445.91 seconds |
Started | Jul 25 06:49:05 PM PDT 24 |
Finished | Jul 25 06:56:31 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-8ae882c6-29f8-4b42-80ef-d90e22ba6758 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868897954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.2868897954 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.3043031207 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 801489432 ps |
CPU time | 3.4 seconds |
Started | Jul 25 06:49:05 PM PDT 24 |
Finished | Jul 25 06:49:09 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-a8535db3-712a-4e17-bff8-5dfe87b5f78b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043031207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3043031207 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.1304991228 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 34439440742 ps |
CPU time | 704.3 seconds |
Started | Jul 25 06:49:01 PM PDT 24 |
Finished | Jul 25 07:00:46 PM PDT 24 |
Peak memory | 379680 kb |
Host | smart-5518f780-7a92-4ba5-9076-0391a7cfdf78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304991228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1304991228 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.2886756050 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 511166730 ps |
CPU time | 15.82 seconds |
Started | Jul 25 06:48:48 PM PDT 24 |
Finished | Jul 25 06:49:04 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-2bbf4a78-2025-4586-b4a7-3000b0768e40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886756050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2886756050 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.3030512824 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 124757219094 ps |
CPU time | 8480.81 seconds |
Started | Jul 25 06:49:05 PM PDT 24 |
Finished | Jul 25 09:10:26 PM PDT 24 |
Peak memory | 388388 kb |
Host | smart-ba78e93c-bd42-4069-9141-7bf5a5b800bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030512824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.3030512824 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4011815894 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 830071274 ps |
CPU time | 28.07 seconds |
Started | Jul 25 06:49:02 PM PDT 24 |
Finished | Jul 25 06:49:30 PM PDT 24 |
Peak memory | 211824 kb |
Host | smart-beca3402-fc54-4263-bfbb-2137d296371e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4011815894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.4011815894 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2791631358 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 18154400514 ps |
CPU time | 204.2 seconds |
Started | Jul 25 06:49:02 PM PDT 24 |
Finished | Jul 25 06:52:26 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-2911a439-9068-4bbe-9b19-32696f1448bd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791631358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.2791631358 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.4244223729 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1491048972 ps |
CPU time | 21.92 seconds |
Started | Jul 25 06:49:05 PM PDT 24 |
Finished | Jul 25 06:49:27 PM PDT 24 |
Peak memory | 271660 kb |
Host | smart-86085a0a-0bde-4fa7-af68-3cf1a391e78b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244223729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.4244223729 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1127026995 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 49258967518 ps |
CPU time | 1103.32 seconds |
Started | Jul 25 06:49:13 PM PDT 24 |
Finished | Jul 25 07:07:37 PM PDT 24 |
Peak memory | 379092 kb |
Host | smart-26c21ad0-f614-4c9c-8ac5-f47772d74af0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127026995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.1127026995 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.3627219549 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 83859606 ps |
CPU time | 0.69 seconds |
Started | Jul 25 06:49:15 PM PDT 24 |
Finished | Jul 25 06:49:16 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-6f5edab2-74fb-4ed8-bed1-c19597cf97de |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627219549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3627219549 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.3683772726 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 21658058804 ps |
CPU time | 770.94 seconds |
Started | Jul 25 06:49:13 PM PDT 24 |
Finished | Jul 25 07:02:04 PM PDT 24 |
Peak memory | 203900 kb |
Host | smart-6e7a5043-ec80-487d-9398-184b1503aab7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683772726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .3683772726 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.863920775 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 72765079351 ps |
CPU time | 951.05 seconds |
Started | Jul 25 06:49:12 PM PDT 24 |
Finished | Jul 25 07:05:04 PM PDT 24 |
Peak memory | 360684 kb |
Host | smart-ef519f0e-32c1-48d5-aa7f-72a1a62b77d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863920775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executabl e.863920775 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.3349037854 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 18730877911 ps |
CPU time | 104.43 seconds |
Started | Jul 25 06:49:12 PM PDT 24 |
Finished | Jul 25 06:50:57 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-f9ba7e48-7301-4be6-8a1b-87d1a9d6ea98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349037854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.3349037854 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.1798357371 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 751463398 ps |
CPU time | 25.16 seconds |
Started | Jul 25 06:49:12 PM PDT 24 |
Finished | Jul 25 06:49:38 PM PDT 24 |
Peak memory | 277120 kb |
Host | smart-223662fd-be56-4322-bd0c-134f2d2ed1a5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798357371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.1798357371 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1384003058 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 1598972785 ps |
CPU time | 130.27 seconds |
Started | Jul 25 06:49:14 PM PDT 24 |
Finished | Jul 25 06:51:25 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-6e64c626-a43d-4e66-8e02-ba531b7c87d2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384003058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.1384003058 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.2576792947 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 82867415872 ps |
CPU time | 355.6 seconds |
Started | Jul 25 06:49:16 PM PDT 24 |
Finished | Jul 25 06:55:12 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-4de1201e-25e0-46ee-979c-428413e60e10 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576792947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.2576792947 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.3366344768 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 21795832841 ps |
CPU time | 375.47 seconds |
Started | Jul 25 06:49:14 PM PDT 24 |
Finished | Jul 25 06:55:30 PM PDT 24 |
Peak memory | 358736 kb |
Host | smart-ee75f391-6e84-411b-abb6-60a9b2447034 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366344768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.3366344768 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.4235407745 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 535927930 ps |
CPU time | 104.98 seconds |
Started | Jul 25 06:49:13 PM PDT 24 |
Finished | Jul 25 06:50:58 PM PDT 24 |
Peak memory | 361596 kb |
Host | smart-2e058c59-b2b9-41d3-86cc-39f05a1058b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235407745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.4235407745 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1130819748 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 13733777963 ps |
CPU time | 321.17 seconds |
Started | Jul 25 06:49:13 PM PDT 24 |
Finished | Jul 25 06:54:35 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-154ad254-b5e7-42d5-8a76-5b1eaaca61bf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130819748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.1130819748 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.1999337804 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 345094621 ps |
CPU time | 3.36 seconds |
Started | Jul 25 06:49:13 PM PDT 24 |
Finished | Jul 25 06:49:17 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-6fecef03-07eb-4040-8985-f0e169ec1821 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999337804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1999337804 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.3705402538 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 7524471770 ps |
CPU time | 147.55 seconds |
Started | Jul 25 06:49:15 PM PDT 24 |
Finished | Jul 25 06:51:43 PM PDT 24 |
Peak memory | 360332 kb |
Host | smart-8570c57b-36de-4dc4-94aa-8a4fac412ac0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705402538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3705402538 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.3482293447 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 787590374 ps |
CPU time | 10.65 seconds |
Started | Jul 25 06:49:13 PM PDT 24 |
Finished | Jul 25 06:49:23 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-79d99abb-8389-4b3b-a194-ee7cf08226ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482293447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3482293447 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.1427053414 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 208983464589 ps |
CPU time | 2166.14 seconds |
Started | Jul 25 06:49:13 PM PDT 24 |
Finished | Jul 25 07:25:20 PM PDT 24 |
Peak memory | 381156 kb |
Host | smart-65773c3c-024e-434d-b9d2-0f94436e8fb5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427053414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.1427053414 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2321884035 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 1100791959 ps |
CPU time | 26.69 seconds |
Started | Jul 25 06:49:16 PM PDT 24 |
Finished | Jul 25 06:49:43 PM PDT 24 |
Peak memory | 211468 kb |
Host | smart-e606d753-53cf-45f0-94e9-ab49b46d03a4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2321884035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2321884035 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1077047659 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 6780808995 ps |
CPU time | 218.82 seconds |
Started | Jul 25 06:49:11 PM PDT 24 |
Finished | Jul 25 06:52:50 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-e9523865-bd51-4048-9578-4d8186977aec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077047659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.1077047659 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3031355882 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 803013437 ps |
CPU time | 128.66 seconds |
Started | Jul 25 06:49:13 PM PDT 24 |
Finished | Jul 25 06:51:22 PM PDT 24 |
Peak memory | 370780 kb |
Host | smart-ac86ef5d-b0e8-4fff-a2c9-c651ec11d046 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031355882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3031355882 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2278803066 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 58400868367 ps |
CPU time | 950.15 seconds |
Started | Jul 25 06:49:22 PM PDT 24 |
Finished | Jul 25 07:05:13 PM PDT 24 |
Peak memory | 377016 kb |
Host | smart-74641b66-c2c5-4beb-a0ad-08aa255b7664 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278803066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.2278803066 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.731848755 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 39203470 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:49:22 PM PDT 24 |
Finished | Jul 25 06:49:22 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-2ff78875-b5f0-405b-a53a-98d00b4b2a74 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731848755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.731848755 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.123365817 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 22086908881 ps |
CPU time | 765.68 seconds |
Started | Jul 25 06:49:14 PM PDT 24 |
Finished | Jul 25 07:01:59 PM PDT 24 |
Peak memory | 203932 kb |
Host | smart-4b79c298-315d-410c-84fe-ef05c99e403c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123365817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection. 123365817 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.19069265 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 7405079989 ps |
CPU time | 843.14 seconds |
Started | Jul 25 06:49:21 PM PDT 24 |
Finished | Jul 25 07:03:25 PM PDT 24 |
Peak memory | 354580 kb |
Host | smart-e78d24a6-f39e-4914-8cb1-37abd288af47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19069265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable .19069265 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.2255812929 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 156080746579 ps |
CPU time | 113.63 seconds |
Started | Jul 25 06:49:20 PM PDT 24 |
Finished | Jul 25 06:51:14 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-9a0316b7-5f4d-4b36-9652-f3ccb12080ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255812929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.2255812929 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.2435500136 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 4478624992 ps |
CPU time | 86.06 seconds |
Started | Jul 25 06:49:20 PM PDT 24 |
Finished | Jul 25 06:50:46 PM PDT 24 |
Peak memory | 365684 kb |
Host | smart-ca5a1cbf-7ea0-4251-b7b4-3faff2a76f03 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435500136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.2435500136 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1447178609 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 13926353998 ps |
CPU time | 162.03 seconds |
Started | Jul 25 06:49:19 PM PDT 24 |
Finished | Jul 25 06:52:01 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-3b861f82-a65e-4d7d-a711-d8d89f993531 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447178609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1447178609 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.1749110496 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 105598885526 ps |
CPU time | 348.91 seconds |
Started | Jul 25 06:49:23 PM PDT 24 |
Finished | Jul 25 06:55:12 PM PDT 24 |
Peak memory | 212272 kb |
Host | smart-6be11d67-f267-4780-9fac-45e7a562cb64 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749110496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.1749110496 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.3331834346 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 43827851796 ps |
CPU time | 1172.5 seconds |
Started | Jul 25 06:49:12 PM PDT 24 |
Finished | Jul 25 07:08:45 PM PDT 24 |
Peak memory | 378100 kb |
Host | smart-eae7db79-67ad-4120-b69f-d960975e9d3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331834346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.3331834346 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.2317691709 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 763973855 ps |
CPU time | 10.72 seconds |
Started | Jul 25 06:49:12 PM PDT 24 |
Finished | Jul 25 06:49:23 PM PDT 24 |
Peak memory | 237784 kb |
Host | smart-287e071b-ef42-40a2-8800-b0bad6ade242 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317691709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.2317691709 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.115777580 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 7451645597 ps |
CPU time | 190.44 seconds |
Started | Jul 25 06:49:23 PM PDT 24 |
Finished | Jul 25 06:52:34 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-cc99f7c0-2303-4ebe-b018-0c1083874c36 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115777580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.sram_ctrl_partial_access_b2b.115777580 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.3711861569 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 356797211 ps |
CPU time | 3.07 seconds |
Started | Jul 25 06:49:20 PM PDT 24 |
Finished | Jul 25 06:49:24 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-7e2e89a0-1d69-4f7a-aa6f-de5c667d6e84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711861569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3711861569 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.1358372089 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 2451699473 ps |
CPU time | 470.05 seconds |
Started | Jul 25 06:49:21 PM PDT 24 |
Finished | Jul 25 06:57:11 PM PDT 24 |
Peak memory | 378068 kb |
Host | smart-1e114b7c-4a49-4514-93e3-57c3b4f5beb7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358372089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1358372089 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.2422256262 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 553102358 ps |
CPU time | 18.01 seconds |
Started | Jul 25 06:49:13 PM PDT 24 |
Finished | Jul 25 06:49:31 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-85cdab57-adaf-4a75-91eb-e6da454fe055 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422256262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2422256262 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.1619156066 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 406503750009 ps |
CPU time | 5205.44 seconds |
Started | Jul 25 06:49:21 PM PDT 24 |
Finished | Jul 25 08:16:07 PM PDT 24 |
Peak memory | 380144 kb |
Host | smart-3370d95c-fa49-456b-9840-ecd2d60e421c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619156066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.1619156066 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1656785368 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 1942735740 ps |
CPU time | 156.88 seconds |
Started | Jul 25 06:49:21 PM PDT 24 |
Finished | Jul 25 06:51:58 PM PDT 24 |
Peak memory | 378676 kb |
Host | smart-65ff9530-1bb9-4383-926a-498152a8881d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1656785368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.1656785368 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.718588427 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 3734752008 ps |
CPU time | 262.73 seconds |
Started | Jul 25 06:49:15 PM PDT 24 |
Finished | Jul 25 06:53:38 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-1b3965af-0ed0-4a7a-bce1-f97fec62ba2c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718588427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .sram_ctrl_stress_pipeline.718588427 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.102971782 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 6053032429 ps |
CPU time | 121.38 seconds |
Started | Jul 25 06:49:20 PM PDT 24 |
Finished | Jul 25 06:51:22 PM PDT 24 |
Peak memory | 367800 kb |
Host | smart-e96f471e-b306-468c-a6e8-913699216913 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102971782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_throughput_w_partial_write.102971782 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2345190072 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 22260182136 ps |
CPU time | 908.42 seconds |
Started | Jul 25 06:49:30 PM PDT 24 |
Finished | Jul 25 07:04:39 PM PDT 24 |
Peak memory | 371920 kb |
Host | smart-f15712b5-b67d-40c9-a449-b7d3f137bff1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345190072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2345190072 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.1711681600 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 46611243 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:49:31 PM PDT 24 |
Finished | Jul 25 06:49:31 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-18f9ffda-d201-47a8-b89a-4097b82008b3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711681600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1711681600 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.1540673175 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 307789251402 ps |
CPU time | 1363.74 seconds |
Started | Jul 25 06:49:30 PM PDT 24 |
Finished | Jul 25 07:12:14 PM PDT 24 |
Peak memory | 203856 kb |
Host | smart-d5f3372f-f2c4-45b2-8e49-e1cf9f7a0f8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540673175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .1540673175 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.2285999654 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 8149887634 ps |
CPU time | 46.74 seconds |
Started | Jul 25 06:49:29 PM PDT 24 |
Finished | Jul 25 06:50:16 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-f8a61c4f-caeb-4995-8bb5-3b093249a570 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285999654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.2285999654 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.991820582 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 2861845494 ps |
CPU time | 31.43 seconds |
Started | Jul 25 06:49:29 PM PDT 24 |
Finished | Jul 25 06:50:01 PM PDT 24 |
Peak memory | 290144 kb |
Host | smart-68f00bb2-1a7e-41c6-b1d0-0f0babc9d1ae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991820582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.sram_ctrl_max_throughput.991820582 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.892301937 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 2537810089 ps |
CPU time | 77.51 seconds |
Started | Jul 25 06:49:32 PM PDT 24 |
Finished | Jul 25 06:50:50 PM PDT 24 |
Peak memory | 219528 kb |
Host | smart-016d12c1-f9ad-48ba-b830-9fd676c8faad |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892301937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_mem_partial_access.892301937 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.4242659323 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 2636811322 ps |
CPU time | 153.86 seconds |
Started | Jul 25 06:49:30 PM PDT 24 |
Finished | Jul 25 06:52:04 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-164ecda0-7cfe-4bf3-8f10-200e0f0e95c6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242659323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.4242659323 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.980681968 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 120531131723 ps |
CPU time | 891.17 seconds |
Started | Jul 25 06:49:21 PM PDT 24 |
Finished | Jul 25 07:04:13 PM PDT 24 |
Peak memory | 377692 kb |
Host | smart-f19c9cc5-77af-4c0a-9923-ac843af4b970 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980681968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multip le_keys.980681968 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.1768992459 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 891769017 ps |
CPU time | 86.88 seconds |
Started | Jul 25 06:49:29 PM PDT 24 |
Finished | Jul 25 06:50:56 PM PDT 24 |
Peak memory | 347280 kb |
Host | smart-fc73f7de-a44a-494d-8b67-f6c58b122840 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768992459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.1768992459 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2355607872 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 28146499599 ps |
CPU time | 715.9 seconds |
Started | Jul 25 06:49:33 PM PDT 24 |
Finished | Jul 25 07:01:29 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-b67178e5-cf7e-4946-af5a-9561e6baab84 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355607872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.2355607872 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.3823766978 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 3354567241 ps |
CPU time | 3.81 seconds |
Started | Jul 25 06:49:30 PM PDT 24 |
Finished | Jul 25 06:49:34 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-cee89def-a88a-408b-88eb-2e883474e922 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823766978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3823766978 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.1518274296 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 18190803715 ps |
CPU time | 253.61 seconds |
Started | Jul 25 06:49:32 PM PDT 24 |
Finished | Jul 25 06:53:46 PM PDT 24 |
Peak memory | 367688 kb |
Host | smart-d5383eea-c8ac-4682-a115-b51aa5b6fcd6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518274296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1518274296 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.3727202695 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 2003976830 ps |
CPU time | 30.82 seconds |
Started | Jul 25 06:49:20 PM PDT 24 |
Finished | Jul 25 06:49:52 PM PDT 24 |
Peak memory | 282844 kb |
Host | smart-34dd5482-46e7-4bc7-86b4-5f21683fdd44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727202695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3727202695 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.36585512 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 171818262928 ps |
CPU time | 7119.29 seconds |
Started | Jul 25 06:49:29 PM PDT 24 |
Finished | Jul 25 08:48:10 PM PDT 24 |
Peak memory | 383264 kb |
Host | smart-470aa8ec-c2c2-4616-aa3e-17a36f5a775f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36585512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.sram_ctrl_stress_all.36585512 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1676379371 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 753366167 ps |
CPU time | 44.66 seconds |
Started | Jul 25 06:49:32 PM PDT 24 |
Finished | Jul 25 06:50:17 PM PDT 24 |
Peak memory | 261084 kb |
Host | smart-06f1c1d8-0218-49bf-98c2-7ef1e88ea112 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1676379371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.1676379371 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.560503806 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 4322884960 ps |
CPU time | 307.23 seconds |
Started | Jul 25 06:49:32 PM PDT 24 |
Finished | Jul 25 06:54:40 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-a90c2424-338a-4a04-b3b8-1fbdb53ab542 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560503806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_stress_pipeline.560503806 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2241270774 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 2807866944 ps |
CPU time | 7.08 seconds |
Started | Jul 25 06:49:33 PM PDT 24 |
Finished | Jul 25 06:49:40 PM PDT 24 |
Peak memory | 218048 kb |
Host | smart-275c00df-b168-441f-a17a-0faa2561e161 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241270774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.2241270774 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1553986379 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 22337111416 ps |
CPU time | 1075.67 seconds |
Started | Jul 25 06:49:37 PM PDT 24 |
Finished | Jul 25 07:07:33 PM PDT 24 |
Peak memory | 380024 kb |
Host | smart-bb52d5cc-429c-4991-ab87-0ecf12bab4d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553986379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.1553986379 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.1215664005 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 10898862 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:49:46 PM PDT 24 |
Finished | Jul 25 06:49:47 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-cd4156a6-0aef-4815-a0c6-a26408a15687 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215664005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.1215664005 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.367676269 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 113001301467 ps |
CPU time | 2202.44 seconds |
Started | Jul 25 06:49:30 PM PDT 24 |
Finished | Jul 25 07:26:13 PM PDT 24 |
Peak memory | 203848 kb |
Host | smart-e8791df9-36d4-4241-9238-654f7b7439e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367676269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 367676269 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.20494060 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 34835127573 ps |
CPU time | 718.25 seconds |
Started | Jul 25 06:49:37 PM PDT 24 |
Finished | Jul 25 07:01:35 PM PDT 24 |
Peak memory | 372372 kb |
Host | smart-191584d1-a516-487f-abae-60ebdd3de29e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20494060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable .20494060 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.851784721 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 748421334 ps |
CPU time | 29.3 seconds |
Started | Jul 25 06:49:37 PM PDT 24 |
Finished | Jul 25 06:50:07 PM PDT 24 |
Peak memory | 268600 kb |
Host | smart-6ccd4f6b-d0d6-4e1d-85a7-941a7b8509f9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851784721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.sram_ctrl_max_throughput.851784721 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1379200836 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 3827041802 ps |
CPU time | 64.57 seconds |
Started | Jul 25 06:49:45 PM PDT 24 |
Finished | Jul 25 06:50:50 PM PDT 24 |
Peak memory | 219564 kb |
Host | smart-2a0aeb59-320f-4c78-8f67-5aeb971fe7ac |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379200836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.1379200836 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.1561745249 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 39527311158 ps |
CPU time | 318.18 seconds |
Started | Jul 25 06:49:51 PM PDT 24 |
Finished | Jul 25 06:55:09 PM PDT 24 |
Peak memory | 204236 kb |
Host | smart-c23d33af-473a-48a3-9a8a-9d8b26fc53b0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561745249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.1561745249 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.217539151 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 33549768624 ps |
CPU time | 951.51 seconds |
Started | Jul 25 06:49:30 PM PDT 24 |
Finished | Jul 25 07:05:22 PM PDT 24 |
Peak memory | 379088 kb |
Host | smart-be535e70-975a-4a85-90db-8c7d2ad7fcac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217539151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip le_keys.217539151 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.4865940 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 1989107286 ps |
CPU time | 21.63 seconds |
Started | Jul 25 06:49:32 PM PDT 24 |
Finished | Jul 25 06:49:54 PM PDT 24 |
Peak memory | 259052 kb |
Host | smart-6704e878-5bf5-43c0-ba21-6f68b3d3583c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4865940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sra m_ctrl_partial_access.4865940 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2091717484 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 12048367903 ps |
CPU time | 278 seconds |
Started | Jul 25 06:49:38 PM PDT 24 |
Finished | Jul 25 06:54:16 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-d7ab4cf3-7a17-42b1-993a-3ce33c67c507 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091717484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.2091717484 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.3313585143 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 1213003880 ps |
CPU time | 3.27 seconds |
Started | Jul 25 06:49:40 PM PDT 24 |
Finished | Jul 25 06:49:43 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-f552fbb3-1c50-4f60-8b6f-840261cd79f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313585143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3313585143 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.4226979748 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 45456927075 ps |
CPU time | 1641.46 seconds |
Started | Jul 25 06:49:38 PM PDT 24 |
Finished | Jul 25 07:17:00 PM PDT 24 |
Peak memory | 381176 kb |
Host | smart-45b38163-1c26-4878-8798-7951af178d53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226979748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.4226979748 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.4291703969 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 6494382889 ps |
CPU time | 44.12 seconds |
Started | Jul 25 06:49:31 PM PDT 24 |
Finished | Jul 25 06:50:15 PM PDT 24 |
Peak memory | 289796 kb |
Host | smart-fc866a71-ff10-42a0-a18c-647b9f0148e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291703969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.4291703969 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.4275892939 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 189444074197 ps |
CPU time | 5229.09 seconds |
Started | Jul 25 06:49:47 PM PDT 24 |
Finished | Jul 25 08:16:57 PM PDT 24 |
Peak memory | 390360 kb |
Host | smart-6415363c-0587-4e65-8107-e46dc1bae864 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275892939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.4275892939 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1126424242 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 11995186138 ps |
CPU time | 92.83 seconds |
Started | Jul 25 06:49:46 PM PDT 24 |
Finished | Jul 25 06:51:19 PM PDT 24 |
Peak memory | 319756 kb |
Host | smart-f423ae38-46b7-47e8-bb79-06275f531f65 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1126424242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1126424242 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3296310282 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 6477871190 ps |
CPU time | 276.01 seconds |
Started | Jul 25 06:49:32 PM PDT 24 |
Finished | Jul 25 06:54:08 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-ee699406-5266-46c5-8dc1-e8707f382ae1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296310282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.3296310282 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1001955438 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 3225348208 ps |
CPU time | 87.4 seconds |
Started | Jul 25 06:49:39 PM PDT 24 |
Finished | Jul 25 06:51:07 PM PDT 24 |
Peak memory | 359688 kb |
Host | smart-a7378800-a4c3-464c-9d3d-b55d09196c0c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001955438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.1001955438 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1461264011 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 33053489771 ps |
CPU time | 410.63 seconds |
Started | Jul 25 06:49:51 PM PDT 24 |
Finished | Jul 25 06:56:41 PM PDT 24 |
Peak memory | 366752 kb |
Host | smart-3d3c69a9-777a-4755-9139-a5363321e8d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461264011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.1461264011 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.3632605587 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 31643337 ps |
CPU time | 0.63 seconds |
Started | Jul 25 06:49:47 PM PDT 24 |
Finished | Jul 25 06:49:48 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-313b456e-b1bb-4619-a1bd-3e564201d174 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632605587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3632605587 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.1690585472 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 56755805735 ps |
CPU time | 1105.04 seconds |
Started | Jul 25 06:49:46 PM PDT 24 |
Finished | Jul 25 07:08:12 PM PDT 24 |
Peak memory | 203880 kb |
Host | smart-f665f8ec-4a2a-4432-90cf-b825681eba2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690585472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .1690585472 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.2373250714 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 13170654703 ps |
CPU time | 546.11 seconds |
Started | Jul 25 06:49:45 PM PDT 24 |
Finished | Jul 25 06:58:51 PM PDT 24 |
Peak memory | 370812 kb |
Host | smart-ee6923cb-b2f6-4871-8f37-1a0325f925f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373250714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.2373250714 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.4122509521 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 12130836559 ps |
CPU time | 72.1 seconds |
Started | Jul 25 06:49:49 PM PDT 24 |
Finished | Jul 25 06:51:01 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-36febbc8-bdde-4a85-82c8-64225c4c7233 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122509521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.4122509521 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.1075314152 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 2545513416 ps |
CPU time | 26.17 seconds |
Started | Jul 25 06:49:51 PM PDT 24 |
Finished | Jul 25 06:50:17 PM PDT 24 |
Peak memory | 280884 kb |
Host | smart-b70a3d91-19d8-4d73-812a-8696705c5525 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075314152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.1075314152 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3431993975 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 2742547769 ps |
CPU time | 147.81 seconds |
Started | Jul 25 06:49:45 PM PDT 24 |
Finished | Jul 25 06:52:13 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-68358f77-f0e8-4d17-8575-4c03c5ef53b0 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431993975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.3431993975 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.3095968206 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 16415668199 ps |
CPU time | 256.15 seconds |
Started | Jul 25 06:49:45 PM PDT 24 |
Finished | Jul 25 06:54:02 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-46f922ce-8c24-477e-a406-dfc5f4680a9a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095968206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.3095968206 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.1735761897 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 9086323428 ps |
CPU time | 558.76 seconds |
Started | Jul 25 06:49:45 PM PDT 24 |
Finished | Jul 25 06:59:04 PM PDT 24 |
Peak memory | 379072 kb |
Host | smart-800d6665-52be-42b5-975b-e80cdba36533 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735761897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.1735761897 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.1884762763 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 13070926829 ps |
CPU time | 15.36 seconds |
Started | Jul 25 06:49:46 PM PDT 24 |
Finished | Jul 25 06:50:01 PM PDT 24 |
Peak memory | 229816 kb |
Host | smart-f09d06a0-afc3-48d6-baff-a98ea180c1c0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884762763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.1884762763 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2410354274 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 42499853567 ps |
CPU time | 582.58 seconds |
Started | Jul 25 06:49:51 PM PDT 24 |
Finished | Jul 25 06:59:34 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-740b55db-29dc-40ca-9964-614e2c3d0fd7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410354274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.2410354274 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.2390714813 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 4211421333 ps |
CPU time | 3.77 seconds |
Started | Jul 25 06:49:45 PM PDT 24 |
Finished | Jul 25 06:49:49 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-fbafea92-54f4-4203-80f3-0e923f744017 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390714813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2390714813 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.3791899460 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 4493831868 ps |
CPU time | 684.96 seconds |
Started | Jul 25 06:49:46 PM PDT 24 |
Finished | Jul 25 07:01:12 PM PDT 24 |
Peak memory | 379084 kb |
Host | smart-62455d6a-0a22-476f-9532-19b3e52e9013 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791899460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3791899460 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.366803649 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 3949214498 ps |
CPU time | 7.83 seconds |
Started | Jul 25 06:49:46 PM PDT 24 |
Finished | Jul 25 06:49:54 PM PDT 24 |
Peak memory | 204412 kb |
Host | smart-86b9eccb-9896-4805-802d-0e79ef0537b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366803649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.366803649 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.219286846 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 274872275253 ps |
CPU time | 7680.61 seconds |
Started | Jul 25 06:49:52 PM PDT 24 |
Finished | Jul 25 08:57:53 PM PDT 24 |
Peak memory | 380176 kb |
Host | smart-b4a8700c-e693-44a4-8457-c2f64c330ad4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219286846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_stress_all.219286846 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.535171212 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 443235345 ps |
CPU time | 12.38 seconds |
Started | Jul 25 06:49:51 PM PDT 24 |
Finished | Jul 25 06:50:03 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-1a9a740b-063a-4efe-a91c-fe2392e49545 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=535171212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.535171212 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3918288759 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 4933495007 ps |
CPU time | 347.29 seconds |
Started | Jul 25 06:49:46 PM PDT 24 |
Finished | Jul 25 06:55:33 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-46f2f716-303a-403e-9f57-8220f53b5c3a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918288759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.3918288759 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.833054346 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 768614846 ps |
CPU time | 64.16 seconds |
Started | Jul 25 06:49:45 PM PDT 24 |
Finished | Jul 25 06:50:49 PM PDT 24 |
Peak memory | 342260 kb |
Host | smart-32b65b79-7dd9-4992-9eaf-6a51d82f8e4f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833054346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_throughput_w_partial_write.833054346 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2870613611 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 14963169512 ps |
CPU time | 1163.1 seconds |
Started | Jul 25 06:49:54 PM PDT 24 |
Finished | Jul 25 07:09:17 PM PDT 24 |
Peak memory | 376064 kb |
Host | smart-1e48041e-9b4f-43ce-a36a-783ea0fad592 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870613611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.2870613611 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.3080462748 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 64079399 ps |
CPU time | 0.63 seconds |
Started | Jul 25 06:50:08 PM PDT 24 |
Finished | Jul 25 06:50:09 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-03cc55e5-55fa-42c6-9387-c413c1767039 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080462748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3080462748 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.448816255 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 405041918828 ps |
CPU time | 2561.14 seconds |
Started | Jul 25 06:49:54 PM PDT 24 |
Finished | Jul 25 07:32:35 PM PDT 24 |
Peak memory | 204064 kb |
Host | smart-46bc6244-7a57-4f13-a9a6-f5dcfc6aff3d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448816255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection. 448816255 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.1731054466 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 18015725224 ps |
CPU time | 914.16 seconds |
Started | Jul 25 06:49:53 PM PDT 24 |
Finished | Jul 25 07:05:08 PM PDT 24 |
Peak memory | 379120 kb |
Host | smart-00a04402-c9d7-46e3-9503-bbcdba0edb54 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731054466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.1731054466 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.4058665275 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 15412940699 ps |
CPU time | 51.16 seconds |
Started | Jul 25 06:49:58 PM PDT 24 |
Finished | Jul 25 06:50:49 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-f71ad5fa-10ea-4dd3-918e-3fc5b9766323 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058665275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.4058665275 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.2844734220 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 2679630408 ps |
CPU time | 7.21 seconds |
Started | Jul 25 06:49:54 PM PDT 24 |
Finished | Jul 25 06:50:01 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-1135e0a5-3c79-4b7c-afa1-983ef17a26b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844734220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.2844734220 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3339064437 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 10302979725 ps |
CPU time | 79.5 seconds |
Started | Jul 25 06:50:02 PM PDT 24 |
Finished | Jul 25 06:51:21 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-9fbdd77b-b414-41aa-ae49-4390c82395a3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339064437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.3339064437 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.410533667 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 20697299491 ps |
CPU time | 344.45 seconds |
Started | Jul 25 06:50:03 PM PDT 24 |
Finished | Jul 25 06:55:47 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-1fe63ba8-34c7-45de-81cf-16e78fbdb214 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410533667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl _mem_walk.410533667 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.3162097746 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 45083024032 ps |
CPU time | 211.34 seconds |
Started | Jul 25 06:49:59 PM PDT 24 |
Finished | Jul 25 06:53:30 PM PDT 24 |
Peak memory | 367980 kb |
Host | smart-e669d48c-ac9a-45b7-8794-330a75c32105 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162097746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.3162097746 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.4186238580 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 499951012 ps |
CPU time | 11.19 seconds |
Started | Jul 25 06:49:52 PM PDT 24 |
Finished | Jul 25 06:50:04 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-eb276d9b-490b-4b45-9cfe-7dbccc1843ad |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186238580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.4186238580 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3768852239 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 18172998815 ps |
CPU time | 442.21 seconds |
Started | Jul 25 06:49:53 PM PDT 24 |
Finished | Jul 25 06:57:16 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-30f5fcce-3d7c-4b5a-a68f-00af136b9c0a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768852239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.3768852239 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.2709594951 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 352277657 ps |
CPU time | 3.23 seconds |
Started | Jul 25 06:50:08 PM PDT 24 |
Finished | Jul 25 06:50:11 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-a8f3d0e4-2fc5-426b-b418-67539bbbdff3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709594951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2709594951 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.3964660622 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 8331537837 ps |
CPU time | 583.55 seconds |
Started | Jul 25 06:49:55 PM PDT 24 |
Finished | Jul 25 06:59:38 PM PDT 24 |
Peak memory | 376016 kb |
Host | smart-3786166c-9bcb-4669-a529-e67c26f9a008 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964660622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3964660622 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.2988536778 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 820427797 ps |
CPU time | 5.37 seconds |
Started | Jul 25 06:49:58 PM PDT 24 |
Finished | Jul 25 06:50:04 PM PDT 24 |
Peak memory | 208900 kb |
Host | smart-77015ae3-d375-4b38-8716-f372248ffdab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988536778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2988536778 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.1198093452 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 37617472165 ps |
CPU time | 2649.05 seconds |
Started | Jul 25 06:50:01 PM PDT 24 |
Finished | Jul 25 07:34:10 PM PDT 24 |
Peak memory | 370008 kb |
Host | smart-d1ca4d0f-a6f7-4986-8b72-90a5a14fc86d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198093452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.1198093452 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.813032556 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 271273005 ps |
CPU time | 9.36 seconds |
Started | Jul 25 06:50:02 PM PDT 24 |
Finished | Jul 25 06:50:11 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-2d94a750-c64c-423e-b3d3-1846293e1343 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=813032556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.813032556 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1964938494 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 4111266581 ps |
CPU time | 249.63 seconds |
Started | Jul 25 06:49:53 PM PDT 24 |
Finished | Jul 25 06:54:03 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-8c0219e8-8ba3-4724-80bb-4271a40c1512 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964938494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.1964938494 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4052552788 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 689232008 ps |
CPU time | 9.6 seconds |
Started | Jul 25 06:49:54 PM PDT 24 |
Finished | Jul 25 06:50:04 PM PDT 24 |
Peak memory | 226520 kb |
Host | smart-a59c8ff1-e63d-4176-a486-aa27d329173f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052552788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.4052552788 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1431838897 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 33557057469 ps |
CPU time | 432.48 seconds |
Started | Jul 25 06:50:09 PM PDT 24 |
Finished | Jul 25 06:57:21 PM PDT 24 |
Peak memory | 332420 kb |
Host | smart-e5e11366-aeae-49c2-aff1-9ab72fc34c44 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431838897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.1431838897 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.4191156758 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 55206545 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:50:20 PM PDT 24 |
Finished | Jul 25 06:50:21 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-ddd2572e-d9f6-4cb6-bbd6-c699b3e36eda |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191156758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.4191156758 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.3689868824 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 86206498353 ps |
CPU time | 551.24 seconds |
Started | Jul 25 06:50:02 PM PDT 24 |
Finished | Jul 25 06:59:13 PM PDT 24 |
Peak memory | 203852 kb |
Host | smart-54b7385f-a551-4f39-858d-9e5862b93ea0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689868824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .3689868824 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.1099208058 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 26253822623 ps |
CPU time | 1271.48 seconds |
Started | Jul 25 06:50:18 PM PDT 24 |
Finished | Jul 25 07:11:29 PM PDT 24 |
Peak memory | 381148 kb |
Host | smart-b573b731-f106-4ab9-81ef-27f3e1c29c33 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099208058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.1099208058 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.2105929775 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 42720061945 ps |
CPU time | 87.23 seconds |
Started | Jul 25 06:50:20 PM PDT 24 |
Finished | Jul 25 06:51:47 PM PDT 24 |
Peak memory | 215980 kb |
Host | smart-ab064d4c-86db-488d-b41b-739527890d6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105929775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.2105929775 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.2689818756 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 682663698 ps |
CPU time | 6.89 seconds |
Started | Jul 25 06:50:10 PM PDT 24 |
Finished | Jul 25 06:50:17 PM PDT 24 |
Peak memory | 219148 kb |
Host | smart-fb86ac88-c7a8-4bfc-8efc-5e41ebcce144 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689818756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.2689818756 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2761668047 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 10188540073 ps |
CPU time | 142.7 seconds |
Started | Jul 25 06:50:09 PM PDT 24 |
Finished | Jul 25 06:52:32 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-a0ea623a-e2af-4601-8c4a-8cf59d60a5b9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761668047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.2761668047 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.1354433381 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 43774162852 ps |
CPU time | 264.45 seconds |
Started | Jul 25 06:50:09 PM PDT 24 |
Finished | Jul 25 06:54:33 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-2a238f2e-3081-40c5-a7b4-1b9ceaf5e352 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354433381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.1354433381 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.81263855 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 46863005514 ps |
CPU time | 792.07 seconds |
Started | Jul 25 06:50:02 PM PDT 24 |
Finished | Jul 25 07:03:14 PM PDT 24 |
Peak memory | 375968 kb |
Host | smart-a9f30c60-3cbe-4dca-94f3-e415f03f1fec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81263855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multipl e_keys.81263855 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.708344293 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 2019633297 ps |
CPU time | 63.2 seconds |
Started | Jul 25 06:50:01 PM PDT 24 |
Finished | Jul 25 06:51:05 PM PDT 24 |
Peak memory | 317672 kb |
Host | smart-83bda884-061c-4cc7-8c6a-b4b0426b4117 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708344293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.s ram_ctrl_partial_access.708344293 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.233504924 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 8472274542 ps |
CPU time | 410 seconds |
Started | Jul 25 06:50:09 PM PDT 24 |
Finished | Jul 25 06:56:59 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-0166070d-a68b-4be9-910a-abd587c5b5a6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233504924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.sram_ctrl_partial_access_b2b.233504924 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.3643358034 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 685449324 ps |
CPU time | 3.36 seconds |
Started | Jul 25 06:50:09 PM PDT 24 |
Finished | Jul 25 06:50:13 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-44febfb7-2f02-4d65-9b80-93b4257e16bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643358034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3643358034 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.4137960650 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 30443203857 ps |
CPU time | 1023.21 seconds |
Started | Jul 25 06:50:11 PM PDT 24 |
Finished | Jul 25 07:07:14 PM PDT 24 |
Peak memory | 382144 kb |
Host | smart-ed3018f8-4034-4843-9ea2-9dd6f7447e07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137960650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.4137960650 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.2342389572 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 683703028 ps |
CPU time | 11.84 seconds |
Started | Jul 25 06:50:01 PM PDT 24 |
Finished | Jul 25 06:50:13 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-cc42035d-2cfb-4a86-9989-430f52b1bb5a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342389572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2342389572 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2744260739 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 1196049080 ps |
CPU time | 71.68 seconds |
Started | Jul 25 06:50:09 PM PDT 24 |
Finished | Jul 25 06:51:21 PM PDT 24 |
Peak memory | 269364 kb |
Host | smart-9a01e49e-0fcf-431e-9dfb-3b847dc5ba82 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2744260739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.2744260739 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1845903755 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 3335385591 ps |
CPU time | 241.12 seconds |
Started | Jul 25 06:50:02 PM PDT 24 |
Finished | Jul 25 06:54:03 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-dc62b4f9-f3ae-46f7-9108-80e8b0910ab1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845903755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.1845903755 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.872627058 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 2791453507 ps |
CPU time | 7 seconds |
Started | Jul 25 06:50:09 PM PDT 24 |
Finished | Jul 25 06:50:16 PM PDT 24 |
Peak memory | 211480 kb |
Host | smart-e6597329-c294-44dc-825f-89b3f6f5e4b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872627058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_throughput_w_partial_write.872627058 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.267623319 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 7914741029 ps |
CPU time | 439.92 seconds |
Started | Jul 25 06:46:00 PM PDT 24 |
Finished | Jul 25 06:53:20 PM PDT 24 |
Peak memory | 362420 kb |
Host | smart-bd234c80-1bd5-4743-8bb0-c0f26476b9b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267623319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.sram_ctrl_access_during_key_req.267623319 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.2730703451 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 47505653 ps |
CPU time | 0.65 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:46:11 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-af33ffde-5f9b-4d42-94f8-3370b12afcb2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730703451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2730703451 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.89006073 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 211670225943 ps |
CPU time | 2498.88 seconds |
Started | Jul 25 06:45:59 PM PDT 24 |
Finished | Jul 25 07:27:38 PM PDT 24 |
Peak memory | 203812 kb |
Host | smart-35964a99-bcff-4f12-bf96-7fab69cd1004 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89006073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.89006073 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.3518663188 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 21946428488 ps |
CPU time | 610.13 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:56:21 PM PDT 24 |
Peak memory | 376200 kb |
Host | smart-bfd7ca86-c10f-4de1-8c0d-1afc5dbca9f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518663188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.3518663188 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.1227046276 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 16748645230 ps |
CPU time | 101.14 seconds |
Started | Jul 25 06:46:00 PM PDT 24 |
Finished | Jul 25 06:47:41 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-bd2ab5f1-8454-43de-94c0-89060bdd07ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227046276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.1227046276 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.1106537722 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 2113199087 ps |
CPU time | 15.52 seconds |
Started | Jul 25 06:45:58 PM PDT 24 |
Finished | Jul 25 06:46:14 PM PDT 24 |
Peak memory | 252204 kb |
Host | smart-6b0b87ac-a94a-47e5-9ea7-07788fd4f5f4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106537722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.1106537722 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1711358339 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 5134249727 ps |
CPU time | 158.27 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:48:50 PM PDT 24 |
Peak memory | 219516 kb |
Host | smart-72742289-7324-4196-a8cb-f3e223182292 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711358339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.1711358339 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.2994995199 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 10369508444 ps |
CPU time | 174.63 seconds |
Started | Jul 25 06:46:10 PM PDT 24 |
Finished | Jul 25 06:49:05 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-3766d398-2db3-4006-b2c5-072ea9cbac7a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994995199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.2994995199 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.1440986320 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 12393446725 ps |
CPU time | 441.66 seconds |
Started | Jul 25 06:45:59 PM PDT 24 |
Finished | Jul 25 06:53:20 PM PDT 24 |
Peak memory | 375948 kb |
Host | smart-ce486576-a6fa-4cfc-a54b-2d473ea575af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440986320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.1440986320 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.444071292 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 943089278 ps |
CPU time | 14.64 seconds |
Started | Jul 25 06:46:00 PM PDT 24 |
Finished | Jul 25 06:46:15 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-e911c9d8-87d2-4fba-b88d-1cf213133548 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444071292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr am_ctrl_partial_access.444071292 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.3901889734 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 1411409124 ps |
CPU time | 3.35 seconds |
Started | Jul 25 06:46:12 PM PDT 24 |
Finished | Jul 25 06:46:15 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-ab124024-ced2-4c79-b893-e95af268f04b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901889734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3901889734 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.520210735 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 22345304500 ps |
CPU time | 1203.54 seconds |
Started | Jul 25 06:46:10 PM PDT 24 |
Finished | Jul 25 07:06:14 PM PDT 24 |
Peak memory | 377040 kb |
Host | smart-8e3e1cff-f51e-45ae-9698-f6a53e673661 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520210735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.520210735 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.345591053 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 673974263 ps |
CPU time | 2.73 seconds |
Started | Jul 25 06:46:13 PM PDT 24 |
Finished | Jul 25 06:46:16 PM PDT 24 |
Peak memory | 222308 kb |
Host | smart-da38749d-31db-44d8-92f4-9808070e6601 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345591053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_sec_cm.345591053 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.1047805782 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 5511560851 ps |
CPU time | 117.71 seconds |
Started | Jul 25 06:46:01 PM PDT 24 |
Finished | Jul 25 06:47:59 PM PDT 24 |
Peak memory | 370808 kb |
Host | smart-e1385a7e-3ace-4484-9bc9-b53422bb8bd7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047805782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1047805782 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.3558522364 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 50945412613 ps |
CPU time | 6907.02 seconds |
Started | Jul 25 06:46:10 PM PDT 24 |
Finished | Jul 25 08:41:18 PM PDT 24 |
Peak memory | 388524 kb |
Host | smart-19e5daec-915b-4d7c-88a8-7da136bf5751 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558522364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.3558522364 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.646255168 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 949124982 ps |
CPU time | 12.78 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:46:24 PM PDT 24 |
Peak memory | 211512 kb |
Host | smart-da9a0471-e1fe-4f47-8323-8d8fad403a8b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=646255168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.646255168 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.126304638 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 10911429028 ps |
CPU time | 181.44 seconds |
Started | Jul 25 06:45:59 PM PDT 24 |
Finished | Jul 25 06:49:01 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-03172e43-4b5d-472d-9500-fca18f2d1d48 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126304638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_stress_pipeline.126304638 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1616623889 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 723374931 ps |
CPU time | 6.81 seconds |
Started | Jul 25 06:46:00 PM PDT 24 |
Finished | Jul 25 06:46:07 PM PDT 24 |
Peak memory | 212344 kb |
Host | smart-5b63d67e-76d9-4f99-9075-4b4ec5fac29e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616623889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1616623889 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3929750594 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 12455087082 ps |
CPU time | 422.92 seconds |
Started | Jul 25 06:50:18 PM PDT 24 |
Finished | Jul 25 06:57:21 PM PDT 24 |
Peak memory | 373352 kb |
Host | smart-b493c55d-29af-424d-8d04-5745c87c6a38 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929750594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.3929750594 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.848156680 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 13936145 ps |
CPU time | 0.68 seconds |
Started | Jul 25 06:50:26 PM PDT 24 |
Finished | Jul 25 06:50:27 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-06945e95-1c5d-444c-bfc7-6bde70b20ec3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848156680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.848156680 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.711193565 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 524124892797 ps |
CPU time | 2196.75 seconds |
Started | Jul 25 06:50:19 PM PDT 24 |
Finished | Jul 25 07:26:57 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-0c063348-9cd0-4b80-b416-3b7d816f9c63 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711193565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection. 711193565 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.1734971346 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 111965067064 ps |
CPU time | 1371.42 seconds |
Started | Jul 25 06:50:18 PM PDT 24 |
Finished | Jul 25 07:13:10 PM PDT 24 |
Peak memory | 378048 kb |
Host | smart-34f96e15-075c-41b9-be13-a5ff35feea6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734971346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.1734971346 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.4239511368 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 47088643715 ps |
CPU time | 61.86 seconds |
Started | Jul 25 06:50:17 PM PDT 24 |
Finished | Jul 25 06:51:19 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-65f20544-010a-4b9e-a931-6a33d2569091 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239511368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.4239511368 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.3442632267 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 2973789480 ps |
CPU time | 53.6 seconds |
Started | Jul 25 06:50:18 PM PDT 24 |
Finished | Jul 25 06:51:11 PM PDT 24 |
Peak memory | 336148 kb |
Host | smart-ea94753b-bd40-44d4-8f87-5eb7801c4b81 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442632267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.3442632267 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.1398397149 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 41398531827 ps |
CPU time | 183.33 seconds |
Started | Jul 25 06:50:25 PM PDT 24 |
Finished | Jul 25 06:53:28 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-c21d8c5e-ddcb-4441-9cd4-fb76db84ba2a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398397149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.1398397149 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1216908536 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 83088035578 ps |
CPU time | 1295.41 seconds |
Started | Jul 25 06:50:17 PM PDT 24 |
Finished | Jul 25 07:11:52 PM PDT 24 |
Peak memory | 368812 kb |
Host | smart-70bdf9b7-90eb-4d94-a3ac-50c380c4b882 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216908536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1216908536 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.1287113152 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 4869526461 ps |
CPU time | 16.95 seconds |
Started | Jul 25 06:50:17 PM PDT 24 |
Finished | Jul 25 06:50:34 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-6df1e888-5cb3-427f-beb7-e96eaa82a99a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287113152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.1287113152 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.721038761 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 58565323723 ps |
CPU time | 521.71 seconds |
Started | Jul 25 06:50:19 PM PDT 24 |
Finished | Jul 25 06:59:00 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-d9d8a3ce-baf5-4888-8bc0-8f78ecaf05b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721038761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 30.sram_ctrl_partial_access_b2b.721038761 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.1931782934 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 2791337467 ps |
CPU time | 4.06 seconds |
Started | Jul 25 06:50:18 PM PDT 24 |
Finished | Jul 25 06:50:22 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-f5e79cca-00d8-4455-8591-8d3b0629a522 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931782934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1931782934 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.559818408 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 935659043 ps |
CPU time | 119.86 seconds |
Started | Jul 25 06:50:20 PM PDT 24 |
Finished | Jul 25 06:52:20 PM PDT 24 |
Peak memory | 326356 kb |
Host | smart-9fb10ac3-e0e0-422e-80a5-8b754e0386cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559818408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.559818408 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.4241874597 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 557840782 ps |
CPU time | 16.19 seconds |
Started | Jul 25 06:50:10 PM PDT 24 |
Finished | Jul 25 06:50:26 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-ab6e4709-08c5-44de-b00f-d3aea83c229d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241874597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.4241874597 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.301176794 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 197989933571 ps |
CPU time | 1273.59 seconds |
Started | Jul 25 06:50:27 PM PDT 24 |
Finished | Jul 25 07:11:41 PM PDT 24 |
Peak memory | 373996 kb |
Host | smart-0d0db371-b21c-4576-a3d0-dcce36d8c935 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301176794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_stress_all.301176794 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2159151249 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 572365589 ps |
CPU time | 17.58 seconds |
Started | Jul 25 06:50:27 PM PDT 24 |
Finished | Jul 25 06:50:44 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-2d9e4192-61f5-464d-b8f8-69106ad0fc22 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2159151249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2159151249 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1610576685 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 8102662770 ps |
CPU time | 308.36 seconds |
Started | Jul 25 06:50:17 PM PDT 24 |
Finished | Jul 25 06:55:26 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-9b51e65e-1c1b-4bf9-b042-67865ae4afd3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610576685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.1610576685 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3879179183 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 2927264251 ps |
CPU time | 36.35 seconds |
Started | Jul 25 06:50:17 PM PDT 24 |
Finished | Jul 25 06:50:54 PM PDT 24 |
Peak memory | 293684 kb |
Host | smart-404d0cfb-db42-4aed-abce-5b8fab1349c2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879179183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3879179183 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3258513488 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 6096155181 ps |
CPU time | 431.73 seconds |
Started | Jul 25 06:50:26 PM PDT 24 |
Finished | Jul 25 06:57:38 PM PDT 24 |
Peak memory | 368844 kb |
Host | smart-7a5a3343-7425-4b2c-abcf-f1124655d3b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258513488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.3258513488 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.409481336 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 42092628 ps |
CPU time | 0.65 seconds |
Started | Jul 25 06:50:33 PM PDT 24 |
Finished | Jul 25 06:50:34 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-e112cc2b-c2f5-431a-895e-9a71bd9e48ac |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409481336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.409481336 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.4017363983 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 309575223278 ps |
CPU time | 2074.35 seconds |
Started | Jul 25 06:50:26 PM PDT 24 |
Finished | Jul 25 07:25:00 PM PDT 24 |
Peak memory | 204068 kb |
Host | smart-7310e21b-1765-4b56-9ba5-b7c8d212e636 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017363983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .4017363983 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.130481858 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 53004111194 ps |
CPU time | 712.64 seconds |
Started | Jul 25 06:50:24 PM PDT 24 |
Finished | Jul 25 07:02:17 PM PDT 24 |
Peak memory | 371916 kb |
Host | smart-68171a4d-3ab6-4516-861b-d0d66bace405 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130481858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executabl e.130481858 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.4067766059 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 13498509960 ps |
CPU time | 44.55 seconds |
Started | Jul 25 06:50:26 PM PDT 24 |
Finished | Jul 25 06:51:11 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-8c5cf6e8-a1a9-4c9e-bb0b-de94505f2df2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067766059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.4067766059 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.1662549887 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 3009089331 ps |
CPU time | 30.64 seconds |
Started | Jul 25 06:50:27 PM PDT 24 |
Finished | Jul 25 06:50:58 PM PDT 24 |
Peak memory | 292780 kb |
Host | smart-8e51bf9e-70e6-4b43-874c-c03b8369d091 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662549887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.1662549887 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1816527718 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 6096136925 ps |
CPU time | 166.41 seconds |
Started | Jul 25 06:50:27 PM PDT 24 |
Finished | Jul 25 06:53:14 PM PDT 24 |
Peak memory | 219600 kb |
Host | smart-05a24d93-2bfd-4726-97a7-1648f6c49c0f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816527718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.1816527718 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.2353311589 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 40774099017 ps |
CPU time | 160.09 seconds |
Started | Jul 25 06:50:25 PM PDT 24 |
Finished | Jul 25 06:53:05 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-57c8d052-fa60-4676-bece-3aa4879b5d04 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353311589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.2353311589 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.881125818 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 17170582555 ps |
CPU time | 1287.74 seconds |
Started | Jul 25 06:50:24 PM PDT 24 |
Finished | Jul 25 07:11:52 PM PDT 24 |
Peak memory | 381048 kb |
Host | smart-b21db447-23ec-4e5f-8ba0-9de730a6037e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881125818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip le_keys.881125818 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.2549472864 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 778529409 ps |
CPU time | 10.24 seconds |
Started | Jul 25 06:50:25 PM PDT 24 |
Finished | Jul 25 06:50:36 PM PDT 24 |
Peak memory | 219992 kb |
Host | smart-5a0d2ec8-7173-4599-8983-c29eb012d61c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549472864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.2549472864 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.4274569069 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 77987385956 ps |
CPU time | 348.47 seconds |
Started | Jul 25 06:50:26 PM PDT 24 |
Finished | Jul 25 06:56:14 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-79db189a-e343-4912-b437-21f87dc27ada |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274569069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.4274569069 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.1441894223 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 696284932 ps |
CPU time | 3.18 seconds |
Started | Jul 25 06:50:26 PM PDT 24 |
Finished | Jul 25 06:50:30 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-91835b80-bc61-4c88-b9d1-ed3963fe2193 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441894223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1441894223 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.3943438254 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 8662709028 ps |
CPU time | 496.53 seconds |
Started | Jul 25 06:50:25 PM PDT 24 |
Finished | Jul 25 06:58:42 PM PDT 24 |
Peak memory | 377000 kb |
Host | smart-292c09c3-4850-4d17-9891-c3d25ce0d226 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943438254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3943438254 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.1309582728 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 1466387102 ps |
CPU time | 6.18 seconds |
Started | Jul 25 06:50:25 PM PDT 24 |
Finished | Jul 25 06:50:32 PM PDT 24 |
Peak memory | 218600 kb |
Host | smart-5a25c228-4ee6-4aa3-9c91-1d9102a0c90b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309582728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1309582728 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.297758123 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 154893661313 ps |
CPU time | 3531.47 seconds |
Started | Jul 25 06:50:35 PM PDT 24 |
Finished | Jul 25 07:49:27 PM PDT 24 |
Peak memory | 376152 kb |
Host | smart-90c5a6cc-c339-41eb-a4c8-91d08a3d33fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297758123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_stress_all.297758123 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4039813572 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 491467453 ps |
CPU time | 6.97 seconds |
Started | Jul 25 06:50:27 PM PDT 24 |
Finished | Jul 25 06:50:34 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-aa6f5d91-a451-4994-8221-90f8a3bb384f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4039813572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.4039813572 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2571504812 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 9178455896 ps |
CPU time | 134.06 seconds |
Started | Jul 25 06:50:26 PM PDT 24 |
Finished | Jul 25 06:52:40 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-078224ac-75ce-4bf3-bdff-a070443f4fe3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571504812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.2571504812 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2329878347 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 2105490501 ps |
CPU time | 25.34 seconds |
Started | Jul 25 06:50:26 PM PDT 24 |
Finished | Jul 25 06:50:52 PM PDT 24 |
Peak memory | 273680 kb |
Host | smart-59d5426e-ca03-4fea-91dc-745ca22dee3c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329878347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2329878347 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2265636234 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 42938572306 ps |
CPU time | 626.61 seconds |
Started | Jul 25 06:50:34 PM PDT 24 |
Finished | Jul 25 07:01:01 PM PDT 24 |
Peak memory | 379960 kb |
Host | smart-df16978d-f8ad-4bcd-87fd-237c1415efbe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265636234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.2265636234 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.2189881223 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 27438029 ps |
CPU time | 0.62 seconds |
Started | Jul 25 06:50:42 PM PDT 24 |
Finished | Jul 25 06:50:43 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-40e1dc51-33e3-4726-9840-22e9e400ac51 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189881223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.2189881223 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.619531967 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 379292147071 ps |
CPU time | 1978.22 seconds |
Started | Jul 25 06:50:35 PM PDT 24 |
Finished | Jul 25 07:23:33 PM PDT 24 |
Peak memory | 203276 kb |
Host | smart-ecc022a7-2057-4581-a567-c272d3332974 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619531967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection. 619531967 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.1195803860 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 5631492311 ps |
CPU time | 341.55 seconds |
Started | Jul 25 06:50:33 PM PDT 24 |
Finished | Jul 25 06:56:15 PM PDT 24 |
Peak memory | 362212 kb |
Host | smart-8f4613b3-761a-49e6-b8aa-914300308bfd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195803860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.1195803860 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.3430052226 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 12936093153 ps |
CPU time | 71.94 seconds |
Started | Jul 25 06:50:32 PM PDT 24 |
Finished | Jul 25 06:51:45 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-dbca9fa8-e0b5-4d44-89af-a19fc0028213 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430052226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.3430052226 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.3589102406 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 3024272933 ps |
CPU time | 51.59 seconds |
Started | Jul 25 06:50:40 PM PDT 24 |
Finished | Jul 25 06:51:32 PM PDT 24 |
Peak memory | 301244 kb |
Host | smart-e82c65fc-0a10-44e7-a3dd-865e388084c1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589102406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.3589102406 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2269607848 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 8945638857 ps |
CPU time | 149.79 seconds |
Started | Jul 25 06:50:43 PM PDT 24 |
Finished | Jul 25 06:53:13 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-b4015b02-9389-4f15-8fa9-dedca20dd588 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269607848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.2269607848 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.3193226397 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 21337369519 ps |
CPU time | 346.18 seconds |
Started | Jul 25 06:50:40 PM PDT 24 |
Finished | Jul 25 06:56:26 PM PDT 24 |
Peak memory | 211364 kb |
Host | smart-51fc321e-d82d-4d53-9aea-888ec0e1acd5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193226397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3193226397 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.4245320626 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 28637608171 ps |
CPU time | 1577.61 seconds |
Started | Jul 25 06:50:40 PM PDT 24 |
Finished | Jul 25 07:16:58 PM PDT 24 |
Peak memory | 380108 kb |
Host | smart-0452a615-9943-4a30-bff9-80bc1b4a55b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245320626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.4245320626 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1131884017 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 7095278793 ps |
CPU time | 104.91 seconds |
Started | Jul 25 06:50:34 PM PDT 24 |
Finished | Jul 25 06:52:19 PM PDT 24 |
Peak memory | 342600 kb |
Host | smart-482d8fc8-0391-496e-b142-0fb5de58060a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131884017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1131884017 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1119931570 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 6562100511 ps |
CPU time | 369.38 seconds |
Started | Jul 25 06:50:32 PM PDT 24 |
Finished | Jul 25 06:56:41 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-c10af1a9-3be9-4f0b-8efc-ac63ade28f1b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119931570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.1119931570 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.3964065470 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 1400575112 ps |
CPU time | 3.7 seconds |
Started | Jul 25 06:50:34 PM PDT 24 |
Finished | Jul 25 06:50:38 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-e2327d5a-cccd-452a-b85b-dfaf7a920940 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964065470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3964065470 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.3390794387 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 9078242282 ps |
CPU time | 580.97 seconds |
Started | Jul 25 06:50:32 PM PDT 24 |
Finished | Jul 25 07:00:14 PM PDT 24 |
Peak memory | 363704 kb |
Host | smart-f6616bc5-43ec-4319-bda9-ad01b213c128 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390794387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3390794387 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.60802239 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 2372077426 ps |
CPU time | 15.21 seconds |
Started | Jul 25 06:50:36 PM PDT 24 |
Finished | Jul 25 06:50:51 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-826c1311-fe37-419e-83a2-5496ffc7274e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60802239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.60802239 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1587543344 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 1128701174 ps |
CPU time | 36.46 seconds |
Started | Jul 25 06:50:41 PM PDT 24 |
Finished | Jul 25 06:51:18 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-d7b78e27-7e12-4329-a1d3-b71ce52950d1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1587543344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1587543344 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1290467017 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 12054487105 ps |
CPU time | 137.45 seconds |
Started | Jul 25 06:50:39 PM PDT 24 |
Finished | Jul 25 06:52:56 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-083d7599-28c0-4e9e-abba-c0b5544a2aeb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290467017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.1290467017 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1567254051 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 1013949786 ps |
CPU time | 25.57 seconds |
Started | Jul 25 06:50:34 PM PDT 24 |
Finished | Jul 25 06:51:00 PM PDT 24 |
Peak memory | 274912 kb |
Host | smart-02e01adc-7c26-4226-84d1-f63616b52f34 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567254051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1567254051 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.232868708 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 10385847163 ps |
CPU time | 170.6 seconds |
Started | Jul 25 06:51:17 PM PDT 24 |
Finished | Jul 25 06:54:08 PM PDT 24 |
Peak memory | 334076 kb |
Host | smart-0c675d40-5b13-400b-998e-d66d412374cd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232868708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 33.sram_ctrl_access_during_key_req.232868708 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.1268096235 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 14701295 ps |
CPU time | 0.65 seconds |
Started | Jul 25 06:50:50 PM PDT 24 |
Finished | Jul 25 06:50:51 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-9530a214-282a-4e51-8103-f6c29a1b3363 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268096235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.1268096235 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.2473872258 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 690195542875 ps |
CPU time | 2209.29 seconds |
Started | Jul 25 06:50:42 PM PDT 24 |
Finished | Jul 25 07:27:32 PM PDT 24 |
Peak memory | 203460 kb |
Host | smart-29862faa-4ccd-4eed-abeb-e8b1bf14be1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473872258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .2473872258 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.3389379473 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 19821908561 ps |
CPU time | 276.83 seconds |
Started | Jul 25 06:50:51 PM PDT 24 |
Finished | Jul 25 06:55:28 PM PDT 24 |
Peak memory | 367516 kb |
Host | smart-ac24295b-2581-4063-b1f9-16b5cbc719f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389379473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.3389379473 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.627131541 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 46102070724 ps |
CPU time | 110.2 seconds |
Started | Jul 25 06:50:51 PM PDT 24 |
Finished | Jul 25 06:52:41 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-7955c893-c21a-4dce-95b8-de14917824df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627131541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esc alation.627131541 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.430686279 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 1452714878 ps |
CPU time | 9.73 seconds |
Started | Jul 25 06:50:41 PM PDT 24 |
Finished | Jul 25 06:50:51 PM PDT 24 |
Peak memory | 226728 kb |
Host | smart-5fea2b27-9d92-4bed-92e3-6212c6b20b3e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430686279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.sram_ctrl_max_throughput.430686279 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.263368115 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 1394253761 ps |
CPU time | 76.3 seconds |
Started | Jul 25 06:50:51 PM PDT 24 |
Finished | Jul 25 06:52:08 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-c3f34381-cadf-489c-9721-a954a6ebe324 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263368115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .sram_ctrl_mem_partial_access.263368115 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.764816954 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 21878178551 ps |
CPU time | 316.59 seconds |
Started | Jul 25 06:50:53 PM PDT 24 |
Finished | Jul 25 06:56:09 PM PDT 24 |
Peak memory | 211460 kb |
Host | smart-c132aa6f-afd6-40bf-bc25-28fa985e3646 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764816954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl _mem_walk.764816954 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.2378692926 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 22199373035 ps |
CPU time | 1308.49 seconds |
Started | Jul 25 06:50:41 PM PDT 24 |
Finished | Jul 25 07:12:30 PM PDT 24 |
Peak memory | 377028 kb |
Host | smart-2bc0e5d7-8926-4387-b88f-d2a79f3884ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378692926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.2378692926 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.3196030323 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 9631308336 ps |
CPU time | 27.7 seconds |
Started | Jul 25 06:50:42 PM PDT 24 |
Finished | Jul 25 06:51:10 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-f61c1682-b43c-44b5-8b8d-4f73154e98d0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196030323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.3196030323 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3775811480 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 16577857314 ps |
CPU time | 350.62 seconds |
Started | Jul 25 06:50:41 PM PDT 24 |
Finished | Jul 25 06:56:32 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-7953a789-ffe5-49a8-8267-8927d122cf13 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775811480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.3775811480 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.4293334886 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 1413274652 ps |
CPU time | 3.51 seconds |
Started | Jul 25 06:50:50 PM PDT 24 |
Finished | Jul 25 06:50:54 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-6d042982-582b-4bb6-9779-1d743f5aec4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293334886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.4293334886 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.2154745307 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 8081613624 ps |
CPU time | 1640.81 seconds |
Started | Jul 25 06:50:50 PM PDT 24 |
Finished | Jul 25 07:18:12 PM PDT 24 |
Peak memory | 381084 kb |
Host | smart-f02a4bdd-64d6-45de-939b-524b48218fc9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154745307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2154745307 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.2622179380 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 1556032988 ps |
CPU time | 110.15 seconds |
Started | Jul 25 06:50:41 PM PDT 24 |
Finished | Jul 25 06:52:31 PM PDT 24 |
Peak memory | 369696 kb |
Host | smart-763d5070-3b76-4577-aa55-0f3bfc6af9b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622179380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2622179380 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.2408764572 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 958322199824 ps |
CPU time | 6331.84 seconds |
Started | Jul 25 06:50:50 PM PDT 24 |
Finished | Jul 25 08:36:23 PM PDT 24 |
Peak memory | 383164 kb |
Host | smart-56beae78-52e4-43d0-8da5-2d26a3b7175f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408764572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.2408764572 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1166987401 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 480561442 ps |
CPU time | 7.46 seconds |
Started | Jul 25 06:50:51 PM PDT 24 |
Finished | Jul 25 06:50:58 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-7e12ae3b-0567-4467-ba0b-047a62e6d907 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1166987401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1166987401 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2018571825 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 21916512663 ps |
CPU time | 364.7 seconds |
Started | Jul 25 06:50:42 PM PDT 24 |
Finished | Jul 25 06:56:46 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-3a6033bf-2816-476c-a33a-201313493058 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018571825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.2018571825 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2446770932 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 3493764226 ps |
CPU time | 91.87 seconds |
Started | Jul 25 06:50:50 PM PDT 24 |
Finished | Jul 25 06:52:22 PM PDT 24 |
Peak memory | 354516 kb |
Host | smart-3bc9bfd5-038e-47a5-9b83-7559b5d40439 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446770932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2446770932 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.1391695385 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 31020544826 ps |
CPU time | 968.29 seconds |
Started | Jul 25 06:50:58 PM PDT 24 |
Finished | Jul 25 07:07:06 PM PDT 24 |
Peak memory | 370940 kb |
Host | smart-09d6b033-129e-4160-969c-5436bddba2d3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391695385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.1391695385 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.2561421367 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 22903934 ps |
CPU time | 0.67 seconds |
Started | Jul 25 06:50:58 PM PDT 24 |
Finished | Jul 25 06:50:59 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-621ddcc2-de3d-4f5f-99f9-bba66e919850 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561421367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2561421367 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.756961227 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 60119668466 ps |
CPU time | 1141.85 seconds |
Started | Jul 25 06:50:52 PM PDT 24 |
Finished | Jul 25 07:09:54 PM PDT 24 |
Peak memory | 203800 kb |
Host | smart-9c0abfa1-a5aa-40cc-8a9b-0739d56179c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756961227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection. 756961227 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.3117295582 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 8998560431 ps |
CPU time | 847.64 seconds |
Started | Jul 25 06:51:00 PM PDT 24 |
Finished | Jul 25 07:05:07 PM PDT 24 |
Peak memory | 362744 kb |
Host | smart-74a03932-c2f3-42cd-bb0d-abf6c7e02a8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117295582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.3117295582 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.2194487645 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 171138992836 ps |
CPU time | 66.95 seconds |
Started | Jul 25 06:50:57 PM PDT 24 |
Finished | Jul 25 06:52:04 PM PDT 24 |
Peak memory | 215744 kb |
Host | smart-3268f719-0813-4cae-bfd0-93586425ab6b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194487645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.2194487645 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.3855399451 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 2688759128 ps |
CPU time | 63.88 seconds |
Started | Jul 25 06:50:58 PM PDT 24 |
Finished | Jul 25 06:52:02 PM PDT 24 |
Peak memory | 302376 kb |
Host | smart-1c20fd2b-92f8-4965-a02e-2c631ff39e2e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855399451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.3855399451 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3391441951 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 11132876033 ps |
CPU time | 80.06 seconds |
Started | Jul 25 06:51:00 PM PDT 24 |
Finished | Jul 25 06:52:21 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-75dcbb12-03a0-4d7c-a6ab-fcda25ac5eea |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391441951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.3391441951 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.2371833983 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 13819597447 ps |
CPU time | 319.06 seconds |
Started | Jul 25 06:51:00 PM PDT 24 |
Finished | Jul 25 06:56:19 PM PDT 24 |
Peak memory | 203292 kb |
Host | smart-1e78d1ea-301f-45ab-bacd-1b14445c969d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371833983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.2371833983 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.2595689698 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 5392271135 ps |
CPU time | 232.88 seconds |
Started | Jul 25 06:50:51 PM PDT 24 |
Finished | Jul 25 06:54:44 PM PDT 24 |
Peak memory | 357016 kb |
Host | smart-294d8da6-ad7c-4f72-8adc-056fafd5a8fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595689698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.2595689698 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.4032925308 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 1078631991 ps |
CPU time | 15.15 seconds |
Started | Jul 25 06:50:50 PM PDT 24 |
Finished | Jul 25 06:51:05 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-56f28cce-1c9c-4464-9d68-58c8f880d6b7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032925308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.4032925308 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2942859511 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 41225370814 ps |
CPU time | 548.64 seconds |
Started | Jul 25 06:50:52 PM PDT 24 |
Finished | Jul 25 07:00:01 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-e9fe3ef7-f2b5-4789-9a9d-4a324859f21a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942859511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.2942859511 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.1157145612 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 2412217766 ps |
CPU time | 3.41 seconds |
Started | Jul 25 06:50:57 PM PDT 24 |
Finished | Jul 25 06:51:01 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-84a9223c-fc70-4fe1-ac2d-5df5a09af2e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157145612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1157145612 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.1361873852 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 4435018766 ps |
CPU time | 339.47 seconds |
Started | Jul 25 06:50:59 PM PDT 24 |
Finished | Jul 25 06:56:38 PM PDT 24 |
Peak memory | 367844 kb |
Host | smart-82e1f320-a2d6-462c-b658-565a8acf54e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361873852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1361873852 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.1403760808 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 1765686288 ps |
CPU time | 16.25 seconds |
Started | Jul 25 06:50:52 PM PDT 24 |
Finished | Jul 25 06:51:09 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-c3add15e-4da6-4fbf-9d12-b6c68ee0dc64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403760808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1403760808 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.963946949 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 333847261998 ps |
CPU time | 5417.77 seconds |
Started | Jul 25 06:50:57 PM PDT 24 |
Finished | Jul 25 08:21:15 PM PDT 24 |
Peak memory | 353588 kb |
Host | smart-44a3c353-a319-4b7a-9b41-415ff00c4eb0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963946949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_stress_all.963946949 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1925267739 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 6191583715 ps |
CPU time | 16.23 seconds |
Started | Jul 25 06:50:59 PM PDT 24 |
Finished | Jul 25 06:51:15 PM PDT 24 |
Peak memory | 213076 kb |
Host | smart-63899c61-c259-465f-ad9b-8a14673f5de6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1925267739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1925267739 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4216329370 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 8456830219 ps |
CPU time | 232.65 seconds |
Started | Jul 25 06:50:49 PM PDT 24 |
Finished | Jul 25 06:54:42 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-5b90bb39-752f-481d-b944-25c5c86f2839 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216329370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.4216329370 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1497134590 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 9511223539 ps |
CPU time | 8.77 seconds |
Started | Jul 25 06:50:58 PM PDT 24 |
Finished | Jul 25 06:51:07 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-fcbcc65b-59c0-4956-af06-67f080c54801 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497134590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1497134590 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3092578248 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 10615205912 ps |
CPU time | 414.94 seconds |
Started | Jul 25 06:51:07 PM PDT 24 |
Finished | Jul 25 06:58:02 PM PDT 24 |
Peak memory | 376100 kb |
Host | smart-e9432a05-a67a-4e2d-adbe-a27ffd1b7f86 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092578248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.3092578248 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.3651504647 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 32225742 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:51:16 PM PDT 24 |
Finished | Jul 25 06:51:17 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-a8b56077-3333-4627-9d7f-46748bae5d5f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651504647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.3651504647 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.4288741198 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 40059031371 ps |
CPU time | 1437.61 seconds |
Started | Jul 25 06:50:58 PM PDT 24 |
Finished | Jul 25 07:14:56 PM PDT 24 |
Peak memory | 204000 kb |
Host | smart-83669174-3b5f-4f2d-b2c9-39a211af330d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288741198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .4288741198 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.1457109086 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 8230314226 ps |
CPU time | 318.52 seconds |
Started | Jul 25 06:51:10 PM PDT 24 |
Finished | Jul 25 06:56:28 PM PDT 24 |
Peak memory | 347464 kb |
Host | smart-41dfabe4-dbd4-47cf-a754-f8d32936d4da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457109086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.1457109086 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.961942076 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 16716827545 ps |
CPU time | 15.81 seconds |
Started | Jul 25 06:51:09 PM PDT 24 |
Finished | Jul 25 06:51:25 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-9a8ccbd4-ed66-4711-86f1-3e965d376156 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961942076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esc alation.961942076 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.1716344506 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 674932251 ps |
CPU time | 6.48 seconds |
Started | Jul 25 06:51:09 PM PDT 24 |
Finished | Jul 25 06:51:15 PM PDT 24 |
Peak memory | 211328 kb |
Host | smart-75285c24-ed5e-4fcc-b84e-6f3a39d9dde1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716344506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.1716344506 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1809493314 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 1593527692 ps |
CPU time | 122.59 seconds |
Started | Jul 25 06:51:09 PM PDT 24 |
Finished | Jul 25 06:53:11 PM PDT 24 |
Peak memory | 219520 kb |
Host | smart-0b56fd21-5f7d-4b2a-ad24-d0dd8ae842dd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809493314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.1809493314 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.2307004069 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 31487816716 ps |
CPU time | 158.14 seconds |
Started | Jul 25 06:51:08 PM PDT 24 |
Finished | Jul 25 06:53:46 PM PDT 24 |
Peak memory | 204024 kb |
Host | smart-a578e65a-3351-43f8-a70e-a2d8c6363894 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307004069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.2307004069 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.3569536777 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 13716855105 ps |
CPU time | 972.03 seconds |
Started | Jul 25 06:50:59 PM PDT 24 |
Finished | Jul 25 07:07:11 PM PDT 24 |
Peak memory | 382124 kb |
Host | smart-6d3d9c66-4c09-43dc-984c-72aaebb04261 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569536777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.3569536777 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.90806317 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 1030373917 ps |
CPU time | 16.16 seconds |
Started | Jul 25 06:51:00 PM PDT 24 |
Finished | Jul 25 06:51:16 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-560731f7-94a7-4bf5-b21b-1d476e876989 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90806317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sr am_ctrl_partial_access.90806317 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2487570841 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 75600735283 ps |
CPU time | 431.43 seconds |
Started | Jul 25 06:50:59 PM PDT 24 |
Finished | Jul 25 06:58:10 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-5c45065e-e916-49a1-a168-a5fb7d9f9fbe |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487570841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.2487570841 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.1870991078 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 390855869 ps |
CPU time | 3.28 seconds |
Started | Jul 25 06:51:10 PM PDT 24 |
Finished | Jul 25 06:51:14 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-5be32535-5c50-43fe-8070-0e9b62901243 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870991078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.1870991078 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.2957257922 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 12096100851 ps |
CPU time | 1206.3 seconds |
Started | Jul 25 06:51:09 PM PDT 24 |
Finished | Jul 25 07:11:15 PM PDT 24 |
Peak memory | 381156 kb |
Host | smart-544637b0-6939-4fcb-a198-20b2e7f0a575 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957257922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2957257922 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.2566316907 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 912105981 ps |
CPU time | 19.9 seconds |
Started | Jul 25 06:50:59 PM PDT 24 |
Finished | Jul 25 06:51:19 PM PDT 24 |
Peak memory | 254068 kb |
Host | smart-f9578462-9b9b-494a-8281-fef73e60e367 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566316907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2566316907 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.3226279190 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 222224235762 ps |
CPU time | 6896.09 seconds |
Started | Jul 25 06:51:08 PM PDT 24 |
Finished | Jul 25 08:46:05 PM PDT 24 |
Peak memory | 390372 kb |
Host | smart-fcd30212-7794-4ae5-860e-91522844abfc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226279190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.3226279190 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4286315565 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 4615769296 ps |
CPU time | 183.2 seconds |
Started | Jul 25 06:51:08 PM PDT 24 |
Finished | Jul 25 06:54:11 PM PDT 24 |
Peak memory | 352576 kb |
Host | smart-2d25dcc7-eb56-4359-93ce-edab8e9168ff |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4286315565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.4286315565 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.145725574 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 4028288542 ps |
CPU time | 160.19 seconds |
Started | Jul 25 06:51:00 PM PDT 24 |
Finished | Jul 25 06:53:40 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-1879ed23-944c-4604-8ede-5594b9e6537d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145725574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .sram_ctrl_stress_pipeline.145725574 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2135638251 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 2365620056 ps |
CPU time | 44.53 seconds |
Started | Jul 25 06:51:09 PM PDT 24 |
Finished | Jul 25 06:51:53 PM PDT 24 |
Peak memory | 301360 kb |
Host | smart-dbd455e6-9227-4f41-838b-118c28f2bd8a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135638251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.2135638251 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.212474940 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 61891475550 ps |
CPU time | 1346.62 seconds |
Started | Jul 25 06:51:16 PM PDT 24 |
Finished | Jul 25 07:13:43 PM PDT 24 |
Peak memory | 377012 kb |
Host | smart-18446d2f-0cf4-4dd0-a8fa-ef30879930a3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212474940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 36.sram_ctrl_access_during_key_req.212474940 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.3115628298 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 43956444 ps |
CPU time | 0.68 seconds |
Started | Jul 25 06:51:22 PM PDT 24 |
Finished | Jul 25 06:51:23 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-8db73d20-4a3a-43ef-bce4-31a8aa7ab028 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115628298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3115628298 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.834413112 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 103545833333 ps |
CPU time | 1828.13 seconds |
Started | Jul 25 06:51:15 PM PDT 24 |
Finished | Jul 25 07:21:43 PM PDT 24 |
Peak memory | 203776 kb |
Host | smart-ecdb1749-bbb2-4fd6-a9c1-b541ba0952cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834413112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection. 834413112 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.2118686760 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 73538707163 ps |
CPU time | 1331.57 seconds |
Started | Jul 25 06:51:17 PM PDT 24 |
Finished | Jul 25 07:13:28 PM PDT 24 |
Peak memory | 379080 kb |
Host | smart-19e88865-a470-4e55-98c8-bdf58ef91cde |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118686760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.2118686760 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.3527159608 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 5352928795 ps |
CPU time | 30.09 seconds |
Started | Jul 25 06:51:14 PM PDT 24 |
Finished | Jul 25 06:51:44 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-8eead322-2cdc-49ed-b10b-db3f8f927438 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527159608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.3527159608 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.494875194 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 4054725642 ps |
CPU time | 14.55 seconds |
Started | Jul 25 06:51:15 PM PDT 24 |
Finished | Jul 25 06:51:30 PM PDT 24 |
Peak memory | 242672 kb |
Host | smart-8dcad704-adcc-40aa-a3c6-e72f6de30553 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494875194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.sram_ctrl_max_throughput.494875194 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.4182932027 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 2790681716 ps |
CPU time | 72.74 seconds |
Started | Jul 25 06:51:23 PM PDT 24 |
Finished | Jul 25 06:52:36 PM PDT 24 |
Peak memory | 211484 kb |
Host | smart-7fbd19e8-8d95-44b3-b5dc-67e71c727e37 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182932027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.4182932027 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.3662565974 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 8968901772 ps |
CPU time | 175.29 seconds |
Started | Jul 25 06:51:21 PM PDT 24 |
Finished | Jul 25 06:54:17 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-2b5ff0d3-03f6-4cf5-b0a5-611afefd98cf |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662565974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.3662565974 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.1199483465 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 121431166000 ps |
CPU time | 1510.71 seconds |
Started | Jul 25 06:51:14 PM PDT 24 |
Finished | Jul 25 07:16:25 PM PDT 24 |
Peak memory | 380152 kb |
Host | smart-18940017-ec0f-451f-b28f-4feaafcbb2ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199483465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.1199483465 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.444568909 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 1499011966 ps |
CPU time | 8.75 seconds |
Started | Jul 25 06:51:14 PM PDT 24 |
Finished | Jul 25 06:51:23 PM PDT 24 |
Peak memory | 229748 kb |
Host | smart-12e91c46-171e-43fe-806c-4abb90fe37dd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444568909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s ram_ctrl_partial_access.444568909 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1146836796 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 17636012137 ps |
CPU time | 435.7 seconds |
Started | Jul 25 06:51:16 PM PDT 24 |
Finished | Jul 25 06:58:31 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-9ffe3193-06cb-42d8-ac1a-df37dee1cf91 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146836796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.1146836796 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.3243476511 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 1350568637 ps |
CPU time | 3.2 seconds |
Started | Jul 25 06:51:22 PM PDT 24 |
Finished | Jul 25 06:51:25 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-764da209-fb0b-4a4f-90aa-c00297ece8e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243476511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3243476511 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.2234093217 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 35346180153 ps |
CPU time | 643.75 seconds |
Started | Jul 25 06:51:17 PM PDT 24 |
Finished | Jul 25 07:02:01 PM PDT 24 |
Peak memory | 379000 kb |
Host | smart-dc24687a-aedf-47f6-a1ad-866735143768 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234093217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2234093217 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.1247711037 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 740409768 ps |
CPU time | 6.71 seconds |
Started | Jul 25 06:51:14 PM PDT 24 |
Finished | Jul 25 06:51:20 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-a0ffe895-0870-4ad4-a61e-1ea1ccad475c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247711037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1247711037 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.2507522557 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 134354996621 ps |
CPU time | 5296.47 seconds |
Started | Jul 25 06:51:23 PM PDT 24 |
Finished | Jul 25 08:19:40 PM PDT 24 |
Peak memory | 384232 kb |
Host | smart-47aa7a03-2875-477f-abcd-8fa9388bc6bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507522557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.2507522557 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3298890283 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 2325399456 ps |
CPU time | 31.28 seconds |
Started | Jul 25 06:51:22 PM PDT 24 |
Finished | Jul 25 06:51:53 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-e8af722a-c0de-4a8d-8c2e-ee04b9ab91af |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3298890283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3298890283 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2728662281 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 4080292228 ps |
CPU time | 232.27 seconds |
Started | Jul 25 06:51:15 PM PDT 24 |
Finished | Jul 25 06:55:08 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-f0cbbb62-3560-4e0d-bfb3-f726b4a61271 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728662281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.2728662281 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.499505831 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 711679372 ps |
CPU time | 7 seconds |
Started | Jul 25 06:51:17 PM PDT 24 |
Finished | Jul 25 06:51:24 PM PDT 24 |
Peak memory | 219320 kb |
Host | smart-810a6595-4463-43fa-8cb3-0941c55d4fbc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499505831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.499505831 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2656445442 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 145689683333 ps |
CPU time | 1828.09 seconds |
Started | Jul 25 06:51:33 PM PDT 24 |
Finished | Jul 25 07:22:01 PM PDT 24 |
Peak memory | 380036 kb |
Host | smart-ad351d82-65b7-4667-b84e-6bf98d788bf3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656445442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.2656445442 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.4048993240 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 19908121 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:51:32 PM PDT 24 |
Finished | Jul 25 06:51:33 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-c7eaec71-9df3-4871-9572-1e11fe0cee28 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048993240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.4048993240 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.453510617 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 147519156184 ps |
CPU time | 2021.35 seconds |
Started | Jul 25 06:51:24 PM PDT 24 |
Finished | Jul 25 07:25:06 PM PDT 24 |
Peak memory | 203848 kb |
Host | smart-29f81d97-ef30-4d2f-b38f-f34e22c27dec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453510617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection. 453510617 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.215591967 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 28382959494 ps |
CPU time | 936.02 seconds |
Started | Jul 25 06:51:31 PM PDT 24 |
Finished | Jul 25 07:07:07 PM PDT 24 |
Peak memory | 379040 kb |
Host | smart-1333a0d6-299b-4799-8a68-f200e4974302 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215591967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executabl e.215591967 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.1642159156 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 29913686257 ps |
CPU time | 58.05 seconds |
Started | Jul 25 06:51:33 PM PDT 24 |
Finished | Jul 25 06:52:32 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-2e25bdb9-11b4-4264-938b-20f2700b1c73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642159156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.1642159156 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.21181195 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 1394261275 ps |
CPU time | 9.04 seconds |
Started | Jul 25 06:51:33 PM PDT 24 |
Finished | Jul 25 06:51:42 PM PDT 24 |
Peak memory | 223736 kb |
Host | smart-4cefa41a-e109-436c-b47b-4cda0ca745b4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21181195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 37.sram_ctrl_max_throughput.21181195 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.515310606 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 15494355086 ps |
CPU time | 86.48 seconds |
Started | Jul 25 06:51:32 PM PDT 24 |
Finished | Jul 25 06:52:58 PM PDT 24 |
Peak memory | 211428 kb |
Host | smart-49cc6358-5ca4-4d37-b752-4e6dcf3cc513 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515310606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_mem_partial_access.515310606 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.128489878 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 14411604774 ps |
CPU time | 314.58 seconds |
Started | Jul 25 06:51:33 PM PDT 24 |
Finished | Jul 25 06:56:47 PM PDT 24 |
Peak memory | 211344 kb |
Host | smart-e491e7c1-523f-4989-b8bc-d5b7193078a5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128489878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _mem_walk.128489878 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.1670135049 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 18635013310 ps |
CPU time | 1140.82 seconds |
Started | Jul 25 06:51:26 PM PDT 24 |
Finished | Jul 25 07:10:27 PM PDT 24 |
Peak memory | 381084 kb |
Host | smart-6b380335-60d9-4024-8f45-e3533d70cb3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670135049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.1670135049 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.2429755365 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 1525030864 ps |
CPU time | 21.52 seconds |
Started | Jul 25 06:51:24 PM PDT 24 |
Finished | Jul 25 06:51:46 PM PDT 24 |
Peak memory | 256780 kb |
Host | smart-e35299f0-eceb-47a7-b491-ff212bc4a790 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429755365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.2429755365 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3767021949 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 5871436772 ps |
CPU time | 325.1 seconds |
Started | Jul 25 06:51:21 PM PDT 24 |
Finished | Jul 25 06:56:46 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-88923801-d2f4-47a6-b195-a01fecf9162b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767021949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.3767021949 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.2239753725 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 1352647551 ps |
CPU time | 3.52 seconds |
Started | Jul 25 06:51:31 PM PDT 24 |
Finished | Jul 25 06:51:35 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-3832dc18-c41e-4813-a1c6-24e1e978628e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239753725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2239753725 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.3238927098 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 6200171089 ps |
CPU time | 347.52 seconds |
Started | Jul 25 06:51:30 PM PDT 24 |
Finished | Jul 25 06:57:18 PM PDT 24 |
Peak memory | 358720 kb |
Host | smart-c0b21d7c-cd5d-4485-8d8d-34342d9e0b7e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238927098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3238927098 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.1363623715 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 12075245147 ps |
CPU time | 34.63 seconds |
Started | Jul 25 06:51:23 PM PDT 24 |
Finished | Jul 25 06:51:57 PM PDT 24 |
Peak memory | 287304 kb |
Host | smart-594e6fd5-56fc-4c89-86f5-cbe3118a1a00 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363623715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1363623715 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.3843878718 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 179742571437 ps |
CPU time | 7659.64 seconds |
Started | Jul 25 06:51:31 PM PDT 24 |
Finished | Jul 25 08:59:11 PM PDT 24 |
Peak memory | 382204 kb |
Host | smart-55a3abce-2504-49fc-abe2-414088db8e24 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843878718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.3843878718 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.119689559 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 365027757 ps |
CPU time | 10.64 seconds |
Started | Jul 25 06:51:31 PM PDT 24 |
Finished | Jul 25 06:51:41 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-4096a24b-c7bc-40fb-9c67-c7cf96ca1a87 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=119689559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.119689559 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.53788306 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 2588949153 ps |
CPU time | 134.3 seconds |
Started | Jul 25 06:51:23 PM PDT 24 |
Finished | Jul 25 06:53:38 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-bc480fd2-a44e-45e3-847f-d0b08b3e7c30 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53788306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_stress_pipeline.53788306 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4193270476 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 4314000970 ps |
CPU time | 138.75 seconds |
Started | Jul 25 06:51:32 PM PDT 24 |
Finished | Jul 25 06:53:51 PM PDT 24 |
Peak memory | 364808 kb |
Host | smart-29771f2b-7aa3-4472-ac9a-02306011ea25 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193270476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.4193270476 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1378307986 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 87159758472 ps |
CPU time | 929.53 seconds |
Started | Jul 25 06:51:40 PM PDT 24 |
Finished | Jul 25 07:07:09 PM PDT 24 |
Peak memory | 379100 kb |
Host | smart-c6646a9e-c3c8-4802-ac72-daf2df510c0a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378307986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.1378307986 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.2041419051 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 13324227 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:51:41 PM PDT 24 |
Finished | Jul 25 06:51:42 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-0eb74399-c2a4-4685-a996-d09960baf1f6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041419051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.2041419051 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.2558671521 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 100681680602 ps |
CPU time | 2290.75 seconds |
Started | Jul 25 06:51:39 PM PDT 24 |
Finished | Jul 25 07:29:50 PM PDT 24 |
Peak memory | 203972 kb |
Host | smart-47a2858c-d68e-46f9-91aa-817c2a4abedd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558671521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2558671521 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.2927540286 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 13860102613 ps |
CPU time | 501.16 seconds |
Started | Jul 25 06:51:41 PM PDT 24 |
Finished | Jul 25 07:00:02 PM PDT 24 |
Peak memory | 372872 kb |
Host | smart-94a79004-25b0-4865-a09a-021b0f7b6f51 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927540286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.2927540286 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.2060656964 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 19484705257 ps |
CPU time | 58.19 seconds |
Started | Jul 25 06:51:39 PM PDT 24 |
Finished | Jul 25 06:52:37 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-4183c1e4-795f-41bf-84ac-32eb3b1c406c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060656964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.2060656964 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.2404899751 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 2923272274 ps |
CPU time | 20.24 seconds |
Started | Jul 25 06:51:45 PM PDT 24 |
Finished | Jul 25 06:52:05 PM PDT 24 |
Peak memory | 263752 kb |
Host | smart-982b7437-1102-48d5-bc78-1f145aa54bc5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404899751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.2404899751 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.923180842 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 19682108254 ps |
CPU time | 150.95 seconds |
Started | Jul 25 06:51:39 PM PDT 24 |
Finished | Jul 25 06:54:10 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-66bccb08-19fd-42d4-b033-b9cf86bc51e4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923180842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_mem_partial_access.923180842 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.688533242 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 15760925378 ps |
CPU time | 246.45 seconds |
Started | Jul 25 06:51:40 PM PDT 24 |
Finished | Jul 25 06:55:47 PM PDT 24 |
Peak memory | 212308 kb |
Host | smart-4df88b58-8f5b-431c-bc5c-4a8f8b8b778e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688533242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _mem_walk.688533242 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.1731290477 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 10533286476 ps |
CPU time | 709.67 seconds |
Started | Jul 25 06:51:45 PM PDT 24 |
Finished | Jul 25 07:03:35 PM PDT 24 |
Peak memory | 366680 kb |
Host | smart-00487659-de92-4650-8f90-17a98149f865 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731290477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.1731290477 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.3209082951 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1274665481 ps |
CPU time | 11.94 seconds |
Started | Jul 25 06:51:41 PM PDT 24 |
Finished | Jul 25 06:51:53 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-b93cfbd6-4197-43ef-abf5-60648ecd80f8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209082951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.3209082951 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3866321892 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 37396746758 ps |
CPU time | 410.56 seconds |
Started | Jul 25 06:51:41 PM PDT 24 |
Finished | Jul 25 06:58:32 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-cf1d3d67-e2a2-4425-b65e-ce286fc2c080 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866321892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.3866321892 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.2192521585 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 750642924 ps |
CPU time | 3.36 seconds |
Started | Jul 25 06:51:41 PM PDT 24 |
Finished | Jul 25 06:51:44 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-a1f976cb-6659-4516-92e4-4d599bf60462 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192521585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2192521585 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.336793754 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 5600074187 ps |
CPU time | 998.56 seconds |
Started | Jul 25 06:51:39 PM PDT 24 |
Finished | Jul 25 07:08:17 PM PDT 24 |
Peak memory | 380172 kb |
Host | smart-8e3971f1-14fe-4196-9904-46b38a573119 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336793754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.336793754 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.1767309224 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 1302235356 ps |
CPU time | 146.89 seconds |
Started | Jul 25 06:51:31 PM PDT 24 |
Finished | Jul 25 06:53:58 PM PDT 24 |
Peak memory | 368688 kb |
Host | smart-f0e616e2-1e1b-42d1-a4c7-6919b41948da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767309224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1767309224 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.4219168827 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 33729888698 ps |
CPU time | 1039.02 seconds |
Started | Jul 25 06:51:41 PM PDT 24 |
Finished | Jul 25 07:09:00 PM PDT 24 |
Peak memory | 353556 kb |
Host | smart-8de24640-982e-4b27-96ba-fc7e5b38e3a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219168827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.4219168827 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3773031337 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 5016254847 ps |
CPU time | 82.95 seconds |
Started | Jul 25 06:51:41 PM PDT 24 |
Finished | Jul 25 06:53:04 PM PDT 24 |
Peak memory | 279968 kb |
Host | smart-3b188d56-1fba-4c16-8086-f99ee94e5910 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3773031337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3773031337 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3635551569 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 11027423193 ps |
CPU time | 139.23 seconds |
Started | Jul 25 06:51:40 PM PDT 24 |
Finished | Jul 25 06:53:59 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-d987dd80-a906-4d90-8f9d-ff2cf07fd322 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635551569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.3635551569 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2961427720 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 1374372450 ps |
CPU time | 6.29 seconds |
Started | Jul 25 06:51:41 PM PDT 24 |
Finished | Jul 25 06:51:48 PM PDT 24 |
Peak memory | 211320 kb |
Host | smart-8e1821c0-1aba-4336-b329-d516ea67b3cb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961427720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2961427720 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.298229071 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 9033598716 ps |
CPU time | 723.13 seconds |
Started | Jul 25 06:51:47 PM PDT 24 |
Finished | Jul 25 07:03:50 PM PDT 24 |
Peak memory | 379068 kb |
Host | smart-87208043-b0f3-415c-a969-6b88ce335bbf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298229071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sram_ctrl_access_during_key_req.298229071 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.1518079618 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 42607676 ps |
CPU time | 0.65 seconds |
Started | Jul 25 06:51:47 PM PDT 24 |
Finished | Jul 25 06:51:48 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-373de9c1-c2ee-430e-9eff-8ea32179059d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518079618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.1518079618 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.2828613914 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 37031909914 ps |
CPU time | 858.03 seconds |
Started | Jul 25 06:51:42 PM PDT 24 |
Finished | Jul 25 07:06:00 PM PDT 24 |
Peak memory | 203892 kb |
Host | smart-066bbeb7-5bfa-440c-9f81-e7573adf2362 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828613914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .2828613914 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.2296497686 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 9611543760 ps |
CPU time | 464.77 seconds |
Started | Jul 25 06:51:46 PM PDT 24 |
Finished | Jul 25 06:59:31 PM PDT 24 |
Peak memory | 377020 kb |
Host | smart-c03940c8-0b4f-4b76-a95f-f3de24cb3804 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296497686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.2296497686 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.1227627006 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 45768519676 ps |
CPU time | 82.28 seconds |
Started | Jul 25 06:51:49 PM PDT 24 |
Finished | Jul 25 06:53:11 PM PDT 24 |
Peak memory | 215764 kb |
Host | smart-47a3bff8-8656-44c9-a00b-1760fcefcc8f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227627006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.1227627006 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.9633907 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 2501634502 ps |
CPU time | 8.14 seconds |
Started | Jul 25 06:51:46 PM PDT 24 |
Finished | Jul 25 06:51:54 PM PDT 24 |
Peak memory | 219588 kb |
Host | smart-99e157b8-66cc-4efb-be74-2d80d7eca685 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9633907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 39.sram_ctrl_max_throughput.9633907 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2965635898 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 1392483522 ps |
CPU time | 71.89 seconds |
Started | Jul 25 06:51:46 PM PDT 24 |
Finished | Jul 25 06:52:58 PM PDT 24 |
Peak memory | 219440 kb |
Host | smart-db971ac0-e27e-4da5-bcfc-91a12ff7e8eb |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965635898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.2965635898 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.977058685 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 27629697620 ps |
CPU time | 161.72 seconds |
Started | Jul 25 06:51:46 PM PDT 24 |
Finished | Jul 25 06:54:28 PM PDT 24 |
Peak memory | 204368 kb |
Host | smart-f697b646-b707-48a9-9bdf-fcc3bbfa4d86 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977058685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _mem_walk.977058685 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.1227591997 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 12769349207 ps |
CPU time | 1140.79 seconds |
Started | Jul 25 06:51:40 PM PDT 24 |
Finished | Jul 25 07:10:41 PM PDT 24 |
Peak memory | 381104 kb |
Host | smart-442ad11a-54ad-4a81-b1f9-36e69b623fce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227591997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.1227591997 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.3149835926 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 1516901994 ps |
CPU time | 8.81 seconds |
Started | Jul 25 06:51:48 PM PDT 24 |
Finished | Jul 25 06:51:57 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-e84e9483-339f-4965-9d90-64b4c7784340 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149835926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.3149835926 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1809735287 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 59680594053 ps |
CPU time | 367.6 seconds |
Started | Jul 25 06:51:45 PM PDT 24 |
Finished | Jul 25 06:57:53 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-96c13b43-32cb-40ab-be8e-5ac97edc5caf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809735287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.1809735287 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.793570188 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 1260295577 ps |
CPU time | 3.45 seconds |
Started | Jul 25 06:51:47 PM PDT 24 |
Finished | Jul 25 06:51:50 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-0474c8b3-cd7b-4e0b-b12e-3b610e447239 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793570188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.793570188 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.3775830332 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 2927403596 ps |
CPU time | 88.35 seconds |
Started | Jul 25 06:51:47 PM PDT 24 |
Finished | Jul 25 06:53:15 PM PDT 24 |
Peak memory | 333456 kb |
Host | smart-ddb52d97-ea84-4d08-86fc-41f56c2641d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775830332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3775830332 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.838266378 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 1319954050 ps |
CPU time | 15.61 seconds |
Started | Jul 25 06:51:41 PM PDT 24 |
Finished | Jul 25 06:51:57 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-0c1510d1-1c2f-462d-adcf-c88bc6ecd747 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838266378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.838266378 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.3046385237 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 259270525714 ps |
CPU time | 2452.09 seconds |
Started | Jul 25 06:51:46 PM PDT 24 |
Finished | Jul 25 07:32:39 PM PDT 24 |
Peak memory | 294248 kb |
Host | smart-23059842-63ef-4d2a-a5ab-e2c2a069c6c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046385237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.3046385237 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.601080065 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 959118834 ps |
CPU time | 137.98 seconds |
Started | Jul 25 06:51:49 PM PDT 24 |
Finished | Jul 25 06:54:07 PM PDT 24 |
Peak memory | 379008 kb |
Host | smart-2fa7e6ec-5082-45ed-bbf0-65a7898e6d38 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=601080065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.601080065 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2618697804 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 8637313485 ps |
CPU time | 324.5 seconds |
Started | Jul 25 06:51:46 PM PDT 24 |
Finished | Jul 25 06:57:11 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-5c1ffb7e-cf27-40a6-a13f-3a46dc46b6ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618697804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.2618697804 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3357597796 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 781707859 ps |
CPU time | 47.26 seconds |
Started | Jul 25 06:51:49 PM PDT 24 |
Finished | Jul 25 06:52:36 PM PDT 24 |
Peak memory | 301232 kb |
Host | smart-9a520551-d9a5-4468-b17d-9a5b7cd099e1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357597796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3357597796 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1721333605 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 33424513592 ps |
CPU time | 1193.54 seconds |
Started | Jul 25 06:46:10 PM PDT 24 |
Finished | Jul 25 07:06:03 PM PDT 24 |
Peak memory | 380056 kb |
Host | smart-6d24a776-4ce7-42df-8f34-68bc34352e8f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721333605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.1721333605 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.4076814132 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 38018567 ps |
CPU time | 0.63 seconds |
Started | Jul 25 06:46:19 PM PDT 24 |
Finished | Jul 25 06:46:20 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-b74d48ae-c404-47c7-a8a5-8baa4caa6fef |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076814132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.4076814132 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.1972879156 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 106067435794 ps |
CPU time | 2394.75 seconds |
Started | Jul 25 06:46:13 PM PDT 24 |
Finished | Jul 25 07:26:08 PM PDT 24 |
Peak memory | 203328 kb |
Host | smart-99e66e30-a453-409a-96b1-022502ea02b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972879156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 1972879156 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.1944615152 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 37447663369 ps |
CPU time | 663.01 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:57:14 PM PDT 24 |
Peak memory | 369324 kb |
Host | smart-d7453311-1408-4c8f-9807-b0c6d715a139 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944615152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.1944615152 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.3023870533 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 48824558040 ps |
CPU time | 92.76 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:47:44 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-bd437535-c08b-4d3b-ad98-d1fbebdbb522 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023870533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.3023870533 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.320318019 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 731987112 ps |
CPU time | 15.31 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:46:26 PM PDT 24 |
Peak memory | 252108 kb |
Host | smart-568ce41c-10ed-4fa8-8406-ea2fc04ee9bd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320318019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.sram_ctrl_max_throughput.320318019 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3369437028 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 10943484329 ps |
CPU time | 77.5 seconds |
Started | Jul 25 06:46:10 PM PDT 24 |
Finished | Jul 25 06:47:28 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-1ed1ecb7-910f-4633-914c-db5588024ff8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369437028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.3369437028 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.2164076073 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 21541454465 ps |
CPU time | 345.82 seconds |
Started | Jul 25 06:46:10 PM PDT 24 |
Finished | Jul 25 06:51:56 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-69557c76-0d4c-482e-b04d-86e32fa37f1f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164076073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.2164076073 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.1470136147 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 70682227257 ps |
CPU time | 1042.38 seconds |
Started | Jul 25 06:46:12 PM PDT 24 |
Finished | Jul 25 07:03:35 PM PDT 24 |
Peak memory | 380084 kb |
Host | smart-8c7e03c7-45a9-449e-bd62-ed0ba974db7f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470136147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.1470136147 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.1884879502 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 1723681426 ps |
CPU time | 17.3 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:46:29 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-1f6eaa66-4fc6-401f-8ef7-444df9286b48 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884879502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.1884879502 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3983272994 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 43206518752 ps |
CPU time | 513.09 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:54:44 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-ff11b237-d6e4-4eb2-90c6-547d44268c8a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983272994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.3983272994 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.1596161710 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 1467558021 ps |
CPU time | 3.79 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:46:15 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-cefa10e2-88cc-4922-a5dc-8e1506ea2732 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596161710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1596161710 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.288246441 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 167250778367 ps |
CPU time | 520.88 seconds |
Started | Jul 25 06:46:10 PM PDT 24 |
Finished | Jul 25 06:54:51 PM PDT 24 |
Peak memory | 376136 kb |
Host | smart-b4540a12-3f4b-47a9-8506-a78468a9b186 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288246441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.288246441 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.3134807683 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 789685716 ps |
CPU time | 3.35 seconds |
Started | Jul 25 06:46:18 PM PDT 24 |
Finished | Jul 25 06:46:22 PM PDT 24 |
Peak memory | 222564 kb |
Host | smart-b15eea12-ec2a-4c2d-b976-fea9a18e04c6 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134807683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.3134807683 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.2223711211 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 8159053562 ps |
CPU time | 21.78 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:46:33 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-e05f7444-c243-47a6-b6e3-ef40f5c452d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223711211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2223711211 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.2146278180 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 198424551667 ps |
CPU time | 5539.6 seconds |
Started | Jul 25 06:46:24 PM PDT 24 |
Finished | Jul 25 08:18:45 PM PDT 24 |
Peak memory | 380108 kb |
Host | smart-eabb7775-d0b0-4d77-9cf1-3dabacaa5bb1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146278180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.2146278180 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3505682894 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 1860848066 ps |
CPU time | 22.64 seconds |
Started | Jul 25 06:46:21 PM PDT 24 |
Finished | Jul 25 06:46:44 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-6247a786-8051-45ec-9d0b-7a0f7a9374ca |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3505682894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3505682894 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2941335816 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 4955553201 ps |
CPU time | 370.7 seconds |
Started | Jul 25 06:46:12 PM PDT 24 |
Finished | Jul 25 06:52:23 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-386a57a3-20ab-49a6-aab2-8a8d5d14a39f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941335816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.2941335816 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3261980322 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 1572299672 ps |
CPU time | 79.97 seconds |
Started | Jul 25 06:46:11 PM PDT 24 |
Finished | Jul 25 06:47:31 PM PDT 24 |
Peak memory | 372912 kb |
Host | smart-ad101010-4d78-46a1-a1c9-4396fbedbee0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261980322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3261980322 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3084539440 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 43391872115 ps |
CPU time | 1423.57 seconds |
Started | Jul 25 06:51:53 PM PDT 24 |
Finished | Jul 25 07:15:37 PM PDT 24 |
Peak memory | 380104 kb |
Host | smart-d73fc06d-142d-42e2-b127-39fcd0151bbd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084539440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.3084539440 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.715304985 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 23768460 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:51:55 PM PDT 24 |
Finished | Jul 25 06:51:56 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-ede22f56-fbb0-419a-baa2-784ff8c7787c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715304985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.715304985 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.1454421249 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 15335369792 ps |
CPU time | 477.15 seconds |
Started | Jul 25 06:51:49 PM PDT 24 |
Finished | Jul 25 06:59:46 PM PDT 24 |
Peak memory | 203924 kb |
Host | smart-408f2060-7fa1-4917-adda-b55d648865f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454421249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .1454421249 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.4022121120 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 7856036669 ps |
CPU time | 1091.42 seconds |
Started | Jul 25 06:51:58 PM PDT 24 |
Finished | Jul 25 07:10:09 PM PDT 24 |
Peak memory | 378284 kb |
Host | smart-f58b04bb-300d-474e-a9ac-69470af8d91f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022121120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.4022121120 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.1347996818 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 4102309686 ps |
CPU time | 21.9 seconds |
Started | Jul 25 06:51:53 PM PDT 24 |
Finished | Jul 25 06:52:15 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-b15e2668-d3da-4330-8bb4-8abb4c3f7bf5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347996818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.1347996818 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.213022107 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 710879832 ps |
CPU time | 22.43 seconds |
Started | Jul 25 06:51:53 PM PDT 24 |
Finished | Jul 25 06:52:16 PM PDT 24 |
Peak memory | 271748 kb |
Host | smart-92ba992f-ffaa-4b7c-8d19-1c659baca371 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213022107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.sram_ctrl_max_throughput.213022107 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2227157179 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 4851274119 ps |
CPU time | 140.79 seconds |
Started | Jul 25 06:51:55 PM PDT 24 |
Finished | Jul 25 06:54:16 PM PDT 24 |
Peak memory | 219516 kb |
Host | smart-092f7d20-10e0-4799-a773-d671447cfbe6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227157179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.2227157179 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.2187278729 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 10952687482 ps |
CPU time | 156.73 seconds |
Started | Jul 25 06:51:54 PM PDT 24 |
Finished | Jul 25 06:54:31 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-c7155153-6925-477c-9cfd-16ce97ac7809 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187278729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.2187278729 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.2160147407 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 12835258441 ps |
CPU time | 1142.35 seconds |
Started | Jul 25 06:51:45 PM PDT 24 |
Finished | Jul 25 07:10:48 PM PDT 24 |
Peak memory | 372956 kb |
Host | smart-9079545e-6c60-4fa5-a2b2-c719a4e3a0b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160147407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.2160147407 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.814060231 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 1636125061 ps |
CPU time | 99.34 seconds |
Started | Jul 25 06:51:53 PM PDT 24 |
Finished | Jul 25 06:53:32 PM PDT 24 |
Peak memory | 341152 kb |
Host | smart-21683229-7d2e-4048-a064-6804b7a5daf3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814060231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s ram_ctrl_partial_access.814060231 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1510807418 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 58383813597 ps |
CPU time | 359.67 seconds |
Started | Jul 25 06:51:55 PM PDT 24 |
Finished | Jul 25 06:57:55 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-6c09e36c-572d-45a9-8356-30fb86937e3d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510807418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.1510807418 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.1686217395 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 347372306 ps |
CPU time | 3.05 seconds |
Started | Jul 25 06:51:55 PM PDT 24 |
Finished | Jul 25 06:51:58 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-5a67c796-53a6-400f-a16d-98cae3105027 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686217395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1686217395 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.4239774573 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 6196184569 ps |
CPU time | 626.03 seconds |
Started | Jul 25 06:51:53 PM PDT 24 |
Finished | Jul 25 07:02:19 PM PDT 24 |
Peak memory | 379180 kb |
Host | smart-a34bf701-2cc9-49f9-ae39-7d6337af177c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239774573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.4239774573 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.2006775395 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 1031851554 ps |
CPU time | 11.4 seconds |
Started | Jul 25 06:51:46 PM PDT 24 |
Finished | Jul 25 06:51:58 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-ed074d17-7544-4f0b-891b-6e1ee3e30e82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006775395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2006775395 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.1715960902 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 123478931410 ps |
CPU time | 1589.03 seconds |
Started | Jul 25 06:51:56 PM PDT 24 |
Finished | Jul 25 07:18:25 PM PDT 24 |
Peak memory | 380172 kb |
Host | smart-93ce894f-8bc4-4069-aaff-950810e5507b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715960902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.1715960902 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2947650722 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 57047877661 ps |
CPU time | 317.1 seconds |
Started | Jul 25 06:51:56 PM PDT 24 |
Finished | Jul 25 06:57:14 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-891688ba-3448-4a1f-8faa-dd03913d5aa3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947650722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.2947650722 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2257158866 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 12131200181 ps |
CPU time | 41.02 seconds |
Started | Jul 25 06:53:11 PM PDT 24 |
Finished | Jul 25 06:53:53 PM PDT 24 |
Peak memory | 288012 kb |
Host | smart-4050c60a-2a68-4527-8ac6-c5fba0b9955d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257158866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.2257158866 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1859497092 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 18304703961 ps |
CPU time | 460.18 seconds |
Started | Jul 25 06:52:03 PM PDT 24 |
Finished | Jul 25 06:59:43 PM PDT 24 |
Peak memory | 380200 kb |
Host | smart-a12b68f4-4235-464b-9572-de483d4a7dcd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859497092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.1859497092 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.2686454903 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 14922632 ps |
CPU time | 0.69 seconds |
Started | Jul 25 06:52:02 PM PDT 24 |
Finished | Jul 25 06:52:02 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-4bd588fe-5717-47ec-9b13-c1a6b099a708 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686454903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2686454903 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.2188055700 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 94507298020 ps |
CPU time | 1166.26 seconds |
Started | Jul 25 06:52:00 PM PDT 24 |
Finished | Jul 25 07:11:27 PM PDT 24 |
Peak memory | 203964 kb |
Host | smart-fa80db31-8895-4848-8ecc-c0e10ef32caa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188055700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .2188055700 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.4045266418 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 47076667974 ps |
CPU time | 1285.33 seconds |
Started | Jul 25 06:52:01 PM PDT 24 |
Finished | Jul 25 07:13:27 PM PDT 24 |
Peak memory | 376000 kb |
Host | smart-ae676e1e-29db-4d0e-96f0-ee38e2c048f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045266418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.4045266418 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.3312249386 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 13818610029 ps |
CPU time | 57.68 seconds |
Started | Jul 25 06:52:00 PM PDT 24 |
Finished | Jul 25 06:52:58 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-377db6b8-5e81-452a-8eee-66652bfc22ca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312249386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3312249386 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.3080554611 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 766032536 ps |
CPU time | 76.93 seconds |
Started | Jul 25 06:52:01 PM PDT 24 |
Finished | Jul 25 06:53:18 PM PDT 24 |
Peak memory | 341180 kb |
Host | smart-415c8702-f604-41f2-9fe8-563f185c3896 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080554611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.3080554611 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3392375235 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 11808814128 ps |
CPU time | 84.35 seconds |
Started | Jul 25 06:52:03 PM PDT 24 |
Finished | Jul 25 06:53:27 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-24f20d98-a4f4-4a7d-8019-ff782ac5f942 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392375235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.3392375235 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.3366044465 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 7903320509 ps |
CPU time | 132.38 seconds |
Started | Jul 25 06:52:00 PM PDT 24 |
Finished | Jul 25 06:54:12 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-1bf5c6d2-72b4-48f3-849c-5e125b929276 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366044465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.3366044465 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.3522053945 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 26114302720 ps |
CPU time | 1472.36 seconds |
Started | Jul 25 06:52:01 PM PDT 24 |
Finished | Jul 25 07:16:33 PM PDT 24 |
Peak memory | 379044 kb |
Host | smart-243c61f8-2048-49fd-8a46-f85a23085b16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522053945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.3522053945 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.1984122747 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 820315318 ps |
CPU time | 14.44 seconds |
Started | Jul 25 06:52:02 PM PDT 24 |
Finished | Jul 25 06:52:16 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-ef5fb1ad-0d80-429b-92de-8cd6f09cce90 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984122747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.1984122747 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4008075062 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 52952533451 ps |
CPU time | 376.58 seconds |
Started | Jul 25 06:52:00 PM PDT 24 |
Finished | Jul 25 06:58:16 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-f2735433-8840-467f-9f1c-811ff3ba5685 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008075062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.4008075062 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.311464991 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 723370312 ps |
CPU time | 3.47 seconds |
Started | Jul 25 06:52:00 PM PDT 24 |
Finished | Jul 25 06:52:04 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-c59698fb-0245-4abc-b189-ad1c18dfb22f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311464991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.311464991 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.2441461641 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 43245947364 ps |
CPU time | 346.11 seconds |
Started | Jul 25 06:52:03 PM PDT 24 |
Finished | Jul 25 06:57:50 PM PDT 24 |
Peak memory | 318792 kb |
Host | smart-568f4467-face-4175-bc11-bc70a768cd36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441461641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2441461641 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.1873384496 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 587428189 ps |
CPU time | 28.69 seconds |
Started | Jul 25 06:52:03 PM PDT 24 |
Finished | Jul 25 06:52:31 PM PDT 24 |
Peak memory | 280840 kb |
Host | smart-c2aa9ac1-8097-4450-9c41-a1f36e327367 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873384496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1873384496 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.1941760349 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 23337710166 ps |
CPU time | 2321.92 seconds |
Started | Jul 25 06:52:00 PM PDT 24 |
Finished | Jul 25 07:30:42 PM PDT 24 |
Peak memory | 383196 kb |
Host | smart-48ebc94c-b855-45b1-b42b-3b2b09fb702c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941760349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.1941760349 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1646582270 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 461763123 ps |
CPU time | 9.45 seconds |
Started | Jul 25 06:52:04 PM PDT 24 |
Finished | Jul 25 06:52:14 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-6da29818-c7d9-4819-9123-e1e4c50f0495 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1646582270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1646582270 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.512510041 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 3802792226 ps |
CPU time | 260.84 seconds |
Started | Jul 25 06:52:02 PM PDT 24 |
Finished | Jul 25 06:56:23 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-ddcbc10d-c6d0-4eb5-9c54-8361655dc389 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512510041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_stress_pipeline.512510041 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1186745716 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 3371068685 ps |
CPU time | 62.24 seconds |
Started | Jul 25 06:52:01 PM PDT 24 |
Finished | Jul 25 06:53:03 PM PDT 24 |
Peak memory | 308300 kb |
Host | smart-07d9419e-ac83-40f8-bdbb-98ff84a78b06 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186745716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1186745716 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2921719889 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 18939866587 ps |
CPU time | 344.79 seconds |
Started | Jul 25 06:52:21 PM PDT 24 |
Finished | Jul 25 06:58:06 PM PDT 24 |
Peak memory | 373900 kb |
Host | smart-edb73384-cb14-460f-82d3-22cfbedfe5f5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921719889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.2921719889 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.1069899868 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 13441995 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:52:21 PM PDT 24 |
Finished | Jul 25 06:52:22 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-e1dbbd27-3d15-4d3e-87cb-3b8a9f9ef454 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069899868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.1069899868 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.1469718481 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 34321431440 ps |
CPU time | 1074.42 seconds |
Started | Jul 25 06:52:06 PM PDT 24 |
Finished | Jul 25 07:10:01 PM PDT 24 |
Peak memory | 204056 kb |
Host | smart-3022885c-e893-4076-9dae-f438e4ca607d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469718481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .1469718481 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.3363658302 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 10926239640 ps |
CPU time | 713.13 seconds |
Started | Jul 25 06:52:42 PM PDT 24 |
Finished | Jul 25 07:04:36 PM PDT 24 |
Peak memory | 377072 kb |
Host | smart-889c99da-74fd-46fe-8165-999c094387fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363658302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.3363658302 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.2441795063 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 7609093522 ps |
CPU time | 51.52 seconds |
Started | Jul 25 06:52:06 PM PDT 24 |
Finished | Jul 25 06:52:58 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-2bf511a9-f05c-43ea-9b0b-f59f5774f56e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441795063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.2441795063 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.3539974003 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 3149618001 ps |
CPU time | 131.43 seconds |
Started | Jul 25 06:52:05 PM PDT 24 |
Finished | Jul 25 06:54:17 PM PDT 24 |
Peak memory | 358616 kb |
Host | smart-35ee9019-f478-49ec-b284-4bd489739c5a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539974003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.3539974003 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3529310744 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 9128830510 ps |
CPU time | 154.73 seconds |
Started | Jul 25 06:52:24 PM PDT 24 |
Finished | Jul 25 06:54:59 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-71d428ba-c1b3-4363-8026-e6936b2bfc18 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529310744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.3529310744 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.1671786040 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 34599767874 ps |
CPU time | 169.04 seconds |
Started | Jul 25 06:52:21 PM PDT 24 |
Finished | Jul 25 06:55:11 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-ab4d27be-f7dc-4f5e-937d-4b1ffd3279ee |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671786040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.1671786040 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.2537870123 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 132458469436 ps |
CPU time | 1192.69 seconds |
Started | Jul 25 06:52:00 PM PDT 24 |
Finished | Jul 25 07:11:53 PM PDT 24 |
Peak memory | 365772 kb |
Host | smart-fc870ed4-5cc1-4da8-8a66-d9db082775da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537870123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.2537870123 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.2823681835 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 2909491305 ps |
CPU time | 10.79 seconds |
Started | Jul 25 06:52:05 PM PDT 24 |
Finished | Jul 25 06:52:16 PM PDT 24 |
Peak memory | 225380 kb |
Host | smart-fbae1a7a-be54-4b38-bd34-e17536d665e4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823681835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.2823681835 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3690039951 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 23330227023 ps |
CPU time | 337.49 seconds |
Started | Jul 25 06:52:07 PM PDT 24 |
Finished | Jul 25 06:57:45 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-45e0bfca-6511-4ed5-bb6c-71dcef764ae0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690039951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.3690039951 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.3568420580 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 368080463 ps |
CPU time | 3.35 seconds |
Started | Jul 25 06:52:22 PM PDT 24 |
Finished | Jul 25 06:52:25 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-ba8a4900-b48d-4637-8808-054c0b3a0c31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568420580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3568420580 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.3095844689 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 3827075390 ps |
CPU time | 213.47 seconds |
Started | Jul 25 06:52:20 PM PDT 24 |
Finished | Jul 25 06:55:54 PM PDT 24 |
Peak memory | 370604 kb |
Host | smart-88433f78-64ba-402c-a5f6-98087611e60b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095844689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3095844689 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.1536861084 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 896102986 ps |
CPU time | 15.54 seconds |
Started | Jul 25 06:52:03 PM PDT 24 |
Finished | Jul 25 06:52:19 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-f560ea32-8626-4fb8-bc9a-d585047927d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536861084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1536861084 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.1800449637 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 129573028205 ps |
CPU time | 3413.13 seconds |
Started | Jul 25 06:52:22 PM PDT 24 |
Finished | Jul 25 07:49:16 PM PDT 24 |
Peak memory | 372944 kb |
Host | smart-cb9dea7f-62b1-4736-86f1-58d5841d17b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800449637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1800449637 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.703596427 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 215607634 ps |
CPU time | 9.35 seconds |
Started | Jul 25 06:52:22 PM PDT 24 |
Finished | Jul 25 06:52:32 PM PDT 24 |
Peak memory | 211960 kb |
Host | smart-bc917874-9ca6-4f45-b614-975112163065 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=703596427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.703596427 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1726359711 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 7347810054 ps |
CPU time | 257.44 seconds |
Started | Jul 25 06:52:08 PM PDT 24 |
Finished | Jul 25 06:56:25 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-15111549-cd65-49e7-a339-afa644441664 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726359711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.1726359711 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2034538448 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 1517674852 ps |
CPU time | 33 seconds |
Started | Jul 25 06:52:08 PM PDT 24 |
Finished | Jul 25 06:52:41 PM PDT 24 |
Peak memory | 292972 kb |
Host | smart-05dd0d0a-0bfc-438c-8975-d31c44a3a604 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034538448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2034538448 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.551968039 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 15127259792 ps |
CPU time | 1317.77 seconds |
Started | Jul 25 06:52:28 PM PDT 24 |
Finished | Jul 25 07:14:26 PM PDT 24 |
Peak memory | 379788 kb |
Host | smart-ef3b9699-4cc3-41a7-95fd-c892cd0b7da7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551968039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 43.sram_ctrl_access_during_key_req.551968039 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.1511473886 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 21032098 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:52:37 PM PDT 24 |
Finished | Jul 25 06:52:37 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-55d99e5b-ba1a-4d25-b59b-ce15145d1d64 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511473886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1511473886 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.1583942586 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 154258351333 ps |
CPU time | 898.77 seconds |
Started | Jul 25 06:52:22 PM PDT 24 |
Finished | Jul 25 07:07:21 PM PDT 24 |
Peak memory | 203824 kb |
Host | smart-9a0f9f91-3b4b-4298-8da4-78d638b90326 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583942586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .1583942586 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.482440627 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 7138580608 ps |
CPU time | 620.83 seconds |
Started | Jul 25 06:52:29 PM PDT 24 |
Finished | Jul 25 07:02:50 PM PDT 24 |
Peak memory | 377032 kb |
Host | smart-ebc18312-e456-4b97-b025-705c3ac06c1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482440627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl e.482440627 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.162205279 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 7272988501 ps |
CPU time | 41.78 seconds |
Started | Jul 25 06:52:29 PM PDT 24 |
Finished | Jul 25 06:53:11 PM PDT 24 |
Peak memory | 211500 kb |
Host | smart-1bfc5127-021b-4630-b28f-956aad77effd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162205279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc alation.162205279 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.3454417108 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 2981198855 ps |
CPU time | 150.12 seconds |
Started | Jul 25 06:52:24 PM PDT 24 |
Finished | Jul 25 06:54:54 PM PDT 24 |
Peak memory | 370888 kb |
Host | smart-03e4c4ea-391a-40d4-a2f4-f241cd3f9e0a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454417108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.3454417108 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3338883803 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 13757521503 ps |
CPU time | 89.12 seconds |
Started | Jul 25 06:52:29 PM PDT 24 |
Finished | Jul 25 06:53:58 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-c622b7c5-71db-47a1-8874-4da6961ac455 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338883803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.3338883803 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.2142728060 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 13969677792 ps |
CPU time | 302.66 seconds |
Started | Jul 25 06:52:28 PM PDT 24 |
Finished | Jul 25 06:57:31 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-4adddba7-f96b-4d5a-8555-8a5724bed3af |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142728060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.2142728060 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.2090318295 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 145061367141 ps |
CPU time | 1141.52 seconds |
Started | Jul 25 06:52:23 PM PDT 24 |
Finished | Jul 25 07:11:25 PM PDT 24 |
Peak memory | 382188 kb |
Host | smart-737141be-a2c5-4645-ab69-863699c5b35a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090318295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2090318295 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.2378003146 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 1521466947 ps |
CPU time | 67.75 seconds |
Started | Jul 25 06:52:22 PM PDT 24 |
Finished | Jul 25 06:53:30 PM PDT 24 |
Peak memory | 310440 kb |
Host | smart-44d48633-fa51-4998-a170-9f4d9eb81208 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378003146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.2378003146 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3981451861 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 66800252182 ps |
CPU time | 269.77 seconds |
Started | Jul 25 06:52:23 PM PDT 24 |
Finished | Jul 25 06:56:53 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-c814ac1c-b0e7-4370-93f2-79cd7634a12f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981451861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3981451861 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.2007115060 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 1550861989 ps |
CPU time | 3.54 seconds |
Started | Jul 25 06:52:29 PM PDT 24 |
Finished | Jul 25 06:52:33 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-d0d76ca0-a151-4877-aaab-cb5acfe1d66d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007115060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.2007115060 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.3877731298 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 434915720 ps |
CPU time | 43.12 seconds |
Started | Jul 25 06:52:21 PM PDT 24 |
Finished | Jul 25 06:53:04 PM PDT 24 |
Peak memory | 302264 kb |
Host | smart-7a803721-585b-4819-81da-4e953d8fff1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877731298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3877731298 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.357648499 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 95018219299 ps |
CPU time | 4260.14 seconds |
Started | Jul 25 06:52:37 PM PDT 24 |
Finished | Jul 25 08:03:38 PM PDT 24 |
Peak memory | 381180 kb |
Host | smart-d7aeff98-cdfb-4c02-be75-426977260f51 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357648499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_stress_all.357648499 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3057756265 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 2246175830 ps |
CPU time | 43.54 seconds |
Started | Jul 25 06:52:38 PM PDT 24 |
Finished | Jul 25 06:53:21 PM PDT 24 |
Peak memory | 211516 kb |
Host | smart-603be633-89d0-4110-a4f1-ef22cafa0efc |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3057756265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3057756265 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1828281134 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 2851557190 ps |
CPU time | 226.41 seconds |
Started | Jul 25 06:52:23 PM PDT 24 |
Finished | Jul 25 06:56:10 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-d85114c9-7c68-4e7e-8c25-fb6453fe1920 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828281134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.1828281134 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.158034183 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 2919336029 ps |
CPU time | 84.83 seconds |
Started | Jul 25 06:52:30 PM PDT 24 |
Finished | Jul 25 06:53:55 PM PDT 24 |
Peak memory | 341056 kb |
Host | smart-1fa2573f-79b4-462c-b594-3744832931cc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158034183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_throughput_w_partial_write.158034183 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1181451171 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 15782685746 ps |
CPU time | 359.39 seconds |
Started | Jul 25 06:52:37 PM PDT 24 |
Finished | Jul 25 06:58:36 PM PDT 24 |
Peak memory | 367168 kb |
Host | smart-0d96d63b-f598-4e21-abd8-140907314e64 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181451171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.1181451171 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.2988346653 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 25640646 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:52:44 PM PDT 24 |
Finished | Jul 25 06:52:45 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-ac503cea-99eb-47eb-be3f-4cbb64c5a0f8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988346653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2988346653 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.888506330 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 45252103271 ps |
CPU time | 1608.92 seconds |
Started | Jul 25 06:52:36 PM PDT 24 |
Finished | Jul 25 07:19:26 PM PDT 24 |
Peak memory | 203912 kb |
Host | smart-dd6d6fab-0c99-42fe-9cd5-e743cfc6d9ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888506330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection. 888506330 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.1522264353 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 14781660263 ps |
CPU time | 826.8 seconds |
Started | Jul 25 06:52:38 PM PDT 24 |
Finished | Jul 25 07:06:25 PM PDT 24 |
Peak memory | 378076 kb |
Host | smart-05648ee9-0295-431e-8859-a26aa4b671b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522264353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.1522264353 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.247199726 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 3507540255 ps |
CPU time | 22.17 seconds |
Started | Jul 25 06:52:38 PM PDT 24 |
Finished | Jul 25 06:53:00 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-e380c866-0a10-4480-98a6-4c24052f01c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247199726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_esc alation.247199726 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.3142428197 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 1806773721 ps |
CPU time | 65.46 seconds |
Started | Jul 25 06:52:35 PM PDT 24 |
Finished | Jul 25 06:53:41 PM PDT 24 |
Peak memory | 320712 kb |
Host | smart-60ca97bf-52b8-4741-900e-e2ac7e45751f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142428197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.3142428197 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2450091702 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 9806284085 ps |
CPU time | 155.79 seconds |
Started | Jul 25 06:52:36 PM PDT 24 |
Finished | Jul 25 06:55:12 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-b8a294ae-1b97-4ae8-94ac-60936459df4d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450091702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.2450091702 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.1372459080 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 14570496468 ps |
CPU time | 309.63 seconds |
Started | Jul 25 06:52:36 PM PDT 24 |
Finished | Jul 25 06:57:46 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-654db8aa-a859-4209-bd47-ea3d626a08b7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372459080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1372459080 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.2952457195 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 12464336023 ps |
CPU time | 823.06 seconds |
Started | Jul 25 06:52:36 PM PDT 24 |
Finished | Jul 25 07:06:19 PM PDT 24 |
Peak memory | 372936 kb |
Host | smart-6b9bbc32-65f1-4ed7-a41e-272cc3230a8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952457195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.2952457195 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.3642512606 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 3384689783 ps |
CPU time | 16.93 seconds |
Started | Jul 25 06:52:36 PM PDT 24 |
Finished | Jul 25 06:52:53 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-4bff6b44-59af-42e5-a47b-3ac98d44c9ae |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642512606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.3642512606 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1214269625 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 15164975536 ps |
CPU time | 201.34 seconds |
Started | Jul 25 06:52:38 PM PDT 24 |
Finished | Jul 25 06:56:00 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-72bef46d-5073-406e-b370-75157de57eb9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214269625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.1214269625 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.773549906 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 509102892 ps |
CPU time | 3.24 seconds |
Started | Jul 25 06:52:35 PM PDT 24 |
Finished | Jul 25 06:52:39 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-90a3448a-b2a9-4ed0-9403-315cc1d40a7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773549906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.773549906 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.1985413343 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 3781163537 ps |
CPU time | 156.58 seconds |
Started | Jul 25 06:52:38 PM PDT 24 |
Finished | Jul 25 06:55:14 PM PDT 24 |
Peak memory | 363576 kb |
Host | smart-d7e7df31-abff-4ee6-b93c-0235406f79e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985413343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1985413343 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.2268655498 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 1423641779 ps |
CPU time | 4.33 seconds |
Started | Jul 25 06:52:37 PM PDT 24 |
Finished | Jul 25 06:52:42 PM PDT 24 |
Peak memory | 203368 kb |
Host | smart-a83203cf-6af6-4555-bfba-04c6369a9f71 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268655498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2268655498 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.3430695898 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 219907027424 ps |
CPU time | 7388.57 seconds |
Started | Jul 25 06:52:37 PM PDT 24 |
Finished | Jul 25 08:55:46 PM PDT 24 |
Peak memory | 378064 kb |
Host | smart-a1ef58d0-ba49-422c-96f1-a57d48ac0c84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430695898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.3430695898 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2214692306 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 5201382168 ps |
CPU time | 33.13 seconds |
Started | Jul 25 06:52:37 PM PDT 24 |
Finished | Jul 25 06:53:10 PM PDT 24 |
Peak memory | 243432 kb |
Host | smart-7b364699-f437-4c9d-95ff-5bfeabae075e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2214692306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2214692306 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.218473338 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 37075177389 ps |
CPU time | 185.34 seconds |
Started | Jul 25 06:52:36 PM PDT 24 |
Finished | Jul 25 06:55:42 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-6d1c8f35-3feb-4ca9-9fca-7ba8a848df1c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218473338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .sram_ctrl_stress_pipeline.218473338 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2341737772 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 698729674 ps |
CPU time | 6.11 seconds |
Started | Jul 25 06:52:35 PM PDT 24 |
Finished | Jul 25 06:52:41 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-08a8a922-f274-4034-9edc-2aaa4fefedb4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341737772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.2341737772 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.324835085 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 15408995616 ps |
CPU time | 146.09 seconds |
Started | Jul 25 06:52:55 PM PDT 24 |
Finished | Jul 25 06:55:21 PM PDT 24 |
Peak memory | 320760 kb |
Host | smart-a9609948-1c61-49bf-bc37-cbacca087fbc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324835085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 45.sram_ctrl_access_during_key_req.324835085 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.1678517766 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 20729702 ps |
CPU time | 0.62 seconds |
Started | Jul 25 06:52:51 PM PDT 24 |
Finished | Jul 25 06:52:52 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-7f0db10b-1e54-4533-b0fb-e9b3c197f248 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678517766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1678517766 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.3621847107 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 423459120101 ps |
CPU time | 1224.97 seconds |
Started | Jul 25 06:52:43 PM PDT 24 |
Finished | Jul 25 07:13:09 PM PDT 24 |
Peak memory | 203940 kb |
Host | smart-ceca1fa5-30bb-4c5a-b808-621431fcbe11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621847107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .3621847107 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.1713607053 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 14638131013 ps |
CPU time | 258.65 seconds |
Started | Jul 25 06:52:52 PM PDT 24 |
Finished | Jul 25 06:57:11 PM PDT 24 |
Peak memory | 340232 kb |
Host | smart-6a21b2bd-a57e-43a6-a4c1-9dce0119a09a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713607053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.1713607053 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.1340000961 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 11249457579 ps |
CPU time | 71.59 seconds |
Started | Jul 25 06:52:54 PM PDT 24 |
Finished | Jul 25 06:54:06 PM PDT 24 |
Peak memory | 211428 kb |
Host | smart-3cb373e4-b662-413c-84a8-a9b8c8e26e17 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340000961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.1340000961 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.4208228405 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 720992466 ps |
CPU time | 13.33 seconds |
Started | Jul 25 06:52:44 PM PDT 24 |
Finished | Jul 25 06:52:57 PM PDT 24 |
Peak memory | 240256 kb |
Host | smart-51cb4029-5573-4c30-a833-a361eb7124bf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208228405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.4208228405 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.4102490231 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 9646074390 ps |
CPU time | 167.46 seconds |
Started | Jul 25 06:52:54 PM PDT 24 |
Finished | Jul 25 06:55:42 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-6b7d9ebe-fdd6-4cc1-afc4-0b47c979d36a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102490231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.4102490231 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.3632996715 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 5371539338 ps |
CPU time | 154.79 seconds |
Started | Jul 25 06:52:52 PM PDT 24 |
Finished | Jul 25 06:55:27 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-7e8bf513-d913-46e0-b76b-3f84bbe9ada3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632996715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.3632996715 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.1146811080 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 16877337979 ps |
CPU time | 253.35 seconds |
Started | Jul 25 06:52:45 PM PDT 24 |
Finished | Jul 25 06:56:58 PM PDT 24 |
Peak memory | 376960 kb |
Host | smart-f1553c9a-74c7-40f9-9bd5-4dff699f4e5f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146811080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.1146811080 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.1789532867 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 1265470309 ps |
CPU time | 20.6 seconds |
Started | Jul 25 06:52:44 PM PDT 24 |
Finished | Jul 25 06:53:04 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-cd787184-4905-428d-bb9e-f1bc4cff35d7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789532867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.1789532867 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3513951545 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 20454688752 ps |
CPU time | 386.03 seconds |
Started | Jul 25 06:52:47 PM PDT 24 |
Finished | Jul 25 06:59:13 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-8c2e6b87-0605-4352-8510-b71e25657dc5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513951545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.3513951545 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.2508729204 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 629735624 ps |
CPU time | 3.6 seconds |
Started | Jul 25 06:53:01 PM PDT 24 |
Finished | Jul 25 06:53:05 PM PDT 24 |
Peak memory | 203064 kb |
Host | smart-747363ce-d6ba-4e1b-8cdc-d6e8de5f3c3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508729204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2508729204 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.3457658338 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 6350213338 ps |
CPU time | 268.3 seconds |
Started | Jul 25 06:52:52 PM PDT 24 |
Finished | Jul 25 06:57:21 PM PDT 24 |
Peak memory | 361872 kb |
Host | smart-24da1f96-8e9d-4467-aefc-91cbdba68a61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457658338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3457658338 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.817816085 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 1737397214 ps |
CPU time | 20.13 seconds |
Started | Jul 25 06:52:47 PM PDT 24 |
Finished | Jul 25 06:53:07 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-528e0a03-a109-4bc9-99fb-202868d817c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817816085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.817816085 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.4090458849 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 551750957030 ps |
CPU time | 6271.91 seconds |
Started | Jul 25 06:52:52 PM PDT 24 |
Finished | Jul 25 08:37:25 PM PDT 24 |
Peak memory | 383276 kb |
Host | smart-d3637722-9999-4379-8940-3fb59cb719c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090458849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.4090458849 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1740968596 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 5028053239 ps |
CPU time | 131.27 seconds |
Started | Jul 25 06:52:53 PM PDT 24 |
Finished | Jul 25 06:55:05 PM PDT 24 |
Peak memory | 337220 kb |
Host | smart-2c172112-af3f-448e-a0d4-204819ba54f1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1740968596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1740968596 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.4166669636 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 4461682138 ps |
CPU time | 282.42 seconds |
Started | Jul 25 06:52:46 PM PDT 24 |
Finished | Jul 25 06:57:29 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-a8decab4-0091-4efd-885b-1f6ce55dbf26 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166669636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.4166669636 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.13669455 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 3262327505 ps |
CPU time | 138.52 seconds |
Started | Jul 25 06:52:45 PM PDT 24 |
Finished | Jul 25 06:55:04 PM PDT 24 |
Peak memory | 371912 kb |
Host | smart-398b0edc-c0f3-49bb-949d-790475cc5a65 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.sram_ctrl_throughput_w_partial_write.13669455 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.52148203 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 15648996709 ps |
CPU time | 1101.08 seconds |
Started | Jul 25 06:53:02 PM PDT 24 |
Finished | Jul 25 07:11:23 PM PDT 24 |
Peak memory | 379272 kb |
Host | smart-0e258c5d-e17e-4f59-8593-d76c236fae94 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52148203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.sram_ctrl_access_during_key_req.52148203 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.2818142816 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 42959275 ps |
CPU time | 0.65 seconds |
Started | Jul 25 06:53:13 PM PDT 24 |
Finished | Jul 25 06:53:13 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-85665136-b9a0-4e9d-9f32-7229f78e30eb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818142816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2818142816 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.873868654 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 498278497447 ps |
CPU time | 2307.39 seconds |
Started | Jul 25 06:53:01 PM PDT 24 |
Finished | Jul 25 07:31:29 PM PDT 24 |
Peak memory | 203816 kb |
Host | smart-f767837f-7447-43ea-96a8-bd55faeead44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873868654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection. 873868654 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.3234567385 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 5484128519 ps |
CPU time | 33.96 seconds |
Started | Jul 25 06:53:02 PM PDT 24 |
Finished | Jul 25 06:53:36 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-dd17df5f-c452-4ff7-826d-1bcedbc3edd1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234567385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.3234567385 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.1165072515 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 1540466089 ps |
CPU time | 44.65 seconds |
Started | Jul 25 06:53:01 PM PDT 24 |
Finished | Jul 25 06:53:45 PM PDT 24 |
Peak memory | 323768 kb |
Host | smart-fc9f20a7-bd91-4e57-b2c8-62fe7b5853d0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165072515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.1165072515 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2071989568 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 5789589366 ps |
CPU time | 172.56 seconds |
Started | Jul 25 06:53:04 PM PDT 24 |
Finished | Jul 25 06:55:57 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-dbd016a1-aebe-4b54-b1e4-3d22eceac53e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071989568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.2071989568 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.1399946674 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 3983816413 ps |
CPU time | 252.47 seconds |
Started | Jul 25 06:53:01 PM PDT 24 |
Finished | Jul 25 06:57:14 PM PDT 24 |
Peak memory | 212564 kb |
Host | smart-755e7310-aefe-4441-8dbb-6f56ffc3b340 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399946674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.1399946674 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.3516551840 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 80459022628 ps |
CPU time | 889.82 seconds |
Started | Jul 25 06:52:54 PM PDT 24 |
Finished | Jul 25 07:07:44 PM PDT 24 |
Peak memory | 381120 kb |
Host | smart-4ebf965a-340b-4bed-88a4-90e820497e61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516551840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.3516551840 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.848249941 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 4208379619 ps |
CPU time | 7.64 seconds |
Started | Jul 25 06:53:01 PM PDT 24 |
Finished | Jul 25 06:53:09 PM PDT 24 |
Peak memory | 203032 kb |
Host | smart-d4af2a3c-e9b8-40c7-9229-df3bb4006614 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848249941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s ram_ctrl_partial_access.848249941 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1439359125 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 112157321148 ps |
CPU time | 285.71 seconds |
Started | Jul 25 06:53:02 PM PDT 24 |
Finished | Jul 25 06:57:48 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-23e76f49-91a1-4825-8178-9ad873f5dc1d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439359125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.1439359125 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.2333867433 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 1405118165 ps |
CPU time | 3.31 seconds |
Started | Jul 25 06:53:03 PM PDT 24 |
Finished | Jul 25 06:53:06 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-d35d08bf-7f61-4463-b507-01be969be694 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333867433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2333867433 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.1680158008 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 102386845060 ps |
CPU time | 943.62 seconds |
Started | Jul 25 06:53:03 PM PDT 24 |
Finished | Jul 25 07:08:47 PM PDT 24 |
Peak memory | 378076 kb |
Host | smart-3faa87cc-0679-4f52-8070-12f58b38f286 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680158008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1680158008 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.3427797520 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 2746507506 ps |
CPU time | 18.52 seconds |
Started | Jul 25 06:52:52 PM PDT 24 |
Finished | Jul 25 06:53:11 PM PDT 24 |
Peak memory | 267620 kb |
Host | smart-ec766adb-2d1a-4bec-aa12-c8ac4814abcd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427797520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3427797520 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.1173705215 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 65879256599 ps |
CPU time | 1490.86 seconds |
Started | Jul 25 06:53:14 PM PDT 24 |
Finished | Jul 25 07:18:05 PM PDT 24 |
Peak memory | 380148 kb |
Host | smart-9ce5716b-af46-4787-84ca-ab61c3aa6c98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173705215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.1173705215 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4263080352 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 1987549033 ps |
CPU time | 16.6 seconds |
Started | Jul 25 06:53:13 PM PDT 24 |
Finished | Jul 25 06:53:29 PM PDT 24 |
Peak memory | 211528 kb |
Host | smart-d1b41572-6ef8-481a-9118-adf9ffc0d729 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4263080352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.4263080352 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2718609069 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 14168472814 ps |
CPU time | 207.79 seconds |
Started | Jul 25 06:53:02 PM PDT 24 |
Finished | Jul 25 06:56:30 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-84901f7f-0c8f-4ee7-ad25-f30b88230be7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718609069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.2718609069 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.144248369 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 852443690 ps |
CPU time | 53.54 seconds |
Started | Jul 25 06:53:02 PM PDT 24 |
Finished | Jul 25 06:53:56 PM PDT 24 |
Peak memory | 301320 kb |
Host | smart-73f9d322-4ea7-48ce-a6c6-5d4c2775368a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144248369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_throughput_w_partial_write.144248369 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.850191781 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 59355858794 ps |
CPU time | 504.08 seconds |
Started | Jul 25 06:53:13 PM PDT 24 |
Finished | Jul 25 07:01:37 PM PDT 24 |
Peak memory | 377020 kb |
Host | smart-098c2848-94a4-4fe4-8e5e-d42fd41ab940 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850191781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 47.sram_ctrl_access_during_key_req.850191781 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.1653175393 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 22921426 ps |
CPU time | 0.65 seconds |
Started | Jul 25 06:53:22 PM PDT 24 |
Finished | Jul 25 06:53:23 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-a5e10175-40f1-42ea-a645-1eb36c5d18af |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653175393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1653175393 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.2167629927 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 39217983745 ps |
CPU time | 1316.38 seconds |
Started | Jul 25 06:53:13 PM PDT 24 |
Finished | Jul 25 07:15:10 PM PDT 24 |
Peak memory | 204008 kb |
Host | smart-9ac5902c-233b-47fa-875a-a466d594cf57 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167629927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .2167629927 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.3590237800 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 49020980611 ps |
CPU time | 614.87 seconds |
Started | Jul 25 06:53:12 PM PDT 24 |
Finished | Jul 25 07:03:27 PM PDT 24 |
Peak memory | 380084 kb |
Host | smart-5a3f99ec-a614-486f-a8d6-d6c121d52a20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590237800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.3590237800 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.999661472 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 10140948035 ps |
CPU time | 68.14 seconds |
Started | Jul 25 06:53:14 PM PDT 24 |
Finished | Jul 25 06:54:22 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-308bfa9e-035f-44ad-991a-c21f143ed4e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999661472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esc alation.999661472 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.377463063 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 3245220926 ps |
CPU time | 29.33 seconds |
Started | Jul 25 06:53:11 PM PDT 24 |
Finished | Jul 25 06:53:41 PM PDT 24 |
Peak memory | 284920 kb |
Host | smart-d63d4757-a292-4c28-b32b-dcd76ead59ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377463063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.sram_ctrl_max_throughput.377463063 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.652741083 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 10148158207 ps |
CPU time | 151.41 seconds |
Started | Jul 25 06:53:13 PM PDT 24 |
Finished | Jul 25 06:55:45 PM PDT 24 |
Peak memory | 219500 kb |
Host | smart-90ac8466-ee78-4539-af88-115149c02276 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652741083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_mem_partial_access.652741083 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.89685944 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 28857589770 ps |
CPU time | 163.97 seconds |
Started | Jul 25 06:53:11 PM PDT 24 |
Finished | Jul 25 06:55:55 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-be5c04d8-8fed-4172-8e76-8b22e460498a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89685944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ mem_walk.89685944 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.3632378514 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 24934950720 ps |
CPU time | 1322.38 seconds |
Started | Jul 25 06:53:15 PM PDT 24 |
Finished | Jul 25 07:15:18 PM PDT 24 |
Peak memory | 375016 kb |
Host | smart-3e5818a4-4ea3-4f1f-969f-c687dd4c2d2f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632378514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.3632378514 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.2040758369 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 3361206084 ps |
CPU time | 86.01 seconds |
Started | Jul 25 06:53:14 PM PDT 24 |
Finished | Jul 25 06:54:40 PM PDT 24 |
Peak memory | 332920 kb |
Host | smart-d5e91e66-d0f3-4968-a5cc-8bdc9f7a12e2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040758369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2040758369 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3836375683 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 78685678813 ps |
CPU time | 475.39 seconds |
Started | Jul 25 06:53:13 PM PDT 24 |
Finished | Jul 25 07:01:09 PM PDT 24 |
Peak memory | 203084 kb |
Host | smart-ab57c736-048b-47bc-946a-e778772ea6e6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836375683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.3836375683 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.1744510076 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 1361516120 ps |
CPU time | 3.4 seconds |
Started | Jul 25 06:53:12 PM PDT 24 |
Finished | Jul 25 06:53:16 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-0cb61d54-c503-48cb-a503-070ee0923cd9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744510076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1744510076 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.1430901826 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 7067659984 ps |
CPU time | 614.13 seconds |
Started | Jul 25 06:53:13 PM PDT 24 |
Finished | Jul 25 07:03:28 PM PDT 24 |
Peak memory | 369884 kb |
Host | smart-9ffc7abd-6954-4fea-a0fd-ebca57313777 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430901826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.1430901826 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.460977732 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 456334093 ps |
CPU time | 109.22 seconds |
Started | Jul 25 06:53:12 PM PDT 24 |
Finished | Jul 25 06:55:02 PM PDT 24 |
Peak memory | 352348 kb |
Host | smart-e38ffeb5-0de1-4bdc-983a-f9846230449f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460977732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.460977732 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.3599655472 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 44812496264 ps |
CPU time | 6355.72 seconds |
Started | Jul 25 06:53:23 PM PDT 24 |
Finished | Jul 25 08:39:19 PM PDT 24 |
Peak memory | 381204 kb |
Host | smart-ef4d693c-a617-4c9a-aaeb-e430095d3546 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599655472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.3599655472 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2346161374 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 9665814627 ps |
CPU time | 175.53 seconds |
Started | Jul 25 06:53:12 PM PDT 24 |
Finished | Jul 25 06:56:08 PM PDT 24 |
Peak memory | 359504 kb |
Host | smart-8019ff48-e55f-4fcc-b7af-645a89bc5efd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2346161374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2346161374 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1609922691 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 4720083445 ps |
CPU time | 304.47 seconds |
Started | Jul 25 06:53:11 PM PDT 24 |
Finished | Jul 25 06:58:15 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-3e282cb0-cc92-44ab-bb65-619bac0c718f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609922691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.1609922691 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.667257570 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 2891446398 ps |
CPU time | 31.44 seconds |
Started | Jul 25 06:53:11 PM PDT 24 |
Finished | Jul 25 06:53:43 PM PDT 24 |
Peak memory | 281888 kb |
Host | smart-f2f04938-e09e-4cfa-8c63-8ec66b84d74e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667257570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.667257570 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3179987719 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 39993202997 ps |
CPU time | 982.98 seconds |
Started | Jul 25 06:53:23 PM PDT 24 |
Finished | Jul 25 07:09:47 PM PDT 24 |
Peak memory | 375956 kb |
Host | smart-dc061e9b-fb27-4e3a-89b2-308306208975 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179987719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.3179987719 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.1098839695 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 25155189 ps |
CPU time | 0.65 seconds |
Started | Jul 25 06:54:46 PM PDT 24 |
Finished | Jul 25 06:54:47 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-a927af6e-891c-48b4-bc47-e6d67f5c6e03 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098839695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1098839695 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.2970431688 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 16448637345 ps |
CPU time | 555.21 seconds |
Started | Jul 25 06:53:24 PM PDT 24 |
Finished | Jul 25 07:02:39 PM PDT 24 |
Peak memory | 203940 kb |
Host | smart-cd94ec90-0870-4777-905e-6b8d5333b864 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970431688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .2970431688 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.2137088611 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 3030511313 ps |
CPU time | 468.48 seconds |
Started | Jul 25 06:53:23 PM PDT 24 |
Finished | Jul 25 07:01:12 PM PDT 24 |
Peak memory | 366684 kb |
Host | smart-72948196-941a-418e-8616-eb488cc446f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137088611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2137088611 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.2281465775 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 7396347749 ps |
CPU time | 13.39 seconds |
Started | Jul 25 06:53:25 PM PDT 24 |
Finished | Jul 25 06:53:39 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-bfae3d54-0669-4a5a-9cb0-b4f9dc82c1e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281465775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.2281465775 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.2952613116 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 795981432 ps |
CPU time | 88.22 seconds |
Started | Jul 25 06:53:22 PM PDT 24 |
Finished | Jul 25 06:54:51 PM PDT 24 |
Peak memory | 358660 kb |
Host | smart-ba974030-c93f-47d6-9d3f-d8868475352e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952613116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.2952613116 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2428792927 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 10476087947 ps |
CPU time | 86.28 seconds |
Started | Jul 25 06:53:34 PM PDT 24 |
Finished | Jul 25 06:55:01 PM PDT 24 |
Peak memory | 211428 kb |
Host | smart-4dc44550-fc3a-4673-9a92-7caeba2f94fe |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428792927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.2428792927 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.176439972 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 9475424588 ps |
CPU time | 181.36 seconds |
Started | Jul 25 06:53:32 PM PDT 24 |
Finished | Jul 25 06:56:33 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-53e07e65-df70-4cd2-b5bf-759856a25d25 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176439972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl _mem_walk.176439972 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.1263729843 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 7641158417 ps |
CPU time | 429.23 seconds |
Started | Jul 25 06:53:23 PM PDT 24 |
Finished | Jul 25 07:00:33 PM PDT 24 |
Peak memory | 370848 kb |
Host | smart-591841ec-8858-4a7e-a295-87b86424ca85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263729843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.1263729843 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.4123591093 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 1360032686 ps |
CPU time | 18.53 seconds |
Started | Jul 25 06:53:22 PM PDT 24 |
Finished | Jul 25 06:53:41 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-35eb4181-3e44-403f-8bf8-2465e0d78236 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123591093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.4123591093 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2056613786 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 40537871607 ps |
CPU time | 441.86 seconds |
Started | Jul 25 06:53:22 PM PDT 24 |
Finished | Jul 25 07:00:45 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-68221aa8-f5f2-4bbe-aafa-d664c2fea449 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056613786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.2056613786 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.1828923915 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 361469181 ps |
CPU time | 3.52 seconds |
Started | Jul 25 06:53:23 PM PDT 24 |
Finished | Jul 25 06:53:27 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-23279a95-6be3-4635-b312-c7be05293f65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828923915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1828923915 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.2009506553 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 16146598247 ps |
CPU time | 460.74 seconds |
Started | Jul 25 06:53:22 PM PDT 24 |
Finished | Jul 25 07:01:04 PM PDT 24 |
Peak memory | 377968 kb |
Host | smart-d12c2663-9ca8-4cd7-8218-bc543970b39e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009506553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2009506553 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.286621466 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 3785540430 ps |
CPU time | 21.13 seconds |
Started | Jul 25 06:53:23 PM PDT 24 |
Finished | Jul 25 06:53:44 PM PDT 24 |
Peak memory | 266572 kb |
Host | smart-06c2c213-852c-4246-8b9a-bb61c0dd0de7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286621466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.286621466 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.2114086986 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 201681856577 ps |
CPU time | 5030.97 seconds |
Started | Jul 25 06:53:33 PM PDT 24 |
Finished | Jul 25 08:17:25 PM PDT 24 |
Peak memory | 389360 kb |
Host | smart-bce3644c-13d3-42b0-a266-4e4da8e04c61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114086986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.2114086986 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1058735564 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 6091631440 ps |
CPU time | 36.37 seconds |
Started | Jul 25 06:53:35 PM PDT 24 |
Finished | Jul 25 06:54:11 PM PDT 24 |
Peak memory | 218628 kb |
Host | smart-feef65a3-a968-43a4-93c5-0ea1e0144f9c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1058735564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1058735564 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2113625905 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 5017746406 ps |
CPU time | 339.03 seconds |
Started | Jul 25 06:53:24 PM PDT 24 |
Finished | Jul 25 06:59:03 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-b7046d9e-0e74-4e1b-aff8-3f10d48877b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113625905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.2113625905 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3074875996 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 1451471225 ps |
CPU time | 6.82 seconds |
Started | Jul 25 06:53:22 PM PDT 24 |
Finished | Jul 25 06:53:29 PM PDT 24 |
Peak memory | 212332 kb |
Host | smart-f7cb14a8-41ef-4389-ac8e-741ade8bd683 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074875996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3074875996 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.820916676 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 4543904917 ps |
CPU time | 221.62 seconds |
Started | Jul 25 06:53:35 PM PDT 24 |
Finished | Jul 25 06:57:17 PM PDT 24 |
Peak memory | 367772 kb |
Host | smart-7f25ce93-9d73-4aad-9d58-cab932904c30 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820916676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 49.sram_ctrl_access_during_key_req.820916676 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.3866482072 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 63842910 ps |
CPU time | 0.63 seconds |
Started | Jul 25 06:53:40 PM PDT 24 |
Finished | Jul 25 06:53:41 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-fd69a0a8-5ff1-491d-b1e1-af55a3e9b71e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866482072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.3866482072 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.85444601 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 30417956834 ps |
CPU time | 2167.46 seconds |
Started | Jul 25 06:53:32 PM PDT 24 |
Finished | Jul 25 07:29:40 PM PDT 24 |
Peak memory | 203868 kb |
Host | smart-68afab60-2162-4c77-bd89-936b600a036c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85444601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.85444601 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.3574375848 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 29329105836 ps |
CPU time | 1030.83 seconds |
Started | Jul 25 06:53:33 PM PDT 24 |
Finished | Jul 25 07:10:45 PM PDT 24 |
Peak memory | 369836 kb |
Host | smart-c6c58c40-d3ec-4db9-b55b-f0050f222632 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574375848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.3574375848 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.1703243881 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 5111830894 ps |
CPU time | 29.22 seconds |
Started | Jul 25 06:53:31 PM PDT 24 |
Finished | Jul 25 06:54:00 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-a353bb20-692d-4a2f-b745-0c3d40cf8d32 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703243881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.1703243881 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.3509495270 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 1354849742 ps |
CPU time | 8.05 seconds |
Started | Jul 25 06:53:34 PM PDT 24 |
Finished | Jul 25 06:53:42 PM PDT 24 |
Peak memory | 219532 kb |
Host | smart-22570446-265c-4154-96af-717572f01f21 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509495270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.3509495270 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3523497412 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 1810300317 ps |
CPU time | 120.19 seconds |
Started | Jul 25 06:53:45 PM PDT 24 |
Finished | Jul 25 06:55:46 PM PDT 24 |
Peak memory | 211372 kb |
Host | smart-0c2fb206-5b1a-41a4-a963-637bd1d4b49a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523497412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.3523497412 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.3984023051 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 5421579997 ps |
CPU time | 287.25 seconds |
Started | Jul 25 06:53:45 PM PDT 24 |
Finished | Jul 25 06:58:33 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-6aac1206-ee92-4cc2-8b6b-41f6b776b96e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984023051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.3984023051 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.2818153488 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 40693081310 ps |
CPU time | 646.03 seconds |
Started | Jul 25 06:53:32 PM PDT 24 |
Finished | Jul 25 07:04:18 PM PDT 24 |
Peak memory | 367492 kb |
Host | smart-2ec77b0a-7f58-4b6a-a10e-17a8857061fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818153488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.2818153488 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.659025506 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 2155951219 ps |
CPU time | 167.79 seconds |
Started | Jul 25 06:53:32 PM PDT 24 |
Finished | Jul 25 06:56:20 PM PDT 24 |
Peak memory | 363652 kb |
Host | smart-a313b119-5b58-4fdc-b491-3a16031bfef8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659025506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.s ram_ctrl_partial_access.659025506 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2418702883 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 9470471087 ps |
CPU time | 242.7 seconds |
Started | Jul 25 06:53:33 PM PDT 24 |
Finished | Jul 25 06:57:36 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-da028e06-9cc3-4c0e-82a1-57f944a4eb14 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418702883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.2418702883 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.785264483 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 1423307089 ps |
CPU time | 3.45 seconds |
Started | Jul 25 06:53:43 PM PDT 24 |
Finished | Jul 25 06:53:47 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-4eca748e-ef51-43f1-9dc3-fe71d12dfa8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785264483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.785264483 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.3672743501 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 10187345002 ps |
CPU time | 125.87 seconds |
Started | Jul 25 06:53:39 PM PDT 24 |
Finished | Jul 25 06:55:45 PM PDT 24 |
Peak memory | 313496 kb |
Host | smart-caf63167-6e8b-463b-901a-ffa77dc3db23 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672743501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3672743501 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.2506863365 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 6903678415 ps |
CPU time | 26.35 seconds |
Started | Jul 25 06:53:35 PM PDT 24 |
Finished | Jul 25 06:54:02 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-5a0b89dd-ab42-46c4-a324-79e0416aa2cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506863365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2506863365 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3339556207 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 318258719 ps |
CPU time | 5.96 seconds |
Started | Jul 25 06:53:46 PM PDT 24 |
Finished | Jul 25 06:53:52 PM PDT 24 |
Peak memory | 211496 kb |
Host | smart-47076429-ff20-4b6f-9588-ec593536a927 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3339556207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3339556207 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2998552801 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 21301927740 ps |
CPU time | 411.42 seconds |
Started | Jul 25 06:53:34 PM PDT 24 |
Finished | Jul 25 07:00:26 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-3a0a1f98-1280-4cc8-be88-88f33b2b44de |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998552801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.2998552801 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4265873234 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 3248748403 ps |
CPU time | 125.43 seconds |
Started | Jul 25 06:53:32 PM PDT 24 |
Finished | Jul 25 06:55:38 PM PDT 24 |
Peak memory | 366956 kb |
Host | smart-a80cd76a-6b1f-42ab-ba66-940fa0b85738 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265873234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.4265873234 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3385305317 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 11882121451 ps |
CPU time | 1269.63 seconds |
Started | Jul 25 06:46:21 PM PDT 24 |
Finished | Jul 25 07:07:31 PM PDT 24 |
Peak memory | 380080 kb |
Host | smart-2f46c71a-a3cb-4da1-977d-9e93635dd17c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385305317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.3385305317 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.130311684 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 17035819 ps |
CPU time | 0.63 seconds |
Started | Jul 25 06:46:26 PM PDT 24 |
Finished | Jul 25 06:46:27 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-fb840594-0e18-4f98-a51f-eda4ed4c9170 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130311684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.130311684 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.923574646 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 183587967602 ps |
CPU time | 1475.75 seconds |
Started | Jul 25 06:46:19 PM PDT 24 |
Finished | Jul 25 07:10:55 PM PDT 24 |
Peak memory | 203816 kb |
Host | smart-0844ad39-fc1c-4ec2-9aeb-e9d510fbd922 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923574646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.923574646 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.3351411452 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 2299599123 ps |
CPU time | 207.12 seconds |
Started | Jul 25 06:46:19 PM PDT 24 |
Finished | Jul 25 06:49:46 PM PDT 24 |
Peak memory | 356568 kb |
Host | smart-e447a75b-fd5e-4ca6-b063-602b3977d3a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351411452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.3351411452 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.2255486541 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 10047686339 ps |
CPU time | 64.51 seconds |
Started | Jul 25 06:46:23 PM PDT 24 |
Finished | Jul 25 06:47:28 PM PDT 24 |
Peak memory | 203312 kb |
Host | smart-170b2c2c-5aec-40a8-b1d1-f4fe31539b9a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255486541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.2255486541 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.3772343106 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 924082054 ps |
CPU time | 127.43 seconds |
Started | Jul 25 06:46:22 PM PDT 24 |
Finished | Jul 25 06:48:29 PM PDT 24 |
Peak memory | 368832 kb |
Host | smart-e1ea5ace-0dca-4f48-8ce9-a3f9983a26a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772343106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.3772343106 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1616040806 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 7087659847 ps |
CPU time | 86.23 seconds |
Started | Jul 25 06:46:21 PM PDT 24 |
Finished | Jul 25 06:47:47 PM PDT 24 |
Peak memory | 219612 kb |
Host | smart-e2ea346f-2d04-4b90-9117-63e67bf2708c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616040806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.1616040806 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.1579780644 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 5720883418 ps |
CPU time | 148.89 seconds |
Started | Jul 25 06:46:24 PM PDT 24 |
Finished | Jul 25 06:48:53 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-2fe91a33-fa8c-44ac-b8f2-afc2b1014254 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579780644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.1579780644 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.1757739039 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 910020294 ps |
CPU time | 11.41 seconds |
Started | Jul 25 06:46:21 PM PDT 24 |
Finished | Jul 25 06:46:32 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-6e691a3c-9c10-460b-a0f0-f8a8764d2c59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757739039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.1757739039 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.205322785 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 737761655 ps |
CPU time | 33.87 seconds |
Started | Jul 25 06:46:19 PM PDT 24 |
Finished | Jul 25 06:46:53 PM PDT 24 |
Peak memory | 290772 kb |
Host | smart-d3426d8a-f893-43cd-8147-4f43306b877c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205322785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr am_ctrl_partial_access.205322785 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2304071607 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 31197753062 ps |
CPU time | 192.45 seconds |
Started | Jul 25 06:46:19 PM PDT 24 |
Finished | Jul 25 06:49:32 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-58686dc4-a1f9-42ea-88a7-cef7f846cd85 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304071607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.2304071607 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.1023801781 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 365370965 ps |
CPU time | 3.23 seconds |
Started | Jul 25 06:46:20 PM PDT 24 |
Finished | Jul 25 06:46:23 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-b667f7f5-6279-41c5-9992-af345fd682e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023801781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1023801781 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.1142106191 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 41561536512 ps |
CPU time | 1016.16 seconds |
Started | Jul 25 06:46:21 PM PDT 24 |
Finished | Jul 25 07:03:18 PM PDT 24 |
Peak memory | 370896 kb |
Host | smart-52cd7520-46aa-4e0b-87b1-c68a1c40382f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142106191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1142106191 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.1070242136 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 447185885 ps |
CPU time | 69.96 seconds |
Started | Jul 25 06:46:20 PM PDT 24 |
Finished | Jul 25 06:47:30 PM PDT 24 |
Peak memory | 345204 kb |
Host | smart-ed940221-4f4e-430e-8813-a93ab316c6d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070242136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1070242136 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.3413074993 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 366120655691 ps |
CPU time | 5186.94 seconds |
Started | Jul 25 06:46:29 PM PDT 24 |
Finished | Jul 25 08:12:56 PM PDT 24 |
Peak memory | 383208 kb |
Host | smart-e2052cf8-1ffa-4f80-aee7-77042801fd47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413074993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.3413074993 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.859480483 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 466983077 ps |
CPU time | 17.82 seconds |
Started | Jul 25 06:46:29 PM PDT 24 |
Finished | Jul 25 06:46:47 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-532921c9-4266-4db2-8762-e1ceef6bc659 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=859480483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.859480483 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1221052974 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 8219818192 ps |
CPU time | 255.28 seconds |
Started | Jul 25 06:46:19 PM PDT 24 |
Finished | Jul 25 06:50:34 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-7c225b9b-3547-4edd-965b-65c948474882 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221052974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.1221052974 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2299125938 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 713485076 ps |
CPU time | 20.6 seconds |
Started | Jul 25 06:46:19 PM PDT 24 |
Finished | Jul 25 06:46:40 PM PDT 24 |
Peak memory | 268600 kb |
Host | smart-0d4d3bcf-acd5-4f31-8a17-d6677b6ca721 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299125938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2299125938 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1819133971 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 14487620032 ps |
CPU time | 899.62 seconds |
Started | Jul 25 06:46:29 PM PDT 24 |
Finished | Jul 25 07:01:29 PM PDT 24 |
Peak memory | 380052 kb |
Host | smart-a4faf139-5ccd-42b3-a615-380db8d75fae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819133971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.1819133971 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.3336079916 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 142125866 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:46:37 PM PDT 24 |
Finished | Jul 25 06:46:37 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-6b356e21-8f21-485c-b47d-cc2bd2f50187 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336079916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3336079916 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.2815545984 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 397752066382 ps |
CPU time | 678.35 seconds |
Started | Jul 25 06:46:28 PM PDT 24 |
Finished | Jul 25 06:57:46 PM PDT 24 |
Peak memory | 203964 kb |
Host | smart-22474bad-17cb-4c70-acab-cbed7bdadd7e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815545984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 2815545984 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.906137219 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 60251257296 ps |
CPU time | 640 seconds |
Started | Jul 25 06:46:27 PM PDT 24 |
Finished | Jul 25 06:57:07 PM PDT 24 |
Peak memory | 365184 kb |
Host | smart-584b2115-e375-499b-9eed-98ff4fdc3378 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906137219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable .906137219 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.4036335039 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 11147469658 ps |
CPU time | 76.36 seconds |
Started | Jul 25 06:46:30 PM PDT 24 |
Finished | Jul 25 06:47:46 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-1d77e86e-94ee-485a-a0cd-67653f43d5e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036335039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.4036335039 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.812980770 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 3268179910 ps |
CPU time | 72.57 seconds |
Started | Jul 25 06:46:28 PM PDT 24 |
Finished | Jul 25 06:47:41 PM PDT 24 |
Peak memory | 352580 kb |
Host | smart-811d5b01-d081-4665-8a4c-151766efe9b9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812980770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.sram_ctrl_max_throughput.812980770 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3363403424 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 2672598623 ps |
CPU time | 83.82 seconds |
Started | Jul 25 06:46:35 PM PDT 24 |
Finished | Jul 25 06:47:59 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-49bc47d2-ced7-4b5c-beb6-6570952ba605 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363403424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.3363403424 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.2145979213 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 21875579968 ps |
CPU time | 293.79 seconds |
Started | Jul 25 06:46:27 PM PDT 24 |
Finished | Jul 25 06:51:21 PM PDT 24 |
Peak memory | 211428 kb |
Host | smart-98cfe355-cf2b-47f3-9268-38a160494cf7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145979213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.2145979213 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.1377967929 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 6944944121 ps |
CPU time | 487.98 seconds |
Started | Jul 25 06:46:27 PM PDT 24 |
Finished | Jul 25 06:54:36 PM PDT 24 |
Peak memory | 381120 kb |
Host | smart-4a84055b-25a7-4a06-b90d-7758f0f248f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377967929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.1377967929 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.2906823835 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 7204920379 ps |
CPU time | 18.16 seconds |
Started | Jul 25 06:46:28 PM PDT 24 |
Finished | Jul 25 06:46:46 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-6ba486b1-4fb1-4588-bf4f-fb04bec06594 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906823835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.2906823835 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1300359166 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 51345077342 ps |
CPU time | 292.85 seconds |
Started | Jul 25 06:46:26 PM PDT 24 |
Finished | Jul 25 06:51:19 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-5b9aae2f-3c8d-4e72-886a-888d881018bf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300359166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.1300359166 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.1435369803 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 1407751341 ps |
CPU time | 3.6 seconds |
Started | Jul 25 06:46:27 PM PDT 24 |
Finished | Jul 25 06:46:31 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-49d7fbbb-8a75-4259-910f-c9b99099c559 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435369803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1435369803 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2895580807 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 1408899484 ps |
CPU time | 39.43 seconds |
Started | Jul 25 06:46:29 PM PDT 24 |
Finished | Jul 25 06:47:09 PM PDT 24 |
Peak memory | 254028 kb |
Host | smart-310dc288-f232-4e0c-9355-4734507e3040 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895580807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2895580807 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.3108255591 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 1632800083 ps |
CPU time | 19.85 seconds |
Started | Jul 25 06:46:29 PM PDT 24 |
Finished | Jul 25 06:46:48 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-ccc31adf-790c-4e6f-87fb-a20e1eb871a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108255591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3108255591 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.2412677989 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 128268435752 ps |
CPU time | 8332.23 seconds |
Started | Jul 25 06:46:37 PM PDT 24 |
Finished | Jul 25 09:05:30 PM PDT 24 |
Peak memory | 382152 kb |
Host | smart-d15fe938-cd47-4dd6-afef-0ce3010b4d22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412677989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.2412677989 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1412121808 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 5182430283 ps |
CPU time | 24.87 seconds |
Started | Jul 25 06:46:36 PM PDT 24 |
Finished | Jul 25 06:47:01 PM PDT 24 |
Peak memory | 211496 kb |
Host | smart-3a3d13c3-6f51-4739-85ef-38ca6d5f3cc6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1412121808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1412121808 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3549302967 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 81042299049 ps |
CPU time | 322.5 seconds |
Started | Jul 25 06:46:29 PM PDT 24 |
Finished | Jul 25 06:51:52 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-6d680d2b-9e06-49ec-885a-7edbeb1b551e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549302967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.3549302967 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.457456140 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 4398078138 ps |
CPU time | 11.86 seconds |
Started | Jul 25 06:46:30 PM PDT 24 |
Finished | Jul 25 06:46:42 PM PDT 24 |
Peak memory | 235960 kb |
Host | smart-c9dcb2cc-7218-4a0c-abfd-e806846a42c4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457456140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.457456140 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3582747396 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 43000905028 ps |
CPU time | 615.34 seconds |
Started | Jul 25 06:46:48 PM PDT 24 |
Finished | Jul 25 06:57:03 PM PDT 24 |
Peak memory | 380164 kb |
Host | smart-a819ee5a-0352-460a-b1c0-11aa1f6a20ae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582747396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.3582747396 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.2690604793 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 29786624 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:46:45 PM PDT 24 |
Finished | Jul 25 06:46:46 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-f71301e7-5af7-470a-acfb-f87e33248e98 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690604793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2690604793 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.773961551 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 12879583469 ps |
CPU time | 662.93 seconds |
Started | Jul 25 06:46:37 PM PDT 24 |
Finished | Jul 25 06:57:41 PM PDT 24 |
Peak memory | 203832 kb |
Host | smart-f7b7b371-e500-483e-bf4a-94e91729d9af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773961551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.773961551 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.1036060725 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 19892712085 ps |
CPU time | 1237.19 seconds |
Started | Jul 25 06:46:46 PM PDT 24 |
Finished | Jul 25 07:07:24 PM PDT 24 |
Peak memory | 374024 kb |
Host | smart-8e716089-392e-425a-a0aa-09625abdb011 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036060725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.1036060725 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.551348516 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 17021761531 ps |
CPU time | 89.88 seconds |
Started | Jul 25 06:46:48 PM PDT 24 |
Finished | Jul 25 06:48:18 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-9f7d00e5-ea43-4407-9a21-7a1fa92a73f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551348516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esca lation.551348516 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.2793329121 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 854941417 ps |
CPU time | 64.86 seconds |
Started | Jul 25 06:46:36 PM PDT 24 |
Finished | Jul 25 06:47:41 PM PDT 24 |
Peak memory | 341172 kb |
Host | smart-fb7b31ff-5ae8-431d-ae8f-ac551d3dc516 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793329121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.2793329121 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1230141145 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 5194878851 ps |
CPU time | 82.01 seconds |
Started | Jul 25 06:46:46 PM PDT 24 |
Finished | Jul 25 06:48:09 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-69e6f037-4841-4e63-8d0c-5de908bdd38f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230141145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.1230141145 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.1262805013 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 10954127883 ps |
CPU time | 152.44 seconds |
Started | Jul 25 06:46:45 PM PDT 24 |
Finished | Jul 25 06:49:18 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-900b092e-fe1c-44e4-9525-3bc1e3b1f559 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262805013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.1262805013 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.2110985548 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 82879388887 ps |
CPU time | 1412.48 seconds |
Started | Jul 25 06:46:35 PM PDT 24 |
Finished | Jul 25 07:10:08 PM PDT 24 |
Peak memory | 380004 kb |
Host | smart-7af56d0a-359a-48e4-8b9f-37ddbb2e8110 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110985548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.2110985548 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.3999645543 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 3103489099 ps |
CPU time | 8.17 seconds |
Started | Jul 25 06:46:37 PM PDT 24 |
Finished | Jul 25 06:46:45 PM PDT 24 |
Peak memory | 208816 kb |
Host | smart-ac1f7bcd-29c9-44d0-9dd4-6fa0adb19462 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999645543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.3999645543 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1277599659 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 20615136912 ps |
CPU time | 230.32 seconds |
Started | Jul 25 06:46:35 PM PDT 24 |
Finished | Jul 25 06:50:26 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-5fa8ece2-616a-453d-98a3-18ac07c6d7b6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277599659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.1277599659 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.3940504399 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 349317407 ps |
CPU time | 3.15 seconds |
Started | Jul 25 06:46:45 PM PDT 24 |
Finished | Jul 25 06:46:49 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-e4a9be8e-7b7a-4798-aaca-f58c4b157c66 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940504399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3940504399 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.2356855838 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 8228864609 ps |
CPU time | 364.53 seconds |
Started | Jul 25 06:46:45 PM PDT 24 |
Finished | Jul 25 06:52:50 PM PDT 24 |
Peak memory | 377936 kb |
Host | smart-89bbddc9-4b61-4c6f-bb14-df2d7459ca19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356855838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2356855838 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.151722202 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 675431470 ps |
CPU time | 10.52 seconds |
Started | Jul 25 06:46:38 PM PDT 24 |
Finished | Jul 25 06:46:48 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-c8fb3bb8-cf34-4cdb-b1ea-96e1f96602c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151722202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.151722202 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.1164023094 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 1361544252399 ps |
CPU time | 9224.89 seconds |
Started | Jul 25 06:46:52 PM PDT 24 |
Finished | Jul 25 09:20:38 PM PDT 24 |
Peak memory | 381160 kb |
Host | smart-44734944-fd16-48a0-b22a-61a9934e2d21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164023094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.1164023094 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.338601641 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 5306546231 ps |
CPU time | 342.94 seconds |
Started | Jul 25 06:46:37 PM PDT 24 |
Finished | Jul 25 06:52:20 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-309e890d-0be2-4da8-a7b7-f3dd9a65d610 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338601641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. sram_ctrl_stress_pipeline.338601641 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2139986535 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 1613405232 ps |
CPU time | 105.71 seconds |
Started | Jul 25 06:46:46 PM PDT 24 |
Finished | Jul 25 06:48:32 PM PDT 24 |
Peak memory | 359560 kb |
Host | smart-03ab777c-cfe1-42f7-96e5-aac8f8635b58 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139986535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2139986535 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.393882610 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 4933064716 ps |
CPU time | 302.75 seconds |
Started | Jul 25 06:46:56 PM PDT 24 |
Finished | Jul 25 06:51:59 PM PDT 24 |
Peak memory | 372892 kb |
Host | smart-902f12a1-6395-492c-99a2-381ac87e9b4c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393882610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_access_during_key_req.393882610 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.83233034 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 20076046 ps |
CPU time | 0.64 seconds |
Started | Jul 25 06:46:57 PM PDT 24 |
Finished | Jul 25 06:46:58 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-5f3ea810-6228-4e23-97dc-2981ff9964ca |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83233034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_alert_test.83233034 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.74028154 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 231862608988 ps |
CPU time | 2179.4 seconds |
Started | Jul 25 06:46:47 PM PDT 24 |
Finished | Jul 25 07:23:07 PM PDT 24 |
Peak memory | 203924 kb |
Host | smart-c25fbe83-d1fa-4e3d-b3ea-6c83d32de2b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74028154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.74028154 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.1147016484 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 8324867890 ps |
CPU time | 253.54 seconds |
Started | Jul 25 06:46:55 PM PDT 24 |
Finished | Jul 25 06:51:08 PM PDT 24 |
Peak memory | 361772 kb |
Host | smart-935d471d-23eb-46c4-98fd-b1529ef1514e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147016484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.1147016484 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.1780144992 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 10254678898 ps |
CPU time | 61.03 seconds |
Started | Jul 25 06:46:54 PM PDT 24 |
Finished | Jul 25 06:47:55 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-2fd98800-aba9-45a3-b996-3598676bd448 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780144992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.1780144992 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.4147674147 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 8048058463 ps |
CPU time | 37.32 seconds |
Started | Jul 25 06:46:57 PM PDT 24 |
Finished | Jul 25 06:47:34 PM PDT 24 |
Peak memory | 301348 kb |
Host | smart-4968ce33-6a7b-48e5-a5b9-28e32d33575a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147674147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.4147674147 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1168405422 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 6360278705 ps |
CPU time | 77.32 seconds |
Started | Jul 25 06:46:58 PM PDT 24 |
Finished | Jul 25 06:48:15 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-960cb7cd-60ef-4509-aa26-ab49a6ca5b5c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168405422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.1168405422 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.3124681836 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 40687669163 ps |
CPU time | 321 seconds |
Started | Jul 25 06:47:05 PM PDT 24 |
Finished | Jul 25 06:52:26 PM PDT 24 |
Peak memory | 203300 kb |
Host | smart-941cc802-45ae-4f10-9862-cd95f5dc300b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124681836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.3124681836 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.3251566423 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 23015592879 ps |
CPU time | 982.5 seconds |
Started | Jul 25 06:46:45 PM PDT 24 |
Finished | Jul 25 07:03:08 PM PDT 24 |
Peak memory | 381168 kb |
Host | smart-f08911c9-224f-4a7a-9910-188282038ed0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251566423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.3251566423 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.54723474 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 2105978167 ps |
CPU time | 104.53 seconds |
Started | Jul 25 06:46:47 PM PDT 24 |
Finished | Jul 25 06:48:31 PM PDT 24 |
Peak memory | 370792 kb |
Host | smart-6139cdf5-4dc8-4c5a-8ed4-bd9a9521a5d1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54723474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sra m_ctrl_partial_access.54723474 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3705944725 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 27488786148 ps |
CPU time | 332.57 seconds |
Started | Jul 25 06:46:55 PM PDT 24 |
Finished | Jul 25 06:52:28 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-01e1320e-0d31-417f-8223-6c671a17b814 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705944725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.3705944725 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.3715450600 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 709576368 ps |
CPU time | 3.07 seconds |
Started | Jul 25 06:46:55 PM PDT 24 |
Finished | Jul 25 06:46:58 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-22cb581e-e2ed-462f-9614-86e41d8d018a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715450600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3715450600 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.3173896823 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 8635355140 ps |
CPU time | 1068.43 seconds |
Started | Jul 25 06:46:56 PM PDT 24 |
Finished | Jul 25 07:04:44 PM PDT 24 |
Peak memory | 376052 kb |
Host | smart-479f6b1e-a32f-44be-8e78-2fab338f4b82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173896823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3173896823 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.484165928 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 2072670105 ps |
CPU time | 17.52 seconds |
Started | Jul 25 06:46:46 PM PDT 24 |
Finished | Jul 25 06:47:04 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-26e02004-d948-47cd-b5fb-886cdd741fad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484165928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.484165928 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.2910887563 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 38222635915 ps |
CPU time | 3293.43 seconds |
Started | Jul 25 06:46:55 PM PDT 24 |
Finished | Jul 25 07:41:49 PM PDT 24 |
Peak memory | 383284 kb |
Host | smart-07cca4d8-88c2-40f4-a33d-9de1533fc124 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910887563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.2910887563 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3104152952 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 4408200049 ps |
CPU time | 31.81 seconds |
Started | Jul 25 06:46:55 PM PDT 24 |
Finished | Jul 25 06:47:27 PM PDT 24 |
Peak memory | 211516 kb |
Host | smart-a3e56d9a-dc3b-4598-88b1-6a8715c5d3e6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3104152952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3104152952 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3485587548 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 35057969191 ps |
CPU time | 164.73 seconds |
Started | Jul 25 06:46:46 PM PDT 24 |
Finished | Jul 25 06:49:31 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-f28029e3-54e9-40af-8fdb-480a8959a72d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485587548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.3485587548 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2342198842 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 3246952059 ps |
CPU time | 114.92 seconds |
Started | Jul 25 06:46:54 PM PDT 24 |
Finished | Jul 25 06:48:49 PM PDT 24 |
Peak memory | 366004 kb |
Host | smart-4cd7fe44-50c5-41a6-ab4f-0fd9edcd4af9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342198842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2342198842 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.156344123 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 38020607935 ps |
CPU time | 1706.33 seconds |
Started | Jul 25 06:47:05 PM PDT 24 |
Finished | Jul 25 07:15:31 PM PDT 24 |
Peak memory | 381104 kb |
Host | smart-7bd7ac50-60b8-482a-8fd6-dae4c1f4ec0f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156344123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 9.sram_ctrl_access_during_key_req.156344123 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.2873203595 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 35540440 ps |
CPU time | 0.66 seconds |
Started | Jul 25 06:47:05 PM PDT 24 |
Finished | Jul 25 06:47:06 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-863cd0cc-f4bb-4299-8947-091ceda925e6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873203595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2873203595 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.519788773 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 546107775118 ps |
CPU time | 2345.39 seconds |
Started | Jul 25 06:46:58 PM PDT 24 |
Finished | Jul 25 07:26:04 PM PDT 24 |
Peak memory | 203944 kb |
Host | smart-6ee1f966-e510-4373-b381-89c4dcf9406b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519788773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.519788773 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.1006160213 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 15970601227 ps |
CPU time | 416.64 seconds |
Started | Jul 25 06:46:58 PM PDT 24 |
Finished | Jul 25 06:53:55 PM PDT 24 |
Peak memory | 373380 kb |
Host | smart-45f90146-06ff-4f06-9a30-c85e04a19e65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006160213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.1006160213 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.3457759404 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 10359707531 ps |
CPU time | 61.29 seconds |
Started | Jul 25 06:47:05 PM PDT 24 |
Finished | Jul 25 06:48:06 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-c0ccd64c-4c9e-4037-b386-5647a01d3802 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457759404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.3457759404 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.2919686752 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 7005211815 ps |
CPU time | 21 seconds |
Started | Jul 25 06:46:55 PM PDT 24 |
Finished | Jul 25 06:47:16 PM PDT 24 |
Peak memory | 259008 kb |
Host | smart-d480757c-85b8-4116-9009-7153466091ad |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919686752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.2919686752 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2769831614 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 10644567725 ps |
CPU time | 80.24 seconds |
Started | Jul 25 06:47:15 PM PDT 24 |
Finished | Jul 25 06:48:35 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-e9a4c894-a4d2-44d6-a87a-3167466b1c1d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769831614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.2769831614 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.3764512278 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 16440306038 ps |
CPU time | 153.38 seconds |
Started | Jul 25 06:47:07 PM PDT 24 |
Finished | Jul 25 06:49:41 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-46dfc338-328c-4e71-baa5-030197e179a9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764512278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3764512278 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.4108701487 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 30157639949 ps |
CPU time | 1317.15 seconds |
Started | Jul 25 06:46:55 PM PDT 24 |
Finished | Jul 25 07:08:52 PM PDT 24 |
Peak memory | 375040 kb |
Host | smart-b3b11e46-9b99-4897-8647-b904c5eb8bd1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108701487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.4108701487 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.3146427104 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 6960257751 ps |
CPU time | 24.6 seconds |
Started | Jul 25 06:46:55 PM PDT 24 |
Finished | Jul 25 06:47:20 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-aabef82d-07fe-4acc-9674-6b888bc80637 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146427104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3146427104 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1701539484 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 6304923470 ps |
CPU time | 159.55 seconds |
Started | Jul 25 06:46:55 PM PDT 24 |
Finished | Jul 25 06:49:35 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-41484a68-d34f-4142-a8fa-bf4d738dbad7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701539484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.1701539484 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.2597207412 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 350701105 ps |
CPU time | 3.26 seconds |
Started | Jul 25 06:47:04 PM PDT 24 |
Finished | Jul 25 06:47:07 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-62a68891-8b75-4a8b-ada6-307dad027786 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597207412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2597207412 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.2135389361 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 1891997296 ps |
CPU time | 358.53 seconds |
Started | Jul 25 06:46:57 PM PDT 24 |
Finished | Jul 25 06:52:55 PM PDT 24 |
Peak memory | 377208 kb |
Host | smart-3f6bae4d-0467-43af-8d9a-5a9798dca5a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135389361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2135389361 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.1879211905 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 9247817055 ps |
CPU time | 16.16 seconds |
Started | Jul 25 06:46:58 PM PDT 24 |
Finished | Jul 25 06:47:14 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-5af244de-7312-49ab-93a2-85b1a7259441 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879211905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1879211905 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.614106669 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 5763736472 ps |
CPU time | 117.68 seconds |
Started | Jul 25 06:47:05 PM PDT 24 |
Finished | Jul 25 06:49:03 PM PDT 24 |
Peak memory | 378636 kb |
Host | smart-08f520fc-b3a4-48a1-b70f-ddef871f8ed5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=614106669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.614106669 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3301023562 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 10049450270 ps |
CPU time | 361.12 seconds |
Started | Jul 25 06:46:58 PM PDT 24 |
Finished | Jul 25 06:53:00 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-4c2d650a-2d40-46d8-bbfa-3271be7399a7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301023562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.3301023562 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2001743014 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 789596293 ps |
CPU time | 118.72 seconds |
Started | Jul 25 06:47:04 PM PDT 24 |
Finished | Jul 25 06:49:03 PM PDT 24 |
Peak memory | 370764 kb |
Host | smart-b73ea3e6-c63e-499a-96c8-1a3bb5394ff9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001743014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2001743014 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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