| T798 |
/workspace/coverage/default/11.sram_ctrl_bijection.3312746465 |
|
|
Jul 27 06:45:58 PM PDT 24 |
Jul 27 07:00:05 PM PDT 24 |
300610109805 ps |
| T799 |
/workspace/coverage/default/22.sram_ctrl_bijection.2328270065 |
|
|
Jul 27 06:47:52 PM PDT 24 |
Jul 27 06:57:40 PM PDT 24 |
57945187504 ps |
| T800 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.675255298 |
|
|
Jul 27 06:48:57 PM PDT 24 |
Jul 27 06:51:33 PM PDT 24 |
7226559158 ps |
| T801 |
/workspace/coverage/default/25.sram_ctrl_partial_access.2623864690 |
|
|
Jul 27 06:48:35 PM PDT 24 |
Jul 27 06:48:44 PM PDT 24 |
922039154 ps |
| T802 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.94046414 |
|
|
Jul 27 06:46:01 PM PDT 24 |
Jul 27 06:47:30 PM PDT 24 |
10910718835 ps |
| T803 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.4170934804 |
|
|
Jul 27 06:46:25 PM PDT 24 |
Jul 27 06:51:20 PM PDT 24 |
5254308286 ps |
| T804 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3201812497 |
|
|
Jul 27 06:47:12 PM PDT 24 |
Jul 27 06:47:37 PM PDT 24 |
7460933623 ps |
| T805 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.1187105322 |
|
|
Jul 27 06:48:21 PM PDT 24 |
Jul 27 06:51:07 PM PDT 24 |
22234714721 ps |
| T806 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1169552226 |
|
|
Jul 27 06:49:13 PM PDT 24 |
Jul 27 07:08:27 PM PDT 24 |
14099634729 ps |
| T807 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.763252585 |
|
|
Jul 27 06:49:14 PM PDT 24 |
Jul 27 06:49:55 PM PDT 24 |
7207789674 ps |
| T808 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3771160005 |
|
|
Jul 27 06:46:44 PM PDT 24 |
Jul 27 06:47:02 PM PDT 24 |
1113334521 ps |
| T809 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3256552485 |
|
|
Jul 27 06:45:30 PM PDT 24 |
Jul 27 06:49:53 PM PDT 24 |
4259667854 ps |
| T810 |
/workspace/coverage/default/7.sram_ctrl_partial_access.3069427245 |
|
|
Jul 27 06:45:29 PM PDT 24 |
Jul 27 06:45:43 PM PDT 24 |
406590816 ps |
| T811 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.3031199346 |
|
|
Jul 27 06:45:10 PM PDT 24 |
Jul 27 06:50:27 PM PDT 24 |
86338692514 ps |
| T812 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3012463392 |
|
|
Jul 27 06:51:00 PM PDT 24 |
Jul 27 06:55:12 PM PDT 24 |
7882701247 ps |
| T813 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.840511183 |
|
|
Jul 27 06:49:58 PM PDT 24 |
Jul 27 06:51:06 PM PDT 24 |
790231321 ps |
| T814 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2751783128 |
|
|
Jul 27 06:50:51 PM PDT 24 |
Jul 27 06:50:51 PM PDT 24 |
11772612 ps |
| T815 |
/workspace/coverage/default/41.sram_ctrl_regwen.1548567575 |
|
|
Jul 27 06:51:58 PM PDT 24 |
Jul 27 07:03:28 PM PDT 24 |
25324606326 ps |
| T816 |
/workspace/coverage/default/1.sram_ctrl_stress_all.3513973158 |
|
|
Jul 27 06:45:12 PM PDT 24 |
Jul 27 07:16:17 PM PDT 24 |
215821527103 ps |
| T817 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1143093700 |
|
|
Jul 27 06:51:38 PM PDT 24 |
Jul 27 06:55:40 PM PDT 24 |
4366064479 ps |
| T818 |
/workspace/coverage/default/8.sram_ctrl_regwen.1092182373 |
|
|
Jul 27 06:45:38 PM PDT 24 |
Jul 27 07:04:00 PM PDT 24 |
3415931065 ps |
| T819 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.625061224 |
|
|
Jul 27 06:45:06 PM PDT 24 |
Jul 27 06:51:51 PM PDT 24 |
36798208100 ps |
| T820 |
/workspace/coverage/default/14.sram_ctrl_smoke.4159864441 |
|
|
Jul 27 06:46:33 PM PDT 24 |
Jul 27 06:46:51 PM PDT 24 |
994683980 ps |
| T821 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1595824526 |
|
|
Jul 27 06:53:31 PM PDT 24 |
Jul 27 06:53:32 PM PDT 24 |
23232561 ps |
| T822 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.2513269108 |
|
|
Jul 27 06:51:43 PM PDT 24 |
Jul 27 06:52:58 PM PDT 24 |
13686288367 ps |
| T823 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2787317481 |
|
|
Jul 27 06:50:47 PM PDT 24 |
Jul 27 06:50:51 PM PDT 24 |
703057788 ps |
| T824 |
/workspace/coverage/default/28.sram_ctrl_smoke.3545598169 |
|
|
Jul 27 06:49:16 PM PDT 24 |
Jul 27 06:49:36 PM PDT 24 |
7785580415 ps |
| T825 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2769696656 |
|
|
Jul 27 06:51:32 PM PDT 24 |
Jul 27 06:53:58 PM PDT 24 |
2780982778 ps |
| T826 |
/workspace/coverage/default/6.sram_ctrl_smoke.3407896202 |
|
|
Jul 27 06:45:28 PM PDT 24 |
Jul 27 06:45:38 PM PDT 24 |
3205271828 ps |
| T827 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.213280108 |
|
|
Jul 27 06:48:36 PM PDT 24 |
Jul 27 06:56:12 PM PDT 24 |
35548249313 ps |
| T828 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.365255046 |
|
|
Jul 27 06:51:06 PM PDT 24 |
Jul 27 06:51:09 PM PDT 24 |
1406263042 ps |
| T829 |
/workspace/coverage/default/37.sram_ctrl_executable.2383808292 |
|
|
Jul 27 06:51:06 PM PDT 24 |
Jul 27 07:10:24 PM PDT 24 |
95839567434 ps |
| T830 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.980390259 |
|
|
Jul 27 06:50:17 PM PDT 24 |
Jul 27 07:18:56 PM PDT 24 |
69843342034 ps |
| T831 |
/workspace/coverage/default/32.sram_ctrl_alert_test.1191636752 |
|
|
Jul 27 06:50:07 PM PDT 24 |
Jul 27 06:50:07 PM PDT 24 |
22935790 ps |
| T832 |
/workspace/coverage/default/27.sram_ctrl_bijection.2704661792 |
|
|
Jul 27 06:49:03 PM PDT 24 |
Jul 27 07:08:32 PM PDT 24 |
120099994795 ps |
| T833 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2253048767 |
|
|
Jul 27 06:45:30 PM PDT 24 |
Jul 27 06:47:01 PM PDT 24 |
10942284110 ps |
| T834 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.4118607544 |
|
|
Jul 27 06:45:49 PM PDT 24 |
Jul 27 06:46:49 PM PDT 24 |
10319375594 ps |
| T835 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.3823972480 |
|
|
Jul 27 06:49:03 PM PDT 24 |
Jul 27 06:53:06 PM PDT 24 |
4001791899 ps |
| T836 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2754343508 |
|
|
Jul 27 06:50:05 PM PDT 24 |
Jul 27 06:52:52 PM PDT 24 |
10242760755 ps |
| T837 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.867444244 |
|
|
Jul 27 06:48:38 PM PDT 24 |
Jul 27 06:49:10 PM PDT 24 |
737366064 ps |
| T838 |
/workspace/coverage/default/24.sram_ctrl_regwen.948928769 |
|
|
Jul 27 06:48:29 PM PDT 24 |
Jul 27 07:06:40 PM PDT 24 |
12346072148 ps |
| T839 |
/workspace/coverage/default/13.sram_ctrl_regwen.3679634476 |
|
|
Jul 27 06:46:25 PM PDT 24 |
Jul 27 07:02:32 PM PDT 24 |
77139453517 ps |
| T840 |
/workspace/coverage/default/21.sram_ctrl_partial_access.2012131752 |
|
|
Jul 27 06:47:43 PM PDT 24 |
Jul 27 06:48:04 PM PDT 24 |
4629474486 ps |
| T841 |
/workspace/coverage/default/30.sram_ctrl_smoke.234087820 |
|
|
Jul 27 06:49:40 PM PDT 24 |
Jul 27 06:49:49 PM PDT 24 |
2333744948 ps |
| T842 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.215413134 |
|
|
Jul 27 06:53:53 PM PDT 24 |
Jul 27 06:55:39 PM PDT 24 |
2320163217 ps |
| T843 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.4052531968 |
|
|
Jul 27 06:46:33 PM PDT 24 |
Jul 27 06:51:59 PM PDT 24 |
10978942776 ps |
| T844 |
/workspace/coverage/default/38.sram_ctrl_bijection.1715962221 |
|
|
Jul 27 06:51:15 PM PDT 24 |
Jul 27 07:24:03 PM PDT 24 |
86366937891 ps |
| T845 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3605827062 |
|
|
Jul 27 06:49:39 PM PDT 24 |
Jul 27 06:49:42 PM PDT 24 |
363933403 ps |
| T846 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3569168729 |
|
|
Jul 27 06:49:07 PM PDT 24 |
Jul 27 07:12:44 PM PDT 24 |
12246959906 ps |
| T847 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.106977988 |
|
|
Jul 27 06:52:32 PM PDT 24 |
Jul 27 07:11:07 PM PDT 24 |
88307377263 ps |
| T848 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2928962072 |
|
|
Jul 27 06:48:10 PM PDT 24 |
Jul 27 06:50:52 PM PDT 24 |
4900696680 ps |
| T849 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1307342318 |
|
|
Jul 27 06:45:28 PM PDT 24 |
Jul 27 06:49:52 PM PDT 24 |
4807086856 ps |
| T850 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3176047485 |
|
|
Jul 27 06:48:14 PM PDT 24 |
Jul 27 06:48:31 PM PDT 24 |
589368085 ps |
| T851 |
/workspace/coverage/default/4.sram_ctrl_partial_access.4042783218 |
|
|
Jul 27 06:45:19 PM PDT 24 |
Jul 27 06:46:25 PM PDT 24 |
1730481912 ps |
| T852 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1284934026 |
|
|
Jul 27 06:52:49 PM PDT 24 |
Jul 27 06:53:06 PM PDT 24 |
2559809329 ps |
| T853 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1649521156 |
|
|
Jul 27 06:46:19 PM PDT 24 |
Jul 27 06:46:42 PM PDT 24 |
1435155636 ps |
| T854 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1759558139 |
|
|
Jul 27 06:45:20 PM PDT 24 |
Jul 27 07:05:08 PM PDT 24 |
6820544479 ps |
| T855 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.968747913 |
|
|
Jul 27 06:53:12 PM PDT 24 |
Jul 27 06:53:26 PM PDT 24 |
1201730470 ps |
| T856 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1341730458 |
|
|
Jul 27 06:51:08 PM PDT 24 |
Jul 27 06:52:05 PM PDT 24 |
3095600868 ps |
| T857 |
/workspace/coverage/default/45.sram_ctrl_bijection.3190868438 |
|
|
Jul 27 06:52:40 PM PDT 24 |
Jul 27 07:14:10 PM PDT 24 |
126880209166 ps |
| T858 |
/workspace/coverage/default/42.sram_ctrl_alert_test.20303100 |
|
|
Jul 27 06:52:12 PM PDT 24 |
Jul 27 06:52:13 PM PDT 24 |
22279001 ps |
| T859 |
/workspace/coverage/default/9.sram_ctrl_executable.2154288879 |
|
|
Jul 27 06:45:49 PM PDT 24 |
Jul 27 07:01:50 PM PDT 24 |
20838420600 ps |
| T860 |
/workspace/coverage/default/16.sram_ctrl_alert_test.2495482236 |
|
|
Jul 27 06:47:04 PM PDT 24 |
Jul 27 06:47:05 PM PDT 24 |
23055293 ps |
| T861 |
/workspace/coverage/default/45.sram_ctrl_smoke.2177232533 |
|
|
Jul 27 06:52:41 PM PDT 24 |
Jul 27 06:52:57 PM PDT 24 |
2376216169 ps |
| T862 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.407702773 |
|
|
Jul 27 06:50:33 PM PDT 24 |
Jul 27 06:53:10 PM PDT 24 |
29221632180 ps |
| T863 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2657022306 |
|
|
Jul 27 06:50:58 PM PDT 24 |
Jul 27 06:55:42 PM PDT 24 |
7639818636 ps |
| T864 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1634711315 |
|
|
Jul 27 06:53:28 PM PDT 24 |
Jul 27 06:59:53 PM PDT 24 |
27546138794 ps |
| T865 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2374442784 |
|
|
Jul 27 06:48:04 PM PDT 24 |
Jul 27 06:51:04 PM PDT 24 |
21108200413 ps |
| T866 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.1280357146 |
|
|
Jul 27 06:52:40 PM PDT 24 |
Jul 27 06:52:52 PM PDT 24 |
2853197349 ps |
| T867 |
/workspace/coverage/default/31.sram_ctrl_alert_test.410852299 |
|
|
Jul 27 06:49:54 PM PDT 24 |
Jul 27 06:49:55 PM PDT 24 |
44038109 ps |
| T868 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.122860450 |
|
|
Jul 27 06:50:26 PM PDT 24 |
Jul 27 06:58:31 PM PDT 24 |
17756149090 ps |
| T869 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1058113572 |
|
|
Jul 27 06:45:49 PM PDT 24 |
Jul 27 06:45:50 PM PDT 24 |
25902998 ps |
| T870 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1113765671 |
|
|
Jul 27 06:46:14 PM PDT 24 |
Jul 27 06:53:33 PM PDT 24 |
24613428991 ps |
| T871 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.613059531 |
|
|
Jul 27 06:52:48 PM PDT 24 |
Jul 27 06:55:21 PM PDT 24 |
3128420346 ps |
| T872 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1054263024 |
|
|
Jul 27 06:52:57 PM PDT 24 |
Jul 27 06:53:06 PM PDT 24 |
212428992 ps |
| T873 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3039099481 |
|
|
Jul 27 06:48:05 PM PDT 24 |
Jul 27 06:48:09 PM PDT 24 |
2590699769 ps |
| T874 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.850109823 |
|
|
Jul 27 06:50:33 PM PDT 24 |
Jul 27 07:17:50 PM PDT 24 |
29922385437 ps |
| T875 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3507392812 |
|
|
Jul 27 06:52:11 PM PDT 24 |
Jul 27 06:52:44 PM PDT 24 |
3040165113 ps |
| T876 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.4251038642 |
|
|
Jul 27 06:46:55 PM PDT 24 |
Jul 27 06:49:02 PM PDT 24 |
21912476045 ps |
| T877 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1158128658 |
|
|
Jul 27 06:51:14 PM PDT 24 |
Jul 27 06:52:34 PM PDT 24 |
24495221378 ps |
| T878 |
/workspace/coverage/default/31.sram_ctrl_bijection.1976957402 |
|
|
Jul 27 06:49:48 PM PDT 24 |
Jul 27 07:25:22 PM PDT 24 |
116111034575 ps |
| T879 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.964890530 |
|
|
Jul 27 06:47:10 PM PDT 24 |
Jul 27 06:47:16 PM PDT 24 |
934862223 ps |
| T880 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.360538766 |
|
|
Jul 27 06:52:52 PM PDT 24 |
Jul 27 06:53:25 PM PDT 24 |
1334778243 ps |
| T881 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.874349667 |
|
|
Jul 27 06:51:55 PM PDT 24 |
Jul 27 06:51:58 PM PDT 24 |
744921235 ps |
| T882 |
/workspace/coverage/default/33.sram_ctrl_regwen.303693377 |
|
|
Jul 27 06:50:23 PM PDT 24 |
Jul 27 07:03:17 PM PDT 24 |
45822784324 ps |
| T883 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3699173421 |
|
|
Jul 27 06:46:16 PM PDT 24 |
Jul 27 06:50:20 PM PDT 24 |
38576441185 ps |
| T884 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.173073039 |
|
|
Jul 27 06:48:38 PM PDT 24 |
Jul 27 06:55:54 PM PDT 24 |
5550060167 ps |
| T885 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1661224704 |
|
|
Jul 27 06:46:25 PM PDT 24 |
Jul 27 06:47:26 PM PDT 24 |
3331216044 ps |
| T886 |
/workspace/coverage/default/26.sram_ctrl_partial_access.580450026 |
|
|
Jul 27 06:48:49 PM PDT 24 |
Jul 27 06:49:39 PM PDT 24 |
1143729690 ps |
| T887 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.428999072 |
|
|
Jul 27 06:49:38 PM PDT 24 |
Jul 27 06:56:06 PM PDT 24 |
13494060891 ps |
| T888 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2371988497 |
|
|
Jul 27 06:45:20 PM PDT 24 |
Jul 27 06:54:13 PM PDT 24 |
83256860213 ps |
| T889 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3719586922 |
|
|
Jul 27 06:50:32 PM PDT 24 |
Jul 27 06:53:01 PM PDT 24 |
4575770226 ps |
| T890 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2644192514 |
|
|
Jul 27 06:50:06 PM PDT 24 |
Jul 27 06:52:49 PM PDT 24 |
28841971168 ps |
| T891 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2189579249 |
|
|
Jul 27 06:48:19 PM PDT 24 |
Jul 27 06:49:00 PM PDT 24 |
3125671726 ps |
| T892 |
/workspace/coverage/default/23.sram_ctrl_regwen.4164792046 |
|
|
Jul 27 06:48:20 PM PDT 24 |
Jul 27 07:10:49 PM PDT 24 |
16800688051 ps |
| T893 |
/workspace/coverage/default/21.sram_ctrl_executable.1161192447 |
|
|
Jul 27 06:47:54 PM PDT 24 |
Jul 27 07:14:58 PM PDT 24 |
31536831990 ps |
| T894 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1014479943 |
|
|
Jul 27 06:45:53 PM PDT 24 |
Jul 27 08:56:47 PM PDT 24 |
1344214231981 ps |
| T895 |
/workspace/coverage/default/23.sram_ctrl_executable.1010868396 |
|
|
Jul 27 06:48:23 PM PDT 24 |
Jul 27 06:58:43 PM PDT 24 |
9117941279 ps |
| T896 |
/workspace/coverage/default/48.sram_ctrl_executable.1135779663 |
|
|
Jul 27 06:53:37 PM PDT 24 |
Jul 27 07:19:09 PM PDT 24 |
96745470901 ps |
| T897 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2668600557 |
|
|
Jul 27 06:53:44 PM PDT 24 |
Jul 27 06:54:03 PM PDT 24 |
1470562705 ps |
| T898 |
/workspace/coverage/default/16.sram_ctrl_bijection.2648970316 |
|
|
Jul 27 06:46:52 PM PDT 24 |
Jul 27 07:30:07 PM PDT 24 |
573200345301 ps |
| T899 |
/workspace/coverage/default/35.sram_ctrl_executable.1245690734 |
|
|
Jul 27 06:50:40 PM PDT 24 |
Jul 27 07:13:00 PM PDT 24 |
115995301833 ps |
| T900 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3622591410 |
|
|
Jul 27 06:46:52 PM PDT 24 |
Jul 27 06:53:58 PM PDT 24 |
17561349138 ps |
| T901 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3382450607 |
|
|
Jul 27 06:48:55 PM PDT 24 |
Jul 27 06:50:34 PM PDT 24 |
11184403826 ps |
| T902 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.210657284 |
|
|
Jul 27 06:49:54 PM PDT 24 |
Jul 27 06:53:36 PM PDT 24 |
149739827257 ps |
| T903 |
/workspace/coverage/default/40.sram_ctrl_stress_all.1176050843 |
|
|
Jul 27 06:51:46 PM PDT 24 |
Jul 27 07:40:21 PM PDT 24 |
173089348582 ps |
| T904 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3964340450 |
|
|
Jul 27 06:52:52 PM PDT 24 |
Jul 27 06:55:41 PM PDT 24 |
38256370281 ps |
| T905 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2976019881 |
|
|
Jul 27 06:51:38 PM PDT 24 |
Jul 27 06:52:02 PM PDT 24 |
837385010 ps |
| T906 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.2718916643 |
|
|
Jul 27 06:52:03 PM PDT 24 |
Jul 27 06:57:31 PM PDT 24 |
28222753671 ps |
| T907 |
/workspace/coverage/default/2.sram_ctrl_smoke.416994026 |
|
|
Jul 27 06:45:13 PM PDT 24 |
Jul 27 06:45:32 PM PDT 24 |
879173402 ps |
| T908 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3404588079 |
|
|
Jul 27 06:52:22 PM PDT 24 |
Jul 27 06:53:50 PM PDT 24 |
9896229296 ps |
| T909 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1475117026 |
|
|
Jul 27 06:53:38 PM PDT 24 |
Jul 27 06:58:48 PM PDT 24 |
10720169193 ps |
| T910 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.646297936 |
|
|
Jul 27 06:49:04 PM PDT 24 |
Jul 27 06:50:43 PM PDT 24 |
1502788348 ps |
| T911 |
/workspace/coverage/default/5.sram_ctrl_bijection.2419927508 |
|
|
Jul 27 06:45:24 PM PDT 24 |
Jul 27 07:26:50 PM PDT 24 |
105891923387 ps |
| T912 |
/workspace/coverage/default/9.sram_ctrl_bijection.653733607 |
|
|
Jul 27 06:45:49 PM PDT 24 |
Jul 27 07:11:10 PM PDT 24 |
280753656635 ps |
| T913 |
/workspace/coverage/default/35.sram_ctrl_smoke.3305306082 |
|
|
Jul 27 06:50:33 PM PDT 24 |
Jul 27 06:50:46 PM PDT 24 |
1943471128 ps |
| T914 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3916732222 |
|
|
Jul 27 06:47:45 PM PDT 24 |
Jul 27 06:47:46 PM PDT 24 |
28435464 ps |
| T915 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.959519733 |
|
|
Jul 27 06:49:13 PM PDT 24 |
Jul 27 06:50:44 PM PDT 24 |
11103033115 ps |
| T916 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2196984064 |
|
|
Jul 27 06:53:29 PM PDT 24 |
Jul 27 06:55:10 PM PDT 24 |
10385626303 ps |
| T917 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3415151413 |
|
|
Jul 27 06:50:41 PM PDT 24 |
Jul 27 06:57:56 PM PDT 24 |
17158261943 ps |
| T918 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2787293975 |
|
|
Jul 27 06:48:47 PM PDT 24 |
Jul 27 06:48:55 PM PDT 24 |
1492227735 ps |
| T919 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.408829899 |
|
|
Jul 27 06:45:59 PM PDT 24 |
Jul 27 07:00:31 PM PDT 24 |
37160412330 ps |
| T920 |
/workspace/coverage/default/28.sram_ctrl_alert_test.2490774350 |
|
|
Jul 27 06:49:21 PM PDT 24 |
Jul 27 06:49:22 PM PDT 24 |
35447301 ps |
| T35 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1441366803 |
|
|
Jul 27 06:45:18 PM PDT 24 |
Jul 27 06:45:22 PM PDT 24 |
957797051 ps |
| T921 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2499252179 |
|
|
Jul 27 06:46:05 PM PDT 24 |
Jul 27 06:53:09 PM PDT 24 |
57803950372 ps |
| T922 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1572677431 |
|
|
Jul 27 06:49:13 PM PDT 24 |
Jul 27 06:54:01 PM PDT 24 |
25650158254 ps |
| T923 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.4060989655 |
|
|
Jul 27 06:47:51 PM PDT 24 |
Jul 27 06:47:54 PM PDT 24 |
1405167176 ps |
| T924 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.2570022399 |
|
|
Jul 27 06:53:04 PM PDT 24 |
Jul 27 06:53:44 PM PDT 24 |
2887904600 ps |
| T925 |
/workspace/coverage/default/19.sram_ctrl_alert_test.469629909 |
|
|
Jul 27 06:47:34 PM PDT 24 |
Jul 27 06:47:35 PM PDT 24 |
32171346 ps |
| T926 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2737754208 |
|
|
Jul 27 06:49:05 PM PDT 24 |
Jul 27 06:51:26 PM PDT 24 |
5632101591 ps |
| T927 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3910860607 |
|
|
Jul 27 06:53:04 PM PDT 24 |
Jul 27 06:53:19 PM PDT 24 |
3029732176 ps |
| T928 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1012048341 |
|
|
Jul 27 06:45:29 PM PDT 24 |
Jul 27 06:45:30 PM PDT 24 |
18076852 ps |
| T929 |
/workspace/coverage/default/26.sram_ctrl_smoke.205749306 |
|
|
Jul 27 06:48:48 PM PDT 24 |
Jul 27 06:49:01 PM PDT 24 |
849247794 ps |
| T930 |
/workspace/coverage/default/43.sram_ctrl_alert_test.635732932 |
|
|
Jul 27 06:52:32 PM PDT 24 |
Jul 27 06:52:32 PM PDT 24 |
11884762 ps |
| T931 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3599804776 |
|
|
Jul 27 06:46:45 PM PDT 24 |
Jul 27 06:49:37 PM PDT 24 |
8016407684 ps |
| T932 |
/workspace/coverage/default/42.sram_ctrl_partial_access.1667899620 |
|
|
Jul 27 06:52:03 PM PDT 24 |
Jul 27 06:52:15 PM PDT 24 |
3499582059 ps |
| T933 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2861151324 |
|
|
Jul 27 06:48:48 PM PDT 24 |
Jul 27 06:58:40 PM PDT 24 |
91910101921 ps |
| T934 |
/workspace/coverage/default/46.sram_ctrl_executable.441481775 |
|
|
Jul 27 06:53:04 PM PDT 24 |
Jul 27 07:12:37 PM PDT 24 |
19549027923 ps |
| T935 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.1291280463 |
|
|
Jul 27 06:50:39 PM PDT 24 |
Jul 27 06:52:17 PM PDT 24 |
3023338136 ps |
| T936 |
/workspace/coverage/default/18.sram_ctrl_smoke.2067515546 |
|
|
Jul 27 06:47:18 PM PDT 24 |
Jul 27 06:48:31 PM PDT 24 |
7782290558 ps |
| T937 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.3221531041 |
|
|
Jul 27 06:48:32 PM PDT 24 |
Jul 27 06:50:37 PM PDT 24 |
3060761901 ps |
| T938 |
/workspace/coverage/default/11.sram_ctrl_executable.2621995843 |
|
|
Jul 27 06:46:07 PM PDT 24 |
Jul 27 07:03:32 PM PDT 24 |
32812815919 ps |
| T939 |
/workspace/coverage/default/36.sram_ctrl_executable.2898505120 |
|
|
Jul 27 06:50:59 PM PDT 24 |
Jul 27 06:58:23 PM PDT 24 |
30844926423 ps |
| T940 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4287716355 |
|
|
Jul 27 06:46:07 PM PDT 24 |
Jul 27 06:47:13 PM PDT 24 |
13489664817 ps |
| T941 |
/workspace/coverage/default/22.sram_ctrl_smoke.1916649673 |
|
|
Jul 27 06:47:55 PM PDT 24 |
Jul 27 06:48:02 PM PDT 24 |
1693289457 ps |
| T942 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3342574369 |
|
|
Jul 27 06:53:05 PM PDT 24 |
Jul 27 06:56:34 PM PDT 24 |
12111811983 ps |
| T943 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2818236037 |
|
|
Jul 27 06:47:27 PM PDT 24 |
Jul 27 06:49:52 PM PDT 24 |
9808722890 ps |
| T944 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3416177022 |
|
|
Jul 27 06:49:47 PM PDT 24 |
Jul 27 06:51:10 PM PDT 24 |
2192860947 ps |
| T945 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1058195250 |
|
|
Jul 27 06:50:58 PM PDT 24 |
Jul 27 06:51:28 PM PDT 24 |
3908500495 ps |
| T946 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1907859774 |
|
|
Jul 27 06:46:16 PM PDT 24 |
Jul 27 06:46:27 PM PDT 24 |
1352796437 ps |
| T947 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1804893014 |
|
|
Jul 27 06:47:08 PM PDT 24 |
Jul 27 06:47:25 PM PDT 24 |
2240876734 ps |
| T948 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.626473092 |
|
|
Jul 27 06:45:49 PM PDT 24 |
Jul 27 06:45:52 PM PDT 24 |
349074833 ps |
| T949 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.11105967 |
|
|
Jul 27 06:50:57 PM PDT 24 |
Jul 27 06:57:25 PM PDT 24 |
26518562086 ps |
| T66 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.680222476 |
|
|
Jul 27 06:44:36 PM PDT 24 |
Jul 27 06:45:02 PM PDT 24 |
3853138318 ps |
| T67 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.726101506 |
|
|
Jul 27 06:44:26 PM PDT 24 |
Jul 27 06:44:28 PM PDT 24 |
330131514 ps |
| T68 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3104411529 |
|
|
Jul 27 06:44:53 PM PDT 24 |
Jul 27 06:44:53 PM PDT 24 |
56511600 ps |
| T108 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3129189479 |
|
|
Jul 27 06:44:52 PM PDT 24 |
Jul 27 06:44:53 PM PDT 24 |
15185042 ps |
| T115 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2966352394 |
|
|
Jul 27 06:44:43 PM PDT 24 |
Jul 27 06:44:44 PM PDT 24 |
37888323 ps |
| T950 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3059791393 |
|
|
Jul 27 06:44:52 PM PDT 24 |
Jul 27 06:44:56 PM PDT 24 |
45169658 ps |
| T63 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2961697175 |
|
|
Jul 27 06:44:36 PM PDT 24 |
Jul 27 06:44:40 PM PDT 24 |
3576346228 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2498646302 |
|
|
Jul 27 06:44:44 PM PDT 24 |
Jul 27 06:44:48 PM PDT 24 |
351109336 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3975837947 |
|
|
Jul 27 06:44:30 PM PDT 24 |
Jul 27 06:44:32 PM PDT 24 |
76837755 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4283865637 |
|
|
Jul 27 06:44:22 PM PDT 24 |
Jul 27 06:44:26 PM PDT 24 |
1434441359 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4006756866 |
|
|
Jul 27 06:44:28 PM PDT 24 |
Jul 27 06:44:30 PM PDT 24 |
1300152792 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.576520603 |
|
|
Jul 27 06:44:26 PM PDT 24 |
Jul 27 06:44:31 PM PDT 24 |
4878231876 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3007823820 |
|
|
Jul 27 06:44:25 PM PDT 24 |
Jul 27 06:45:18 PM PDT 24 |
28204969958 ps |
| T955 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4045312552 |
|
|
Jul 27 06:44:37 PM PDT 24 |
Jul 27 06:44:42 PM PDT 24 |
236901576 ps |
| T956 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4091845219 |
|
|
Jul 27 06:44:53 PM PDT 24 |
Jul 27 06:44:56 PM PDT 24 |
1628175662 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3238668916 |
|
|
Jul 27 06:44:18 PM PDT 24 |
Jul 27 06:44:19 PM PDT 24 |
29487742 ps |
| T957 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2040885467 |
|
|
Jul 27 06:44:35 PM PDT 24 |
Jul 27 06:44:39 PM PDT 24 |
1783348223 ps |
| T116 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3804859562 |
|
|
Jul 27 06:44:26 PM PDT 24 |
Jul 27 06:44:27 PM PDT 24 |
42310174 ps |
| T65 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1075535047 |
|
|
Jul 27 06:44:28 PM PDT 24 |
Jul 27 06:44:29 PM PDT 24 |
345540901 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2836946122 |
|
|
Jul 27 06:44:18 PM PDT 24 |
Jul 27 06:44:18 PM PDT 24 |
16716485 ps |
| T959 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2702254230 |
|
|
Jul 27 06:44:47 PM PDT 24 |
Jul 27 06:44:51 PM PDT 24 |
1461567425 ps |
| T960 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1384883615 |
|
|
Jul 27 06:44:20 PM PDT 24 |
Jul 27 06:44:23 PM PDT 24 |
197236589 ps |
| T961 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2707107387 |
|
|
Jul 27 06:44:26 PM PDT 24 |
Jul 27 06:44:29 PM PDT 24 |
71280610 ps |
| T124 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1695828839 |
|
|
Jul 27 06:44:35 PM PDT 24 |
Jul 27 06:44:38 PM PDT 24 |
237933632 ps |
| T117 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3969723125 |
|
|
Jul 27 06:44:20 PM PDT 24 |
Jul 27 06:44:21 PM PDT 24 |
13447766 ps |
| T84 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1606275895 |
|
|
Jul 27 06:44:44 PM PDT 24 |
Jul 27 06:44:45 PM PDT 24 |
24755851 ps |
| T133 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1731427754 |
|
|
Jul 27 06:44:52 PM PDT 24 |
Jul 27 06:44:54 PM PDT 24 |
169267512 ps |
| T962 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2685802822 |
|
|
Jul 27 06:44:20 PM PDT 24 |
Jul 27 06:44:23 PM PDT 24 |
93867076 ps |
| T127 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3038109005 |
|
|
Jul 27 06:44:44 PM PDT 24 |
Jul 27 06:44:46 PM PDT 24 |
173247362 ps |
| T85 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1383313446 |
|
|
Jul 27 06:44:52 PM PDT 24 |
Jul 27 06:44:53 PM PDT 24 |
56053971 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3038675012 |
|
|
Jul 27 06:44:51 PM PDT 24 |
Jul 27 06:44:55 PM PDT 24 |
698307098 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4239728891 |
|
|
Jul 27 06:44:43 PM PDT 24 |
Jul 27 06:44:44 PM PDT 24 |
37646485 ps |
| T965 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2115000807 |
|
|
Jul 27 06:44:39 PM PDT 24 |
Jul 27 06:44:40 PM PDT 24 |
28992267 ps |
| T966 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.389576422 |
|
|
Jul 27 06:44:35 PM PDT 24 |
Jul 27 06:44:38 PM PDT 24 |
742538391 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2659099072 |
|
|
Jul 27 06:44:29 PM PDT 24 |
Jul 27 06:44:31 PM PDT 24 |
146199926 ps |
| T968 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3186243076 |
|
|
Jul 27 06:44:44 PM PDT 24 |
Jul 27 06:44:48 PM PDT 24 |
83095101 ps |
| T110 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2786651566 |
|
|
Jul 27 06:44:53 PM PDT 24 |
Jul 27 06:44:54 PM PDT 24 |
20871649 ps |
| T86 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2850523384 |
|
|
Jul 27 06:44:53 PM PDT 24 |
Jul 27 06:45:49 PM PDT 24 |
28275866704 ps |
| T87 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.929817370 |
|
|
Jul 27 06:44:45 PM PDT 24 |
Jul 27 06:45:37 PM PDT 24 |
9428236271 ps |
| T88 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1164379709 |
|
|
Jul 27 06:44:25 PM PDT 24 |
Jul 27 06:44:26 PM PDT 24 |
24256444 ps |
| T89 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3142479034 |
|
|
Jul 27 06:44:48 PM PDT 24 |
Jul 27 06:44:49 PM PDT 24 |
71220222 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1264352039 |
|
|
Jul 27 06:44:30 PM PDT 24 |
Jul 27 06:44:34 PM PDT 24 |
134674409 ps |
| T90 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1867866627 |
|
|
Jul 27 06:44:29 PM PDT 24 |
Jul 27 06:44:30 PM PDT 24 |
49059070 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.731494989 |
|
|
Jul 27 06:44:30 PM PDT 24 |
Jul 27 06:44:30 PM PDT 24 |
48367703 ps |
| T128 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2151811799 |
|
|
Jul 27 06:44:27 PM PDT 24 |
Jul 27 06:44:30 PM PDT 24 |
374655404 ps |
| T91 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1076688821 |
|
|
Jul 27 06:44:39 PM PDT 24 |
Jul 27 06:45:07 PM PDT 24 |
13155749704 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2901819400 |
|
|
Jul 27 06:44:30 PM PDT 24 |
Jul 27 06:44:31 PM PDT 24 |
13188031 ps |
| T125 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2067195058 |
|
|
Jul 27 06:44:52 PM PDT 24 |
Jul 27 06:44:53 PM PDT 24 |
152411909 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3523694928 |
|
|
Jul 27 06:44:26 PM PDT 24 |
Jul 27 06:44:27 PM PDT 24 |
14407804 ps |
| T130 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.139140414 |
|
|
Jul 27 06:44:52 PM PDT 24 |
Jul 27 06:44:55 PM PDT 24 |
678567457 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3481185876 |
|
|
Jul 27 06:44:43 PM PDT 24 |
Jul 27 06:44:47 PM PDT 24 |
62833298 ps |
| T974 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2906051737 |
|
|
Jul 27 06:44:38 PM PDT 24 |
Jul 27 06:44:39 PM PDT 24 |
47018613 ps |
| T975 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.759387982 |
|
|
Jul 27 06:44:45 PM PDT 24 |
Jul 27 06:44:46 PM PDT 24 |
15428482 ps |
| T131 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1432206057 |
|
|
Jul 27 06:44:48 PM PDT 24 |
Jul 27 06:44:50 PM PDT 24 |
537875567 ps |
| T976 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1603641294 |
|
|
Jul 27 06:44:54 PM PDT 24 |
Jul 27 06:44:59 PM PDT 24 |
297062713 ps |
| T132 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1574503232 |
|
|
Jul 27 06:44:36 PM PDT 24 |
Jul 27 06:44:39 PM PDT 24 |
744868180 ps |
| T977 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1690650424 |
|
|
Jul 27 06:44:37 PM PDT 24 |
Jul 27 06:44:41 PM PDT 24 |
1363916575 ps |
| T978 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1120526988 |
|
|
Jul 27 06:44:28 PM PDT 24 |
Jul 27 06:44:30 PM PDT 24 |
43127809 ps |
| T979 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2065317243 |
|
|
Jul 27 06:44:44 PM PDT 24 |
Jul 27 06:44:49 PM PDT 24 |
394119252 ps |
| T126 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1870086078 |
|
|
Jul 27 06:44:19 PM PDT 24 |
Jul 27 06:44:21 PM PDT 24 |
142692220 ps |
| T92 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3276163196 |
|
|
Jul 27 06:44:38 PM PDT 24 |
Jul 27 06:45:12 PM PDT 24 |
21741571156 ps |
| T980 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.453052557 |
|
|
Jul 27 06:44:37 PM PDT 24 |
Jul 27 06:44:38 PM PDT 24 |
33185257 ps |
| T981 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.841148395 |
|
|
Jul 27 06:44:43 PM PDT 24 |
Jul 27 06:44:45 PM PDT 24 |
26315044 ps |
| T982 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3335137295 |
|
|
Jul 27 06:44:42 PM PDT 24 |
Jul 27 06:44:43 PM PDT 24 |
37198695 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2187443196 |
|
|
Jul 27 06:44:25 PM PDT 24 |
Jul 27 06:44:26 PM PDT 24 |
50716312 ps |
| T134 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1191974933 |
|
|
Jul 27 06:44:44 PM PDT 24 |
Jul 27 06:44:46 PM PDT 24 |
880594231 ps |
| T93 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4289862075 |
|
|
Jul 27 06:44:34 PM PDT 24 |
Jul 27 06:44:35 PM PDT 24 |
18738847 ps |
| T984 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2957054814 |
|
|
Jul 27 06:44:38 PM PDT 24 |
Jul 27 06:44:38 PM PDT 24 |
65559495 ps |
| T985 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1945630021 |
|
|
Jul 27 06:44:34 PM PDT 24 |
Jul 27 06:44:35 PM PDT 24 |
25750090 ps |
| T986 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2288299406 |
|
|
Jul 27 06:44:38 PM PDT 24 |
Jul 27 06:44:42 PM PDT 24 |
430305379 ps |
| T987 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4268346230 |
|
|
Jul 27 06:44:52 PM PDT 24 |
Jul 27 06:44:55 PM PDT 24 |
34430291 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.130647156 |
|
|
Jul 27 06:44:29 PM PDT 24 |
Jul 27 06:44:29 PM PDT 24 |
50006079 ps |
| T988 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3424326329 |
|
|
Jul 27 06:45:03 PM PDT 24 |
Jul 27 06:45:07 PM PDT 24 |
735155793 ps |
| T95 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2621745986 |
|
|
Jul 27 06:44:39 PM PDT 24 |
Jul 27 06:45:08 PM PDT 24 |
3885277741 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1002474534 |
|
|
Jul 27 06:44:25 PM PDT 24 |
Jul 27 06:44:27 PM PDT 24 |
100460088 ps |
| T100 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3544918338 |
|
|
Jul 27 06:44:37 PM PDT 24 |
Jul 27 06:45:35 PM PDT 24 |
14692739657 ps |
| T990 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4147295571 |
|
|
Jul 27 06:44:44 PM PDT 24 |
Jul 27 06:44:44 PM PDT 24 |
81837318 ps |
| T991 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1638240601 |
|
|
Jul 27 06:44:49 PM PDT 24 |
Jul 27 06:44:53 PM PDT 24 |
41870099 ps |
| T101 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3385535117 |
|
|
Jul 27 06:44:26 PM PDT 24 |
Jul 27 06:44:26 PM PDT 24 |
21415685 ps |
| T992 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1237864944 |
|
|
Jul 27 06:44:44 PM PDT 24 |
Jul 27 06:44:47 PM PDT 24 |
722366244 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.272665566 |
|
|
Jul 27 06:44:51 PM PDT 24 |
Jul 27 06:44:52 PM PDT 24 |
36456201 ps |
| T994 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1323306110 |
|
|
Jul 27 06:44:37 PM PDT 24 |
Jul 27 06:44:38 PM PDT 24 |
12337338 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3429562212 |
|
|
Jul 27 06:44:27 PM PDT 24 |
Jul 27 06:44:28 PM PDT 24 |
45651185 ps |
| T996 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2221315941 |
|
|
Jul 27 06:44:53 PM PDT 24 |
Jul 27 06:44:54 PM PDT 24 |
16134880 ps |
| T997 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2376003667 |
|
|
Jul 27 06:44:37 PM PDT 24 |
Jul 27 06:44:42 PM PDT 24 |
140982542 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.482253095 |
|
|
Jul 27 06:44:22 PM PDT 24 |
Jul 27 06:44:50 PM PDT 24 |
3899390955 ps |
| T135 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1805881528 |
|
|
Jul 27 06:44:25 PM PDT 24 |
Jul 27 06:44:28 PM PDT 24 |
208011027 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1615111708 |
|
|
Jul 27 06:44:31 PM PDT 24 |
Jul 27 06:44:32 PM PDT 24 |
34617222 ps |
| T999 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3211913158 |
|
|
Jul 27 06:44:30 PM PDT 24 |
Jul 27 06:44:31 PM PDT 24 |
17778222 ps |
| T1000 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2545550715 |
|
|
Jul 27 06:44:48 PM PDT 24 |
Jul 27 06:44:50 PM PDT 24 |
25617977 ps |
| T1001 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2532176993 |
|
|
Jul 27 06:44:49 PM PDT 24 |
Jul 27 06:44:49 PM PDT 24 |
16062354 ps |
| T1002 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2839536932 |
|
|
Jul 27 06:44:48 PM PDT 24 |
Jul 27 06:44:49 PM PDT 24 |
33091741 ps |
| T1003 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2047380789 |
|
|
Jul 27 06:44:28 PM PDT 24 |
Jul 27 06:44:29 PM PDT 24 |
22302301 ps |
| T1004 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3721309821 |
|
|
Jul 27 06:44:25 PM PDT 24 |
Jul 27 06:44:30 PM PDT 24 |
362325496 ps |
| T1005 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1351554055 |
|
|
Jul 27 06:44:37 PM PDT 24 |
Jul 27 06:44:40 PM PDT 24 |
370136854 ps |
| T1006 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2932927490 |
|
|
Jul 27 06:44:35 PM PDT 24 |
Jul 27 06:44:37 PM PDT 24 |
358337105 ps |
| T1007 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1653362745 |
|
|
Jul 27 06:44:30 PM PDT 24 |
Jul 27 06:44:31 PM PDT 24 |
39966883 ps |