SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.99 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.62 |
T1008 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2833091864 | Jul 27 06:44:29 PM PDT 24 | Jul 27 06:44:33 PM PDT 24 | 350604830 ps | ||
T103 | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4009451113 | Jul 27 06:44:44 PM PDT 24 | Jul 27 06:45:34 PM PDT 24 | 7240568700 ps | ||
T104 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1737557652 | Jul 27 06:44:34 PM PDT 24 | Jul 27 06:44:35 PM PDT 24 | 17315430 ps | ||
T1009 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1682864779 | Jul 27 06:44:37 PM PDT 24 | Jul 27 06:44:41 PM PDT 24 | 1662523355 ps | ||
T1010 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2642827498 | Jul 27 06:44:18 PM PDT 24 | Jul 27 06:44:20 PM PDT 24 | 235675823 ps | ||
T105 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3077383513 | Jul 27 06:44:19 PM PDT 24 | Jul 27 06:44:21 PM PDT 24 | 183601930 ps | ||
T129 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2378609311 | Jul 27 06:44:42 PM PDT 24 | Jul 27 06:44:44 PM PDT 24 | 122171872 ps | ||
T1011 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3057569607 | Jul 27 06:44:52 PM PDT 24 | Jul 27 06:44:53 PM PDT 24 | 21670925 ps | ||
T106 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3769621898 | Jul 27 06:44:25 PM PDT 24 | Jul 27 06:45:15 PM PDT 24 | 7344551490 ps | ||
T1012 | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2275168207 | Jul 27 06:44:27 PM PDT 24 | Jul 27 06:44:28 PM PDT 24 | 33066254 ps | ||
T1013 | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3731697105 | Jul 27 06:44:51 PM PDT 24 | Jul 27 06:44:52 PM PDT 24 | 76472771 ps | ||
T1014 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4216634052 | Jul 27 06:44:27 PM PDT 24 | Jul 27 06:44:30 PM PDT 24 | 358297530 ps | ||
T1015 | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4216086228 | Jul 27 06:44:44 PM PDT 24 | Jul 27 06:45:23 PM PDT 24 | 33580229202 ps | ||
T1016 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.143452727 | Jul 27 06:44:47 PM PDT 24 | Jul 27 06:44:49 PM PDT 24 | 231822598 ps | ||
T1017 | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3288734600 | Jul 27 06:44:37 PM PDT 24 | Jul 27 06:44:38 PM PDT 24 | 49280803 ps | ||
T1018 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.833076440 | Jul 27 06:44:44 PM PDT 24 | Jul 27 06:44:48 PM PDT 24 | 3449029334 ps | ||
T1019 | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2265516400 | Jul 27 06:44:44 PM PDT 24 | Jul 27 06:45:13 PM PDT 24 | 7505067063 ps | ||
T1020 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1500719852 | Jul 27 06:45:03 PM PDT 24 | Jul 27 06:45:05 PM PDT 24 | 479190043 ps | ||
T1021 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2251971636 | Jul 27 06:44:37 PM PDT 24 | Jul 27 06:44:40 PM PDT 24 | 191156299 ps | ||
T1022 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1009320986 | Jul 27 06:44:36 PM PDT 24 | Jul 27 06:45:04 PM PDT 24 | 16064887866 ps | ||
T1023 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3938316047 | Jul 27 06:44:36 PM PDT 24 | Jul 27 06:44:39 PM PDT 24 | 27679908 ps | ||
T1024 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3339416809 | Jul 27 06:44:27 PM PDT 24 | Jul 27 06:44:29 PM PDT 24 | 161504677 ps | ||
T1025 | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3557486617 | Jul 27 06:44:43 PM PDT 24 | Jul 27 06:45:10 PM PDT 24 | 7635067215 ps | ||
T1026 | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.448198022 | Jul 27 06:44:19 PM PDT 24 | Jul 27 06:45:09 PM PDT 24 | 7417707678 ps | ||
T1027 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4055345395 | Jul 27 06:44:28 PM PDT 24 | Jul 27 06:44:32 PM PDT 24 | 1298032710 ps | ||
T1028 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1869085551 | Jul 27 06:44:44 PM PDT 24 | Jul 27 06:44:47 PM PDT 24 | 363455129 ps | ||
T142 | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1000978810 | Jul 27 06:45:03 PM PDT 24 | Jul 27 06:45:52 PM PDT 24 | 7478302487 ps | ||
T1029 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3090336559 | Jul 27 06:44:55 PM PDT 24 | Jul 27 06:44:58 PM PDT 24 | 374534314 ps | ||
T1030 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2875166456 | Jul 27 06:45:03 PM PDT 24 | Jul 27 06:45:08 PM PDT 24 | 126174505 ps | ||
T1031 | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.606755621 | Jul 27 06:44:27 PM PDT 24 | Jul 27 06:45:19 PM PDT 24 | 28436969902 ps | ||
T1032 | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3446398216 | Jul 27 06:44:25 PM PDT 24 | Jul 27 06:44:26 PM PDT 24 | 28449126 ps | ||
T1033 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1450700970 | Jul 27 06:44:30 PM PDT 24 | Jul 27 06:44:31 PM PDT 24 | 24774181 ps | ||
T1034 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3233099410 | Jul 27 06:44:20 PM PDT 24 | Jul 27 06:44:21 PM PDT 24 | 39269199 ps | ||
T1035 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1517427176 | Jul 27 06:44:53 PM PDT 24 | Jul 27 06:45:46 PM PDT 24 | 17224341474 ps | ||
T1036 | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.62215692 | Jul 27 06:44:26 PM PDT 24 | Jul 27 06:44:53 PM PDT 24 | 3886132067 ps | ||
T1037 | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3594670206 | Jul 27 06:44:35 PM PDT 24 | Jul 27 06:44:36 PM PDT 24 | 42930078 ps | ||
T1038 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3505682940 | Jul 27 06:44:30 PM PDT 24 | Jul 27 06:44:31 PM PDT 24 | 50687955 ps | ||
T136 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1386261791 | Jul 27 06:44:36 PM PDT 24 | Jul 27 06:44:39 PM PDT 24 | 637516800 ps |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1011168123 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 16043151580 ps |
CPU time | 385.29 seconds |
Started | Jul 27 06:45:29 PM PDT 24 |
Finished | Jul 27 06:51:54 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-e5d63800-6ecc-4351-accb-dbfa38511130 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011168123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.1011168123 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.547340744 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 2241884105 ps |
CPU time | 44.67 seconds |
Started | Jul 27 06:51:58 PM PDT 24 |
Finished | Jul 27 06:52:43 PM PDT 24 |
Peak memory | 211672 kb |
Host | smart-af91450e-ea63-40fb-a639-345f00d4e698 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=547340744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.547340744 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.861841917 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 450132751217 ps |
CPU time | 3141.22 seconds |
Started | Jul 27 06:53:30 PM PDT 24 |
Finished | Jul 27 07:45:52 PM PDT 24 |
Peak memory | 382180 kb |
Host | smart-cf392bcd-c72e-4e15-9d3a-c1f4055a459b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861841917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_stress_all.861841917 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.515664706 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 10364437654 ps |
CPU time | 831.77 seconds |
Started | Jul 27 06:50:41 PM PDT 24 |
Finished | Jul 27 07:04:33 PM PDT 24 |
Peak memory | 378052 kb |
Host | smart-9f294069-a9fa-4f50-8287-86538d593c5a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515664706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 35.sram_ctrl_access_during_key_req.515664706 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.3843487858 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 354860815 ps |
CPU time | 2.79 seconds |
Started | Jul 27 06:45:09 PM PDT 24 |
Finished | Jul 27 06:45:12 PM PDT 24 |
Peak memory | 222376 kb |
Host | smart-deadb112-c64a-4802-b74b-80f890939946 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843487858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3843487858 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1432206057 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 537875567 ps |
CPU time | 2.35 seconds |
Started | Jul 27 06:44:48 PM PDT 24 |
Finished | Jul 27 06:44:50 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-46867f75-57bf-4534-a64a-f48ee72e42b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432206057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.1432206057 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3905816173 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 1038259578 ps |
CPU time | 24.07 seconds |
Started | Jul 27 06:45:09 PM PDT 24 |
Finished | Jul 27 06:45:34 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-9c1dabf4-15da-4111-8b08-3e755e4f642d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3905816173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3905816173 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.2036182909 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 73711410211 ps |
CPU time | 1252.57 seconds |
Started | Jul 27 06:45:09 PM PDT 24 |
Finished | Jul 27 07:06:02 PM PDT 24 |
Peak memory | 375980 kb |
Host | smart-537bbf8e-2c82-40db-90a4-775949734fa3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036182909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2036182909 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.680222476 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 3853138318 ps |
CPU time | 26.01 seconds |
Started | Jul 27 06:44:36 PM PDT 24 |
Finished | Jul 27 06:45:02 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-410eff21-0b8a-41ce-9b0c-7be2b9901782 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680222476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.680222476 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.1043759886 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 278422155004 ps |
CPU time | 9605.99 seconds |
Started | Jul 27 06:50:48 PM PDT 24 |
Finished | Jul 27 09:30:55 PM PDT 24 |
Peak memory | 382072 kb |
Host | smart-bf7e357d-f95e-4c98-9f06-73b6d3dfe679 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043759886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.1043759886 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.161906837 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 655926332 ps |
CPU time | 3.43 seconds |
Started | Jul 27 06:45:08 PM PDT 24 |
Finished | Jul 27 06:45:11 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-5b8e28b7-0569-4cb9-ba66-88319662467b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161906837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.161906837 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1191974933 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 880594231 ps |
CPU time | 2.43 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:46 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-5a928392-3542-4650-8c34-ee50c83e56b0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191974933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.1191974933 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.886639238 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 41522387 ps |
CPU time | 0.64 seconds |
Started | Jul 27 06:45:13 PM PDT 24 |
Finished | Jul 27 06:45:14 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-89c37b8c-b21a-4899-93c0-ed2489bb2ebc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886639238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.886639238 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.3791202902 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 206789306343 ps |
CPU time | 5089.19 seconds |
Started | Jul 27 06:50:32 PM PDT 24 |
Finished | Jul 27 08:15:21 PM PDT 24 |
Peak memory | 373988 kb |
Host | smart-0d55089d-4043-4806-a3b0-5ae07ac15df1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791202902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.3791202902 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1805881528 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 208011027 ps |
CPU time | 2.36 seconds |
Started | Jul 27 06:44:25 PM PDT 24 |
Finished | Jul 27 06:44:28 PM PDT 24 |
Peak memory | 211252 kb |
Host | smart-af44a47f-b574-4639-bcd5-40ea5952c7e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805881528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.1805881528 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3038109005 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 173247362 ps |
CPU time | 2.12 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:46 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-85e69475-9f82-4deb-a118-d7cd310cd9f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038109005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.3038109005 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1000978810 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 7478302487 ps |
CPU time | 48.91 seconds |
Started | Jul 27 06:45:03 PM PDT 24 |
Finished | Jul 27 06:45:52 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-62ed93d8-6477-4c44-af56-504e010c038d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000978810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.1000978810 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2806206186 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 9357336657 ps |
CPU time | 193.8 seconds |
Started | Jul 27 06:46:01 PM PDT 24 |
Finished | Jul 27 06:49:15 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-0e36b09e-2ca9-4690-a4cd-e414293350ad |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806206186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.2806206186 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1551346672 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 10659211440 ps |
CPU time | 162.98 seconds |
Started | Jul 27 06:45:15 PM PDT 24 |
Finished | Jul 27 06:47:58 PM PDT 24 |
Peak memory | 219432 kb |
Host | smart-70088dfa-f2d2-4c9c-af5d-980311138283 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551346672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.1551346672 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4289862075 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 18738847 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:44:34 PM PDT 24 |
Finished | Jul 27 06:44:35 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-1462fc58-01f9-49ab-8224-1d44dee4e9f1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289862075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.4289862075 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3969723125 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 13447766 ps |
CPU time | 0.67 seconds |
Started | Jul 27 06:44:20 PM PDT 24 |
Finished | Jul 27 06:44:21 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-40fd2d15-ddfc-43f5-ab8d-051a1bda30e4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969723125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.3969723125 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3077383513 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 183601930 ps |
CPU time | 1.28 seconds |
Started | Jul 27 06:44:19 PM PDT 24 |
Finished | Jul 27 06:44:21 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-aceda87c-d411-4243-a7b5-be69d941f380 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077383513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.3077383513 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2836946122 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 16716485 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:44:18 PM PDT 24 |
Finished | Jul 27 06:44:18 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-df33a7e0-82ee-4405-932c-e6c46e132e87 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836946122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.2836946122 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4283865637 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 1434441359 ps |
CPU time | 3.77 seconds |
Started | Jul 27 06:44:22 PM PDT 24 |
Finished | Jul 27 06:44:26 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-616c1b0a-e70f-4a65-b218-35da9e23ce48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283865637 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.4283865637 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3233099410 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 39269199 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:44:20 PM PDT 24 |
Finished | Jul 27 06:44:21 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-a998daea-29bd-4411-a46a-88b69d636454 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233099410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.3233099410 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.482253095 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 3899390955 ps |
CPU time | 28.03 seconds |
Started | Jul 27 06:44:22 PM PDT 24 |
Finished | Jul 27 06:44:50 PM PDT 24 |
Peak memory | 203032 kb |
Host | smart-178328e0-0322-4c08-889d-21bedc853006 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482253095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.482253095 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3238668916 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 29487742 ps |
CPU time | 0.86 seconds |
Started | Jul 27 06:44:18 PM PDT 24 |
Finished | Jul 27 06:44:19 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-d6ae560e-591d-49e4-8eab-8b05e6e18162 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238668916 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3238668916 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2685802822 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 93867076 ps |
CPU time | 2.8 seconds |
Started | Jul 27 06:44:20 PM PDT 24 |
Finished | Jul 27 06:44:23 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-ffad0548-ce7a-48cf-9941-2e6a6bfaa6cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685802822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.2685802822 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1870086078 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 142692220 ps |
CPU time | 2.18 seconds |
Started | Jul 27 06:44:19 PM PDT 24 |
Finished | Jul 27 06:44:21 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-ba24d3c0-33cf-4db4-8c0f-c1da2e1d0931 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870086078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.1870086078 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2187443196 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 50716312 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:44:25 PM PDT 24 |
Finished | Jul 27 06:44:26 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-12db7d15-e1b0-4a67-9e3c-d5d5129ee020 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187443196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.2187443196 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.726101506 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 330131514 ps |
CPU time | 1.84 seconds |
Started | Jul 27 06:44:26 PM PDT 24 |
Finished | Jul 27 06:44:28 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-1a6f25c3-2843-4987-8575-d90daceb4c72 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726101506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.726101506 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3523694928 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 14407804 ps |
CPU time | 0.67 seconds |
Started | Jul 27 06:44:26 PM PDT 24 |
Finished | Jul 27 06:44:27 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-b9728796-c5d6-499d-ab12-c6ae76cd6776 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523694928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.3523694928 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4055345395 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 1298032710 ps |
CPU time | 4.59 seconds |
Started | Jul 27 06:44:28 PM PDT 24 |
Finished | Jul 27 06:44:32 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-0f271f40-2e72-4d2a-9a07-4bb5b86d0cf6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055345395 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.4055345395 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2047380789 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 22302301 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:44:28 PM PDT 24 |
Finished | Jul 27 06:44:29 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-7bda9371-adb4-4a48-bc7c-ec596fc6aaff |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047380789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2047380789 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.448198022 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 7417707678 ps |
CPU time | 49.44 seconds |
Started | Jul 27 06:44:19 PM PDT 24 |
Finished | Jul 27 06:45:09 PM PDT 24 |
Peak memory | 203316 kb |
Host | smart-473f33b0-453e-4f8c-84d7-7417d303134e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448198022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.448198022 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1164379709 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 24256444 ps |
CPU time | 0.78 seconds |
Started | Jul 27 06:44:25 PM PDT 24 |
Finished | Jul 27 06:44:26 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-280d8850-64c5-4f0d-b761-307df7ba241e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164379709 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1164379709 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1384883615 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 197236589 ps |
CPU time | 3.4 seconds |
Started | Jul 27 06:44:20 PM PDT 24 |
Finished | Jul 27 06:44:23 PM PDT 24 |
Peak memory | 211284 kb |
Host | smart-5a54508f-c35e-4c70-94ed-836a82cec144 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384883615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.1384883615 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2642827498 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 235675823 ps |
CPU time | 2.26 seconds |
Started | Jul 27 06:44:18 PM PDT 24 |
Finished | Jul 27 06:44:20 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-32c76348-ddcd-4c86-a037-08403088ee86 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642827498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.2642827498 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2040885467 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 1783348223 ps |
CPU time | 3.7 seconds |
Started | Jul 27 06:44:35 PM PDT 24 |
Finished | Jul 27 06:44:39 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-6cd66c28-015c-495d-b4fb-6fb22b57e947 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040885467 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2040885467 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2621745986 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 3885277741 ps |
CPU time | 28.14 seconds |
Started | Jul 27 06:44:39 PM PDT 24 |
Finished | Jul 27 06:45:08 PM PDT 24 |
Peak memory | 203048 kb |
Host | smart-4b5f3a6c-1433-402e-9a99-315fc0583be9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621745986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2621745986 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2906051737 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 47018613 ps |
CPU time | 0.69 seconds |
Started | Jul 27 06:44:38 PM PDT 24 |
Finished | Jul 27 06:44:39 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-5b25bdc3-d97f-46cd-b891-9abb321e7430 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906051737 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2906051737 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3938316047 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 27679908 ps |
CPU time | 2.65 seconds |
Started | Jul 27 06:44:36 PM PDT 24 |
Finished | Jul 27 06:44:39 PM PDT 24 |
Peak memory | 203004 kb |
Host | smart-8aa1f4cf-75d7-4abe-9bf8-5f0d55036df8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938316047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.3938316047 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1574503232 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 744868180 ps |
CPU time | 2.38 seconds |
Started | Jul 27 06:44:36 PM PDT 24 |
Finished | Jul 27 06:44:39 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-82969614-b73f-434b-9a05-1f9679d9305f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574503232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.1574503232 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2498646302 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 351109336 ps |
CPU time | 3.48 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:48 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-bf6e62b9-f7e6-47a8-a9bd-c3bad037651e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498646302 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2498646302 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4147295571 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 81837318 ps |
CPU time | 0.64 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:44 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-f975cea2-ef32-4095-a1dc-7f81ccc34ca5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147295571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.4147295571 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1076688821 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 13155749704 ps |
CPU time | 27.9 seconds |
Started | Jul 27 06:44:39 PM PDT 24 |
Finished | Jul 27 06:45:07 PM PDT 24 |
Peak memory | 203056 kb |
Host | smart-83583f43-9bdd-4138-ac52-99a4442d44ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076688821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1076688821 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3142479034 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 71220222 ps |
CPU time | 0.92 seconds |
Started | Jul 27 06:44:48 PM PDT 24 |
Finished | Jul 27 06:44:49 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-a21e9e6d-c626-461a-82fa-2d518396bc88 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142479034 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.3142479034 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1638240601 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 41870099 ps |
CPU time | 3.98 seconds |
Started | Jul 27 06:44:49 PM PDT 24 |
Finished | Jul 27 06:44:53 PM PDT 24 |
Peak memory | 211268 kb |
Host | smart-59c486a7-04b7-44ee-b341-5d3ce85562c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638240601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1638240601 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.833076440 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 3449029334 ps |
CPU time | 3.57 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:48 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-5c2e1502-0ebe-4178-bc91-2f069270e291 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833076440 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.833076440 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4239728891 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 37646485 ps |
CPU time | 0.61 seconds |
Started | Jul 27 06:44:43 PM PDT 24 |
Finished | Jul 27 06:44:44 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-cdd436c7-16ba-406c-a28d-d2625e4ad29d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239728891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.4239728891 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.929817370 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 9428236271 ps |
CPU time | 52.31 seconds |
Started | Jul 27 06:44:45 PM PDT 24 |
Finished | Jul 27 06:45:37 PM PDT 24 |
Peak memory | 203328 kb |
Host | smart-d349ef2c-3601-4304-b5e9-7ee8ff0aaf28 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929817370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.929817370 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2532176993 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 16062354 ps |
CPU time | 0.75 seconds |
Started | Jul 27 06:44:49 PM PDT 24 |
Finished | Jul 27 06:44:49 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-4c107038-30f0-4a70-b136-0570f50111d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532176993 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2532176993 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.841148395 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 26315044 ps |
CPU time | 2.14 seconds |
Started | Jul 27 06:44:43 PM PDT 24 |
Finished | Jul 27 06:44:45 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-098dcd76-47f1-4940-a708-1462906f4b58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841148395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.841148395 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1869085551 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 363455129 ps |
CPU time | 3.29 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:47 PM PDT 24 |
Peak memory | 210924 kb |
Host | smart-d6f124f4-0b5d-4b84-ac54-f25ae66fd8b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869085551 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1869085551 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2966352394 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 37888323 ps |
CPU time | 0.62 seconds |
Started | Jul 27 06:44:43 PM PDT 24 |
Finished | Jul 27 06:44:44 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-c4d29c72-bbda-43a0-a51a-3ce8a67e830e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966352394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.2966352394 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2265516400 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 7505067063 ps |
CPU time | 28.7 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:45:13 PM PDT 24 |
Peak memory | 203092 kb |
Host | smart-5c6619e3-e6e5-4c05-bad5-8104dbc6d2af |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265516400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2265516400 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2545550715 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 25617977 ps |
CPU time | 0.8 seconds |
Started | Jul 27 06:44:48 PM PDT 24 |
Finished | Jul 27 06:44:50 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-f274302e-c68f-4efa-9876-fd6ebc32171e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545550715 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2545550715 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3481185876 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 62833298 ps |
CPU time | 3.95 seconds |
Started | Jul 27 06:44:43 PM PDT 24 |
Finished | Jul 27 06:44:47 PM PDT 24 |
Peak memory | 211208 kb |
Host | smart-da536ab4-87df-4cad-971c-762c40f4f1ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481185876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3481185876 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2702254230 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 1461567425 ps |
CPU time | 4.81 seconds |
Started | Jul 27 06:44:47 PM PDT 24 |
Finished | Jul 27 06:44:51 PM PDT 24 |
Peak memory | 212612 kb |
Host | smart-e5e1e053-a7e1-4614-8926-feb3e6064bce |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702254230 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2702254230 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2839536932 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 33091741 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:44:48 PM PDT 24 |
Finished | Jul 27 06:44:49 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-1f4b759e-0a3a-4ac2-9c85-18ebd9faab22 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839536932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.2839536932 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4009451113 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 7240568700 ps |
CPU time | 49.62 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:45:34 PM PDT 24 |
Peak memory | 203284 kb |
Host | smart-d311e253-2fba-49e4-9698-2f14c4d45db0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009451113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.4009451113 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1606275895 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 24755851 ps |
CPU time | 0.75 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:45 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-793c306d-c543-4563-ac7d-3a53bf7970a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606275895 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1606275895 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2065317243 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 394119252 ps |
CPU time | 4.48 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:49 PM PDT 24 |
Peak memory | 211168 kb |
Host | smart-d493fc4e-ec02-4c88-b072-cc979a6df252 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065317243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.2065317243 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2378609311 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 122171872 ps |
CPU time | 1.58 seconds |
Started | Jul 27 06:44:42 PM PDT 24 |
Finished | Jul 27 06:44:44 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-b27625da-ca02-4023-a0db-3ddc6025122d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378609311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.2378609311 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1237864944 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 722366244 ps |
CPU time | 3.65 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:47 PM PDT 24 |
Peak memory | 211236 kb |
Host | smart-fe50b84f-42b7-448b-be84-78137fff5ae7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237864944 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1237864944 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3335137295 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 37198695 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:44:42 PM PDT 24 |
Finished | Jul 27 06:44:43 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-69b55fa7-17fd-423c-8783-6e8c735e15e5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335137295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.3335137295 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3557486617 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 7635067215 ps |
CPU time | 26.57 seconds |
Started | Jul 27 06:44:43 PM PDT 24 |
Finished | Jul 27 06:45:10 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-afdbdeed-93a0-44bb-a804-15e3ac3b6513 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557486617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3557486617 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.759387982 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 15428482 ps |
CPU time | 0.78 seconds |
Started | Jul 27 06:44:45 PM PDT 24 |
Finished | Jul 27 06:44:46 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-bb51afd3-3fab-420a-b871-7095654d3f5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759387982 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.759387982 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3186243076 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 83095101 ps |
CPU time | 4.23 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:44:48 PM PDT 24 |
Peak memory | 212256 kb |
Host | smart-64eec1bf-f8d0-4323-aff4-f08c976eb8b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186243076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.3186243076 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.143452727 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 231822598 ps |
CPU time | 1.73 seconds |
Started | Jul 27 06:44:47 PM PDT 24 |
Finished | Jul 27 06:44:49 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-4090f046-8f66-4785-9309-d6e3c93f67a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143452727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.sram_ctrl_tl_intg_err.143452727 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3424326329 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 735155793 ps |
CPU time | 3.8 seconds |
Started | Jul 27 06:45:03 PM PDT 24 |
Finished | Jul 27 06:45:07 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-e80d3ecd-1553-4113-a3a6-f0cb775048d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424326329 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3424326329 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3057569607 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 21670925 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:44:52 PM PDT 24 |
Finished | Jul 27 06:44:53 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-6825283e-387b-41ea-8d90-345a56f23410 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057569607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.3057569607 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4216086228 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 33580229202 ps |
CPU time | 38.34 seconds |
Started | Jul 27 06:44:44 PM PDT 24 |
Finished | Jul 27 06:45:23 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-88b96e18-54f4-4861-81ab-40ebb26f973d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216086228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.4216086228 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2221315941 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 16134880 ps |
CPU time | 0.71 seconds |
Started | Jul 27 06:44:53 PM PDT 24 |
Finished | Jul 27 06:44:54 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-d9ade4d2-f0fc-4a96-aa0c-41b9351bf0c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221315941 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2221315941 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2875166456 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 126174505 ps |
CPU time | 4.45 seconds |
Started | Jul 27 06:45:03 PM PDT 24 |
Finished | Jul 27 06:45:08 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-0a0dd911-9468-4016-ba3e-65e5466cc50f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875166456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.2875166456 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.139140414 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 678567457 ps |
CPU time | 2.4 seconds |
Started | Jul 27 06:44:52 PM PDT 24 |
Finished | Jul 27 06:44:55 PM PDT 24 |
Peak memory | 211200 kb |
Host | smart-0c1c2ad6-2477-43c7-b090-b17782f8d3a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139140414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.sram_ctrl_tl_intg_err.139140414 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4091845219 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 1628175662 ps |
CPU time | 3.42 seconds |
Started | Jul 27 06:44:53 PM PDT 24 |
Finished | Jul 27 06:44:56 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-f4dabf93-e575-4ffa-9dad-cf29ac3e70cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091845219 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.4091845219 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.272665566 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 36456201 ps |
CPU time | 0.64 seconds |
Started | Jul 27 06:44:51 PM PDT 24 |
Finished | Jul 27 06:44:52 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-2eb52c75-d00c-4fb9-adf1-ab7e83bee006 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272665566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.272665566 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3129189479 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 15185042 ps |
CPU time | 0.69 seconds |
Started | Jul 27 06:44:52 PM PDT 24 |
Finished | Jul 27 06:44:53 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-d94c0d52-93d8-4a4d-9776-1675d5bd548b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129189479 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3129189479 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3059791393 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 45169658 ps |
CPU time | 3.46 seconds |
Started | Jul 27 06:44:52 PM PDT 24 |
Finished | Jul 27 06:44:56 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-9435dcae-471c-4839-9a48-f10df5e021a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059791393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.3059791393 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1500719852 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 479190043 ps |
CPU time | 1.65 seconds |
Started | Jul 27 06:45:03 PM PDT 24 |
Finished | Jul 27 06:45:05 PM PDT 24 |
Peak memory | 211152 kb |
Host | smart-6a26d6db-9db7-46c8-a464-438ab561d3b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500719852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.1500719852 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3090336559 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 374534314 ps |
CPU time | 3.39 seconds |
Started | Jul 27 06:44:55 PM PDT 24 |
Finished | Jul 27 06:44:58 PM PDT 24 |
Peak memory | 212024 kb |
Host | smart-9c2af724-090a-4c55-81f0-6e7a3f2dcd5a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090336559 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3090336559 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1383313446 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 56053971 ps |
CPU time | 0.69 seconds |
Started | Jul 27 06:44:52 PM PDT 24 |
Finished | Jul 27 06:44:53 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-b9f47d2e-00d8-42d5-9ac9-a8c54011c198 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383313446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.1383313446 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1517427176 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 17224341474 ps |
CPU time | 52.78 seconds |
Started | Jul 27 06:44:53 PM PDT 24 |
Finished | Jul 27 06:45:46 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-c06fe5bc-ea4f-41ad-a9fc-1b1c28bdc883 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517427176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1517427176 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3731697105 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 76472771 ps |
CPU time | 0.7 seconds |
Started | Jul 27 06:44:51 PM PDT 24 |
Finished | Jul 27 06:44:52 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-627003e4-82a2-412b-9090-c7a22e584f11 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731697105 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3731697105 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4268346230 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 34430291 ps |
CPU time | 2.35 seconds |
Started | Jul 27 06:44:52 PM PDT 24 |
Finished | Jul 27 06:44:55 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-e98e75b7-ed85-4e4e-ac35-3137aee4b4e0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268346230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.4268346230 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1731427754 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 169267512 ps |
CPU time | 1.49 seconds |
Started | Jul 27 06:44:52 PM PDT 24 |
Finished | Jul 27 06:44:54 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-6f8cdbec-89cd-4362-8a74-1f18a2e9a736 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731427754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.1731427754 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3038675012 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 698307098 ps |
CPU time | 3.65 seconds |
Started | Jul 27 06:44:51 PM PDT 24 |
Finished | Jul 27 06:44:55 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-96404052-42a8-4a06-8208-e2183f5862e5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038675012 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3038675012 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3104411529 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 56511600 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:44:53 PM PDT 24 |
Finished | Jul 27 06:44:53 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-720c05e4-fb9b-4110-9663-05c486c43a83 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104411529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.3104411529 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2850523384 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 28275866704 ps |
CPU time | 56.39 seconds |
Started | Jul 27 06:44:53 PM PDT 24 |
Finished | Jul 27 06:45:49 PM PDT 24 |
Peak memory | 203344 kb |
Host | smart-98cd13f2-5bdd-4e38-b9fd-33547694093b |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850523384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2850523384 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2786651566 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 20871649 ps |
CPU time | 0.69 seconds |
Started | Jul 27 06:44:53 PM PDT 24 |
Finished | Jul 27 06:44:54 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-013cbf40-1421-4be0-899b-63bfb3cd649b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786651566 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2786651566 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1603641294 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 297062713 ps |
CPU time | 5.04 seconds |
Started | Jul 27 06:44:54 PM PDT 24 |
Finished | Jul 27 06:44:59 PM PDT 24 |
Peak memory | 211208 kb |
Host | smart-3a21fc32-f965-414d-8090-8689adccf1f4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603641294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.1603641294 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2067195058 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 152411909 ps |
CPU time | 1.45 seconds |
Started | Jul 27 06:44:52 PM PDT 24 |
Finished | Jul 27 06:44:53 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-635c688b-caac-4d86-b12c-6a3d7d8a5e1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067195058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.2067195058 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3505682940 |
Short name | T1038 |
Test name | |
Test status | |
Simulation time | 50687955 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:44:30 PM PDT 24 |
Finished | Jul 27 06:44:31 PM PDT 24 |
Peak memory | 202532 kb |
Host | smart-8b4df94e-4102-4179-93db-f337512c71a8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505682940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.3505682940 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1120526988 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 43127809 ps |
CPU time | 1.74 seconds |
Started | Jul 27 06:44:28 PM PDT 24 |
Finished | Jul 27 06:44:30 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-eebe49d7-4a69-4747-9e3f-78048768f4e2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120526988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.1120526988 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1653362745 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 39966883 ps |
CPU time | 0.72 seconds |
Started | Jul 27 06:44:30 PM PDT 24 |
Finished | Jul 27 06:44:31 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-7d6fa4a9-84fb-4693-9442-5a1609e7e3a3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653362745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.1653362745 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.576520603 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 4878231876 ps |
CPU time | 4.71 seconds |
Started | Jul 27 06:44:26 PM PDT 24 |
Finished | Jul 27 06:44:31 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-0a751a6d-2760-4f9f-aa45-e3897765d49a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576520603 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.576520603 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3804859562 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 42310174 ps |
CPU time | 0.67 seconds |
Started | Jul 27 06:44:26 PM PDT 24 |
Finished | Jul 27 06:44:27 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-ffde3559-dcf8-4b79-b90f-504a9f39efa3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804859562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.3804859562 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3007823820 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 28204969958 ps |
CPU time | 52.64 seconds |
Started | Jul 27 06:44:25 PM PDT 24 |
Finished | Jul 27 06:45:18 PM PDT 24 |
Peak memory | 203300 kb |
Host | smart-b007ef59-088f-4977-9b6b-f7d735bb8dd4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007823820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3007823820 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3429562212 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 45651185 ps |
CPU time | 0.72 seconds |
Started | Jul 27 06:44:27 PM PDT 24 |
Finished | Jul 27 06:44:28 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-107fc882-adae-420f-b3b0-cb62ccae854b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429562212 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3429562212 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3975837947 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 76837755 ps |
CPU time | 1.8 seconds |
Started | Jul 27 06:44:30 PM PDT 24 |
Finished | Jul 27 06:44:32 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-9d9401d5-d106-461c-93ad-9ccf9bbac8be |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975837947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.3975837947 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2151811799 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 374655404 ps |
CPU time | 2.22 seconds |
Started | Jul 27 06:44:27 PM PDT 24 |
Finished | Jul 27 06:44:30 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-d9d17978-a1ef-429d-a2f7-4054c83865b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151811799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.2151811799 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.130647156 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 50006079 ps |
CPU time | 0.67 seconds |
Started | Jul 27 06:44:29 PM PDT 24 |
Finished | Jul 27 06:44:29 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-bca2294a-64f6-46ac-82ea-f669f9a3ac31 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130647156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.130647156 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3339416809 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 161504677 ps |
CPU time | 1.81 seconds |
Started | Jul 27 06:44:27 PM PDT 24 |
Finished | Jul 27 06:44:29 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-43f3a987-60b9-4a74-8d58-78206409feb8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339416809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3339416809 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1867866627 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 49059070 ps |
CPU time | 0.75 seconds |
Started | Jul 27 06:44:29 PM PDT 24 |
Finished | Jul 27 06:44:30 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-3beb8bae-16d9-4c0b-a035-78906fa4af1f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867866627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1867866627 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3721309821 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 362325496 ps |
CPU time | 4.63 seconds |
Started | Jul 27 06:44:25 PM PDT 24 |
Finished | Jul 27 06:44:30 PM PDT 24 |
Peak memory | 211224 kb |
Host | smart-8479e9f1-13c5-407f-93b8-b46d9dd234b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721309821 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3721309821 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1450700970 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 24774181 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:44:30 PM PDT 24 |
Finished | Jul 27 06:44:31 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-a698017e-3c69-4ec4-8123-318e1805bd48 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450700970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.1450700970 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3769621898 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 7344551490 ps |
CPU time | 49.01 seconds |
Started | Jul 27 06:44:25 PM PDT 24 |
Finished | Jul 27 06:45:15 PM PDT 24 |
Peak memory | 203348 kb |
Host | smart-62117a33-101f-4eca-a50f-18bb681d98a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769621898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3769621898 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.731494989 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 48367703 ps |
CPU time | 0.81 seconds |
Started | Jul 27 06:44:30 PM PDT 24 |
Finished | Jul 27 06:44:30 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-ff15dbff-adf4-4f75-903d-85a5d81e05ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731494989 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.731494989 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2659099072 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 146199926 ps |
CPU time | 2.57 seconds |
Started | Jul 27 06:44:29 PM PDT 24 |
Finished | Jul 27 06:44:31 PM PDT 24 |
Peak memory | 211212 kb |
Host | smart-5acd477a-aad9-424d-9faa-06656e573f08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659099072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.2659099072 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1615111708 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 34617222 ps |
CPU time | 0.77 seconds |
Started | Jul 27 06:44:31 PM PDT 24 |
Finished | Jul 27 06:44:32 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-0d1fd0c9-1588-4ece-a210-cc7432b38570 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615111708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.1615111708 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1002474534 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 100460088 ps |
CPU time | 1.83 seconds |
Started | Jul 27 06:44:25 PM PDT 24 |
Finished | Jul 27 06:44:27 PM PDT 24 |
Peak memory | 203016 kb |
Host | smart-bc01134b-1f6b-4cd0-9fe6-bc2e4ff0f2e8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002474534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.1002474534 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3211913158 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 17778222 ps |
CPU time | 0.73 seconds |
Started | Jul 27 06:44:30 PM PDT 24 |
Finished | Jul 27 06:44:31 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-674a80e7-6db1-45a5-a52c-ad12ae0c07ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211913158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.3211913158 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2833091864 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 350604830 ps |
CPU time | 3.83 seconds |
Started | Jul 27 06:44:29 PM PDT 24 |
Finished | Jul 27 06:44:33 PM PDT 24 |
Peak memory | 212232 kb |
Host | smart-06913d72-2073-4588-ad3f-183ada50cd08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833091864 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2833091864 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2901819400 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 13188031 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:44:30 PM PDT 24 |
Finished | Jul 27 06:44:31 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-09ad4cdf-e550-401f-9827-fe062a910e34 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901819400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.2901819400 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.606755621 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 28436969902 ps |
CPU time | 51.35 seconds |
Started | Jul 27 06:44:27 PM PDT 24 |
Finished | Jul 27 06:45:19 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-d8a8fc4c-6c0e-4f99-9134-964e502a85bb |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606755621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.606755621 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3446398216 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 28449126 ps |
CPU time | 0.8 seconds |
Started | Jul 27 06:44:25 PM PDT 24 |
Finished | Jul 27 06:44:26 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-d207879f-7d5f-40bf-bdd2-9a40d2ebaa89 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446398216 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3446398216 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1264352039 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 134674409 ps |
CPU time | 4.18 seconds |
Started | Jul 27 06:44:30 PM PDT 24 |
Finished | Jul 27 06:44:34 PM PDT 24 |
Peak memory | 203016 kb |
Host | smart-32d36e32-77b8-4322-a00f-cd678de9b4c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264352039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.1264352039 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4006756866 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 1300152792 ps |
CPU time | 2.25 seconds |
Started | Jul 27 06:44:28 PM PDT 24 |
Finished | Jul 27 06:44:30 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-d3bd9bd6-d5b0-4ec3-8711-d72bddfdc959 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006756866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.4006756866 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4216634052 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 358297530 ps |
CPU time | 3.49 seconds |
Started | Jul 27 06:44:27 PM PDT 24 |
Finished | Jul 27 06:44:30 PM PDT 24 |
Peak memory | 212228 kb |
Host | smart-0fc15268-0a25-4f1d-a207-51523b6f5d27 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216634052 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.4216634052 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3385535117 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 21415685 ps |
CPU time | 0.71 seconds |
Started | Jul 27 06:44:26 PM PDT 24 |
Finished | Jul 27 06:44:26 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-fe12084e-c8d4-49aa-aee2-0a85a2302f3c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385535117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.3385535117 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.62215692 |
Short name | T1036 |
Test name | |
Test status | |
Simulation time | 3886132067 ps |
CPU time | 26.87 seconds |
Started | Jul 27 06:44:26 PM PDT 24 |
Finished | Jul 27 06:44:53 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-7fa29db0-b263-48a0-955b-5409be004c22 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62215692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.62215692 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2275168207 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 33066254 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:44:27 PM PDT 24 |
Finished | Jul 27 06:44:28 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-e9f4f8ef-c6d1-4e04-962f-ba381c62f3ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275168207 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2275168207 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2707107387 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 71280610 ps |
CPU time | 3.04 seconds |
Started | Jul 27 06:44:26 PM PDT 24 |
Finished | Jul 27 06:44:29 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-9ad20c02-66fa-4650-ae07-3e30eae5a295 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707107387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.2707107387 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1075535047 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 345540901 ps |
CPU time | 1.45 seconds |
Started | Jul 27 06:44:28 PM PDT 24 |
Finished | Jul 27 06:44:29 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-4bd1af01-db46-4de3-907e-ce8ad0ae8285 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075535047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.1075535047 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.389576422 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 742538391 ps |
CPU time | 3.33 seconds |
Started | Jul 27 06:44:35 PM PDT 24 |
Finished | Jul 27 06:44:38 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-0df7eb8c-bdcf-46ce-b2d9-fc915a3993e2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389576422 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.389576422 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1323306110 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 12337338 ps |
CPU time | 0.63 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:44:38 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-2179de2c-1b3b-4f0c-bbf5-f147b30fda68 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323306110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.1323306110 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1009320986 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 16064887866 ps |
CPU time | 28.65 seconds |
Started | Jul 27 06:44:36 PM PDT 24 |
Finished | Jul 27 06:45:04 PM PDT 24 |
Peak memory | 203092 kb |
Host | smart-04d81f7c-4967-4c04-bdc2-1c39fc4d177c |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009320986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.1009320986 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3594670206 |
Short name | T1037 |
Test name | |
Test status | |
Simulation time | 42930078 ps |
CPU time | 0.67 seconds |
Started | Jul 27 06:44:35 PM PDT 24 |
Finished | Jul 27 06:44:36 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-4a202ad8-77b2-4803-9ad7-0922de24f2ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594670206 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3594670206 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4045312552 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 236901576 ps |
CPU time | 4.81 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:44:42 PM PDT 24 |
Peak memory | 211152 kb |
Host | smart-6c4d5c1d-ca65-4940-9b4b-c8b5ce057dd1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045312552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.4045312552 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1695828839 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 237933632 ps |
CPU time | 2.22 seconds |
Started | Jul 27 06:44:35 PM PDT 24 |
Finished | Jul 27 06:44:38 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-43d6af35-d6da-4c36-b2c9-20cee5ca3fb0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695828839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1695828839 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1351554055 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 370136854 ps |
CPU time | 3.47 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:44:40 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-0f65e752-75aa-47e5-9c11-14d267ba18ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351554055 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1351554055 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2115000807 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 28992267 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:44:39 PM PDT 24 |
Finished | Jul 27 06:44:40 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-f308e49e-b39c-4027-b6b3-d4e4f66a7ffa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115000807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.2115000807 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1945630021 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 25750090 ps |
CPU time | 0.76 seconds |
Started | Jul 27 06:44:34 PM PDT 24 |
Finished | Jul 27 06:44:35 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-5e3f78a4-a11d-4909-a81d-b3d7fc3581ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945630021 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1945630021 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2376003667 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 140982542 ps |
CPU time | 3.94 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:44:42 PM PDT 24 |
Peak memory | 211168 kb |
Host | smart-6eef8726-6f44-4e01-ac2a-a5537cdcfcdb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376003667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.2376003667 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2961697175 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 3576346228 ps |
CPU time | 3.95 seconds |
Started | Jul 27 06:44:36 PM PDT 24 |
Finished | Jul 27 06:44:40 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-b646d30f-1069-4ca0-a752-22b43c066413 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961697175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2961697175 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1690650424 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 1363916575 ps |
CPU time | 3.54 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:44:41 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-9a19a12d-7bba-4821-8ec8-038ac1d05ae2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690650424 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1690650424 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.453052557 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 33185257 ps |
CPU time | 0.63 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:44:38 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-1de78e6a-4d80-41dd-808b-94033fa2ed74 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453052557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_csr_rw.453052557 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3544918338 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 14692739657 ps |
CPU time | 57.18 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:45:35 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-c370ccf1-240e-4773-81f1-75ef18f841fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544918338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3544918338 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3288734600 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 49280803 ps |
CPU time | 0.79 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:44:38 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-dcfc5bcf-257a-489d-b064-155fd30a4fee |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288734600 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3288734600 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2288299406 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 430305379 ps |
CPU time | 4.37 seconds |
Started | Jul 27 06:44:38 PM PDT 24 |
Finished | Jul 27 06:44:42 PM PDT 24 |
Peak memory | 211192 kb |
Host | smart-a811c435-58a3-4b9c-a462-d4c53330d111 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288299406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.2288299406 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2932927490 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 358337105 ps |
CPU time | 2.27 seconds |
Started | Jul 27 06:44:35 PM PDT 24 |
Finished | Jul 27 06:44:37 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-07752224-b35e-41b5-b113-f2e869d10d9a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932927490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.2932927490 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1682864779 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 1662523355 ps |
CPU time | 3.39 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:44:41 PM PDT 24 |
Peak memory | 212300 kb |
Host | smart-07998b6c-537e-4356-8172-30542db9f4ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682864779 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1682864779 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1737557652 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 17315430 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:44:34 PM PDT 24 |
Finished | Jul 27 06:44:35 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-771154dc-1f70-4053-892c-e5889e0312cd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737557652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.1737557652 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3276163196 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 21741571156 ps |
CPU time | 34.07 seconds |
Started | Jul 27 06:44:38 PM PDT 24 |
Finished | Jul 27 06:45:12 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-7878fca3-1eff-4b5a-ba06-9cf5db8d4d54 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276163196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3276163196 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2957054814 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 65559495 ps |
CPU time | 0.73 seconds |
Started | Jul 27 06:44:38 PM PDT 24 |
Finished | Jul 27 06:44:38 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-e04aa289-79d0-424f-9435-59703f82aa20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957054814 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2957054814 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2251971636 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 191156299 ps |
CPU time | 2.92 seconds |
Started | Jul 27 06:44:37 PM PDT 24 |
Finished | Jul 27 06:44:40 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-8e5c76c1-ab47-4504-bec6-f507d963ec72 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251971636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.2251971636 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1386261791 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 637516800 ps |
CPU time | 2.24 seconds |
Started | Jul 27 06:44:36 PM PDT 24 |
Finished | Jul 27 06:44:39 PM PDT 24 |
Peak memory | 203056 kb |
Host | smart-18918e8e-9d2b-4db4-b73f-e3564c2df22b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386261791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.1386261791 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3825962553 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 65907847900 ps |
CPU time | 924.94 seconds |
Started | Jul 27 06:45:07 PM PDT 24 |
Finished | Jul 27 07:00:32 PM PDT 24 |
Peak memory | 379104 kb |
Host | smart-63a7ba82-826c-4e74-b44d-43c87ccaccac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825962553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.3825962553 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.4251031289 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 36471210 ps |
CPU time | 0.64 seconds |
Started | Jul 27 06:45:05 PM PDT 24 |
Finished | Jul 27 06:45:06 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-f9502691-d9df-422b-9ef4-dbf75468a16f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251031289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.4251031289 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.2038862635 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 448922100492 ps |
CPU time | 2130.22 seconds |
Started | Jul 27 06:45:03 PM PDT 24 |
Finished | Jul 27 07:20:33 PM PDT 24 |
Peak memory | 203360 kb |
Host | smart-70d06323-9711-4e8d-b052-31c7f4ced747 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038862635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 2038862635 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.1001166228 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 13238360879 ps |
CPU time | 758.76 seconds |
Started | Jul 27 06:45:07 PM PDT 24 |
Finished | Jul 27 06:57:46 PM PDT 24 |
Peak memory | 379592 kb |
Host | smart-f4bbe0d8-9d99-47ab-af26-36bc20c90cca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001166228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.1001166228 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.3594624372 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 51290849415 ps |
CPU time | 57.26 seconds |
Started | Jul 27 06:45:07 PM PDT 24 |
Finished | Jul 27 06:46:04 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-171a0469-1f5c-48df-8c0f-93438acc7f86 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594624372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.3594624372 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.2892055511 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 799500156 ps |
CPU time | 74.73 seconds |
Started | Jul 27 06:45:03 PM PDT 24 |
Finished | Jul 27 06:46:18 PM PDT 24 |
Peak memory | 367572 kb |
Host | smart-ddabaad9-c5d9-4953-adb3-011918068434 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892055511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.2892055511 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2438937687 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 1628237419 ps |
CPU time | 121.3 seconds |
Started | Jul 27 06:45:07 PM PDT 24 |
Finished | Jul 27 06:47:08 PM PDT 24 |
Peak memory | 219432 kb |
Host | smart-5aa050ce-91ea-45d1-b46a-ad46372213f1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438937687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.2438937687 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.3031199346 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 86338692514 ps |
CPU time | 317.27 seconds |
Started | Jul 27 06:45:10 PM PDT 24 |
Finished | Jul 27 06:50:27 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-eada6c53-53a7-4c6b-a63e-0461c02d3ad8 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031199346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.3031199346 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.3012728534 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 13498026619 ps |
CPU time | 1140.63 seconds |
Started | Jul 27 06:44:52 PM PDT 24 |
Finished | Jul 27 07:03:53 PM PDT 24 |
Peak memory | 381088 kb |
Host | smart-da57ead6-87c4-4842-ad7e-e3ad67f5cbb6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012728534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.3012728534 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.2704537826 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 716615782 ps |
CPU time | 8.68 seconds |
Started | Jul 27 06:44:53 PM PDT 24 |
Finished | Jul 27 06:45:02 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-de2e9779-29b4-43ec-a58f-5346f909360f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704537826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.2704537826 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1055462773 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 8347038727 ps |
CPU time | 243.68 seconds |
Started | Jul 27 06:44:54 PM PDT 24 |
Finished | Jul 27 06:48:58 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-3f82d491-1b61-4346-865b-18478e7c3c8b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055462773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.1055462773 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.3990553646 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 762545862 ps |
CPU time | 3.16 seconds |
Started | Jul 27 06:45:06 PM PDT 24 |
Finished | Jul 27 06:45:09 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-b783b89c-ace8-4af9-b452-6eff3ddbb108 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990553646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3990553646 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.1628710846 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 557991324 ps |
CPU time | 3.01 seconds |
Started | Jul 27 06:45:08 PM PDT 24 |
Finished | Jul 27 06:45:11 PM PDT 24 |
Peak memory | 222492 kb |
Host | smart-2a7180bd-818b-4e3d-8061-51d6287fa082 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628710846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1628710846 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.1432678337 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 403074753 ps |
CPU time | 20.57 seconds |
Started | Jul 27 06:44:51 PM PDT 24 |
Finished | Jul 27 06:45:12 PM PDT 24 |
Peak memory | 274660 kb |
Host | smart-1a20e0e8-9972-4e46-9116-f251f95e1535 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432678337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1432678337 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.1198732850 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 102233081551 ps |
CPU time | 3982.95 seconds |
Started | Jul 27 06:45:07 PM PDT 24 |
Finished | Jul 27 07:51:30 PM PDT 24 |
Peak memory | 382232 kb |
Host | smart-6d0c0e03-1f61-4df9-9e73-e41f31844591 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198732850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.1198732850 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.16221709 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 1207813683 ps |
CPU time | 31.41 seconds |
Started | Jul 27 06:45:05 PM PDT 24 |
Finished | Jul 27 06:45:36 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-7819ddca-fe6c-4efb-93f1-9a9759205a3a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=16221709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.16221709 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3590036233 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 4339732617 ps |
CPU time | 244.73 seconds |
Started | Jul 27 06:44:53 PM PDT 24 |
Finished | Jul 27 06:48:58 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-327b03fc-46fe-47a8-bd16-34960b0616b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590036233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.3590036233 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.80814594 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 1402226008 ps |
CPU time | 14.57 seconds |
Started | Jul 27 06:44:56 PM PDT 24 |
Finished | Jul 27 06:45:10 PM PDT 24 |
Peak memory | 252024 kb |
Host | smart-77eb227e-5315-4bdd-8e31-92d5f59c4f4a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80814594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.sram_ctrl_throughput_w_partial_write.80814594 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.591760207 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 10468925032 ps |
CPU time | 194.81 seconds |
Started | Jul 27 06:45:05 PM PDT 24 |
Finished | Jul 27 06:48:20 PM PDT 24 |
Peak memory | 329928 kb |
Host | smart-ea7810b2-4999-4ce0-a471-0fbc99a01852 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591760207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.sram_ctrl_access_during_key_req.591760207 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.1006103919 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 153424975577 ps |
CPU time | 2545.95 seconds |
Started | Jul 27 06:45:08 PM PDT 24 |
Finished | Jul 27 07:27:34 PM PDT 24 |
Peak memory | 204004 kb |
Host | smart-1ffbfe13-0fda-4692-a13d-8d9dc93b2416 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006103919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 1006103919 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.1468772477 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 11609084205 ps |
CPU time | 329.86 seconds |
Started | Jul 27 06:45:07 PM PDT 24 |
Finished | Jul 27 06:50:37 PM PDT 24 |
Peak memory | 372980 kb |
Host | smart-60f48a10-be10-4a66-96ea-607745f8dd38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468772477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.1468772477 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.2975686915 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 454452963 ps |
CPU time | 4.04 seconds |
Started | Jul 27 06:45:08 PM PDT 24 |
Finished | Jul 27 06:45:12 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-2d485254-7c0b-44b2-a0e7-9ad2b46b0da2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975686915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.2975686915 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.1805753521 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 1567691658 ps |
CPU time | 53.1 seconds |
Started | Jul 27 06:45:08 PM PDT 24 |
Finished | Jul 27 06:46:01 PM PDT 24 |
Peak memory | 322708 kb |
Host | smart-c0cb7021-8f8e-4981-9bff-120ca04dc1b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805753521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.1805753521 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2895014451 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 5116713136 ps |
CPU time | 145.48 seconds |
Started | Jul 27 06:45:10 PM PDT 24 |
Finished | Jul 27 06:47:36 PM PDT 24 |
Peak memory | 219536 kb |
Host | smart-52d08510-aa78-4b59-99ed-4e17f87ecf4a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895014451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.2895014451 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.3668838069 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 5533709200 ps |
CPU time | 295.63 seconds |
Started | Jul 27 06:45:09 PM PDT 24 |
Finished | Jul 27 06:50:05 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-c9602965-f04b-407d-9754-c36d4510aa84 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668838069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.3668838069 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.2385443375 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 22996609209 ps |
CPU time | 619.67 seconds |
Started | Jul 27 06:45:08 PM PDT 24 |
Finished | Jul 27 06:55:28 PM PDT 24 |
Peak memory | 378280 kb |
Host | smart-fa30ec33-97da-49e5-833f-bc693dde0817 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385443375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.2385443375 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.1211244582 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 1001213197 ps |
CPU time | 23.3 seconds |
Started | Jul 27 06:45:07 PM PDT 24 |
Finished | Jul 27 06:45:30 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-6acee9dd-83e8-4db1-b352-f81729bdd18e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211244582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.1211244582 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.625061224 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 36798208100 ps |
CPU time | 404.52 seconds |
Started | Jul 27 06:45:06 PM PDT 24 |
Finished | Jul 27 06:51:51 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-cea16700-bd57-4291-ae0e-751b41d36e15 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625061224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.sram_ctrl_partial_access_b2b.625061224 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.4080608216 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 27714370683 ps |
CPU time | 901.67 seconds |
Started | Jul 27 06:45:07 PM PDT 24 |
Finished | Jul 27 07:00:09 PM PDT 24 |
Peak memory | 373836 kb |
Host | smart-825852fd-8345-47f3-9feb-841daa8d7402 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080608216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.4080608216 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.3803505339 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 2204739499 ps |
CPU time | 15.54 seconds |
Started | Jul 27 06:45:06 PM PDT 24 |
Finished | Jul 27 06:45:21 PM PDT 24 |
Peak memory | 249408 kb |
Host | smart-4b59e2c8-2a5c-400e-b4b9-fc9a8afcd976 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803505339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3803505339 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.3513973158 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 215821527103 ps |
CPU time | 1865.25 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 07:16:17 PM PDT 24 |
Peak memory | 382184 kb |
Host | smart-5a387b87-9873-422c-93b6-3b6fe67092fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513973158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.3513973158 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1318029261 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 4747641561 ps |
CPU time | 280.54 seconds |
Started | Jul 27 06:45:09 PM PDT 24 |
Finished | Jul 27 06:49:50 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-43c77b0c-8f5b-4302-a3eb-22204ed5af97 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318029261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1318029261 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.768087082 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 3413726624 ps |
CPU time | 51.68 seconds |
Started | Jul 27 06:45:06 PM PDT 24 |
Finished | Jul 27 06:45:57 PM PDT 24 |
Peak memory | 320808 kb |
Host | smart-2770fc13-865c-4525-932e-e8f76668c80f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768087082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.768087082 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2058167349 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 20262844689 ps |
CPU time | 1719.41 seconds |
Started | Jul 27 06:46:05 PM PDT 24 |
Finished | Jul 27 07:14:44 PM PDT 24 |
Peak memory | 378160 kb |
Host | smart-f0efde5e-ebe9-40c8-a11e-8222cb1bedca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058167349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.2058167349 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.272540731 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 41024003 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:46:00 PM PDT 24 |
Finished | Jul 27 06:46:01 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-73ca5c08-a08b-497f-a8c5-3ab3c9687d93 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272540731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.272540731 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.165969425 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 32154806543 ps |
CPU time | 2218.67 seconds |
Started | Jul 27 06:45:58 PM PDT 24 |
Finished | Jul 27 07:22:57 PM PDT 24 |
Peak memory | 204048 kb |
Host | smart-9cb2ad83-f086-4a0f-86ec-749ee47e2fb4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165969425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection. 165969425 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.1538693976 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 49330504331 ps |
CPU time | 1126.16 seconds |
Started | Jul 27 06:45:59 PM PDT 24 |
Finished | Jul 27 07:04:45 PM PDT 24 |
Peak memory | 378112 kb |
Host | smart-3fbddad3-ed75-43f9-99a8-e07185a3f851 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538693976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.1538693976 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.2962151415 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 141085465643 ps |
CPU time | 61.58 seconds |
Started | Jul 27 06:46:01 PM PDT 24 |
Finished | Jul 27 06:47:03 PM PDT 24 |
Peak memory | 211308 kb |
Host | smart-165b3813-f923-4cfe-af57-d0b60aa6f6db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962151415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.2962151415 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.3034896896 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 726031310 ps |
CPU time | 10.84 seconds |
Started | Jul 27 06:46:01 PM PDT 24 |
Finished | Jul 27 06:46:12 PM PDT 24 |
Peak memory | 235768 kb |
Host | smart-e7b682fa-d6f4-4333-98e3-dacb5d75963e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034896896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.3034896896 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.94046414 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 10910718835 ps |
CPU time | 88.96 seconds |
Started | Jul 27 06:46:01 PM PDT 24 |
Finished | Jul 27 06:47:30 PM PDT 24 |
Peak memory | 211356 kb |
Host | smart-a476b80a-5251-4d98-9258-f320cc3e9f8e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94046414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_mem_partial_access.94046414 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.2180242033 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 163379428808 ps |
CPU time | 387.09 seconds |
Started | Jul 27 06:45:59 PM PDT 24 |
Finished | Jul 27 06:52:26 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-808a4d15-35d5-4225-91ec-42a7236b865d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180242033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.2180242033 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.408829899 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 37160412330 ps |
CPU time | 872.22 seconds |
Started | Jul 27 06:45:59 PM PDT 24 |
Finished | Jul 27 07:00:31 PM PDT 24 |
Peak memory | 378024 kb |
Host | smart-28a7229d-bd46-486b-9865-3c97954b4319 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408829899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip le_keys.408829899 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.7531973 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 3694539782 ps |
CPU time | 117.38 seconds |
Started | Jul 27 06:45:58 PM PDT 24 |
Finished | Jul 27 06:47:56 PM PDT 24 |
Peak memory | 369784 kb |
Host | smart-ad079b79-c8e5-427e-b9d8-e20cd878da77 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7531973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sra m_ctrl_partial_access.7531973 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2499252179 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 57803950372 ps |
CPU time | 424.07 seconds |
Started | Jul 27 06:46:05 PM PDT 24 |
Finished | Jul 27 06:53:09 PM PDT 24 |
Peak memory | 203296 kb |
Host | smart-fb866a31-7728-495f-adda-288933367892 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499252179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.2499252179 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.368327472 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 356403034 ps |
CPU time | 3.05 seconds |
Started | Jul 27 06:45:58 PM PDT 24 |
Finished | Jul 27 06:46:01 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-3241006f-870c-4dcc-8562-34678a08b193 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368327472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.368327472 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.3331689684 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 49950385867 ps |
CPU time | 655.54 seconds |
Started | Jul 27 06:46:00 PM PDT 24 |
Finished | Jul 27 06:56:55 PM PDT 24 |
Peak memory | 378060 kb |
Host | smart-ed360c47-4647-45b5-8e7f-9eb635591a2b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331689684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3331689684 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.3305218855 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 2909136385 ps |
CPU time | 11.53 seconds |
Started | Jul 27 06:45:58 PM PDT 24 |
Finished | Jul 27 06:46:10 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-08562ea7-16d8-4f08-bdaf-cd4effbd4e33 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305218855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3305218855 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.3188214793 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 475836795410 ps |
CPU time | 3135.65 seconds |
Started | Jul 27 06:46:01 PM PDT 24 |
Finished | Jul 27 07:38:17 PM PDT 24 |
Peak memory | 366684 kb |
Host | smart-46ad35f6-11cb-4050-bf2f-2c87a56d5467 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188214793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.3188214793 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1870691811 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 6704191511 ps |
CPU time | 83.72 seconds |
Started | Jul 27 06:46:01 PM PDT 24 |
Finished | Jul 27 06:47:25 PM PDT 24 |
Peak memory | 337216 kb |
Host | smart-7f7e33ab-8016-44b2-8653-40ad731df31f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1870691811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1870691811 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3625897591 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 13626035297 ps |
CPU time | 188.23 seconds |
Started | Jul 27 06:46:05 PM PDT 24 |
Finished | Jul 27 06:49:13 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-2172a21c-fbd2-4a5c-82cd-3c56b39f3d8d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625897591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.3625897591 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3873766791 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 3369823482 ps |
CPU time | 74.89 seconds |
Started | Jul 27 06:45:57 PM PDT 24 |
Finished | Jul 27 06:47:12 PM PDT 24 |
Peak memory | 359708 kb |
Host | smart-faf1d307-4a1e-46be-90df-417928c8e7e7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873766791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.3873766791 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3634711130 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 10414495466 ps |
CPU time | 374.96 seconds |
Started | Jul 27 06:46:06 PM PDT 24 |
Finished | Jul 27 06:52:21 PM PDT 24 |
Peak memory | 368776 kb |
Host | smart-0f55bbfc-ab88-4347-8d8b-52dfb49996ff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634711130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3634711130 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.2725822350 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 15033881 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:46:10 PM PDT 24 |
Finished | Jul 27 06:46:10 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-b1356bd8-6886-4a26-9ba9-7e3de754ae93 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725822350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.2725822350 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.3312746465 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 300610109805 ps |
CPU time | 847.17 seconds |
Started | Jul 27 06:45:58 PM PDT 24 |
Finished | Jul 27 07:00:05 PM PDT 24 |
Peak memory | 203992 kb |
Host | smart-b5cb9d9b-1f5c-4fd0-92b7-0ff674a33c53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312746465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .3312746465 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.2621995843 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 32812815919 ps |
CPU time | 1044.25 seconds |
Started | Jul 27 06:46:07 PM PDT 24 |
Finished | Jul 27 07:03:32 PM PDT 24 |
Peak memory | 380064 kb |
Host | smart-760aa0d4-ef42-4389-b028-a5852457811d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621995843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.2621995843 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.4287716355 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 13489664817 ps |
CPU time | 65.55 seconds |
Started | Jul 27 06:46:07 PM PDT 24 |
Finished | Jul 27 06:47:13 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-c6bd1b0d-00df-47ae-9062-452cd7679bf4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287716355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.4287716355 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.2968129231 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 1436892039 ps |
CPU time | 21.7 seconds |
Started | Jul 27 06:45:58 PM PDT 24 |
Finished | Jul 27 06:46:20 PM PDT 24 |
Peak memory | 268444 kb |
Host | smart-b4aafb26-c84d-46d9-8cf9-94e4ba788c51 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968129231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.2968129231 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2314110270 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 20402831543 ps |
CPU time | 164.82 seconds |
Started | Jul 27 06:46:08 PM PDT 24 |
Finished | Jul 27 06:48:53 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-13be2b8b-2804-450d-9fd4-60eb948df12f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314110270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.2314110270 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.14874129 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 5980430365 ps |
CPU time | 152.01 seconds |
Started | Jul 27 06:46:07 PM PDT 24 |
Finished | Jul 27 06:48:39 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-9e3c1e45-ed52-4b81-b6c6-5469e72772cc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14874129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ mem_walk.14874129 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.4041571290 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 9241317538 ps |
CPU time | 521.88 seconds |
Started | Jul 27 06:45:59 PM PDT 24 |
Finished | Jul 27 06:54:41 PM PDT 24 |
Peak memory | 373104 kb |
Host | smart-7389a05a-80bc-4e5e-8d25-2eb70ed5131c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041571290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.4041571290 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.716364430 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 817968754 ps |
CPU time | 83.48 seconds |
Started | Jul 27 06:46:02 PM PDT 24 |
Finished | Jul 27 06:47:26 PM PDT 24 |
Peak memory | 340056 kb |
Host | smart-b100f210-5309-4bf4-b3e8-c39ba3fb3399 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716364430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.s ram_ctrl_partial_access.716364430 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.3036545852 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 351464078 ps |
CPU time | 3.38 seconds |
Started | Jul 27 06:46:07 PM PDT 24 |
Finished | Jul 27 06:46:10 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-77f5cfc2-4ce1-4af5-ba06-c3483ac19841 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036545852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3036545852 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.2652304448 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 20352168972 ps |
CPU time | 693.13 seconds |
Started | Jul 27 06:46:08 PM PDT 24 |
Finished | Jul 27 06:57:42 PM PDT 24 |
Peak memory | 373924 kb |
Host | smart-0450bb52-b453-40b1-891b-e6f7f78ed968 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652304448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2652304448 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.2817053378 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 3147184637 ps |
CPU time | 12.5 seconds |
Started | Jul 27 06:45:58 PM PDT 24 |
Finished | Jul 27 06:46:11 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-bb6d5550-4923-4ca5-b220-f07ac27fffa7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817053378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2817053378 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.898165311 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 73651785429 ps |
CPU time | 2746.25 seconds |
Started | Jul 27 06:46:08 PM PDT 24 |
Finished | Jul 27 07:31:54 PM PDT 24 |
Peak memory | 383168 kb |
Host | smart-e5e9b830-d51f-4455-90ca-8414611090a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898165311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_stress_all.898165311 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3592840705 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 9364287260 ps |
CPU time | 64.56 seconds |
Started | Jul 27 06:46:09 PM PDT 24 |
Finished | Jul 27 06:47:14 PM PDT 24 |
Peak memory | 227740 kb |
Host | smart-7906ded5-df61-4a4a-a930-4d75fd2c2520 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3592840705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3592840705 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1272892765 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 84469240528 ps |
CPU time | 356.27 seconds |
Started | Jul 27 06:45:59 PM PDT 24 |
Finished | Jul 27 06:51:55 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-d0d56c9d-58fe-4396-b3d0-b9cb86b95048 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272892765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.1272892765 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4177243720 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 800582703 ps |
CPU time | 73.23 seconds |
Started | Jul 27 06:46:07 PM PDT 24 |
Finished | Jul 27 06:47:21 PM PDT 24 |
Peak memory | 352396 kb |
Host | smart-6e1066ab-1034-47b6-a569-30a43f350e08 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177243720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.4177243720 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.406474528 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 271401535842 ps |
CPU time | 1128.2 seconds |
Started | Jul 27 06:46:17 PM PDT 24 |
Finished | Jul 27 07:05:05 PM PDT 24 |
Peak memory | 377944 kb |
Host | smart-4394b8f0-4218-47de-b023-421aec620469 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406474528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_access_during_key_req.406474528 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.404554399 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 18382612 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:46:16 PM PDT 24 |
Finished | Jul 27 06:46:17 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-fffef0cf-5f68-4eb5-b43b-87e29ccdcd33 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404554399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.404554399 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.2726659759 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 99869279536 ps |
CPU time | 1675.17 seconds |
Started | Jul 27 06:46:10 PM PDT 24 |
Finished | Jul 27 07:14:06 PM PDT 24 |
Peak memory | 203756 kb |
Host | smart-5d203263-aa05-4ade-93b9-e2d26f3bc74e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726659759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .2726659759 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.3985703560 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 8826179627 ps |
CPU time | 375 seconds |
Started | Jul 27 06:46:16 PM PDT 24 |
Finished | Jul 27 06:52:31 PM PDT 24 |
Peak memory | 368844 kb |
Host | smart-8853ab0d-29ca-4a0a-8b9e-7ce1afbdf3e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985703560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.3985703560 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.3658514559 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 6410723136 ps |
CPU time | 42.39 seconds |
Started | Jul 27 06:46:18 PM PDT 24 |
Finished | Jul 27 06:47:00 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-4706aaad-c8f7-4db5-8642-e08450d1907d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658514559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.3658514559 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.1649521156 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 1435155636 ps |
CPU time | 22.48 seconds |
Started | Jul 27 06:46:19 PM PDT 24 |
Finished | Jul 27 06:46:42 PM PDT 24 |
Peak memory | 268568 kb |
Host | smart-59d31105-5501-4893-bebb-d714f417a9f0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649521156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.1649521156 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3188151343 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 15780569899 ps |
CPU time | 86.19 seconds |
Started | Jul 27 06:46:19 PM PDT 24 |
Finished | Jul 27 06:47:45 PM PDT 24 |
Peak memory | 219624 kb |
Host | smart-8617e2b0-8e19-4887-9314-e00c64018bdc |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188151343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.3188151343 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.375113881 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 9370817613 ps |
CPU time | 165.67 seconds |
Started | Jul 27 06:46:18 PM PDT 24 |
Finished | Jul 27 06:49:04 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-9b2fa081-7cca-45b9-9054-e398ff02b100 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375113881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _mem_walk.375113881 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.1113765671 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 24613428991 ps |
CPU time | 438.78 seconds |
Started | Jul 27 06:46:14 PM PDT 24 |
Finished | Jul 27 06:53:33 PM PDT 24 |
Peak memory | 345260 kb |
Host | smart-c524a4c4-a9d7-42a8-ba46-4aa4f4513e59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113765671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.1113765671 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.2989033114 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 2283753969 ps |
CPU time | 19.48 seconds |
Started | Jul 27 06:46:17 PM PDT 24 |
Finished | Jul 27 06:46:36 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-49a636e1-cc39-4292-9a79-e47cb13df550 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989033114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.2989033114 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3699173421 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 38576441185 ps |
CPU time | 244.23 seconds |
Started | Jul 27 06:46:16 PM PDT 24 |
Finished | Jul 27 06:50:20 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-69d729df-e548-4d08-8f66-1247610e49ee |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699173421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.3699173421 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.448856747 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 631373187 ps |
CPU time | 3.36 seconds |
Started | Jul 27 06:46:16 PM PDT 24 |
Finished | Jul 27 06:46:20 PM PDT 24 |
Peak memory | 203064 kb |
Host | smart-1440a1af-3302-4eba-bc14-06bbc096c153 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448856747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.448856747 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.3176995243 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 7072287363 ps |
CPU time | 775.5 seconds |
Started | Jul 27 06:46:19 PM PDT 24 |
Finished | Jul 27 06:59:14 PM PDT 24 |
Peak memory | 363852 kb |
Host | smart-898a5053-df83-48ee-b298-5da9cc027588 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176995243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3176995243 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.3644955591 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 1877840182 ps |
CPU time | 11.04 seconds |
Started | Jul 27 06:46:08 PM PDT 24 |
Finished | Jul 27 06:46:19 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-9a37ee5c-f910-4853-9d50-874fa5079cec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644955591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3644955591 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.638290706 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 311321739478 ps |
CPU time | 4128.87 seconds |
Started | Jul 27 06:46:19 PM PDT 24 |
Finished | Jul 27 07:55:08 PM PDT 24 |
Peak memory | 379204 kb |
Host | smart-c0ddd142-ac5e-4571-a803-4f695e12fb8f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638290706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_stress_all.638290706 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1907859774 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 1352796437 ps |
CPU time | 11.3 seconds |
Started | Jul 27 06:46:16 PM PDT 24 |
Finished | Jul 27 06:46:27 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-fc5e6def-9034-410c-a506-5bd5eda4ba87 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1907859774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1907859774 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3831187106 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 5331132129 ps |
CPU time | 296.46 seconds |
Started | Jul 27 06:46:19 PM PDT 24 |
Finished | Jul 27 06:51:16 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-b158da51-cf02-4b0d-a3c2-e8c527bfbcec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831187106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.3831187106 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.109564478 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 3402843674 ps |
CPU time | 26.98 seconds |
Started | Jul 27 06:46:17 PM PDT 24 |
Finished | Jul 27 06:46:44 PM PDT 24 |
Peak memory | 274940 kb |
Host | smart-626e744e-69b0-4d3c-bed8-0717889c13b4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109564478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.109564478 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.103132821 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 21636205971 ps |
CPU time | 1866.53 seconds |
Started | Jul 27 06:46:24 PM PDT 24 |
Finished | Jul 27 07:17:31 PM PDT 24 |
Peak memory | 381276 kb |
Host | smart-2660aaa9-8cc4-4da2-b1e8-35b76cff72b3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103132821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 13.sram_ctrl_access_during_key_req.103132821 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.3707216884 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 27828904 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:46:33 PM PDT 24 |
Finished | Jul 27 06:46:34 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-9fad7e6a-8042-4cb9-84b9-bba666a268dd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707216884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3707216884 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.2286258455 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 34165790132 ps |
CPU time | 576.94 seconds |
Started | Jul 27 06:46:15 PM PDT 24 |
Finished | Jul 27 06:55:52 PM PDT 24 |
Peak memory | 203768 kb |
Host | smart-c1e070a1-48e3-4cea-9dba-24d036d5935f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286258455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .2286258455 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.3224788067 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 25221851380 ps |
CPU time | 496.14 seconds |
Started | Jul 27 06:46:23 PM PDT 24 |
Finished | Jul 27 06:54:39 PM PDT 24 |
Peak memory | 370960 kb |
Host | smart-c474a0d8-661c-4899-a271-2769bc195110 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224788067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.3224788067 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.2317326798 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 5215497904 ps |
CPU time | 30.12 seconds |
Started | Jul 27 06:46:24 PM PDT 24 |
Finished | Jul 27 06:46:54 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-4813fd60-725b-45ee-9e4c-3b27ea2727ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317326798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.2317326798 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.1376182766 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 5778321666 ps |
CPU time | 77.98 seconds |
Started | Jul 27 06:46:26 PM PDT 24 |
Finished | Jul 27 06:47:45 PM PDT 24 |
Peak memory | 354492 kb |
Host | smart-48111578-fca2-470b-b7af-930a5156e5cc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376182766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.1376182766 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2139827397 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 4959768091 ps |
CPU time | 142.22 seconds |
Started | Jul 27 06:46:25 PM PDT 24 |
Finished | Jul 27 06:48:48 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-f7aee509-49d0-4673-8a7f-27e5e5024398 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139827397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.2139827397 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.4170934804 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 5254308286 ps |
CPU time | 295.51 seconds |
Started | Jul 27 06:46:25 PM PDT 24 |
Finished | Jul 27 06:51:20 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-b5fa45c6-3cff-429a-8635-fea3416cd301 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170934804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.4170934804 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.3657752409 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 22336452238 ps |
CPU time | 1235.61 seconds |
Started | Jul 27 06:46:16 PM PDT 24 |
Finished | Jul 27 07:06:52 PM PDT 24 |
Peak memory | 376980 kb |
Host | smart-088726d9-bafb-4ff0-8c67-1ceed6cdfe77 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657752409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.3657752409 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.2128214933 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 8145791088 ps |
CPU time | 21.89 seconds |
Started | Jul 27 06:46:16 PM PDT 24 |
Finished | Jul 27 06:46:38 PM PDT 24 |
Peak memory | 262556 kb |
Host | smart-40fa0ee5-5319-46b3-913e-f0fcb6d755f8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128214933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.2128214933 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3871857494 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 29230351464 ps |
CPU time | 418.04 seconds |
Started | Jul 27 06:46:24 PM PDT 24 |
Finished | Jul 27 06:53:22 PM PDT 24 |
Peak memory | 203424 kb |
Host | smart-d6c4517e-fd37-44cc-9557-a12f5efa5b07 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871857494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.3871857494 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.186526584 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 1404573544 ps |
CPU time | 3.49 seconds |
Started | Jul 27 06:46:25 PM PDT 24 |
Finished | Jul 27 06:46:29 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-e4250abb-9a38-47cb-b63d-32ed8b8fcac3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186526584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.186526584 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.3679634476 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 77139453517 ps |
CPU time | 966.44 seconds |
Started | Jul 27 06:46:25 PM PDT 24 |
Finished | Jul 27 07:02:32 PM PDT 24 |
Peak memory | 380044 kb |
Host | smart-d8018233-04f9-4b23-992a-11f2ee489dc5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679634476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3679634476 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.212995371 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 5831724302 ps |
CPU time | 22.94 seconds |
Started | Jul 27 06:46:17 PM PDT 24 |
Finished | Jul 27 06:46:40 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-3557b09d-3066-4ee4-9a4c-1ef1ed310ff4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212995371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.212995371 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.1859591863 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 411503756505 ps |
CPU time | 5607.89 seconds |
Started | Jul 27 06:46:25 PM PDT 24 |
Finished | Jul 27 08:19:53 PM PDT 24 |
Peak memory | 382180 kb |
Host | smart-c0c04e1a-2792-4490-b9d7-36f1006d83ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859591863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.1859591863 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1661224704 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 3331216044 ps |
CPU time | 61.38 seconds |
Started | Jul 27 06:46:25 PM PDT 24 |
Finished | Jul 27 06:47:26 PM PDT 24 |
Peak memory | 302400 kb |
Host | smart-63b53613-e55d-47c6-8f2e-be61d44a16d8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1661224704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1661224704 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2590743525 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 6335403179 ps |
CPU time | 134.54 seconds |
Started | Jul 27 06:46:15 PM PDT 24 |
Finished | Jul 27 06:48:29 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-8f45e663-fc1f-43c7-9622-f1d55b755858 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590743525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.2590743525 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1764740709 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 11175961350 ps |
CPU time | 124.68 seconds |
Started | Jul 27 06:46:24 PM PDT 24 |
Finished | Jul 27 06:48:29 PM PDT 24 |
Peak memory | 371168 kb |
Host | smart-12d27d7b-69bc-4d9c-a096-bce02f7058d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764740709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1764740709 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1877061188 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 10722451163 ps |
CPU time | 720.49 seconds |
Started | Jul 27 06:46:45 PM PDT 24 |
Finished | Jul 27 06:58:45 PM PDT 24 |
Peak memory | 379012 kb |
Host | smart-1d383538-5e02-4997-a4c7-a858d247c76e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877061188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.1877061188 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.441503091 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 11825295 ps |
CPU time | 0.63 seconds |
Started | Jul 27 06:46:43 PM PDT 24 |
Finished | Jul 27 06:46:44 PM PDT 24 |
Peak memory | 202412 kb |
Host | smart-3389e57e-2537-41f7-ab43-22ec019e14bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441503091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.441503091 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.269579434 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 689636475693 ps |
CPU time | 2764.71 seconds |
Started | Jul 27 06:46:32 PM PDT 24 |
Finished | Jul 27 07:32:37 PM PDT 24 |
Peak memory | 203696 kb |
Host | smart-7ea0f669-4584-4952-bcb3-b563cfa43f20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269579434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection. 269579434 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.3914934489 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 9479137648 ps |
CPU time | 959.35 seconds |
Started | Jul 27 06:46:43 PM PDT 24 |
Finished | Jul 27 07:02:43 PM PDT 24 |
Peak memory | 379052 kb |
Host | smart-d105be35-06a2-454e-a057-a8ec3533c3e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914934489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.3914934489 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.379060257 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 10475519096 ps |
CPU time | 62.44 seconds |
Started | Jul 27 06:46:33 PM PDT 24 |
Finished | Jul 27 06:47:36 PM PDT 24 |
Peak memory | 216492 kb |
Host | smart-44e45105-e014-498c-89b1-4f8cea06a620 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379060257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_esc alation.379060257 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.1748471746 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 2971143335 ps |
CPU time | 55.28 seconds |
Started | Jul 27 06:46:32 PM PDT 24 |
Finished | Jul 27 06:47:28 PM PDT 24 |
Peak memory | 334020 kb |
Host | smart-8dad4c5e-bc55-4ed0-b775-db40bb749541 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748471746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.1748471746 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1780554370 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 2627173456 ps |
CPU time | 83.37 seconds |
Started | Jul 27 06:46:43 PM PDT 24 |
Finished | Jul 27 06:48:07 PM PDT 24 |
Peak memory | 219480 kb |
Host | smart-e5872296-2891-45c5-80ac-4147f531a55a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780554370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.1780554370 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.1849969220 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 51207942953 ps |
CPU time | 338.42 seconds |
Started | Jul 27 06:46:44 PM PDT 24 |
Finished | Jul 27 06:52:22 PM PDT 24 |
Peak memory | 212648 kb |
Host | smart-ee3eca37-4cbd-48ae-8cd2-b2d6d018d07d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849969220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.1849969220 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.1768634585 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 116404948370 ps |
CPU time | 1427.76 seconds |
Started | Jul 27 06:46:35 PM PDT 24 |
Finished | Jul 27 07:10:23 PM PDT 24 |
Peak memory | 375928 kb |
Host | smart-96c2019b-6fa3-4053-b1e6-69963ea57b7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768634585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.1768634585 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.3513010933 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 1973738167 ps |
CPU time | 94.24 seconds |
Started | Jul 27 06:46:33 PM PDT 24 |
Finished | Jul 27 06:48:08 PM PDT 24 |
Peak memory | 343196 kb |
Host | smart-ec8a80db-c75b-4b52-af90-ba176d5016f0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513010933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.3513010933 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.4052531968 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 10978942776 ps |
CPU time | 326.19 seconds |
Started | Jul 27 06:46:33 PM PDT 24 |
Finished | Jul 27 06:51:59 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-d75e5638-630d-4ecf-9ca5-10b544e6310d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052531968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.4052531968 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.514742308 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 1491891060 ps |
CPU time | 3.37 seconds |
Started | Jul 27 06:46:44 PM PDT 24 |
Finished | Jul 27 06:46:47 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-d1861a93-b5c5-4ab7-ba95-ab8437337680 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514742308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.514742308 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.4048615559 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 1825573503 ps |
CPU time | 478.3 seconds |
Started | Jul 27 06:46:43 PM PDT 24 |
Finished | Jul 27 06:54:41 PM PDT 24 |
Peak memory | 377840 kb |
Host | smart-07728477-1b9c-4a94-845c-106b75d25744 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048615559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.4048615559 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.4159864441 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 994683980 ps |
CPU time | 17.74 seconds |
Started | Jul 27 06:46:33 PM PDT 24 |
Finished | Jul 27 06:46:51 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-2c5967c7-68c0-4e0c-97cb-d4561b547441 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159864441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.4159864441 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.4202548727 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 1112846420965 ps |
CPU time | 6613.66 seconds |
Started | Jul 27 06:46:45 PM PDT 24 |
Finished | Jul 27 08:36:59 PM PDT 24 |
Peak memory | 381108 kb |
Host | smart-df8aec82-5ad0-48fc-b098-8467fabb6005 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202548727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.4202548727 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2017049472 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 1868761047 ps |
CPU time | 18.22 seconds |
Started | Jul 27 06:46:45 PM PDT 24 |
Finished | Jul 27 06:47:04 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-0452d0e3-11d3-4660-8e7a-9efe3c90c315 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2017049472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.2017049472 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1420756038 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 3891231979 ps |
CPU time | 158.82 seconds |
Started | Jul 27 06:46:35 PM PDT 24 |
Finished | Jul 27 06:49:14 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-6230315d-cc05-4892-8859-3bfd766fe5fc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420756038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.1420756038 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4068438643 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 1573224924 ps |
CPU time | 64.99 seconds |
Started | Jul 27 06:46:36 PM PDT 24 |
Finished | Jul 27 06:47:41 PM PDT 24 |
Peak memory | 349264 kb |
Host | smart-3b1f1ab4-e574-4f86-b6c4-e790fd7d75fe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068438643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.4068438643 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1484967011 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 11966501388 ps |
CPU time | 957.72 seconds |
Started | Jul 27 06:46:44 PM PDT 24 |
Finished | Jul 27 07:02:42 PM PDT 24 |
Peak memory | 377008 kb |
Host | smart-ff0fb88a-2e48-410b-9fae-0d589fed5ba1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484967011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.1484967011 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.95609380 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 14091813 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:46:52 PM PDT 24 |
Finished | Jul 27 06:46:53 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-74c97b09-ab36-4068-9cd6-f71cbb9b6200 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95609380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_alert_test.95609380 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.2475586524 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 66272818351 ps |
CPU time | 2383.07 seconds |
Started | Jul 27 06:46:45 PM PDT 24 |
Finished | Jul 27 07:26:29 PM PDT 24 |
Peak memory | 203468 kb |
Host | smart-2a6dd27f-a26e-423e-889e-d89a20c4a40f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475586524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .2475586524 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.2525750183 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 35124080992 ps |
CPU time | 941.25 seconds |
Started | Jul 27 06:46:45 PM PDT 24 |
Finished | Jul 27 07:02:27 PM PDT 24 |
Peak memory | 370920 kb |
Host | smart-5704a9ee-d272-4e47-8a6e-4b92008f78b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525750183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.2525750183 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.4187681829 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 35307811462 ps |
CPU time | 80.54 seconds |
Started | Jul 27 06:46:45 PM PDT 24 |
Finished | Jul 27 06:48:05 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-81a340e2-f081-4f97-b47e-e8c716f0a71d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187681829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.4187681829 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.1840343370 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 1503707943 ps |
CPU time | 78.86 seconds |
Started | Jul 27 06:46:43 PM PDT 24 |
Finished | Jul 27 06:48:02 PM PDT 24 |
Peak memory | 370792 kb |
Host | smart-8c70ead1-54f9-4e0e-9101-51ae1c31ba63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840343370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.1840343370 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.179902193 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 2445349371 ps |
CPU time | 141.12 seconds |
Started | Jul 27 06:46:55 PM PDT 24 |
Finished | Jul 27 06:49:16 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-1b139238-e70c-47d5-af44-bcdb95c748fa |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179902193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_mem_partial_access.179902193 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.4251038642 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 21912476045 ps |
CPU time | 126.93 seconds |
Started | Jul 27 06:46:55 PM PDT 24 |
Finished | Jul 27 06:49:02 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-5607d07d-d5c0-4979-908d-7dcbb378ade1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251038642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.4251038642 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.608491826 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 10509242160 ps |
CPU time | 1518.78 seconds |
Started | Jul 27 06:46:43 PM PDT 24 |
Finished | Jul 27 07:12:02 PM PDT 24 |
Peak memory | 380060 kb |
Host | smart-7efdc886-c34a-407b-ba68-26ba89ac4eec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608491826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip le_keys.608491826 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.3771160005 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 1113334521 ps |
CPU time | 18.06 seconds |
Started | Jul 27 06:46:44 PM PDT 24 |
Finished | Jul 27 06:47:02 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-70917ea2-3103-4735-aa27-6ee2e3b1c4b5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771160005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.3771160005 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.714648710 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 5751899858 ps |
CPU time | 302.2 seconds |
Started | Jul 27 06:46:44 PM PDT 24 |
Finished | Jul 27 06:51:47 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-6e0339cf-0d9d-429f-a13e-fe39c4b33fc9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714648710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.sram_ctrl_partial_access_b2b.714648710 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.1750799882 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 998999065 ps |
CPU time | 3.51 seconds |
Started | Jul 27 06:46:51 PM PDT 24 |
Finished | Jul 27 06:46:55 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-57c2a570-5cdd-4b70-8d8b-2d103c9d7d41 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750799882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1750799882 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.214023074 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 949211271 ps |
CPU time | 31.45 seconds |
Started | Jul 27 06:46:42 PM PDT 24 |
Finished | Jul 27 06:47:14 PM PDT 24 |
Peak memory | 242568 kb |
Host | smart-89e4a810-c210-4987-8453-96f2a937b8a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214023074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.214023074 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.1618976802 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 4351922356 ps |
CPU time | 4.69 seconds |
Started | Jul 27 06:46:43 PM PDT 24 |
Finished | Jul 27 06:46:48 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-bf9d0ab8-b066-4c2a-afd0-0a3d174e5c21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618976802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1618976802 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.401028054 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 129552516751 ps |
CPU time | 4705.11 seconds |
Started | Jul 27 06:46:52 PM PDT 24 |
Finished | Jul 27 08:05:18 PM PDT 24 |
Peak memory | 382444 kb |
Host | smart-c9467faa-34b3-475b-ba31-4d105a4865ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401028054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_stress_all.401028054 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1606962931 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 3143616840 ps |
CPU time | 184.11 seconds |
Started | Jul 27 06:46:52 PM PDT 24 |
Finished | Jul 27 06:49:57 PM PDT 24 |
Peak memory | 362676 kb |
Host | smart-94cd0185-1ff4-4e75-b870-6d68e07f0893 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1606962931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.1606962931 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3599804776 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 8016407684 ps |
CPU time | 171.04 seconds |
Started | Jul 27 06:46:45 PM PDT 24 |
Finished | Jul 27 06:49:37 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-7efb340d-155f-40df-8a2a-269a97850897 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599804776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.3599804776 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1294980168 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 2951486028 ps |
CPU time | 18.47 seconds |
Started | Jul 27 06:46:45 PM PDT 24 |
Finished | Jul 27 06:47:04 PM PDT 24 |
Peak memory | 259652 kb |
Host | smart-a0f9b90a-e9fe-425e-9b84-5012bcfc4b88 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294980168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.1294980168 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.4080640274 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 38261782852 ps |
CPU time | 574.39 seconds |
Started | Jul 27 06:46:54 PM PDT 24 |
Finished | Jul 27 06:56:28 PM PDT 24 |
Peak memory | 381104 kb |
Host | smart-2b6f730e-b287-465c-a799-52c1b061b82e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080640274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.4080640274 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.2495482236 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 23055293 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:47:04 PM PDT 24 |
Finished | Jul 27 06:47:05 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-bfe7d41f-95ac-4eb1-a304-7186b0061f76 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495482236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.2495482236 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.2648970316 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 573200345301 ps |
CPU time | 2594.19 seconds |
Started | Jul 27 06:46:52 PM PDT 24 |
Finished | Jul 27 07:30:07 PM PDT 24 |
Peak memory | 203800 kb |
Host | smart-7f6b1836-78dc-484c-8512-eba6274ca435 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648970316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .2648970316 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.4117014132 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 242998078569 ps |
CPU time | 1351.28 seconds |
Started | Jul 27 06:47:02 PM PDT 24 |
Finished | Jul 27 07:09:33 PM PDT 24 |
Peak memory | 373972 kb |
Host | smart-3ae44cd5-e181-4bfa-a2a7-be4561efa15e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117014132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.4117014132 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.3132301521 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 26702918361 ps |
CPU time | 87.32 seconds |
Started | Jul 27 06:46:54 PM PDT 24 |
Finished | Jul 27 06:48:22 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-d9c3a7a8-250b-4fbc-9d15-35e5551de6b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132301521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.3132301521 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.2195975955 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 786978365 ps |
CPU time | 59.38 seconds |
Started | Jul 27 06:46:52 PM PDT 24 |
Finished | Jul 27 06:47:51 PM PDT 24 |
Peak memory | 323780 kb |
Host | smart-c4dc05f5-d43e-42ff-8328-820888abfc09 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195975955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.2195975955 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.2632926135 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 1010711469 ps |
CPU time | 62.23 seconds |
Started | Jul 27 06:47:02 PM PDT 24 |
Finished | Jul 27 06:48:04 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-42484a72-fd62-49cc-8343-9930203799b6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632926135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.2632926135 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.2749874265 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 1976701750 ps |
CPU time | 123.77 seconds |
Started | Jul 27 06:47:01 PM PDT 24 |
Finished | Jul 27 06:49:05 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-4e414efe-3479-4c0e-85f8-887cbaa6a418 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749874265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.2749874265 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.2170394345 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 13610340067 ps |
CPU time | 178.32 seconds |
Started | Jul 27 06:46:53 PM PDT 24 |
Finished | Jul 27 06:49:51 PM PDT 24 |
Peak memory | 300008 kb |
Host | smart-8168a744-01a2-4563-85b6-3ec8a4451055 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170394345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.2170394345 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.937866005 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 3381207521 ps |
CPU time | 15.9 seconds |
Started | Jul 27 06:46:54 PM PDT 24 |
Finished | Jul 27 06:47:10 PM PDT 24 |
Peak memory | 236896 kb |
Host | smart-5f62c1a1-f0f0-442a-840c-93964f9be6e5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937866005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_partial_access.937866005 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3622591410 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 17561349138 ps |
CPU time | 425.98 seconds |
Started | Jul 27 06:46:52 PM PDT 24 |
Finished | Jul 27 06:53:58 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-ac096b76-dfa5-4947-aed9-8d710e2e4767 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622591410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.3622591410 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.4029587394 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 1346784443 ps |
CPU time | 3.3 seconds |
Started | Jul 27 06:47:02 PM PDT 24 |
Finished | Jul 27 06:47:05 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-e6affe45-5c3a-4f24-8cf2-d42f39aa428c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029587394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.4029587394 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.2553717295 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 35769086668 ps |
CPU time | 600.91 seconds |
Started | Jul 27 06:47:00 PM PDT 24 |
Finished | Jul 27 06:57:01 PM PDT 24 |
Peak memory | 362356 kb |
Host | smart-525033fd-6c18-40d4-8a90-132fc3ef97db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553717295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2553717295 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.2435108937 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 1476010574 ps |
CPU time | 6.57 seconds |
Started | Jul 27 06:46:51 PM PDT 24 |
Finished | Jul 27 06:46:58 PM PDT 24 |
Peak memory | 219624 kb |
Host | smart-fd8f2c70-c8de-40a1-a658-fdcffa506251 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435108937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2435108937 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.1724082683 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 28317469582 ps |
CPU time | 2080.23 seconds |
Started | Jul 27 06:47:01 PM PDT 24 |
Finished | Jul 27 07:21:41 PM PDT 24 |
Peak memory | 381104 kb |
Host | smart-6c70164d-730e-43c6-8a0d-33aaf884e839 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724082683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.1724082683 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.778067021 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 6159067634 ps |
CPU time | 36.98 seconds |
Started | Jul 27 06:47:01 PM PDT 24 |
Finished | Jul 27 06:47:38 PM PDT 24 |
Peak memory | 262528 kb |
Host | smart-9617938c-1edb-4c24-a345-cbfb986c3083 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=778067021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.778067021 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3701897782 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 3369981021 ps |
CPU time | 236.46 seconds |
Started | Jul 27 06:46:53 PM PDT 24 |
Finished | Jul 27 06:50:49 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-f0c4372d-3122-4a1b-a81c-92fdaf942807 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701897782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.3701897782 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.4276932912 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 698157243 ps |
CPU time | 10.59 seconds |
Started | Jul 27 06:46:55 PM PDT 24 |
Finished | Jul 27 06:47:05 PM PDT 24 |
Peak memory | 228616 kb |
Host | smart-253de729-f225-4368-92c8-663bac19d350 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276932912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.4276932912 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3130024681 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 8675007491 ps |
CPU time | 914.12 seconds |
Started | Jul 27 06:47:10 PM PDT 24 |
Finished | Jul 27 07:02:24 PM PDT 24 |
Peak memory | 371044 kb |
Host | smart-1745768a-ccdb-43e8-a88b-2868fd36a072 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130024681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.3130024681 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.3688159872 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 41359844 ps |
CPU time | 0.67 seconds |
Started | Jul 27 06:47:18 PM PDT 24 |
Finished | Jul 27 06:47:18 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-431b4bc5-88c0-4cc2-be7d-3248188add1d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688159872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.3688159872 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.3490494486 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 101245294674 ps |
CPU time | 2352.84 seconds |
Started | Jul 27 06:47:03 PM PDT 24 |
Finished | Jul 27 07:26:17 PM PDT 24 |
Peak memory | 203712 kb |
Host | smart-bebc9684-4127-42bc-b5ba-18e89f89ce61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490494486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .3490494486 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.657087714 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 19600332122 ps |
CPU time | 626.6 seconds |
Started | Jul 27 06:47:12 PM PDT 24 |
Finished | Jul 27 06:57:38 PM PDT 24 |
Peak memory | 374980 kb |
Host | smart-2c877b8f-8134-45ad-b40c-a96ffc7468a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657087714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl e.657087714 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.3201812497 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 7460933623 ps |
CPU time | 24.93 seconds |
Started | Jul 27 06:47:12 PM PDT 24 |
Finished | Jul 27 06:47:37 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-8e3af6f3-1d36-4e24-8ab6-09bd96c0c3dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201812497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.3201812497 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.964890530 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 934862223 ps |
CPU time | 5.78 seconds |
Started | Jul 27 06:47:10 PM PDT 24 |
Finished | Jul 27 06:47:16 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-5c4426df-fdda-4c03-be9b-b5cd43437ec9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964890530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.sram_ctrl_max_throughput.964890530 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3850420425 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 985091632 ps |
CPU time | 62.92 seconds |
Started | Jul 27 06:47:09 PM PDT 24 |
Finished | Jul 27 06:48:12 PM PDT 24 |
Peak memory | 211364 kb |
Host | smart-f8eb8d65-ee9a-4f0c-961d-f6ff1d7dbe93 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850420425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.3850420425 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.3154959479 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 57745686052 ps |
CPU time | 329.72 seconds |
Started | Jul 27 06:47:09 PM PDT 24 |
Finished | Jul 27 06:52:39 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-4912f1b0-b846-4627-ab92-6e3c1eb491ae |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154959479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.3154959479 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.1936182366 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 4030975240 ps |
CPU time | 561.25 seconds |
Started | Jul 27 06:47:04 PM PDT 24 |
Finished | Jul 27 06:56:25 PM PDT 24 |
Peak memory | 380072 kb |
Host | smart-8b3a2718-58f9-45c2-9e49-bf37df3381f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936182366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1936182366 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.1800523434 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 1546951241 ps |
CPU time | 9.86 seconds |
Started | Jul 27 06:47:11 PM PDT 24 |
Finished | Jul 27 06:47:21 PM PDT 24 |
Peak memory | 220036 kb |
Host | smart-21863859-6595-40e6-868e-df6b7803b0db |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800523434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.1800523434 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.701674649 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 15339354626 ps |
CPU time | 352.28 seconds |
Started | Jul 27 06:47:08 PM PDT 24 |
Finished | Jul 27 06:53:00 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-2404572c-6a53-4f3c-a73c-94ca85928480 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701674649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.sram_ctrl_partial_access_b2b.701674649 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.2979708968 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 672857040 ps |
CPU time | 3.37 seconds |
Started | Jul 27 06:47:11 PM PDT 24 |
Finished | Jul 27 06:47:14 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-3cc7d270-fea1-4df0-8d50-e715eb8047aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979708968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2979708968 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.469545700 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 17314525177 ps |
CPU time | 699.09 seconds |
Started | Jul 27 06:47:10 PM PDT 24 |
Finished | Jul 27 06:58:49 PM PDT 24 |
Peak memory | 378312 kb |
Host | smart-469bf53d-b13a-4426-aef1-25b71419c73d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469545700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.469545700 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.2701798543 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 2828338881 ps |
CPU time | 138.64 seconds |
Started | Jul 27 06:47:01 PM PDT 24 |
Finished | Jul 27 06:49:20 PM PDT 24 |
Peak memory | 369816 kb |
Host | smart-b97fcc2c-4ed6-499d-bafa-45bf9d5d717c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701798543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2701798543 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.668322930 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 63612651111 ps |
CPU time | 2736.18 seconds |
Started | Jul 27 06:47:18 PM PDT 24 |
Finished | Jul 27 07:32:55 PM PDT 24 |
Peak memory | 380008 kb |
Host | smart-0a9ce199-d2d3-4415-9a98-8a1a90b04bcd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668322930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_stress_all.668322930 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1804893014 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 2240876734 ps |
CPU time | 16.93 seconds |
Started | Jul 27 06:47:08 PM PDT 24 |
Finished | Jul 27 06:47:25 PM PDT 24 |
Peak memory | 211756 kb |
Host | smart-603c1c4d-11a1-4566-b691-a3df08d69509 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1804893014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1804893014 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.148035280 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 5959398159 ps |
CPU time | 189.75 seconds |
Started | Jul 27 06:47:00 PM PDT 24 |
Finished | Jul 27 06:50:10 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-daf55acc-9b74-4fea-a8c8-8c52d659ab3f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148035280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17 .sram_ctrl_stress_pipeline.148035280 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1090598793 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 824643737 ps |
CPU time | 167.59 seconds |
Started | Jul 27 06:47:09 PM PDT 24 |
Finished | Jul 27 06:49:57 PM PDT 24 |
Peak memory | 370884 kb |
Host | smart-c22ad433-e4c1-4547-9184-966d1b352a26 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090598793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1090598793 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.236361169 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 51267848464 ps |
CPU time | 1079.32 seconds |
Started | Jul 27 06:47:17 PM PDT 24 |
Finished | Jul 27 07:05:17 PM PDT 24 |
Peak memory | 374868 kb |
Host | smart-655a2bf5-b6a5-450d-84c0-63d3426350b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236361169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_access_during_key_req.236361169 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.4012922432 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 12127213 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:47:26 PM PDT 24 |
Finished | Jul 27 06:47:27 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-439343ed-6c2a-428e-8541-cde35d440c0b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012922432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.4012922432 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.1132367747 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 97638205467 ps |
CPU time | 1603.87 seconds |
Started | Jul 27 06:47:17 PM PDT 24 |
Finished | Jul 27 07:14:01 PM PDT 24 |
Peak memory | 203960 kb |
Host | smart-c2e64293-e879-4fb1-934b-810c64c29d82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132367747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .1132367747 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.2914096326 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 73886762838 ps |
CPU time | 723.74 seconds |
Started | Jul 27 06:47:18 PM PDT 24 |
Finished | Jul 27 06:59:22 PM PDT 24 |
Peak memory | 379088 kb |
Host | smart-d62fe28d-c1a3-40ee-8abc-037399236f1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914096326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.2914096326 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.3087816840 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 10096560861 ps |
CPU time | 69.42 seconds |
Started | Jul 27 06:47:21 PM PDT 24 |
Finished | Jul 27 06:48:31 PM PDT 24 |
Peak memory | 215560 kb |
Host | smart-61496bfd-60e3-49ce-ad02-80de39271c79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087816840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.3087816840 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.1723810223 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 765234462 ps |
CPU time | 32.74 seconds |
Started | Jul 27 06:47:17 PM PDT 24 |
Finished | Jul 27 06:47:50 PM PDT 24 |
Peak memory | 301292 kb |
Host | smart-1056b768-a39d-4d95-a2fe-95408b2da03e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723810223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.1723810223 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.3539675797 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 2883405862 ps |
CPU time | 74.86 seconds |
Started | Jul 27 06:47:26 PM PDT 24 |
Finished | Jul 27 06:48:41 PM PDT 24 |
Peak memory | 219548 kb |
Host | smart-6c998998-b309-486d-8448-b5aec865f714 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539675797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.3539675797 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.1301897867 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 3730061470 ps |
CPU time | 126.61 seconds |
Started | Jul 27 06:47:28 PM PDT 24 |
Finished | Jul 27 06:49:34 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-b9064090-5ed3-4046-8d4e-dd75f4d1f2dc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301897867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.1301897867 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.3609075476 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 9436312317 ps |
CPU time | 218.64 seconds |
Started | Jul 27 06:47:16 PM PDT 24 |
Finished | Jul 27 06:50:55 PM PDT 24 |
Peak memory | 326868 kb |
Host | smart-42347310-219a-44fb-80ea-1c6b0d050361 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609075476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.3609075476 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.1402702934 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 1739671382 ps |
CPU time | 14.69 seconds |
Started | Jul 27 06:47:18 PM PDT 24 |
Finished | Jul 27 06:47:33 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-9f345506-9d2d-4d16-8501-d425c21d671e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402702934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.1402702934 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3369226724 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 51041445917 ps |
CPU time | 220.71 seconds |
Started | Jul 27 06:47:16 PM PDT 24 |
Finished | Jul 27 06:50:57 PM PDT 24 |
Peak memory | 203284 kb |
Host | smart-b0d37c0f-1484-4a7e-a626-e41344f2e262 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369226724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.3369226724 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.1089320022 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 690848365 ps |
CPU time | 3.43 seconds |
Started | Jul 27 06:47:18 PM PDT 24 |
Finished | Jul 27 06:47:21 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-856d7699-f06c-40b6-bfe1-96061878e0d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089320022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.1089320022 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.1506497202 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 16310555490 ps |
CPU time | 1162.87 seconds |
Started | Jul 27 06:47:18 PM PDT 24 |
Finished | Jul 27 07:06:41 PM PDT 24 |
Peak memory | 381012 kb |
Host | smart-36a83d9c-5aa3-4845-8567-369ce6dd57f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506497202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1506497202 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.2067515546 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 7782290558 ps |
CPU time | 72.97 seconds |
Started | Jul 27 06:47:18 PM PDT 24 |
Finished | Jul 27 06:48:31 PM PDT 24 |
Peak memory | 341620 kb |
Host | smart-07b4edef-fc8c-4677-a6db-e162b1106236 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067515546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2067515546 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.3542467710 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 1050126587929 ps |
CPU time | 5759.88 seconds |
Started | Jul 27 06:47:25 PM PDT 24 |
Finished | Jul 27 08:23:25 PM PDT 24 |
Peak memory | 382236 kb |
Host | smart-ab34571d-43bc-4983-9e37-03eadef5935e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542467710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.3542467710 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1556589203 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 1963104884 ps |
CPU time | 13.37 seconds |
Started | Jul 27 06:47:27 PM PDT 24 |
Finished | Jul 27 06:47:40 PM PDT 24 |
Peak memory | 211364 kb |
Host | smart-fb6f641e-8e23-4636-8a04-3aa5aeeb8f76 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1556589203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1556589203 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3461831483 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 6882722879 ps |
CPU time | 204.34 seconds |
Started | Jul 27 06:47:16 PM PDT 24 |
Finished | Jul 27 06:50:40 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-2beecf47-66cc-417d-8712-1be05482bc77 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461831483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.3461831483 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3424052054 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 2995317095 ps |
CPU time | 59.34 seconds |
Started | Jul 27 06:47:18 PM PDT 24 |
Finished | Jul 27 06:48:18 PM PDT 24 |
Peak memory | 324872 kb |
Host | smart-16e3b65b-61f9-4438-a8dd-f8f1f5a4cf3b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424052054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3424052054 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.714059707 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 71218820068 ps |
CPU time | 1188.38 seconds |
Started | Jul 27 06:47:38 PM PDT 24 |
Finished | Jul 27 07:07:26 PM PDT 24 |
Peak memory | 380408 kb |
Host | smart-6016b294-a29f-401f-8002-eb061687171e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714059707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_access_during_key_req.714059707 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.469629909 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 32171346 ps |
CPU time | 0.63 seconds |
Started | Jul 27 06:47:34 PM PDT 24 |
Finished | Jul 27 06:47:35 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-08535a4c-07f9-48fb-81ed-d24a9267c655 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469629909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.469629909 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.4150368163 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 155007916331 ps |
CPU time | 622.64 seconds |
Started | Jul 27 06:47:27 PM PDT 24 |
Finished | Jul 27 06:57:50 PM PDT 24 |
Peak memory | 203908 kb |
Host | smart-64ef8048-f7ad-4f26-b43d-99ecb2b4ea70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150368163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .4150368163 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.4208183589 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 22784337149 ps |
CPU time | 1263.15 seconds |
Started | Jul 27 06:47:36 PM PDT 24 |
Finished | Jul 27 07:08:39 PM PDT 24 |
Peak memory | 375960 kb |
Host | smart-052b5b3b-2656-4693-a073-84b2d903ee26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208183589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.4208183589 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.614932981 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 4720573114 ps |
CPU time | 31.36 seconds |
Started | Jul 27 06:47:28 PM PDT 24 |
Finished | Jul 27 06:47:59 PM PDT 24 |
Peak memory | 215620 kb |
Host | smart-4ca0f015-8ab6-4883-bf11-de1f18021124 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614932981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esc alation.614932981 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.742757265 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 2726809978 ps |
CPU time | 165.53 seconds |
Started | Jul 27 06:47:27 PM PDT 24 |
Finished | Jul 27 06:50:12 PM PDT 24 |
Peak memory | 367720 kb |
Host | smart-1ffcfcde-ed0a-4986-aee6-2094a63d4dd2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742757265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.sram_ctrl_max_throughput.742757265 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.192726198 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 3256090317 ps |
CPU time | 132.25 seconds |
Started | Jul 27 06:47:36 PM PDT 24 |
Finished | Jul 27 06:49:48 PM PDT 24 |
Peak memory | 219500 kb |
Host | smart-34ee2d95-8939-4603-98ae-559820e9f8b2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192726198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sram_ctrl_mem_partial_access.192726198 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.846542062 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 51238388044 ps |
CPU time | 327.68 seconds |
Started | Jul 27 06:47:38 PM PDT 24 |
Finished | Jul 27 06:53:06 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-3c252184-f18e-42ba-a402-8ba280bc97ce |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846542062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _mem_walk.846542062 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.4107697654 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 7437651328 ps |
CPU time | 162.72 seconds |
Started | Jul 27 06:47:27 PM PDT 24 |
Finished | Jul 27 06:50:10 PM PDT 24 |
Peak memory | 361432 kb |
Host | smart-693b5ec8-8687-43b3-9db3-227a098f0a45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107697654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.4107697654 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.2754019608 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 825180602 ps |
CPU time | 42.47 seconds |
Started | Jul 27 06:47:28 PM PDT 24 |
Finished | Jul 27 06:48:10 PM PDT 24 |
Peak memory | 320652 kb |
Host | smart-08046794-6c6f-4f44-acc2-9f3facab1e60 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754019608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.2754019608 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2659193897 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 6183892164 ps |
CPU time | 188.01 seconds |
Started | Jul 27 06:47:27 PM PDT 24 |
Finished | Jul 27 06:50:35 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-dd513e2f-5518-4d7f-a76e-45b3aed1b568 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659193897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.2659193897 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.2380085913 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 1163656331 ps |
CPU time | 3.68 seconds |
Started | Jul 27 06:47:34 PM PDT 24 |
Finished | Jul 27 06:47:38 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-c4605ac0-9a2d-4d83-ba6f-8cf896a058bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380085913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2380085913 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.1051008353 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 19956558949 ps |
CPU time | 393.89 seconds |
Started | Jul 27 06:47:35 PM PDT 24 |
Finished | Jul 27 06:54:09 PM PDT 24 |
Peak memory | 379200 kb |
Host | smart-315edf6d-4397-442c-aedb-d07c78db0806 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051008353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1051008353 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.2870370202 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 1713031584 ps |
CPU time | 5.94 seconds |
Started | Jul 27 06:47:27 PM PDT 24 |
Finished | Jul 27 06:47:33 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-7ac1b6f4-1084-4802-b91b-90097f640b4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870370202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2870370202 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.1678480200 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 83152402129 ps |
CPU time | 4349.43 seconds |
Started | Jul 27 06:47:35 PM PDT 24 |
Finished | Jul 27 08:00:05 PM PDT 24 |
Peak memory | 203304 kb |
Host | smart-3dede669-36b8-4f60-8cc4-625525ceeaa0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678480200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.1678480200 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3909074804 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 285807146 ps |
CPU time | 10.95 seconds |
Started | Jul 27 06:47:34 PM PDT 24 |
Finished | Jul 27 06:47:46 PM PDT 24 |
Peak memory | 211428 kb |
Host | smart-6b6d3020-e56c-4a49-b0ad-9ddb7de70918 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3909074804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3909074804 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2818236037 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 9808722890 ps |
CPU time | 144.68 seconds |
Started | Jul 27 06:47:27 PM PDT 24 |
Finished | Jul 27 06:49:52 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-8e66d2bc-c96e-45d4-a132-ea36f82c961d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818236037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.2818236037 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1069088123 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 3684883488 ps |
CPU time | 61.17 seconds |
Started | Jul 27 06:47:26 PM PDT 24 |
Finished | Jul 27 06:48:27 PM PDT 24 |
Peak memory | 303340 kb |
Host | smart-d5ec11a9-19ce-4e3e-bc41-79d0f27aba43 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069088123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1069088123 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3018838439 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 24192595386 ps |
CPU time | 357.99 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:51:10 PM PDT 24 |
Peak memory | 380132 kb |
Host | smart-6ed795a1-5ad2-4f17-93f5-57823e1a8622 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018838439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.3018838439 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.2624555566 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 50010607 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:45:11 PM PDT 24 |
Finished | Jul 27 06:45:12 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-79b2a763-cabc-4ae6-a027-4e44bee3e566 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624555566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.2624555566 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.2438423667 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 108824979418 ps |
CPU time | 841.98 seconds |
Started | Jul 27 06:45:10 PM PDT 24 |
Finished | Jul 27 06:59:13 PM PDT 24 |
Peak memory | 203796 kb |
Host | smart-84b46bf8-f43c-45ad-a625-269d417715f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438423667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 2438423667 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.772422030 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 22885007474 ps |
CPU time | 1461.25 seconds |
Started | Jul 27 06:45:09 PM PDT 24 |
Finished | Jul 27 07:09:30 PM PDT 24 |
Peak memory | 377052 kb |
Host | smart-b4b8bea2-e97f-4692-8e39-60d4760722db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772422030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable .772422030 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.974570027 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 33050083147 ps |
CPU time | 51.91 seconds |
Started | Jul 27 06:45:10 PM PDT 24 |
Finished | Jul 27 06:46:02 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-4dada0af-abd7-4ace-8816-f9d76ae5353f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974570027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esca lation.974570027 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.455296739 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 2771014462 ps |
CPU time | 6.9 seconds |
Started | Jul 27 06:45:13 PM PDT 24 |
Finished | Jul 27 06:45:20 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-4f37662f-c1ba-4b5c-9991-09d0a0da45ba |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455296739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.sram_ctrl_max_throughput.455296739 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3328413430 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 1416118740 ps |
CPU time | 73.63 seconds |
Started | Jul 27 06:45:11 PM PDT 24 |
Finished | Jul 27 06:46:24 PM PDT 24 |
Peak memory | 211332 kb |
Host | smart-1fb218a0-2f6f-4f1f-a926-701fe58621fd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328413430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.3328413430 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.1288518681 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 20901590685 ps |
CPU time | 343.62 seconds |
Started | Jul 27 06:45:15 PM PDT 24 |
Finished | Jul 27 06:50:58 PM PDT 24 |
Peak memory | 211480 kb |
Host | smart-bcda89c1-d371-44ac-a028-9092e93961ac |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288518681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.1288518681 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.3161941237 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 29937733840 ps |
CPU time | 541.44 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:54:14 PM PDT 24 |
Peak memory | 355940 kb |
Host | smart-51fec0e1-d2c0-4b78-9495-2f8afec7106a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161941237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.3161941237 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.2190698191 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 2385810788 ps |
CPU time | 97.57 seconds |
Started | Jul 27 06:45:14 PM PDT 24 |
Finished | Jul 27 06:46:52 PM PDT 24 |
Peak memory | 339352 kb |
Host | smart-5e21299a-8591-4a71-aef3-524c121cd618 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190698191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.2190698191 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1473618692 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 18171576677 ps |
CPU time | 430.61 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:52:23 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-a3295b4d-bc07-489b-b2dc-4374d4a2682e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473618692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.1473618692 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.2859319499 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 2108330110 ps |
CPU time | 3.47 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:45:16 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-96cb451f-ff99-4fba-8b00-82e7dacb7499 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859319499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2859319499 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.4026329183 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 13812730165 ps |
CPU time | 1019.95 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 07:02:12 PM PDT 24 |
Peak memory | 374988 kb |
Host | smart-fae70157-0f0c-4999-8ba1-aef9aa915389 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026329183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.4026329183 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.3909198102 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 183210680 ps |
CPU time | 2.01 seconds |
Started | Jul 27 06:45:13 PM PDT 24 |
Finished | Jul 27 06:45:15 PM PDT 24 |
Peak memory | 222460 kb |
Host | smart-1632f8b5-5a09-42b2-ac93-e0ac40a432ba |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909198102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.3909198102 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.416994026 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 879173402 ps |
CPU time | 18.49 seconds |
Started | Jul 27 06:45:13 PM PDT 24 |
Finished | Jul 27 06:45:32 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-96c67a22-9881-4c17-a710-82fad3d4a504 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416994026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.416994026 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.2813607260 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 69618401052 ps |
CPU time | 2246.12 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 07:22:39 PM PDT 24 |
Peak memory | 381140 kb |
Host | smart-8cb256bb-889c-4326-948c-9534d0f3ab40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813607260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.2813607260 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2024133679 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 1655284905 ps |
CPU time | 8.12 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:45:20 PM PDT 24 |
Peak memory | 211512 kb |
Host | smart-2e932c7a-662d-4bbc-a237-af3f62adb578 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2024133679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2024133679 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.141816321 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 4292585491 ps |
CPU time | 236.58 seconds |
Started | Jul 27 06:45:09 PM PDT 24 |
Finished | Jul 27 06:49:06 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-b470b2b6-bf44-4791-95d3-61e9986014d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141816321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. sram_ctrl_stress_pipeline.141816321 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2540104870 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 2066424251 ps |
CPU time | 152.19 seconds |
Started | Jul 27 06:45:10 PM PDT 24 |
Finished | Jul 27 06:47:42 PM PDT 24 |
Peak memory | 372816 kb |
Host | smart-89febd30-5f6a-4d00-810a-e5ec696e50f4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540104870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.2540104870 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2798128199 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 35891393527 ps |
CPU time | 985.47 seconds |
Started | Jul 27 06:47:44 PM PDT 24 |
Finished | Jul 27 07:04:09 PM PDT 24 |
Peak memory | 379096 kb |
Host | smart-e84a92e9-9ff2-4cde-a81c-6dfe17a99644 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798128199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.2798128199 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.3916732222 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 28435464 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:47:45 PM PDT 24 |
Finished | Jul 27 06:47:46 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-a9103d75-aa63-4b0f-8d2f-145c6697b81a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916732222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.3916732222 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.3316032297 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 57423168127 ps |
CPU time | 484.81 seconds |
Started | Jul 27 06:47:36 PM PDT 24 |
Finished | Jul 27 06:55:41 PM PDT 24 |
Peak memory | 203476 kb |
Host | smart-58efa530-d7ec-458b-a00d-c959919b9ccc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316032297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .3316032297 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.2392794365 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 2304700423 ps |
CPU time | 28.15 seconds |
Started | Jul 27 06:47:45 PM PDT 24 |
Finished | Jul 27 06:48:13 PM PDT 24 |
Peak memory | 274852 kb |
Host | smart-bd19f90c-43d0-4dec-8fa9-0bcf069a38a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392794365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.2392794365 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.117315731 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 13275533269 ps |
CPU time | 42.27 seconds |
Started | Jul 27 06:47:43 PM PDT 24 |
Finished | Jul 27 06:48:25 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-6061af82-2ac4-4ffc-956b-b2ab84897cfa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117315731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc alation.117315731 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.2676129883 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 726525195 ps |
CPU time | 12.33 seconds |
Started | Jul 27 06:47:44 PM PDT 24 |
Finished | Jul 27 06:47:57 PM PDT 24 |
Peak memory | 240612 kb |
Host | smart-ea6ee33d-b3ea-4b6d-9033-07201af6af08 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676129883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.2676129883 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.540947158 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 2712766099 ps |
CPU time | 71.48 seconds |
Started | Jul 27 06:47:44 PM PDT 24 |
Finished | Jul 27 06:48:55 PM PDT 24 |
Peak memory | 219520 kb |
Host | smart-1461af3f-f920-4d23-981e-4a46293955b3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540947158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20 .sram_ctrl_mem_partial_access.540947158 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.2859274644 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 20225406570 ps |
CPU time | 157.85 seconds |
Started | Jul 27 06:47:44 PM PDT 24 |
Finished | Jul 27 06:50:22 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-c8008528-4e3f-4047-98e2-33049737b3d7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859274644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.2859274644 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.763522321 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 37813087060 ps |
CPU time | 314.01 seconds |
Started | Jul 27 06:47:34 PM PDT 24 |
Finished | Jul 27 06:52:49 PM PDT 24 |
Peak memory | 336280 kb |
Host | smart-ffe444a0-2c98-46fb-af31-a2597a65c29f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763522321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip le_keys.763522321 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.3416116702 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 2491129214 ps |
CPU time | 8.92 seconds |
Started | Jul 27 06:47:37 PM PDT 24 |
Finished | Jul 27 06:47:46 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-735d8918-4c7d-474c-9d68-9754d3475e28 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416116702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.3416116702 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1609857821 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 26998005043 ps |
CPU time | 348.74 seconds |
Started | Jul 27 06:47:34 PM PDT 24 |
Finished | Jul 27 06:53:23 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-13174535-c5c3-4f98-bdee-e35cf7ece8fb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609857821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.1609857821 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.4060989655 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 1405167176 ps |
CPU time | 3.69 seconds |
Started | Jul 27 06:47:51 PM PDT 24 |
Finished | Jul 27 06:47:54 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-3d9cec50-f9fe-408f-8058-b75d723d20cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060989655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.4060989655 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.1054183263 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 5544484420 ps |
CPU time | 341.94 seconds |
Started | Jul 27 06:47:44 PM PDT 24 |
Finished | Jul 27 06:53:26 PM PDT 24 |
Peak memory | 363704 kb |
Host | smart-e84e853d-80fa-418c-b545-59d7d76d2325 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054183263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1054183263 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.2068418541 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 3083374693 ps |
CPU time | 71.19 seconds |
Started | Jul 27 06:47:38 PM PDT 24 |
Finished | Jul 27 06:48:49 PM PDT 24 |
Peak memory | 314580 kb |
Host | smart-a5779ac2-144f-43eb-9ff6-619886184c61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068418541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2068418541 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.1988941474 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 56966444992 ps |
CPU time | 1581.91 seconds |
Started | Jul 27 06:47:45 PM PDT 24 |
Finished | Jul 27 07:14:07 PM PDT 24 |
Peak memory | 383128 kb |
Host | smart-a3669af7-a2f9-47f9-b9e9-7dfc98324700 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988941474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.1988941474 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.931433881 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 364535403 ps |
CPU time | 12.73 seconds |
Started | Jul 27 06:47:42 PM PDT 24 |
Finished | Jul 27 06:47:55 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-48f9c933-5bf3-4f68-b916-30bc318bfc7e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=931433881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.931433881 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.4052001554 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 18808324534 ps |
CPU time | 347.1 seconds |
Started | Jul 27 06:47:34 PM PDT 24 |
Finished | Jul 27 06:53:22 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-d6a59663-c82f-449e-9554-6be51a824f88 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052001554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.4052001554 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.941903362 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 1591479211 ps |
CPU time | 93.67 seconds |
Started | Jul 27 06:47:44 PM PDT 24 |
Finished | Jul 27 06:49:18 PM PDT 24 |
Peak memory | 348244 kb |
Host | smart-3b7bcd2c-07e4-4a89-a4ac-3fef0b5fc3b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941903362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.941903362 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1222110547 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 16329654846 ps |
CPU time | 1616.21 seconds |
Started | Jul 27 06:47:55 PM PDT 24 |
Finished | Jul 27 07:14:52 PM PDT 24 |
Peak memory | 379824 kb |
Host | smart-9413b819-66b7-4249-adf7-97fff8f73a97 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222110547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.1222110547 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.1404391522 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 74889898 ps |
CPU time | 0.62 seconds |
Started | Jul 27 06:47:53 PM PDT 24 |
Finished | Jul 27 06:47:53 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-44a8a883-33bf-4f5f-b9a7-eeea6c3e8388 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404391522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1404391522 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.1285123976 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 276507303339 ps |
CPU time | 1171.54 seconds |
Started | Jul 27 06:47:45 PM PDT 24 |
Finished | Jul 27 07:07:16 PM PDT 24 |
Peak memory | 203868 kb |
Host | smart-4bdbb4cc-e9a6-4d3b-8520-de4e82c295ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285123976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .1285123976 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.1161192447 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 31536831990 ps |
CPU time | 1623.15 seconds |
Started | Jul 27 06:47:54 PM PDT 24 |
Finished | Jul 27 07:14:58 PM PDT 24 |
Peak memory | 381124 kb |
Host | smart-e9ea0a54-429b-40a6-a48a-4881fdeae062 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161192447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.1161192447 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.2923389814 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 24708323136 ps |
CPU time | 45.09 seconds |
Started | Jul 27 06:47:52 PM PDT 24 |
Finished | Jul 27 06:48:37 PM PDT 24 |
Peak memory | 214976 kb |
Host | smart-b6c90453-97b8-47d4-9f20-f5352608bda8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923389814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.2923389814 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.1902370455 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 780356764 ps |
CPU time | 89.86 seconds |
Started | Jul 27 06:47:54 PM PDT 24 |
Finished | Jul 27 06:49:24 PM PDT 24 |
Peak memory | 348280 kb |
Host | smart-fee5a616-d2d5-4194-893a-ffb8b1354c0c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902370455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.1902370455 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.328136003 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 1392089457 ps |
CPU time | 75.45 seconds |
Started | Jul 27 06:47:55 PM PDT 24 |
Finished | Jul 27 06:49:11 PM PDT 24 |
Peak memory | 219500 kb |
Host | smart-3e09939b-8ca8-4272-9e59-e5e1e45d8752 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328136003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_mem_partial_access.328136003 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.2557136778 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 10719723795 ps |
CPU time | 302.23 seconds |
Started | Jul 27 06:47:52 PM PDT 24 |
Finished | Jul 27 06:52:54 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-36573c1d-e8f2-43fb-a345-45d58ae6e713 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557136778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.2557136778 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.1114252993 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 75425517982 ps |
CPU time | 854 seconds |
Started | Jul 27 06:47:43 PM PDT 24 |
Finished | Jul 27 07:01:57 PM PDT 24 |
Peak memory | 378028 kb |
Host | smart-d2e5598e-0f01-4a33-a278-d7470282bc3d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114252993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.1114252993 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.2012131752 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 4629474486 ps |
CPU time | 20.36 seconds |
Started | Jul 27 06:47:43 PM PDT 24 |
Finished | Jul 27 06:48:04 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-ab44886a-5635-4fa6-a72d-6d5e3fc3ce5a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012131752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.2012131752 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2008747540 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 4406912578 ps |
CPU time | 207.18 seconds |
Started | Jul 27 06:47:53 PM PDT 24 |
Finished | Jul 27 06:51:20 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-3841cb39-7e01-460b-ab3b-932b81617d9e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008747540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.2008747540 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.237443746 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 4194827460 ps |
CPU time | 3.82 seconds |
Started | Jul 27 06:47:52 PM PDT 24 |
Finished | Jul 27 06:47:56 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-be7d62bc-376f-4dea-8597-74ec6afeffce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237443746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.237443746 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.274722866 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 12374690507 ps |
CPU time | 918.87 seconds |
Started | Jul 27 06:47:54 PM PDT 24 |
Finished | Jul 27 07:03:13 PM PDT 24 |
Peak memory | 375960 kb |
Host | smart-8f5dced8-6784-4014-acb6-32702b9a8465 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274722866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.274722866 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.2208316216 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 447004771 ps |
CPU time | 131.88 seconds |
Started | Jul 27 06:47:42 PM PDT 24 |
Finished | Jul 27 06:49:54 PM PDT 24 |
Peak memory | 362684 kb |
Host | smart-2365a73f-ef8c-45d5-8913-c36563713742 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208316216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2208316216 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.3124027642 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 225351313144 ps |
CPU time | 5646.4 seconds |
Started | Jul 27 06:47:53 PM PDT 24 |
Finished | Jul 27 08:22:00 PM PDT 24 |
Peak memory | 377000 kb |
Host | smart-1fdff5f3-6b59-4806-8bc1-4288fc2c34df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124027642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.3124027642 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1788324969 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 570711231 ps |
CPU time | 9.43 seconds |
Started | Jul 27 06:47:52 PM PDT 24 |
Finished | Jul 27 06:48:01 PM PDT 24 |
Peak memory | 211372 kb |
Host | smart-b3f8b5d3-ddd7-4f8f-8a36-e1021a072618 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1788324969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1788324969 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1298943739 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 9276129772 ps |
CPU time | 327.72 seconds |
Started | Jul 27 06:47:45 PM PDT 24 |
Finished | Jul 27 06:53:13 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-a924a13f-7549-4293-8a48-dec00c8ba290 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298943739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.1298943739 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.4240546295 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 3157668733 ps |
CPU time | 65.9 seconds |
Started | Jul 27 06:47:54 PM PDT 24 |
Finished | Jul 27 06:49:00 PM PDT 24 |
Peak memory | 334200 kb |
Host | smart-3d1fdacf-1f0c-49b2-8f2d-a097a7928011 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240546295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.4240546295 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1769212773 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 12528492386 ps |
CPU time | 323.88 seconds |
Started | Jul 27 06:48:05 PM PDT 24 |
Finished | Jul 27 06:53:29 PM PDT 24 |
Peak memory | 377020 kb |
Host | smart-68c9da88-a459-4394-af88-3468edb4fa77 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769212773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.1769212773 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.3643999532 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 22246375 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:48:11 PM PDT 24 |
Finished | Jul 27 06:48:12 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-50d06f3b-98de-4547-83da-2d479deaefa9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643999532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.3643999532 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.2328270065 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 57945187504 ps |
CPU time | 588.09 seconds |
Started | Jul 27 06:47:52 PM PDT 24 |
Finished | Jul 27 06:57:40 PM PDT 24 |
Peak memory | 203964 kb |
Host | smart-619fc230-2366-4e41-8855-0367fa768ade |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328270065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .2328270065 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.2623169550 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 12493318140 ps |
CPU time | 360 seconds |
Started | Jul 27 06:48:02 PM PDT 24 |
Finished | Jul 27 06:54:02 PM PDT 24 |
Peak memory | 369464 kb |
Host | smart-095c0ccc-85be-4ab6-8562-3fc8c9763836 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623169550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.2623169550 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.3471031153 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 6900816513 ps |
CPU time | 49.1 seconds |
Started | Jul 27 06:48:04 PM PDT 24 |
Finished | Jul 27 06:48:54 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-45055d25-3200-4de6-a325-5532aec36c64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471031153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.3471031153 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.2572345546 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 14619761818 ps |
CPU time | 54.51 seconds |
Started | Jul 27 06:48:04 PM PDT 24 |
Finished | Jul 27 06:48:59 PM PDT 24 |
Peak memory | 317864 kb |
Host | smart-bb0607d3-de25-4110-b658-4c6928de75d0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572345546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.2572345546 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1684594617 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 3997787080 ps |
CPU time | 65.58 seconds |
Started | Jul 27 06:48:11 PM PDT 24 |
Finished | Jul 27 06:49:17 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-7ade96b5-dddf-4868-acdd-c6a0996b1a8d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684594617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.1684594617 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.2374442784 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 21108200413 ps |
CPU time | 180.53 seconds |
Started | Jul 27 06:48:04 PM PDT 24 |
Finished | Jul 27 06:51:04 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-6ca7cc0a-d261-43fe-9b33-3a3f2d48e3b2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374442784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.2374442784 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.3159671079 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 21814400769 ps |
CPU time | 910.82 seconds |
Started | Jul 27 06:47:55 PM PDT 24 |
Finished | Jul 27 07:03:06 PM PDT 24 |
Peak memory | 380024 kb |
Host | smart-f2b03b52-060b-425d-962c-f2aceddd1340 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159671079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.3159671079 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.2985744364 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 7140321229 ps |
CPU time | 18.38 seconds |
Started | Jul 27 06:48:04 PM PDT 24 |
Finished | Jul 27 06:48:23 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-c4d43db9-707a-4470-b0bf-9deb68fbdf24 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985744364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.2985744364 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1765700019 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 194947953046 ps |
CPU time | 632.37 seconds |
Started | Jul 27 06:48:03 PM PDT 24 |
Finished | Jul 27 06:58:36 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-6d6d6f8c-7d19-4752-9f3d-d1ffcec24f74 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765700019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.1765700019 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.3039099481 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 2590699769 ps |
CPU time | 4.22 seconds |
Started | Jul 27 06:48:05 PM PDT 24 |
Finished | Jul 27 06:48:09 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-1a07f427-b541-418c-9789-b6a3ae55f716 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039099481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3039099481 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.2125948864 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 14451612401 ps |
CPU time | 416.07 seconds |
Started | Jul 27 06:48:04 PM PDT 24 |
Finished | Jul 27 06:55:00 PM PDT 24 |
Peak memory | 344584 kb |
Host | smart-ffd60a59-351b-4957-b997-cea78c61d627 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125948864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2125948864 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.1916649673 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 1693289457 ps |
CPU time | 7.66 seconds |
Started | Jul 27 06:47:55 PM PDT 24 |
Finished | Jul 27 06:48:02 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-9f0b32d2-5e37-47db-a365-c3fcccd52314 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916649673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1916649673 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.1593886129 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 44861038775 ps |
CPU time | 2325.21 seconds |
Started | Jul 27 06:48:11 PM PDT 24 |
Finished | Jul 27 07:26:57 PM PDT 24 |
Peak memory | 371972 kb |
Host | smart-a408105d-7648-46ab-9d0c-ff50f54d62f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593886129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.1593886129 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3176047485 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 589368085 ps |
CPU time | 16.86 seconds |
Started | Jul 27 06:48:14 PM PDT 24 |
Finished | Jul 27 06:48:31 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-2c872209-bd7e-420d-bf8c-653048dd5e3b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3176047485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3176047485 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2724466626 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 36154305264 ps |
CPU time | 356.19 seconds |
Started | Jul 27 06:48:05 PM PDT 24 |
Finished | Jul 27 06:54:01 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-ea2c4e08-d144-4ffd-8dfd-958d6d33575f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724466626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.2724466626 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.26964460 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 783319174 ps |
CPU time | 125.4 seconds |
Started | Jul 27 06:48:03 PM PDT 24 |
Finished | Jul 27 06:50:08 PM PDT 24 |
Peak memory | 365592 kb |
Host | smart-883412f8-e247-44ad-a579-35f64cc1c193 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26964460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.sram_ctrl_throughput_w_partial_write.26964460 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2179103764 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 60669217111 ps |
CPU time | 1202.7 seconds |
Started | Jul 27 06:48:12 PM PDT 24 |
Finished | Jul 27 07:08:15 PM PDT 24 |
Peak memory | 376012 kb |
Host | smart-96412976-3992-47ca-b4d3-64b01921cf33 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179103764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.2179103764 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.154405295 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 15024208 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:48:21 PM PDT 24 |
Finished | Jul 27 06:48:21 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-82d2f283-b318-4990-a1a4-5dcc8faf421e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154405295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.154405295 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.970747561 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 380588244440 ps |
CPU time | 2087.21 seconds |
Started | Jul 27 06:48:10 PM PDT 24 |
Finished | Jul 27 07:22:58 PM PDT 24 |
Peak memory | 203852 kb |
Host | smart-0c2d34d5-64a3-4e63-9d9e-9af774627f4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970747561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection. 970747561 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.1010868396 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 9117941279 ps |
CPU time | 619.94 seconds |
Started | Jul 27 06:48:23 PM PDT 24 |
Finished | Jul 27 06:58:43 PM PDT 24 |
Peak memory | 375056 kb |
Host | smart-8545c173-886d-4665-ab55-9b7e9dee1f8e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010868396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.1010868396 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.2302643611 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 5972599104 ps |
CPU time | 20.18 seconds |
Started | Jul 27 06:48:12 PM PDT 24 |
Finished | Jul 27 06:48:32 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-ae114853-f831-4ca6-a293-d9f9171e4725 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302643611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.2302643611 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.2630946208 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 2892399375 ps |
CPU time | 51.8 seconds |
Started | Jul 27 06:48:13 PM PDT 24 |
Finished | Jul 27 06:49:05 PM PDT 24 |
Peak memory | 301120 kb |
Host | smart-6e91f184-b30d-4ab7-855d-a45d0114d021 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630946208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.2630946208 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1187105322 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 22234714721 ps |
CPU time | 165.79 seconds |
Started | Jul 27 06:48:21 PM PDT 24 |
Finished | Jul 27 06:51:07 PM PDT 24 |
Peak memory | 219764 kb |
Host | smart-5a3db82f-342d-4e1b-bd6a-66194d838394 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187105322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.1187105322 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.614134347 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 21142979578 ps |
CPU time | 171.29 seconds |
Started | Jul 27 06:48:22 PM PDT 24 |
Finished | Jul 27 06:51:14 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-20a77923-a49c-4e83-ac44-cc262ca5b4ac |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614134347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl _mem_walk.614134347 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.3096678698 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 19396927602 ps |
CPU time | 321.43 seconds |
Started | Jul 27 06:48:11 PM PDT 24 |
Finished | Jul 27 06:53:33 PM PDT 24 |
Peak memory | 365068 kb |
Host | smart-28dc770a-ab62-4e87-8943-322ee50397d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096678698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.3096678698 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.633743298 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 6086497566 ps |
CPU time | 22.52 seconds |
Started | Jul 27 06:48:14 PM PDT 24 |
Finished | Jul 27 06:48:37 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-e5d9916d-b975-468b-bf71-b55e2bdf58fd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633743298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s ram_ctrl_partial_access.633743298 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4096346882 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 93992702437 ps |
CPU time | 426.88 seconds |
Started | Jul 27 06:48:09 PM PDT 24 |
Finished | Jul 27 06:55:16 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-955f86ff-95b3-4ef7-827a-be56478811c0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096346882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.4096346882 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.3188303846 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 704848926 ps |
CPU time | 3.22 seconds |
Started | Jul 27 06:48:21 PM PDT 24 |
Finished | Jul 27 06:48:24 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-9d5013ff-a572-4fb5-86aa-2ea931eed944 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188303846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3188303846 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.4164792046 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 16800688051 ps |
CPU time | 1348.49 seconds |
Started | Jul 27 06:48:20 PM PDT 24 |
Finished | Jul 27 07:10:49 PM PDT 24 |
Peak memory | 373012 kb |
Host | smart-3a2b4f7c-80e4-49ce-aba6-f1e5052655d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164792046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.4164792046 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.1104232858 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 9775038662 ps |
CPU time | 20.11 seconds |
Started | Jul 27 06:48:13 PM PDT 24 |
Finished | Jul 27 06:48:34 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-fe055e0f-4f25-4093-aaae-b7486e321d8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104232858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1104232858 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.3176322593 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 151485313833 ps |
CPU time | 2879.33 seconds |
Started | Jul 27 06:48:23 PM PDT 24 |
Finished | Jul 27 07:36:23 PM PDT 24 |
Peak memory | 377320 kb |
Host | smart-24affd0c-bb5d-44ac-8895-b87d043fa3f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176322593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.3176322593 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2189579249 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 3125671726 ps |
CPU time | 40.57 seconds |
Started | Jul 27 06:48:19 PM PDT 24 |
Finished | Jul 27 06:49:00 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-37e97abd-0da9-401b-acad-84fde7d29533 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2189579249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2189579249 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3846051936 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 6796224695 ps |
CPU time | 253.78 seconds |
Started | Jul 27 06:48:09 PM PDT 24 |
Finished | Jul 27 06:52:23 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-a072899b-4823-494d-89cd-96ccf2378546 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846051936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3846051936 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2928962072 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 4900696680 ps |
CPU time | 161.41 seconds |
Started | Jul 27 06:48:10 PM PDT 24 |
Finished | Jul 27 06:50:52 PM PDT 24 |
Peak memory | 372100 kb |
Host | smart-d6f345bb-2b48-4a97-a35d-07aaef85dddd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928962072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2928962072 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.3131164418 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 7599440364 ps |
CPU time | 677.05 seconds |
Started | Jul 27 06:48:30 PM PDT 24 |
Finished | Jul 27 06:59:47 PM PDT 24 |
Peak memory | 378008 kb |
Host | smart-a0da2463-173d-4d86-987f-b5e5083f332f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131164418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.3131164418 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.251977499 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 39884634 ps |
CPU time | 0.63 seconds |
Started | Jul 27 06:48:36 PM PDT 24 |
Finished | Jul 27 06:48:36 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-aaa0452e-ccda-41fb-b8e1-67053c75b5bd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251977499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.251977499 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.3021362535 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 191468635270 ps |
CPU time | 815.37 seconds |
Started | Jul 27 06:48:20 PM PDT 24 |
Finished | Jul 27 07:01:56 PM PDT 24 |
Peak memory | 203824 kb |
Host | smart-91f90eb1-7997-4019-b3dc-b05bb8dc144f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021362535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .3021362535 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.4161833811 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 56558077372 ps |
CPU time | 892.86 seconds |
Started | Jul 27 06:48:28 PM PDT 24 |
Finished | Jul 27 07:03:21 PM PDT 24 |
Peak memory | 380100 kb |
Host | smart-c195590b-f126-4aa2-86fe-34afcec06fd8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161833811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.4161833811 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.329620732 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 9746377748 ps |
CPU time | 61.66 seconds |
Started | Jul 27 06:48:29 PM PDT 24 |
Finished | Jul 27 06:49:30 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-dc47b7f1-afbb-4d08-a441-83c8e11b6a3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329620732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esc alation.329620732 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.3221531041 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 3060761901 ps |
CPU time | 125.27 seconds |
Started | Jul 27 06:48:32 PM PDT 24 |
Finished | Jul 27 06:50:37 PM PDT 24 |
Peak memory | 372940 kb |
Host | smart-d5aba798-2076-4457-999c-049874fd9f0d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221531041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.3221531041 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3098137739 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 61176984802 ps |
CPU time | 195.66 seconds |
Started | Jul 27 06:48:31 PM PDT 24 |
Finished | Jul 27 06:51:46 PM PDT 24 |
Peak memory | 211892 kb |
Host | smart-57a1147d-d711-421b-8595-2b230652ac4d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098137739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.3098137739 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.1523724714 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 82743104468 ps |
CPU time | 340.9 seconds |
Started | Jul 27 06:48:29 PM PDT 24 |
Finished | Jul 27 06:54:10 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-61ce0980-ce2c-4062-adf9-0755efed5f80 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523724714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.1523724714 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.2752573207 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 76472937764 ps |
CPU time | 869.02 seconds |
Started | Jul 27 06:48:22 PM PDT 24 |
Finished | Jul 27 07:02:51 PM PDT 24 |
Peak memory | 364756 kb |
Host | smart-574e96bb-ebb1-4022-83c1-b516ce9c0451 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752573207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.2752573207 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.1330856455 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 687863662 ps |
CPU time | 6.19 seconds |
Started | Jul 27 06:48:30 PM PDT 24 |
Finished | Jul 27 06:48:36 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-4fd890fe-675b-4c41-b31d-31cfca6be5e3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330856455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.1330856455 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2055899122 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 39264724469 ps |
CPU time | 488.68 seconds |
Started | Jul 27 06:48:31 PM PDT 24 |
Finished | Jul 27 06:56:40 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-3a137448-302d-4636-9f90-6120b5d7485e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055899122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.2055899122 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.2846460198 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 387635736 ps |
CPU time | 3.25 seconds |
Started | Jul 27 06:48:27 PM PDT 24 |
Finished | Jul 27 06:48:30 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-a38fd201-a968-4a2e-871a-1e647bda3bf7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846460198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2846460198 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.948928769 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 12346072148 ps |
CPU time | 1090.55 seconds |
Started | Jul 27 06:48:29 PM PDT 24 |
Finished | Jul 27 07:06:40 PM PDT 24 |
Peak memory | 376092 kb |
Host | smart-cdec58e2-d1f8-40ad-a393-4adc2e083e6e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948928769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.948928769 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.235321921 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 762502189 ps |
CPU time | 8.18 seconds |
Started | Jul 27 06:48:23 PM PDT 24 |
Finished | Jul 27 06:48:31 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-ed8d2a3b-0547-4d97-8c7b-999dda0b23ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235321921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.235321921 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.1462078044 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 54914674970 ps |
CPU time | 5214.23 seconds |
Started | Jul 27 06:48:36 PM PDT 24 |
Finished | Jul 27 08:15:31 PM PDT 24 |
Peak memory | 381044 kb |
Host | smart-43d76c88-18ee-46d6-8da1-0a9e6a40f64a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462078044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.1462078044 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3601419105 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 1947103795 ps |
CPU time | 106.99 seconds |
Started | Jul 27 06:48:30 PM PDT 24 |
Finished | Jul 27 06:50:17 PM PDT 24 |
Peak memory | 365696 kb |
Host | smart-0e6cdf9a-8d27-438c-a3a5-521d924fee7a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3601419105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3601419105 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1100105827 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 4582150685 ps |
CPU time | 231.92 seconds |
Started | Jul 27 06:48:20 PM PDT 24 |
Finished | Jul 27 06:52:12 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-fa7793ed-3307-47e8-95c3-735b4704dfef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100105827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.1100105827 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3829762989 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 3909615711 ps |
CPU time | 126.93 seconds |
Started | Jul 27 06:48:30 PM PDT 24 |
Finished | Jul 27 06:50:37 PM PDT 24 |
Peak memory | 371804 kb |
Host | smart-b13a777d-0af5-463e-bad7-edd5553ccb9b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829762989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3829762989 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.213280108 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 35548249313 ps |
CPU time | 455.1 seconds |
Started | Jul 27 06:48:36 PM PDT 24 |
Finished | Jul 27 06:56:12 PM PDT 24 |
Peak memory | 376020 kb |
Host | smart-548f4aeb-6419-4c04-8744-efb58637ed38 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213280108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 25.sram_ctrl_access_during_key_req.213280108 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.3719417007 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 37654478 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:48:46 PM PDT 24 |
Finished | Jul 27 06:48:47 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-6bc56fa3-4ed3-44a8-b86c-21b5703fbaa7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719417007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.3719417007 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.1721918724 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 64552094605 ps |
CPU time | 1484.12 seconds |
Started | Jul 27 06:48:38 PM PDT 24 |
Finished | Jul 27 07:13:22 PM PDT 24 |
Peak memory | 203432 kb |
Host | smart-eb6d2c55-78d8-4856-a640-302ff4e0d333 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721918724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .1721918724 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.3389140530 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 37453850993 ps |
CPU time | 544.03 seconds |
Started | Jul 27 06:48:37 PM PDT 24 |
Finished | Jul 27 06:57:41 PM PDT 24 |
Peak memory | 369876 kb |
Host | smart-c58b4a50-40f4-44d0-afae-594be170e0ca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389140530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.3389140530 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.2139172030 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 11986693490 ps |
CPU time | 37.41 seconds |
Started | Jul 27 06:48:38 PM PDT 24 |
Finished | Jul 27 06:49:15 PM PDT 24 |
Peak memory | 203404 kb |
Host | smart-7ebf1edf-2891-485c-812b-2b1db3ed3252 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139172030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.2139172030 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.1321008527 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 746802160 ps |
CPU time | 43.41 seconds |
Started | Jul 27 06:48:37 PM PDT 24 |
Finished | Jul 27 06:49:20 PM PDT 24 |
Peak memory | 295288 kb |
Host | smart-7e2f9828-626b-4f39-8679-cb6c3cca663d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321008527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.1321008527 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2458480643 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 1453426075 ps |
CPU time | 75.43 seconds |
Started | Jul 27 06:48:46 PM PDT 24 |
Finished | Jul 27 06:50:02 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-9631c41e-8fde-40ed-9213-1844c644fe67 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458480643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.2458480643 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.2240021282 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 82709303197 ps |
CPU time | 388.71 seconds |
Started | Jul 27 06:48:39 PM PDT 24 |
Finished | Jul 27 06:55:07 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-19bbdc5f-550a-43b3-a0c5-cedbe67f0a4b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240021282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.2240021282 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.173073039 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 5550060167 ps |
CPU time | 435.42 seconds |
Started | Jul 27 06:48:38 PM PDT 24 |
Finished | Jul 27 06:55:54 PM PDT 24 |
Peak memory | 379060 kb |
Host | smart-d231caf0-feae-4318-b1ca-04508f3557f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173073039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multip le_keys.173073039 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.2623864690 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 922039154 ps |
CPU time | 8.8 seconds |
Started | Jul 27 06:48:35 PM PDT 24 |
Finished | Jul 27 06:48:44 PM PDT 24 |
Peak memory | 203000 kb |
Host | smart-47b588eb-9cb3-4942-8708-943f6dba5d34 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623864690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.2623864690 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.651533533 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 14658117109 ps |
CPU time | 316.99 seconds |
Started | Jul 27 06:48:35 PM PDT 24 |
Finished | Jul 27 06:53:53 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-26fa4acd-4c55-408b-a537-9405aace5a44 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651533533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.sram_ctrl_partial_access_b2b.651533533 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.1695045937 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 1529010221 ps |
CPU time | 3.37 seconds |
Started | Jul 27 06:48:35 PM PDT 24 |
Finished | Jul 27 06:48:39 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-22b9c3b9-a9e3-4b7c-a027-5ca890504434 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695045937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1695045937 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.1591641295 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 49624560767 ps |
CPU time | 1532.67 seconds |
Started | Jul 27 06:48:39 PM PDT 24 |
Finished | Jul 27 07:14:11 PM PDT 24 |
Peak memory | 381068 kb |
Host | smart-29ad1001-850a-4cf7-b035-b0d4cac0a395 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591641295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1591641295 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.3105574454 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 1589244033 ps |
CPU time | 10.89 seconds |
Started | Jul 27 06:48:38 PM PDT 24 |
Finished | Jul 27 06:48:49 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-c8ad3636-9c15-4728-af94-576218c3e42d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105574454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3105574454 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.4032887550 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 108266355577 ps |
CPU time | 3830.95 seconds |
Started | Jul 27 06:48:48 PM PDT 24 |
Finished | Jul 27 07:52:39 PM PDT 24 |
Peak memory | 381184 kb |
Host | smart-31ba955b-0700-4181-837f-2d703eebf848 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032887550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.4032887550 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2787293975 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 1492227735 ps |
CPU time | 8.67 seconds |
Started | Jul 27 06:48:47 PM PDT 24 |
Finished | Jul 27 06:48:55 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-ced6135b-a3f1-407f-952a-d0c785b5d20a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2787293975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2787293975 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.362459432 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 3259454267 ps |
CPU time | 204.76 seconds |
Started | Jul 27 06:48:37 PM PDT 24 |
Finished | Jul 27 06:52:02 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-6782ba13-2814-4d6b-b37a-ef9f1e8f85d4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362459432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_stress_pipeline.362459432 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.867444244 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 737366064 ps |
CPU time | 31.66 seconds |
Started | Jul 27 06:48:38 PM PDT 24 |
Finished | Jul 27 06:49:10 PM PDT 24 |
Peak memory | 287356 kb |
Host | smart-d7f985ce-92b5-40b2-bb6b-f5a230ac73df |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867444244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.867444244 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3467982201 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 65120949025 ps |
CPU time | 1087.5 seconds |
Started | Jul 27 06:48:56 PM PDT 24 |
Finished | Jul 27 07:07:03 PM PDT 24 |
Peak memory | 372920 kb |
Host | smart-c132b577-585e-4542-beb0-1c047a478fbd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467982201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.3467982201 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.45245143 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 20582681 ps |
CPU time | 0.64 seconds |
Started | Jul 27 06:48:55 PM PDT 24 |
Finished | Jul 27 06:48:56 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-7f4fb1f7-8873-49f0-aeca-5b71b81c099c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45245143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_alert_test.45245143 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.3639706117 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 200114534107 ps |
CPU time | 1283.37 seconds |
Started | Jul 27 06:48:46 PM PDT 24 |
Finished | Jul 27 07:10:10 PM PDT 24 |
Peak memory | 203824 kb |
Host | smart-a23286d8-d85d-41e6-9e9d-ddd821ae0744 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639706117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .3639706117 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.321815167 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 26055140959 ps |
CPU time | 744.41 seconds |
Started | Jul 27 06:48:55 PM PDT 24 |
Finished | Jul 27 07:01:19 PM PDT 24 |
Peak memory | 379100 kb |
Host | smart-9fe0da49-d519-487a-aa5f-7000dfb531de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321815167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl e.321815167 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.3598711798 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 8942737557 ps |
CPU time | 58.47 seconds |
Started | Jul 27 06:48:48 PM PDT 24 |
Finished | Jul 27 06:49:46 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-9052f437-d988-46cc-bf42-144111fa16d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598711798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.3598711798 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.2170708562 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 2960097459 ps |
CPU time | 32 seconds |
Started | Jul 27 06:48:47 PM PDT 24 |
Finished | Jul 27 06:49:19 PM PDT 24 |
Peak memory | 278608 kb |
Host | smart-d0a5395a-00e8-4e46-97a7-3c93d27bdb79 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170708562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.2170708562 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.3382450607 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 11184403826 ps |
CPU time | 98.52 seconds |
Started | Jul 27 06:48:55 PM PDT 24 |
Finished | Jul 27 06:50:34 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-41a37d62-c3b2-4c77-9ba6-962451df22ea |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382450607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.3382450607 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.675255298 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 7226559158 ps |
CPU time | 155.92 seconds |
Started | Jul 27 06:48:57 PM PDT 24 |
Finished | Jul 27 06:51:33 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-56b0ba6f-f7e6-4a18-9908-8bcee5dcb1a3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675255298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl _mem_walk.675255298 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.3508807666 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 28805621765 ps |
CPU time | 963.57 seconds |
Started | Jul 27 06:48:47 PM PDT 24 |
Finished | Jul 27 07:04:50 PM PDT 24 |
Peak memory | 376988 kb |
Host | smart-bd96568e-0dcd-441d-9273-f2b1b4e1a73c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508807666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.3508807666 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.580450026 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 1143729690 ps |
CPU time | 50.05 seconds |
Started | Jul 27 06:48:49 PM PDT 24 |
Finished | Jul 27 06:49:39 PM PDT 24 |
Peak memory | 306076 kb |
Host | smart-53ceade9-8746-4c50-9ac9-55bba0fe2eab |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580450026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s ram_ctrl_partial_access.580450026 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2861151324 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 91910101921 ps |
CPU time | 592.5 seconds |
Started | Jul 27 06:48:48 PM PDT 24 |
Finished | Jul 27 06:58:40 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-6d433280-25cb-4974-b3c9-44daa70fc57b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861151324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.2861151324 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.91462215 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 1539111292 ps |
CPU time | 3.4 seconds |
Started | Jul 27 06:48:56 PM PDT 24 |
Finished | Jul 27 06:48:59 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-cee7abbb-6648-4474-83d6-7e9043a5c9d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91462215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.91462215 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.1180709506 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 46489669138 ps |
CPU time | 438.51 seconds |
Started | Jul 27 06:48:56 PM PDT 24 |
Finished | Jul 27 06:56:14 PM PDT 24 |
Peak memory | 372916 kb |
Host | smart-d018666c-4937-4411-a63f-7e1f892cbb46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180709506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1180709506 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.205749306 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 849247794 ps |
CPU time | 13.67 seconds |
Started | Jul 27 06:48:48 PM PDT 24 |
Finished | Jul 27 06:49:01 PM PDT 24 |
Peak memory | 236000 kb |
Host | smart-72cf522f-a02e-4843-ba56-eda07494642f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205749306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.205749306 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.1175347692 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 277657080969 ps |
CPU time | 3991.41 seconds |
Started | Jul 27 06:48:56 PM PDT 24 |
Finished | Jul 27 07:55:28 PM PDT 24 |
Peak memory | 381188 kb |
Host | smart-5f9b4bf9-36d6-4d4d-b581-8fcd771c4954 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175347692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.1175347692 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1219820257 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 925991671 ps |
CPU time | 8.42 seconds |
Started | Jul 27 06:48:56 PM PDT 24 |
Finished | Jul 27 06:49:04 PM PDT 24 |
Peak memory | 211372 kb |
Host | smart-02bbec29-b95e-479d-bda1-5822ac3146d6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1219820257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1219820257 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1018340805 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 12415277082 ps |
CPU time | 210.87 seconds |
Started | Jul 27 06:48:47 PM PDT 24 |
Finished | Jul 27 06:52:18 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-7da62ed6-f583-4b99-985c-cbb6f263571b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018340805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.1018340805 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.147837275 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 2997961886 ps |
CPU time | 56.39 seconds |
Started | Jul 27 06:48:46 PM PDT 24 |
Finished | Jul 27 06:49:42 PM PDT 24 |
Peak memory | 319684 kb |
Host | smart-ae4bf860-0d27-4462-a7d4-407bd2ecb434 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147837275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.147837275 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.43174999 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 20987780921 ps |
CPU time | 555.72 seconds |
Started | Jul 27 06:49:04 PM PDT 24 |
Finished | Jul 27 06:58:20 PM PDT 24 |
Peak memory | 379036 kb |
Host | smart-224ff984-a642-486c-af20-ceee09cc765a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43174999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.sram_ctrl_access_during_key_req.43174999 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.2147775384 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 59984844 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:49:15 PM PDT 24 |
Finished | Jul 27 06:49:15 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-400e26d7-2207-4dcd-92e2-9c9b5ac20ca3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147775384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.2147775384 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.2704661792 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 120099994795 ps |
CPU time | 1168.73 seconds |
Started | Jul 27 06:49:03 PM PDT 24 |
Finished | Jul 27 07:08:32 PM PDT 24 |
Peak memory | 203880 kb |
Host | smart-6a7c9965-150a-46e8-9437-fd9f9ea9736f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704661792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .2704661792 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.2449140995 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 8121675537 ps |
CPU time | 233.19 seconds |
Started | Jul 27 06:49:05 PM PDT 24 |
Finished | Jul 27 06:52:59 PM PDT 24 |
Peak memory | 324088 kb |
Host | smart-feb3baf0-d1cb-41bf-8b13-542eb1c34970 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449140995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.2449140995 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.2122556298 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 44193209386 ps |
CPU time | 69.77 seconds |
Started | Jul 27 06:49:07 PM PDT 24 |
Finished | Jul 27 06:50:17 PM PDT 24 |
Peak memory | 211344 kb |
Host | smart-7d3c9d28-b656-4be3-be76-5049fcbd7121 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122556298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.2122556298 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.3674808242 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 1450748140 ps |
CPU time | 15.41 seconds |
Started | Jul 27 06:49:06 PM PDT 24 |
Finished | Jul 27 06:49:22 PM PDT 24 |
Peak memory | 252232 kb |
Host | smart-b19c80e1-d67c-427c-97ca-5c74105aeea4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674808242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.3674808242 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.774980278 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 18163064109 ps |
CPU time | 75.5 seconds |
Started | Jul 27 06:49:04 PM PDT 24 |
Finished | Jul 27 06:50:20 PM PDT 24 |
Peak memory | 214028 kb |
Host | smart-112dbf7e-3a5d-47a9-b84d-d64c0bc33045 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774980278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_mem_partial_access.774980278 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.1126177860 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 21320109112 ps |
CPU time | 345.57 seconds |
Started | Jul 27 06:49:02 PM PDT 24 |
Finished | Jul 27 06:54:48 PM PDT 24 |
Peak memory | 204344 kb |
Host | smart-e4c63c8e-7221-4b75-b467-bf65ca11950a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126177860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.1126177860 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.3569168729 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 12246959906 ps |
CPU time | 1416.5 seconds |
Started | Jul 27 06:49:07 PM PDT 24 |
Finished | Jul 27 07:12:44 PM PDT 24 |
Peak memory | 372944 kb |
Host | smart-a0c3ec91-4375-4409-9468-4948c2e307ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569168729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.3569168729 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.2012748530 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 966106140 ps |
CPU time | 14.04 seconds |
Started | Jul 27 06:49:05 PM PDT 24 |
Finished | Jul 27 06:49:19 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-45d491ff-f7e6-48b9-966b-9c98c6b51cc5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012748530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.2012748530 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2065716908 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 27627367802 ps |
CPU time | 373.57 seconds |
Started | Jul 27 06:49:03 PM PDT 24 |
Finished | Jul 27 06:55:17 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-49e9b9c7-8bbe-4151-b959-af36553fbe44 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065716908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.2065716908 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.2186841754 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 711194690 ps |
CPU time | 3.4 seconds |
Started | Jul 27 06:49:06 PM PDT 24 |
Finished | Jul 27 06:49:09 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-d8a9a254-fbe4-4379-a48d-b8523ecc1dee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186841754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2186841754 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.402541914 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 10073092375 ps |
CPU time | 769.72 seconds |
Started | Jul 27 06:49:03 PM PDT 24 |
Finished | Jul 27 07:01:52 PM PDT 24 |
Peak memory | 366800 kb |
Host | smart-b089f89f-1e93-449d-b69b-40ad8b9bd050 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402541914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.402541914 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.187636404 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 656874011 ps |
CPU time | 5.37 seconds |
Started | Jul 27 06:48:54 PM PDT 24 |
Finished | Jul 27 06:48:59 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-208bc66e-63cb-4561-bb26-159003148251 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187636404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.187636404 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.1863137700 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 46310478606 ps |
CPU time | 2703.73 seconds |
Started | Jul 27 06:49:13 PM PDT 24 |
Finished | Jul 27 07:34:17 PM PDT 24 |
Peak memory | 380468 kb |
Host | smart-07d06d3c-1745-4d26-b6e4-535062b11515 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863137700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.1863137700 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2737754208 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 5632101591 ps |
CPU time | 141.37 seconds |
Started | Jul 27 06:49:05 PM PDT 24 |
Finished | Jul 27 06:51:26 PM PDT 24 |
Peak memory | 353548 kb |
Host | smart-a8f26ee4-c8e3-4d1b-8d97-ed93a03ca695 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2737754208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2737754208 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3823972480 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 4001791899 ps |
CPU time | 242.92 seconds |
Started | Jul 27 06:49:03 PM PDT 24 |
Finished | Jul 27 06:53:06 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-593fb312-deea-4a6a-acbc-316198e1bd54 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823972480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.3823972480 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.646297936 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 1502788348 ps |
CPU time | 99.69 seconds |
Started | Jul 27 06:49:04 PM PDT 24 |
Finished | Jul 27 06:50:43 PM PDT 24 |
Peak memory | 372792 kb |
Host | smart-dfd51973-1b72-4248-9a47-6cc6a8ac931f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646297936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_throughput_w_partial_write.646297936 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1169552226 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 14099634729 ps |
CPU time | 1153.65 seconds |
Started | Jul 27 06:49:13 PM PDT 24 |
Finished | Jul 27 07:08:27 PM PDT 24 |
Peak memory | 375884 kb |
Host | smart-f93aa04f-8a91-48e5-9b4a-4eb6824f0abf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169552226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.1169552226 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.2490774350 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 35447301 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:49:21 PM PDT 24 |
Finished | Jul 27 06:49:22 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-6a0f784b-d372-474f-9688-27db4b14e5f6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490774350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.2490774350 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.2323818392 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 50808584781 ps |
CPU time | 1182.72 seconds |
Started | Jul 27 06:49:13 PM PDT 24 |
Finished | Jul 27 07:08:56 PM PDT 24 |
Peak memory | 203980 kb |
Host | smart-bb8479d1-8710-4369-89aa-3a10eaccfa6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323818392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .2323818392 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.2319549767 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 23553918117 ps |
CPU time | 1137.08 seconds |
Started | Jul 27 06:49:14 PM PDT 24 |
Finished | Jul 27 07:08:11 PM PDT 24 |
Peak memory | 374004 kb |
Host | smart-0cbf19b7-248a-47e9-a1d5-8443334ede98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319549767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.2319549767 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.763252585 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 7207789674 ps |
CPU time | 40.87 seconds |
Started | Jul 27 06:49:14 PM PDT 24 |
Finished | Jul 27 06:49:55 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-a9be31f2-2a20-4def-a5ed-1b8092e256c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763252585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc alation.763252585 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.1563223370 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 1525926485 ps |
CPU time | 83.99 seconds |
Started | Jul 27 06:49:13 PM PDT 24 |
Finished | Jul 27 06:50:37 PM PDT 24 |
Peak memory | 341200 kb |
Host | smart-0877d145-b700-4f8c-8bed-e7bba36be86f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563223370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.1563223370 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.959519733 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 11103033115 ps |
CPU time | 90.89 seconds |
Started | Jul 27 06:49:13 PM PDT 24 |
Finished | Jul 27 06:50:44 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-e467b8eb-d5cf-4214-a3c0-cd487b48d448 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959519733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .sram_ctrl_mem_partial_access.959519733 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.2968948593 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 7898661042 ps |
CPU time | 132.87 seconds |
Started | Jul 27 06:49:14 PM PDT 24 |
Finished | Jul 27 06:51:27 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-f67657a0-c629-40db-b878-f4223d2291d1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968948593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.2968948593 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.1225486249 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 161995023031 ps |
CPU time | 1688.6 seconds |
Started | Jul 27 06:49:15 PM PDT 24 |
Finished | Jul 27 07:17:23 PM PDT 24 |
Peak memory | 380056 kb |
Host | smart-44a44ce8-6bf2-421e-9b97-002cfe787e84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225486249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.1225486249 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.339320541 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 3476888767 ps |
CPU time | 9.28 seconds |
Started | Jul 27 06:49:12 PM PDT 24 |
Finished | Jul 27 06:49:22 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-3f5ce0b3-74af-407f-a266-5e079cf01779 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339320541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s ram_ctrl_partial_access.339320541 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1572677431 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 25650158254 ps |
CPU time | 287.69 seconds |
Started | Jul 27 06:49:13 PM PDT 24 |
Finished | Jul 27 06:54:01 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-dc263a10-73cc-4c62-9324-eb7580687d2e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572677431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.1572677431 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.1654787176 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 376149942 ps |
CPU time | 2.96 seconds |
Started | Jul 27 06:49:14 PM PDT 24 |
Finished | Jul 27 06:49:17 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-c9f8f4d4-176e-47ab-89ca-7adf56699423 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654787176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1654787176 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.3859571948 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 44343522131 ps |
CPU time | 766.57 seconds |
Started | Jul 27 06:49:13 PM PDT 24 |
Finished | Jul 27 07:01:59 PM PDT 24 |
Peak memory | 365688 kb |
Host | smart-b4f4da2a-bbe6-4300-baef-362ba9e6e781 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859571948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3859571948 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.3545598169 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 7785580415 ps |
CPU time | 19.93 seconds |
Started | Jul 27 06:49:16 PM PDT 24 |
Finished | Jul 27 06:49:36 PM PDT 24 |
Peak memory | 255784 kb |
Host | smart-2fabb7df-7ea5-4274-8b13-924f67f26ff1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545598169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3545598169 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.4192709922 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 72227420613 ps |
CPU time | 1908.21 seconds |
Started | Jul 27 06:49:21 PM PDT 24 |
Finished | Jul 27 07:21:09 PM PDT 24 |
Peak memory | 382316 kb |
Host | smart-31068330-d12b-4c0e-842d-69bd3af27290 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192709922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.4192709922 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.51523968 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 610236594 ps |
CPU time | 15.23 seconds |
Started | Jul 27 06:49:14 PM PDT 24 |
Finished | Jul 27 06:49:29 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-d39ca783-3b0e-4e66-8260-91d6f1d87dd0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=51523968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.51523968 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2506606515 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 5901723286 ps |
CPU time | 174.61 seconds |
Started | Jul 27 06:49:12 PM PDT 24 |
Finished | Jul 27 06:52:07 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-0d8fd621-b319-4563-8ab9-4695f8ccf643 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506606515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.2506606515 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.356216381 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 2966864355 ps |
CPU time | 53.28 seconds |
Started | Jul 27 06:49:14 PM PDT 24 |
Finished | Jul 27 06:50:07 PM PDT 24 |
Peak memory | 305416 kb |
Host | smart-c65efec5-d7f8-4396-b65a-8fce7769bffb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356216381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_throughput_w_partial_write.356216381 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.374894175 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 49610863980 ps |
CPU time | 611.52 seconds |
Started | Jul 27 06:49:30 PM PDT 24 |
Finished | Jul 27 06:59:41 PM PDT 24 |
Peak memory | 378024 kb |
Host | smart-e8f002c2-e1af-4244-86b9-e4b336e9501c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374894175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 29.sram_ctrl_access_during_key_req.374894175 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.2422023292 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 17750402 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:49:29 PM PDT 24 |
Finished | Jul 27 06:49:30 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-136a4bc8-6121-4e0f-a1d2-15ef68f06de8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422023292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.2422023292 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.1915435455 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 170557021502 ps |
CPU time | 2800.14 seconds |
Started | Jul 27 06:49:22 PM PDT 24 |
Finished | Jul 27 07:36:02 PM PDT 24 |
Peak memory | 203836 kb |
Host | smart-1480f4cc-fbab-426e-8128-f03958650b0e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915435455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .1915435455 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.3114193894 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 30129359935 ps |
CPU time | 258.45 seconds |
Started | Jul 27 06:49:31 PM PDT 24 |
Finished | Jul 27 06:53:50 PM PDT 24 |
Peak memory | 354500 kb |
Host | smart-03fc6dcc-c33a-4685-bcda-4bf91e361465 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114193894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.3114193894 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.4006673672 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 48907310280 ps |
CPU time | 110.76 seconds |
Started | Jul 27 06:49:20 PM PDT 24 |
Finished | Jul 27 06:51:11 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-68e89ba6-9ab7-4c4c-9d5b-821095be66cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006673672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.4006673672 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.556857057 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 2891145494 ps |
CPU time | 43.36 seconds |
Started | Jul 27 06:49:22 PM PDT 24 |
Finished | Jul 27 06:50:06 PM PDT 24 |
Peak memory | 292196 kb |
Host | smart-c17806b8-d0e5-4c7b-85f7-98408a2e9dda |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556857057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.sram_ctrl_max_throughput.556857057 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.4241873799 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 2789901662 ps |
CPU time | 84.58 seconds |
Started | Jul 27 06:49:29 PM PDT 24 |
Finished | Jul 27 06:50:54 PM PDT 24 |
Peak memory | 219552 kb |
Host | smart-ec876980-54db-45f4-8f82-acf305653d7c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241873799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.4241873799 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.904985646 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 23013089733 ps |
CPU time | 346.4 seconds |
Started | Jul 27 06:49:29 PM PDT 24 |
Finished | Jul 27 06:55:16 PM PDT 24 |
Peak memory | 212156 kb |
Host | smart-092fe5cc-ebfe-4dc2-8c28-1998bf68393e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904985646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _mem_walk.904985646 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.3375163219 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 38731777061 ps |
CPU time | 1016.95 seconds |
Started | Jul 27 06:49:22 PM PDT 24 |
Finished | Jul 27 07:06:19 PM PDT 24 |
Peak memory | 379052 kb |
Host | smart-3803511d-a41f-48c8-b0c6-8553219cdc8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375163219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.3375163219 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.3768728209 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 4390649845 ps |
CPU time | 23.66 seconds |
Started | Jul 27 06:49:21 PM PDT 24 |
Finished | Jul 27 06:49:44 PM PDT 24 |
Peak memory | 203056 kb |
Host | smart-7074e20c-bdda-4203-a257-ebc92f39ace7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768728209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.3768728209 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2032957324 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 6441693424 ps |
CPU time | 261.16 seconds |
Started | Jul 27 06:49:22 PM PDT 24 |
Finished | Jul 27 06:53:43 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-29a34020-76d2-4432-918a-d991af7d63b7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032957324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.2032957324 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.410292234 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 357453866 ps |
CPU time | 3.36 seconds |
Started | Jul 27 06:49:29 PM PDT 24 |
Finished | Jul 27 06:49:33 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-424e8074-746b-44a3-a24d-7bbc8e88bb55 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410292234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.410292234 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.4064294880 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 16258996276 ps |
CPU time | 2421.42 seconds |
Started | Jul 27 06:49:27 PM PDT 24 |
Finished | Jul 27 07:29:50 PM PDT 24 |
Peak memory | 377052 kb |
Host | smart-6f9a2c54-b08c-46d7-bdea-abc1758d869c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064294880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.4064294880 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.1296808739 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 2644436686 ps |
CPU time | 115.24 seconds |
Started | Jul 27 06:49:21 PM PDT 24 |
Finished | Jul 27 06:51:16 PM PDT 24 |
Peak memory | 369760 kb |
Host | smart-bac4e066-d446-4eff-af2b-56a0e0264079 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296808739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1296808739 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.1858811606 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 1792652457159 ps |
CPU time | 3277.02 seconds |
Started | Jul 27 06:49:32 PM PDT 24 |
Finished | Jul 27 07:44:09 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-68e7d8d9-a510-4d80-a3f6-b66ff0e08a86 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858811606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.1858811606 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1407145503 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 5761094546 ps |
CPU time | 50.77 seconds |
Started | Jul 27 06:49:32 PM PDT 24 |
Finished | Jul 27 06:50:23 PM PDT 24 |
Peak memory | 211460 kb |
Host | smart-7783f00a-7972-48d6-bb2e-ce06f8f2a9bd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1407145503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1407145503 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3527418066 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 14328050262 ps |
CPU time | 302.99 seconds |
Started | Jul 27 06:49:20 PM PDT 24 |
Finished | Jul 27 06:54:23 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-51a78805-7413-466f-8823-361fce3a9092 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527418066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3527418066 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1689236378 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 793172149 ps |
CPU time | 90.75 seconds |
Started | Jul 27 06:49:21 PM PDT 24 |
Finished | Jul 27 06:50:52 PM PDT 24 |
Peak memory | 347504 kb |
Host | smart-6c33c9a3-7a04-4861-87f1-da2621def6a9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689236378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1689236378 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1250104709 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 42530849059 ps |
CPU time | 604.5 seconds |
Started | Jul 27 06:45:09 PM PDT 24 |
Finished | Jul 27 06:55:14 PM PDT 24 |
Peak memory | 372828 kb |
Host | smart-8cadcbc7-0741-49e5-a4a2-b3bf0d96116f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250104709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.1250104709 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.1472673379 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 22398734 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:45:21 PM PDT 24 |
Finished | Jul 27 06:45:22 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-71ce2a4d-ba2c-4585-a98a-56106dcd3c45 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472673379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1472673379 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.144528472 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 649230049475 ps |
CPU time | 775.07 seconds |
Started | Jul 27 06:45:11 PM PDT 24 |
Finished | Jul 27 06:58:07 PM PDT 24 |
Peak memory | 203984 kb |
Host | smart-0b39cb91-1156-4d86-bd08-ea887cd8ff33 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144528472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.144528472 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.3169167111 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 10486039647 ps |
CPU time | 187.29 seconds |
Started | Jul 27 06:45:15 PM PDT 24 |
Finished | Jul 27 06:48:22 PM PDT 24 |
Peak memory | 359336 kb |
Host | smart-8381bbc9-d1b9-495e-a37d-aa5ee42cad1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169167111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.3169167111 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.1332441774 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 27883114431 ps |
CPU time | 46.16 seconds |
Started | Jul 27 06:45:13 PM PDT 24 |
Finished | Jul 27 06:46:00 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-2b3daab3-70b8-4e8a-8671-ecf3fb3d896b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332441774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.1332441774 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.1519190733 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 690521461 ps |
CPU time | 7.17 seconds |
Started | Jul 27 06:45:15 PM PDT 24 |
Finished | Jul 27 06:45:22 PM PDT 24 |
Peak memory | 216932 kb |
Host | smart-8d779003-4b4d-4420-a2b1-9cb28763a7e8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519190733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.1519190733 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.3395621710 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 10356030380 ps |
CPU time | 173.44 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:48:05 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-22a1e577-ed6c-4a57-9e5b-cbf195d0faff |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395621710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.3395621710 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.2675253653 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 87213057341 ps |
CPU time | 1147.95 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 07:04:20 PM PDT 24 |
Peak memory | 381092 kb |
Host | smart-4aad3a1d-6ba5-4651-a68f-a7f519f99281 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675253653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.2675253653 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.3177644445 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 13130142744 ps |
CPU time | 53.93 seconds |
Started | Jul 27 06:45:15 PM PDT 24 |
Finished | Jul 27 06:46:09 PM PDT 24 |
Peak memory | 321704 kb |
Host | smart-d88fb860-b082-4ea4-a1f1-38f12db549ef |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177644445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.3177644445 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3932171658 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 32126068174 ps |
CPU time | 213.03 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:48:45 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-69a3a78d-1021-455d-8f36-79f3af33a581 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932171658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.3932171658 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.3066275195 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 390972342 ps |
CPU time | 3.16 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:45:15 PM PDT 24 |
Peak memory | 203008 kb |
Host | smart-b15cfb5f-9242-49bf-a2ee-0f4e0efb8266 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066275195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3066275195 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.3651735571 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 2619698509 ps |
CPU time | 308.87 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:50:21 PM PDT 24 |
Peak memory | 365740 kb |
Host | smart-a5daeed9-9051-462d-ba53-e1dc780e4b36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651735571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.3651735571 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.994294860 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 336316938 ps |
CPU time | 2.49 seconds |
Started | Jul 27 06:45:19 PM PDT 24 |
Finished | Jul 27 06:45:22 PM PDT 24 |
Peak memory | 222304 kb |
Host | smart-5a75c5be-57d8-426e-801f-2b995d53efa9 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994294860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_sec_cm.994294860 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.23647368 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 799745964 ps |
CPU time | 63.05 seconds |
Started | Jul 27 06:45:12 PM PDT 24 |
Finished | Jul 27 06:46:15 PM PDT 24 |
Peak memory | 331904 kb |
Host | smart-3209417e-3b6b-41a1-92fd-8235739a8bfb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23647368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.23647368 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.3357675477 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 62196358573 ps |
CPU time | 4378.99 seconds |
Started | Jul 27 06:45:10 PM PDT 24 |
Finished | Jul 27 07:58:09 PM PDT 24 |
Peak memory | 382328 kb |
Host | smart-151d07bf-191a-4c5e-8b5f-e76572ef604b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357675477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.3357675477 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2979541032 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 1975422147 ps |
CPU time | 52.89 seconds |
Started | Jul 27 06:45:10 PM PDT 24 |
Finished | Jul 27 06:46:03 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-514ac920-986d-4142-accd-a0af1a676b4e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2979541032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2979541032 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.535368028 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 23497470571 ps |
CPU time | 295.76 seconds |
Started | Jul 27 06:45:10 PM PDT 24 |
Finished | Jul 27 06:50:06 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-7c9b2841-35f0-43a9-bbfc-6efcb0e3ddf4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535368028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_stress_pipeline.535368028 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1476545889 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 1517579183 ps |
CPU time | 62.4 seconds |
Started | Jul 27 06:45:13 PM PDT 24 |
Finished | Jul 27 06:46:15 PM PDT 24 |
Peak memory | 334028 kb |
Host | smart-e9363758-1bf7-4175-9e93-608d58389bf5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476545889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1476545889 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.428999072 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 13494060891 ps |
CPU time | 387 seconds |
Started | Jul 27 06:49:38 PM PDT 24 |
Finished | Jul 27 06:56:06 PM PDT 24 |
Peak memory | 368868 kb |
Host | smart-baba9b96-919f-4057-8fad-a0c28d052604 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428999072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 30.sram_ctrl_access_during_key_req.428999072 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.1018063350 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 79243834 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:49:46 PM PDT 24 |
Finished | Jul 27 06:49:47 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-56427695-3ff7-4f2c-bb46-9b8dce3fada5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018063350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.1018063350 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.3625491425 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 211761687823 ps |
CPU time | 1232.18 seconds |
Started | Jul 27 06:49:38 PM PDT 24 |
Finished | Jul 27 07:10:11 PM PDT 24 |
Peak memory | 203884 kb |
Host | smart-768f6825-9b99-4a2c-b001-dcbec173ba93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625491425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .3625491425 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.1486900932 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 40066855572 ps |
CPU time | 907.14 seconds |
Started | Jul 27 06:49:38 PM PDT 24 |
Finished | Jul 27 07:04:45 PM PDT 24 |
Peak memory | 379204 kb |
Host | smart-358029ff-2505-4514-a50b-8c6cf7e383e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486900932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.1486900932 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.2483418632 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 20732959094 ps |
CPU time | 32.05 seconds |
Started | Jul 27 06:49:39 PM PDT 24 |
Finished | Jul 27 06:50:11 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-95bfbee6-7119-4e1c-b071-83f124da8603 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483418632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.2483418632 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.3497921798 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 3164975588 ps |
CPU time | 89.92 seconds |
Started | Jul 27 06:49:38 PM PDT 24 |
Finished | Jul 27 06:51:08 PM PDT 24 |
Peak memory | 361652 kb |
Host | smart-74156cfb-e645-475b-ad8f-012cd68b5b6d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497921798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.3497921798 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2308086316 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 4750165682 ps |
CPU time | 160.22 seconds |
Started | Jul 27 06:49:38 PM PDT 24 |
Finished | Jul 27 06:52:19 PM PDT 24 |
Peak memory | 211364 kb |
Host | smart-97e25a3d-e5cb-4453-9dd4-07d274ed7042 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308086316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.2308086316 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.3547761181 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 43133036607 ps |
CPU time | 176.59 seconds |
Started | Jul 27 06:49:39 PM PDT 24 |
Finished | Jul 27 06:52:35 PM PDT 24 |
Peak memory | 211656 kb |
Host | smart-eff1f5ab-531f-4193-90a5-033c9c40a0af |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547761181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.3547761181 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1506313555 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 17460868183 ps |
CPU time | 871.74 seconds |
Started | Jul 27 06:49:38 PM PDT 24 |
Finished | Jul 27 07:04:10 PM PDT 24 |
Peak memory | 380088 kb |
Host | smart-8a8a088a-f926-4699-a604-5f30e36e26ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506313555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1506313555 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.3407622623 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 1546875913 ps |
CPU time | 65.06 seconds |
Started | Jul 27 06:49:37 PM PDT 24 |
Finished | Jul 27 06:50:42 PM PDT 24 |
Peak memory | 310376 kb |
Host | smart-1fbe5d78-7275-4ca2-8675-1ddf1a414db8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407622623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.3407622623 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3121897581 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 5611520319 ps |
CPU time | 327.22 seconds |
Started | Jul 27 06:49:38 PM PDT 24 |
Finished | Jul 27 06:55:06 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-a8b8850a-f3a6-4f0a-abd6-96fd9f79a236 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121897581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3121897581 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.3605827062 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 363933403 ps |
CPU time | 3.36 seconds |
Started | Jul 27 06:49:39 PM PDT 24 |
Finished | Jul 27 06:49:42 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-cef305a9-5e48-4a31-914b-1dfee60f62cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605827062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3605827062 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.1276186129 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 44783692287 ps |
CPU time | 1598.22 seconds |
Started | Jul 27 06:49:37 PM PDT 24 |
Finished | Jul 27 07:16:16 PM PDT 24 |
Peak memory | 377996 kb |
Host | smart-0b5ea408-e17b-4946-b9ab-ccffa4d174a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276186129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1276186129 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.234087820 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 2333744948 ps |
CPU time | 9.56 seconds |
Started | Jul 27 06:49:40 PM PDT 24 |
Finished | Jul 27 06:49:49 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-14cb8b58-90eb-4af0-8196-6dc072efc428 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234087820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.234087820 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.3281439850 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 97424188595 ps |
CPU time | 6760.89 seconds |
Started | Jul 27 06:49:38 PM PDT 24 |
Finished | Jul 27 08:42:20 PM PDT 24 |
Peak memory | 381144 kb |
Host | smart-6f7a75ff-e0f7-4861-bc6d-115deeed3ae7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281439850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.3281439850 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3231858391 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 6770521199 ps |
CPU time | 37.54 seconds |
Started | Jul 27 06:49:38 PM PDT 24 |
Finished | Jul 27 06:50:16 PM PDT 24 |
Peak memory | 212976 kb |
Host | smart-d21b4de0-dd18-428c-9b98-e14d6bff3422 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3231858391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3231858391 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2210055231 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 13341749881 ps |
CPU time | 167.28 seconds |
Started | Jul 27 06:49:37 PM PDT 24 |
Finished | Jul 27 06:52:25 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-b0df94d4-a829-49f9-8faf-7483c5a5683b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210055231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.2210055231 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1942910893 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 1572938152 ps |
CPU time | 76.75 seconds |
Started | Jul 27 06:49:36 PM PDT 24 |
Finished | Jul 27 06:50:53 PM PDT 24 |
Peak memory | 353436 kb |
Host | smart-b1a6c1ce-4aea-4cb2-be30-3b1a42c62c93 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942910893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1942910893 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1814146587 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 88096430589 ps |
CPU time | 1802.45 seconds |
Started | Jul 27 06:49:48 PM PDT 24 |
Finished | Jul 27 07:19:50 PM PDT 24 |
Peak memory | 374716 kb |
Host | smart-803c296f-8bdc-4a25-9d5c-e14c9f18e070 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814146587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.1814146587 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.410852299 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 44038109 ps |
CPU time | 0.67 seconds |
Started | Jul 27 06:49:54 PM PDT 24 |
Finished | Jul 27 06:49:55 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-43b96052-84c8-4df2-9e03-def2a5ddd6fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410852299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.410852299 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.1976957402 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 116111034575 ps |
CPU time | 2133.41 seconds |
Started | Jul 27 06:49:48 PM PDT 24 |
Finished | Jul 27 07:25:22 PM PDT 24 |
Peak memory | 204008 kb |
Host | smart-93503f3e-9cf9-496b-bd8d-5aee7d04c5ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976957402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .1976957402 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.1440221152 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 28266510117 ps |
CPU time | 640.22 seconds |
Started | Jul 27 06:49:56 PM PDT 24 |
Finished | Jul 27 07:00:36 PM PDT 24 |
Peak memory | 378444 kb |
Host | smart-516daf79-43ef-4781-a10e-b72e6ea6173d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440221152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.1440221152 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.2738767948 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 11686130839 ps |
CPU time | 74.52 seconds |
Started | Jul 27 06:49:47 PM PDT 24 |
Finished | Jul 27 06:51:02 PM PDT 24 |
Peak memory | 215196 kb |
Host | smart-3b038ed8-b821-43f2-825a-3c472569d695 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738767948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.2738767948 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.3206476222 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 3057863627 ps |
CPU time | 125.67 seconds |
Started | Jul 27 06:49:47 PM PDT 24 |
Finished | Jul 27 06:51:53 PM PDT 24 |
Peak memory | 371912 kb |
Host | smart-346ceeb1-9ec0-431c-bcb0-372953dda0b4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206476222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.3206476222 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.822931772 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 18284160997 ps |
CPU time | 163.65 seconds |
Started | Jul 27 06:49:54 PM PDT 24 |
Finished | Jul 27 06:52:38 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-a3c92b82-e1c0-4d48-92b9-c266a106accc |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822931772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .sram_ctrl_mem_partial_access.822931772 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.210657284 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 149739827257 ps |
CPU time | 221.82 seconds |
Started | Jul 27 06:49:54 PM PDT 24 |
Finished | Jul 27 06:53:36 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-7cabadaa-c897-432a-b57c-7407d79c17c2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210657284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl _mem_walk.210657284 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.811424234 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 5575031503 ps |
CPU time | 604.81 seconds |
Started | Jul 27 06:49:49 PM PDT 24 |
Finished | Jul 27 06:59:54 PM PDT 24 |
Peak memory | 379012 kb |
Host | smart-a617b1e4-7853-4f56-9010-47054858f07b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811424234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip le_keys.811424234 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.3239900207 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 1593692891 ps |
CPU time | 25.52 seconds |
Started | Jul 27 06:49:46 PM PDT 24 |
Finished | Jul 27 06:50:12 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-1f1991d5-f418-4a6f-9596-d6973af2d06d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239900207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.3239900207 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2577578922 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 31530661196 ps |
CPU time | 449.44 seconds |
Started | Jul 27 06:49:48 PM PDT 24 |
Finished | Jul 27 06:57:18 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-0f675f35-ca8e-4c68-a11f-db12802e599a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577578922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2577578922 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.2220520244 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 753334384 ps |
CPU time | 3.11 seconds |
Started | Jul 27 06:49:56 PM PDT 24 |
Finished | Jul 27 06:50:00 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-3800307e-7641-4781-b49e-11921c3b3ae6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220520244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2220520244 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.2555222062 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 35908656247 ps |
CPU time | 1250.13 seconds |
Started | Jul 27 06:49:53 PM PDT 24 |
Finished | Jul 27 07:10:43 PM PDT 24 |
Peak memory | 379136 kb |
Host | smart-6dd35b24-0481-492d-be02-227bf8c9a0d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555222062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2555222062 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.1990866578 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 3875346802 ps |
CPU time | 10.65 seconds |
Started | Jul 27 06:49:49 PM PDT 24 |
Finished | Jul 27 06:50:00 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-f71a5fa4-233b-4b69-a6a3-984944a90f10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990866578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1990866578 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.3951869338 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 281351820094 ps |
CPU time | 5362.74 seconds |
Started | Jul 27 06:49:55 PM PDT 24 |
Finished | Jul 27 08:19:19 PM PDT 24 |
Peak memory | 380604 kb |
Host | smart-08f8d530-4eee-4c3f-bbed-7247a695a211 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951869338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.3951869338 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1281967043 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 3492433424 ps |
CPU time | 25.93 seconds |
Started | Jul 27 06:49:54 PM PDT 24 |
Finished | Jul 27 06:50:21 PM PDT 24 |
Peak memory | 211408 kb |
Host | smart-c5dc5660-5689-4476-9029-b744a55df629 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1281967043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.1281967043 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3050956955 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 2416529095 ps |
CPU time | 178.22 seconds |
Started | Jul 27 06:49:47 PM PDT 24 |
Finished | Jul 27 06:52:46 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-8ce52079-b3e8-4416-b6cb-0a72db90d01f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050956955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.3050956955 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3416177022 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 2192860947 ps |
CPU time | 82.68 seconds |
Started | Jul 27 06:49:47 PM PDT 24 |
Finished | Jul 27 06:51:10 PM PDT 24 |
Peak memory | 342204 kb |
Host | smart-8e15ece0-6867-4888-a248-dc12a7d701b3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416177022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.3416177022 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1735984980 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 18937533020 ps |
CPU time | 403 seconds |
Started | Jul 27 06:50:04 PM PDT 24 |
Finished | Jul 27 06:56:47 PM PDT 24 |
Peak memory | 378028 kb |
Host | smart-b8feb499-a252-4bde-8ccb-3914cdeec410 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735984980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.1735984980 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.1191636752 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 22935790 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:50:07 PM PDT 24 |
Finished | Jul 27 06:50:07 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-145e9b3f-5345-463f-86ff-7da47d4f5ef8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191636752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1191636752 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.3742378148 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 18433121164 ps |
CPU time | 688.38 seconds |
Started | Jul 27 06:49:55 PM PDT 24 |
Finished | Jul 27 07:01:24 PM PDT 24 |
Peak memory | 204096 kb |
Host | smart-aee3596a-6755-42ca-b91a-3674416da7a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742378148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .3742378148 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.1850662691 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 21236725175 ps |
CPU time | 526.62 seconds |
Started | Jul 27 06:50:06 PM PDT 24 |
Finished | Jul 27 06:58:53 PM PDT 24 |
Peak memory | 364936 kb |
Host | smart-5d868a15-6b39-4d32-8f5d-a597dcb14ff3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850662691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.1850662691 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.920494973 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 11875415101 ps |
CPU time | 80.1 seconds |
Started | Jul 27 06:49:53 PM PDT 24 |
Finished | Jul 27 06:51:13 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-8b11bfca-4439-44b3-9fdf-df8b22ac249f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920494973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_esc alation.920494973 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.568358620 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 3011891560 ps |
CPU time | 15.01 seconds |
Started | Jul 27 06:49:55 PM PDT 24 |
Finished | Jul 27 06:50:10 PM PDT 24 |
Peak memory | 244772 kb |
Host | smart-f9712f30-7dfb-4b6a-b02b-0e5538129b35 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568358620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.sram_ctrl_max_throughput.568358620 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2754343508 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 10242760755 ps |
CPU time | 166.83 seconds |
Started | Jul 27 06:50:05 PM PDT 24 |
Finished | Jul 27 06:52:52 PM PDT 24 |
Peak memory | 211460 kb |
Host | smart-bb85fe12-aa4f-4489-ad58-f50b0beabdcf |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754343508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.2754343508 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.2644192514 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 28841971168 ps |
CPU time | 163.01 seconds |
Started | Jul 27 06:50:06 PM PDT 24 |
Finished | Jul 27 06:52:49 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-8f4bbd69-93ee-4796-a2d2-0d28e7b99186 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644192514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.2644192514 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.3147259866 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 33861291788 ps |
CPU time | 647.21 seconds |
Started | Jul 27 06:49:54 PM PDT 24 |
Finished | Jul 27 07:00:41 PM PDT 24 |
Peak memory | 377332 kb |
Host | smart-36c2cea3-9e4a-43ee-aa3b-dbdb69d6ebf6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147259866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.3147259866 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1770086961 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 8687371739 ps |
CPU time | 72.59 seconds |
Started | Jul 27 06:49:56 PM PDT 24 |
Finished | Jul 27 06:51:08 PM PDT 24 |
Peak memory | 311540 kb |
Host | smart-ef623826-5037-412f-bb67-ef214ca0ca84 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770086961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1770086961 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1121687800 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 78203413615 ps |
CPU time | 470.71 seconds |
Started | Jul 27 06:49:55 PM PDT 24 |
Finished | Jul 27 06:57:46 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-38a41332-6d99-413e-b251-0dc0d9d31eaa |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121687800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.1121687800 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.312775003 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 346861790 ps |
CPU time | 3.25 seconds |
Started | Jul 27 06:50:08 PM PDT 24 |
Finished | Jul 27 06:50:11 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-33f4a79c-4056-4f11-b5e3-8bf9c7b525c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312775003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.312775003 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.4100317692 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 47434168587 ps |
CPU time | 773.76 seconds |
Started | Jul 27 06:50:07 PM PDT 24 |
Finished | Jul 27 07:03:01 PM PDT 24 |
Peak memory | 380096 kb |
Host | smart-2056bdb0-8ff2-4c61-a6cb-f1ae24d0e2ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100317692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.4100317692 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.1333004263 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 787422819 ps |
CPU time | 56.2 seconds |
Started | Jul 27 06:49:54 PM PDT 24 |
Finished | Jul 27 06:50:50 PM PDT 24 |
Peak memory | 335040 kb |
Host | smart-4e27ae4b-f788-44b0-a80c-6b451b3e7d73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333004263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1333004263 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.1153719227 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 114671812763 ps |
CPU time | 2210.71 seconds |
Started | Jul 27 06:50:08 PM PDT 24 |
Finished | Jul 27 07:26:59 PM PDT 24 |
Peak memory | 380080 kb |
Host | smart-42918a41-bb69-4dae-8d2f-76ddddbaf9da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153719227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.1153719227 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2456222186 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 200849593 ps |
CPU time | 7.16 seconds |
Started | Jul 27 06:50:04 PM PDT 24 |
Finished | Jul 27 06:50:12 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-2b4526f7-5f20-48f5-adba-34e7d64a64ab |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2456222186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.2456222186 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3582811043 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 3542749371 ps |
CPU time | 167.46 seconds |
Started | Jul 27 06:49:55 PM PDT 24 |
Finished | Jul 27 06:52:43 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-a5d42c54-8906-4a83-9029-649c8e5671a9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582811043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.3582811043 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.840511183 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 790231321 ps |
CPU time | 68.28 seconds |
Started | Jul 27 06:49:58 PM PDT 24 |
Finished | Jul 27 06:51:06 PM PDT 24 |
Peak memory | 344192 kb |
Host | smart-e89abf02-e3d2-428b-9d61-dae263886f78 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840511183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_throughput_w_partial_write.840511183 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1984711742 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 11623925019 ps |
CPU time | 276.31 seconds |
Started | Jul 27 06:50:17 PM PDT 24 |
Finished | Jul 27 06:54:53 PM PDT 24 |
Peak memory | 349276 kb |
Host | smart-c6054d8f-11f2-40f5-814e-f03a82cd5d6b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984711742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.1984711742 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.2847591425 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 48123923 ps |
CPU time | 0.64 seconds |
Started | Jul 27 06:50:22 PM PDT 24 |
Finished | Jul 27 06:50:23 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-8b53179b-9bb7-4c4d-9744-ea2656453c11 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847591425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.2847591425 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.2294368955 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 33462704355 ps |
CPU time | 2250.43 seconds |
Started | Jul 27 06:50:15 PM PDT 24 |
Finished | Jul 27 07:27:46 PM PDT 24 |
Peak memory | 203964 kb |
Host | smart-fd747bd5-7ff9-491d-8bbb-1be1445149b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294368955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .2294368955 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.3437344263 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 25047583373 ps |
CPU time | 1181.29 seconds |
Started | Jul 27 06:50:17 PM PDT 24 |
Finished | Jul 27 07:09:58 PM PDT 24 |
Peak memory | 380036 kb |
Host | smart-58ddb8e7-ca80-4567-8f2b-26cb574e4bb0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437344263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.3437344263 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.3699765773 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 22186588950 ps |
CPU time | 35.7 seconds |
Started | Jul 27 06:50:17 PM PDT 24 |
Finished | Jul 27 06:50:53 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-6bf5e9bd-f38b-45c2-b5b7-34e0d85f270b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699765773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.3699765773 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.1866544176 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 764466835 ps |
CPU time | 104 seconds |
Started | Jul 27 06:50:19 PM PDT 24 |
Finished | Jul 27 06:52:03 PM PDT 24 |
Peak memory | 355376 kb |
Host | smart-2b391402-1a54-4958-a434-56eff2f8959c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866544176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.1866544176 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.715400954 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 968139111 ps |
CPU time | 65.98 seconds |
Started | Jul 27 06:50:24 PM PDT 24 |
Finished | Jul 27 06:51:30 PM PDT 24 |
Peak memory | 219476 kb |
Host | smart-a079bcd3-cc32-4c31-ad68-e3c51f30fcb9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715400954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .sram_ctrl_mem_partial_access.715400954 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.666925684 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 2634542418 ps |
CPU time | 151.68 seconds |
Started | Jul 27 06:50:25 PM PDT 24 |
Finished | Jul 27 06:52:56 PM PDT 24 |
Peak memory | 211484 kb |
Host | smart-bcb3f211-d5c5-4435-af35-689e3e5944b3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666925684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl _mem_walk.666925684 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.980390259 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 69843342034 ps |
CPU time | 1718.76 seconds |
Started | Jul 27 06:50:17 PM PDT 24 |
Finished | Jul 27 07:18:56 PM PDT 24 |
Peak memory | 378892 kb |
Host | smart-d0db75c8-5a9f-44b0-b5c7-04ece1eb289c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980390259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip le_keys.980390259 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.223393990 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 770027192 ps |
CPU time | 9.58 seconds |
Started | Jul 27 06:50:16 PM PDT 24 |
Finished | Jul 27 06:50:26 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-528d2f5c-8f73-4d4f-8a52-8431183ea2b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223393990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s ram_ctrl_partial_access.223393990 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1426582606 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 89438251304 ps |
CPU time | 509.73 seconds |
Started | Jul 27 06:50:18 PM PDT 24 |
Finished | Jul 27 06:58:47 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-265bb94f-9a3e-4c7f-9a31-0a211f027e95 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426582606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.1426582606 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.2362738566 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 404218180 ps |
CPU time | 3.23 seconds |
Started | Jul 27 06:50:25 PM PDT 24 |
Finished | Jul 27 06:50:28 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-f4318894-caae-489b-b388-773f87cffe94 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362738566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2362738566 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.303693377 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 45822784324 ps |
CPU time | 773.67 seconds |
Started | Jul 27 06:50:23 PM PDT 24 |
Finished | Jul 27 07:03:17 PM PDT 24 |
Peak memory | 358576 kb |
Host | smart-3f0e7da5-b33c-4731-881f-4388755c404c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303693377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.303693377 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.2547208401 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 857205147 ps |
CPU time | 8.72 seconds |
Started | Jul 27 06:50:17 PM PDT 24 |
Finished | Jul 27 06:50:26 PM PDT 24 |
Peak memory | 223696 kb |
Host | smart-1be54d76-fe4f-4dc4-a95b-443f944a545d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547208401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2547208401 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.3925000242 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 373197474103 ps |
CPU time | 7266.69 seconds |
Started | Jul 27 06:50:26 PM PDT 24 |
Finished | Jul 27 08:51:34 PM PDT 24 |
Peak memory | 382160 kb |
Host | smart-31b40349-226a-41f9-a3d5-8820bf06851b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925000242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.3925000242 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1810602552 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 7274568957 ps |
CPU time | 170.75 seconds |
Started | Jul 27 06:50:27 PM PDT 24 |
Finished | Jul 27 06:53:18 PM PDT 24 |
Peak memory | 334160 kb |
Host | smart-8226a614-63c2-4afd-bf40-984109a2a4b4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1810602552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1810602552 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3536787659 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 10435727736 ps |
CPU time | 290.75 seconds |
Started | Jul 27 06:50:17 PM PDT 24 |
Finished | Jul 27 06:55:08 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-30b7b3fc-0c39-4f7d-adea-97ebd8e9277b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536787659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.3536787659 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1953061523 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 773964389 ps |
CPU time | 48.16 seconds |
Started | Jul 27 06:50:16 PM PDT 24 |
Finished | Jul 27 06:51:04 PM PDT 24 |
Peak memory | 301204 kb |
Host | smart-c420335c-e368-455d-b897-c626ec61f28a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953061523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1953061523 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2218750086 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 19122390119 ps |
CPU time | 1459.74 seconds |
Started | Jul 27 06:50:35 PM PDT 24 |
Finished | Jul 27 07:14:54 PM PDT 24 |
Peak memory | 373956 kb |
Host | smart-2df941cb-5ae0-4907-9605-4536475a9039 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218750086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.2218750086 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.596513465 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 33590625 ps |
CPU time | 0.64 seconds |
Started | Jul 27 06:50:33 PM PDT 24 |
Finished | Jul 27 06:50:34 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-3f8ad81b-83df-4151-8ef8-f990844bcbcb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596513465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.596513465 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.615278471 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 32804542657 ps |
CPU time | 560.17 seconds |
Started | Jul 27 06:50:26 PM PDT 24 |
Finished | Jul 27 06:59:46 PM PDT 24 |
Peak memory | 203664 kb |
Host | smart-6025db4e-bcbd-47b0-9429-a5199566bc1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615278471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection. 615278471 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.322343651 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 113831431278 ps |
CPU time | 806.42 seconds |
Started | Jul 27 06:50:36 PM PDT 24 |
Finished | Jul 27 07:04:03 PM PDT 24 |
Peak memory | 371816 kb |
Host | smart-ac168ac5-85cd-40bb-ab89-42948c2a1ef4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322343651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executabl e.322343651 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.881613782 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 28947860550 ps |
CPU time | 64.66 seconds |
Started | Jul 27 06:50:31 PM PDT 24 |
Finished | Jul 27 06:51:36 PM PDT 24 |
Peak memory | 211324 kb |
Host | smart-5bbf6260-8247-4ba2-9168-2296c009cabf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881613782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc alation.881613782 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.3310344922 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 760364354 ps |
CPU time | 26.45 seconds |
Started | Jul 27 06:50:26 PM PDT 24 |
Finished | Jul 27 06:50:52 PM PDT 24 |
Peak memory | 271640 kb |
Host | smart-419f6828-8df2-4622-8295-57169cd06623 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310344922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.3310344922 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3719586922 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 4575770226 ps |
CPU time | 149.01 seconds |
Started | Jul 27 06:50:32 PM PDT 24 |
Finished | Jul 27 06:53:01 PM PDT 24 |
Peak memory | 211356 kb |
Host | smart-c9f58170-5a6f-4ada-9d53-6f6fa055f3f1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719586922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.3719586922 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.407702773 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 29221632180 ps |
CPU time | 155.99 seconds |
Started | Jul 27 06:50:33 PM PDT 24 |
Finished | Jul 27 06:53:10 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-04e7b04c-ff15-4d98-ad83-8b0bc2e407c7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407702773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl _mem_walk.407702773 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.122860450 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 17756149090 ps |
CPU time | 484.01 seconds |
Started | Jul 27 06:50:26 PM PDT 24 |
Finished | Jul 27 06:58:31 PM PDT 24 |
Peak memory | 361176 kb |
Host | smart-20c686b5-33ac-49d1-9da2-82629ac8ffda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122860450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multip le_keys.122860450 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.4158028865 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 393082100 ps |
CPU time | 8.57 seconds |
Started | Jul 27 06:50:24 PM PDT 24 |
Finished | Jul 27 06:50:33 PM PDT 24 |
Peak memory | 230696 kb |
Host | smart-9e990483-4f9c-4b88-9bf2-b5d5f006a834 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158028865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.4158028865 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.4221366380 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 8346816876 ps |
CPU time | 443.92 seconds |
Started | Jul 27 06:50:24 PM PDT 24 |
Finished | Jul 27 06:57:48 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-baa7aef2-4ba1-413f-a90d-343d3a06bd02 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221366380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.4221366380 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.745058063 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 366818158 ps |
CPU time | 3.16 seconds |
Started | Jul 27 06:50:32 PM PDT 24 |
Finished | Jul 27 06:50:36 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-e321d536-b806-4335-9045-ec27d9cd4d11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745058063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.745058063 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.2386169081 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 6223581907 ps |
CPU time | 945.31 seconds |
Started | Jul 27 06:50:32 PM PDT 24 |
Finished | Jul 27 07:06:17 PM PDT 24 |
Peak memory | 380152 kb |
Host | smart-d1a62bbe-ccf4-446b-8584-2ccca25f60a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386169081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2386169081 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.38750493 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 817573424 ps |
CPU time | 13.11 seconds |
Started | Jul 27 06:50:25 PM PDT 24 |
Finished | Jul 27 06:50:38 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-dfcb0d45-7a02-47c4-8778-4125cc188822 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38750493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.38750493 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1342023866 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 2170773519 ps |
CPU time | 28.86 seconds |
Started | Jul 27 06:50:33 PM PDT 24 |
Finished | Jul 27 06:51:02 PM PDT 24 |
Peak memory | 211584 kb |
Host | smart-00712d9c-4c27-409b-a491-9c51efa9d044 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1342023866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1342023866 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.281507330 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 5675652430 ps |
CPU time | 383.16 seconds |
Started | Jul 27 06:50:24 PM PDT 24 |
Finished | Jul 27 06:56:48 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-a3eafd5c-ec44-4ea8-8725-8dc44ff5cf94 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281507330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34 .sram_ctrl_stress_pipeline.281507330 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1398807113 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 1418217446 ps |
CPU time | 37.2 seconds |
Started | Jul 27 06:50:36 PM PDT 24 |
Finished | Jul 27 06:51:13 PM PDT 24 |
Peak memory | 301220 kb |
Host | smart-9aed65ff-9e68-4241-ab30-f7e861a7a89d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398807113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1398807113 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.2751783128 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 11772612 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:50:51 PM PDT 24 |
Finished | Jul 27 06:50:51 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-84604a6c-800b-4c36-a66a-d5bae259f896 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751783128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2751783128 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.4173769135 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 32472090133 ps |
CPU time | 744.98 seconds |
Started | Jul 27 06:50:33 PM PDT 24 |
Finished | Jul 27 07:02:58 PM PDT 24 |
Peak memory | 203784 kb |
Host | smart-d391818d-497d-496c-a1ff-5a6e1bd0fe6e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173769135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .4173769135 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.1245690734 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 115995301833 ps |
CPU time | 1339.13 seconds |
Started | Jul 27 06:50:40 PM PDT 24 |
Finished | Jul 27 07:13:00 PM PDT 24 |
Peak memory | 380068 kb |
Host | smart-3c4c5757-8d67-4a85-ba49-2c62c765610b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245690734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.1245690734 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.47447618 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 5625535282 ps |
CPU time | 37.79 seconds |
Started | Jul 27 06:50:40 PM PDT 24 |
Finished | Jul 27 06:51:18 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-a1e59c22-e199-47d1-9b2c-e213e983fd65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47447618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esca lation.47447618 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.1291280463 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 3023338136 ps |
CPU time | 98.13 seconds |
Started | Jul 27 06:50:39 PM PDT 24 |
Finished | Jul 27 06:52:17 PM PDT 24 |
Peak memory | 352436 kb |
Host | smart-dac41b34-85f6-4707-8e0c-b683ebeaa6fa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291280463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.1291280463 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3293990907 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 968054562 ps |
CPU time | 67.55 seconds |
Started | Jul 27 06:50:48 PM PDT 24 |
Finished | Jul 27 06:51:56 PM PDT 24 |
Peak memory | 211328 kb |
Host | smart-88b78816-204a-4dcc-a101-fbde20128143 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293990907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.3293990907 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.3767674751 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 8231398985 ps |
CPU time | 125.53 seconds |
Started | Jul 27 06:50:49 PM PDT 24 |
Finished | Jul 27 06:52:55 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-c9e84c11-6201-4dc0-9d68-69b36dd93646 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767674751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.3767674751 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.850109823 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 29922385437 ps |
CPU time | 1636.46 seconds |
Started | Jul 27 06:50:33 PM PDT 24 |
Finished | Jul 27 07:17:50 PM PDT 24 |
Peak memory | 381136 kb |
Host | smart-a85fb8fd-8563-4687-aca9-39225b2d95e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850109823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip le_keys.850109823 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.2005709996 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 6200785414 ps |
CPU time | 25.85 seconds |
Started | Jul 27 06:50:42 PM PDT 24 |
Finished | Jul 27 06:51:08 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-7d768201-757b-436f-a2f3-54d573ec8ea4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005709996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.2005709996 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3415151413 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 17158261943 ps |
CPU time | 434.31 seconds |
Started | Jul 27 06:50:41 PM PDT 24 |
Finished | Jul 27 06:57:56 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-d9439747-438a-4edc-9095-3bd64d27a1d4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415151413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.3415151413 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.2787317481 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 703057788 ps |
CPU time | 3.18 seconds |
Started | Jul 27 06:50:47 PM PDT 24 |
Finished | Jul 27 06:50:51 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-1b3b7c97-d9fd-47b0-a11d-1918b1effc3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787317481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2787317481 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.4221424313 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 81443915304 ps |
CPU time | 1802.87 seconds |
Started | Jul 27 06:50:42 PM PDT 24 |
Finished | Jul 27 07:20:45 PM PDT 24 |
Peak memory | 374912 kb |
Host | smart-9342d090-1f76-48cc-b86f-b4b8c7ae668c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221424313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.4221424313 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.3305306082 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 1943471128 ps |
CPU time | 13.46 seconds |
Started | Jul 27 06:50:33 PM PDT 24 |
Finished | Jul 27 06:50:46 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-47ca022f-7464-4523-8e16-62c37133ce73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305306082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3305306082 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1853702054 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 2038096561 ps |
CPU time | 53.93 seconds |
Started | Jul 27 06:50:47 PM PDT 24 |
Finished | Jul 27 06:51:41 PM PDT 24 |
Peak memory | 212424 kb |
Host | smart-03819c5f-e5ff-4530-ba1e-21c8e9f1e65d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1853702054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.1853702054 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1685379343 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 6833241525 ps |
CPU time | 278.33 seconds |
Started | Jul 27 06:50:36 PM PDT 24 |
Finished | Jul 27 06:55:14 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-2cbd7199-f384-44ec-b3c2-492da04d6271 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685379343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1685379343 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4161036958 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 3000116385 ps |
CPU time | 26.5 seconds |
Started | Jul 27 06:50:42 PM PDT 24 |
Finished | Jul 27 06:51:08 PM PDT 24 |
Peak memory | 280964 kb |
Host | smart-f1ee37d4-6061-4caa-a7c4-e1040235e46c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161036958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.4161036958 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3453333318 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 20099580011 ps |
CPU time | 641.04 seconds |
Started | Jul 27 06:50:57 PM PDT 24 |
Finished | Jul 27 07:01:39 PM PDT 24 |
Peak memory | 375208 kb |
Host | smart-38bbbb93-8e8c-4fa1-8c14-39a61c8ef996 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453333318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.3453333318 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.3536795899 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 14207971 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:50:57 PM PDT 24 |
Finished | Jul 27 06:50:58 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-70d2f85a-339a-41b2-be92-4716c0b98844 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536795899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3536795899 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.2898505120 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 30844926423 ps |
CPU time | 443.95 seconds |
Started | Jul 27 06:50:59 PM PDT 24 |
Finished | Jul 27 06:58:23 PM PDT 24 |
Peak memory | 357448 kb |
Host | smart-da4c087a-dc50-46c3-aefc-dad8a410aab6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898505120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.2898505120 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.1774332158 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 36046449073 ps |
CPU time | 51.1 seconds |
Started | Jul 27 06:51:00 PM PDT 24 |
Finished | Jul 27 06:51:51 PM PDT 24 |
Peak memory | 216552 kb |
Host | smart-f5277233-84b9-4c3c-9371-1cb860e7bb58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774332158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.1774332158 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.346083454 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 742982139 ps |
CPU time | 58.84 seconds |
Started | Jul 27 06:50:48 PM PDT 24 |
Finished | Jul 27 06:51:47 PM PDT 24 |
Peak memory | 320680 kb |
Host | smart-a796bf0d-d390-4775-84a8-04a736136e2a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346083454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.sram_ctrl_max_throughput.346083454 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1943523975 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 16321230960 ps |
CPU time | 151.54 seconds |
Started | Jul 27 06:50:58 PM PDT 24 |
Finished | Jul 27 06:53:30 PM PDT 24 |
Peak memory | 219544 kb |
Host | smart-8fb504fe-579d-4ff2-9d0b-5c88ac757996 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943523975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.1943523975 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.3012463392 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 7882701247 ps |
CPU time | 252.59 seconds |
Started | Jul 27 06:51:00 PM PDT 24 |
Finished | Jul 27 06:55:12 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-222c86eb-bed2-4d3f-9d7a-223c021400d8 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012463392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.3012463392 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.3914403013 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 109841453887 ps |
CPU time | 2574.35 seconds |
Started | Jul 27 06:50:49 PM PDT 24 |
Finished | Jul 27 07:33:45 PM PDT 24 |
Peak memory | 381124 kb |
Host | smart-17746480-2dde-4772-834e-39e3887c3163 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914403013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.3914403013 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.1782307109 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 3198261122 ps |
CPU time | 22.82 seconds |
Started | Jul 27 06:50:47 PM PDT 24 |
Finished | Jul 27 06:51:10 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-4c8242c4-ab7a-4ac7-938c-ce699b0052bc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782307109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.1782307109 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1127464753 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 54414149157 ps |
CPU time | 311.56 seconds |
Started | Jul 27 06:50:49 PM PDT 24 |
Finished | Jul 27 06:56:02 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-335b294d-20e8-42a9-8f14-8668f8623f56 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127464753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.1127464753 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.794698364 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 1784889537 ps |
CPU time | 3.54 seconds |
Started | Jul 27 06:50:59 PM PDT 24 |
Finished | Jul 27 06:51:02 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-325e158b-6968-4a2b-8904-6eb47f910bdb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794698364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.794698364 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.2071009108 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 2629000542 ps |
CPU time | 138.83 seconds |
Started | Jul 27 06:50:58 PM PDT 24 |
Finished | Jul 27 06:53:17 PM PDT 24 |
Peak memory | 334904 kb |
Host | smart-54bbb638-2058-47df-a7b8-b33c4a455c78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071009108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2071009108 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.1904279060 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 3575894906 ps |
CPU time | 54.98 seconds |
Started | Jul 27 06:50:49 PM PDT 24 |
Finished | Jul 27 06:51:44 PM PDT 24 |
Peak memory | 327560 kb |
Host | smart-11b70269-c3ed-438c-88a9-af060c472db8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904279060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1904279060 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.1768469505 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 57396561311 ps |
CPU time | 1729.28 seconds |
Started | Jul 27 06:50:59 PM PDT 24 |
Finished | Jul 27 07:19:49 PM PDT 24 |
Peak memory | 390380 kb |
Host | smart-0157ce75-924e-4a35-b10e-489d9ade9bb4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768469505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.1768469505 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1058195250 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 3908500495 ps |
CPU time | 29.33 seconds |
Started | Jul 27 06:50:58 PM PDT 24 |
Finished | Jul 27 06:51:28 PM PDT 24 |
Peak memory | 211476 kb |
Host | smart-9a2eae02-bbcd-44ef-b529-1eef95aae977 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1058195250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1058195250 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2684218573 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 18108960032 ps |
CPU time | 257.62 seconds |
Started | Jul 27 06:50:49 PM PDT 24 |
Finished | Jul 27 06:55:07 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-d3b64fa4-dd07-40f8-a9f7-cbe5f3fc61f8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684218573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.2684218573 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2560549800 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 1192998772 ps |
CPU time | 13.22 seconds |
Started | Jul 27 06:50:50 PM PDT 24 |
Finished | Jul 27 06:51:03 PM PDT 24 |
Peak memory | 244204 kb |
Host | smart-a3e31739-f070-44fb-bccb-510e1b1374a7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560549800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2560549800 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1869521482 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 67310834335 ps |
CPU time | 1003.97 seconds |
Started | Jul 27 06:51:09 PM PDT 24 |
Finished | Jul 27 07:07:53 PM PDT 24 |
Peak memory | 369892 kb |
Host | smart-047c9e43-7c39-4de9-94ba-49fd282bc901 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869521482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.1869521482 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.2560878829 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 29393608 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:51:14 PM PDT 24 |
Finished | Jul 27 06:51:15 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-2fd4ed7c-cacd-4413-8aa0-53b38eebf9d2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560878829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.2560878829 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.3699817581 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 101343294683 ps |
CPU time | 2393.81 seconds |
Started | Jul 27 06:50:58 PM PDT 24 |
Finished | Jul 27 07:30:52 PM PDT 24 |
Peak memory | 203768 kb |
Host | smart-279122c9-4d0e-4137-9b1a-51300a27dc79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699817581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .3699817581 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.2383808292 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 95839567434 ps |
CPU time | 1157.71 seconds |
Started | Jul 27 06:51:06 PM PDT 24 |
Finished | Jul 27 07:10:24 PM PDT 24 |
Peak memory | 380096 kb |
Host | smart-f51c41db-8644-42ec-ba24-0f647d14d8e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383808292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.2383808292 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.3634974761 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 2790981125 ps |
CPU time | 6.37 seconds |
Started | Jul 27 06:51:07 PM PDT 24 |
Finished | Jul 27 06:51:13 PM PDT 24 |
Peak memory | 211152 kb |
Host | smart-604a34fd-cbcb-4174-8499-c354c8983c5e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634974761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.3634974761 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.3278863607 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 7928304303 ps |
CPU time | 38.25 seconds |
Started | Jul 27 06:50:57 PM PDT 24 |
Finished | Jul 27 06:51:36 PM PDT 24 |
Peak memory | 284972 kb |
Host | smart-4c95eae0-f64c-4688-b923-1532796e7155 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278863607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.3278863607 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2438879034 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1444140448 ps |
CPU time | 75.9 seconds |
Started | Jul 27 06:51:07 PM PDT 24 |
Finished | Jul 27 06:52:23 PM PDT 24 |
Peak memory | 219404 kb |
Host | smart-ea985a80-82fa-4725-9fac-48f1f8ec2e3c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438879034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.2438879034 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.2294658703 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 36672878628 ps |
CPU time | 326.99 seconds |
Started | Jul 27 06:51:08 PM PDT 24 |
Finished | Jul 27 06:56:35 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-a789ebd4-fc66-4537-a07e-8ae468798d97 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294658703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.2294658703 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.3337161822 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 19532889937 ps |
CPU time | 809.75 seconds |
Started | Jul 27 06:50:59 PM PDT 24 |
Finished | Jul 27 07:04:29 PM PDT 24 |
Peak memory | 376020 kb |
Host | smart-1ab1ec23-c8c3-45b0-a7c6-74cab78353dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337161822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.3337161822 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.3703885867 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 3041964664 ps |
CPU time | 12.33 seconds |
Started | Jul 27 06:50:57 PM PDT 24 |
Finished | Jul 27 06:51:10 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-aacc7d8c-3e36-4e12-97d5-e94d401f3f6f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703885867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.3703885867 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.11105967 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 26518562086 ps |
CPU time | 388 seconds |
Started | Jul 27 06:50:57 PM PDT 24 |
Finished | Jul 27 06:57:25 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-56c5002e-c135-40b8-a2fe-cd6b7349455c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11105967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_partial_access_b2b.11105967 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.365255046 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 1406263042 ps |
CPU time | 3.39 seconds |
Started | Jul 27 06:51:06 PM PDT 24 |
Finished | Jul 27 06:51:09 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-b126e15f-7803-4759-be76-5822a4dd8608 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365255046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.365255046 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.3262500911 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 8752216893 ps |
CPU time | 549.86 seconds |
Started | Jul 27 06:51:06 PM PDT 24 |
Finished | Jul 27 07:00:16 PM PDT 24 |
Peak memory | 369552 kb |
Host | smart-efa91977-be60-41b1-8835-a6316e818e51 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262500911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3262500911 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.866173550 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 346536998 ps |
CPU time | 4.56 seconds |
Started | Jul 27 06:50:58 PM PDT 24 |
Finished | Jul 27 06:51:03 PM PDT 24 |
Peak memory | 207064 kb |
Host | smart-a9a84790-ab4c-454d-b76c-06b28c844869 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866173550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.866173550 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.905501990 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 21507302901 ps |
CPU time | 3836.11 seconds |
Started | Jul 27 06:51:14 PM PDT 24 |
Finished | Jul 27 07:55:10 PM PDT 24 |
Peak memory | 382132 kb |
Host | smart-afe9770c-05df-43ba-bf7f-38127c8d5b0d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905501990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_stress_all.905501990 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3493023095 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 5519893957 ps |
CPU time | 192.5 seconds |
Started | Jul 27 06:51:06 PM PDT 24 |
Finished | Jul 27 06:54:19 PM PDT 24 |
Peak memory | 361168 kb |
Host | smart-dada29fc-1eb2-4a58-a293-959212e66731 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3493023095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3493023095 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2657022306 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 7639818636 ps |
CPU time | 283.92 seconds |
Started | Jul 27 06:50:58 PM PDT 24 |
Finished | Jul 27 06:55:42 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-88f72bff-80a6-45b1-9939-84d29a903132 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657022306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.2657022306 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1341730458 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 3095600868 ps |
CPU time | 56.21 seconds |
Started | Jul 27 06:51:08 PM PDT 24 |
Finished | Jul 27 06:52:05 PM PDT 24 |
Peak memory | 308204 kb |
Host | smart-36a708d9-a9ed-4421-af56-d6914c63fa82 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341730458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1341730458 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3817607375 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 34441723207 ps |
CPU time | 576.16 seconds |
Started | Jul 27 06:51:15 PM PDT 24 |
Finished | Jul 27 07:00:51 PM PDT 24 |
Peak memory | 378984 kb |
Host | smart-712382de-fee2-41af-a0c8-9264c78764c3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817607375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.3817607375 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.3978154482 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 13662971 ps |
CPU time | 0.69 seconds |
Started | Jul 27 06:51:22 PM PDT 24 |
Finished | Jul 27 06:51:23 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-07f01254-f7e2-4ea7-a18d-f4f0c8216afb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978154482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3978154482 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.1715962221 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 86366937891 ps |
CPU time | 1967.57 seconds |
Started | Jul 27 06:51:15 PM PDT 24 |
Finished | Jul 27 07:24:03 PM PDT 24 |
Peak memory | 203876 kb |
Host | smart-e80044d1-e23f-4ad8-ab70-5c1e7b642b89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715962221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .1715962221 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.1211182898 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 48080987900 ps |
CPU time | 771.74 seconds |
Started | Jul 27 06:51:23 PM PDT 24 |
Finished | Jul 27 07:04:14 PM PDT 24 |
Peak memory | 354524 kb |
Host | smart-2630cee8-d39a-450a-b294-dd546fe7ac2f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211182898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.1211182898 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.1158128658 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 24495221378 ps |
CPU time | 79.28 seconds |
Started | Jul 27 06:51:14 PM PDT 24 |
Finished | Jul 27 06:52:34 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-5ecb0495-eb50-414a-841e-b2f825ef1498 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158128658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.1158128658 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.127354086 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 696377405 ps |
CPU time | 8.92 seconds |
Started | Jul 27 06:51:14 PM PDT 24 |
Finished | Jul 27 06:51:23 PM PDT 24 |
Peak memory | 226992 kb |
Host | smart-918995a4-9df1-4cb0-b8d1-f63d067b58fd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127354086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.sram_ctrl_max_throughput.127354086 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1361863041 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 2437528597 ps |
CPU time | 155.36 seconds |
Started | Jul 27 06:51:23 PM PDT 24 |
Finished | Jul 27 06:53:58 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-775a7a4f-66ce-4050-a275-170ed0295c17 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361863041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.1361863041 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.2377406622 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 52503958664 ps |
CPU time | 315.24 seconds |
Started | Jul 27 06:51:25 PM PDT 24 |
Finished | Jul 27 06:56:41 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-76dd06b4-b601-4a8c-930e-81bbf15b4337 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377406622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.2377406622 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.218838340 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 33611378710 ps |
CPU time | 910.81 seconds |
Started | Jul 27 06:51:16 PM PDT 24 |
Finished | Jul 27 07:06:27 PM PDT 24 |
Peak memory | 374936 kb |
Host | smart-4d656775-c74e-4b82-bb60-0c2bed1b5205 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218838340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip le_keys.218838340 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.89519446 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 1062671936 ps |
CPU time | 10.5 seconds |
Started | Jul 27 06:51:15 PM PDT 24 |
Finished | Jul 27 06:51:25 PM PDT 24 |
Peak memory | 232112 kb |
Host | smart-3306d4bf-0336-494f-99c4-dadf3e528fe2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89519446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sr am_ctrl_partial_access.89519446 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3690306755 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 12952049457 ps |
CPU time | 274.82 seconds |
Started | Jul 27 06:51:16 PM PDT 24 |
Finished | Jul 27 06:55:51 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-a891eea5-81cb-4855-bd66-d2e6a1efad56 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690306755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.3690306755 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.1255198324 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 357798593 ps |
CPU time | 3.07 seconds |
Started | Jul 27 06:51:23 PM PDT 24 |
Finished | Jul 27 06:51:26 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-0e5b0aba-455f-4d59-a107-83cc1f4fc652 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255198324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1255198324 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.4076252175 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 6163884850 ps |
CPU time | 520.12 seconds |
Started | Jul 27 06:51:24 PM PDT 24 |
Finished | Jul 27 07:00:04 PM PDT 24 |
Peak memory | 374860 kb |
Host | smart-055ef35c-88a1-4bfe-820c-a882a60aff0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076252175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.4076252175 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.3083575550 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 893947859 ps |
CPU time | 9.17 seconds |
Started | Jul 27 06:51:17 PM PDT 24 |
Finished | Jul 27 06:51:26 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-109c4da1-e99b-4e40-9d92-60d47207cde2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083575550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3083575550 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.3622365004 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 609919477758 ps |
CPU time | 5338.6 seconds |
Started | Jul 27 06:51:23 PM PDT 24 |
Finished | Jul 27 08:20:22 PM PDT 24 |
Peak memory | 381116 kb |
Host | smart-f9526e33-e9b8-4577-957c-57b38d93f7f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622365004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.3622365004 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3359996487 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 4810467570 ps |
CPU time | 32.62 seconds |
Started | Jul 27 06:51:23 PM PDT 24 |
Finished | Jul 27 06:51:56 PM PDT 24 |
Peak memory | 212528 kb |
Host | smart-caacb8c9-7750-44bb-a6d0-2bd5db4ec769 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3359996487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3359996487 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3962020146 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 3184905659 ps |
CPU time | 195.58 seconds |
Started | Jul 27 06:51:15 PM PDT 24 |
Finished | Jul 27 06:54:31 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-2b3fd0eb-fb05-4f35-8730-1cbc38d7912e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962020146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.3962020146 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1671714422 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 711215397 ps |
CPU time | 6.46 seconds |
Started | Jul 27 06:51:17 PM PDT 24 |
Finished | Jul 27 06:51:23 PM PDT 24 |
Peak memory | 211476 kb |
Host | smart-6a3a22d5-54e0-4973-8cea-a9bef30a8aca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671714422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1671714422 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.230019193 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 14664096514 ps |
CPU time | 1932.54 seconds |
Started | Jul 27 06:51:30 PM PDT 24 |
Finished | Jul 27 07:23:43 PM PDT 24 |
Peak memory | 379044 kb |
Host | smart-89497034-f844-48d0-b208-b7e2080d1b14 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230019193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sram_ctrl_access_during_key_req.230019193 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.3977648548 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 47930871 ps |
CPU time | 0.64 seconds |
Started | Jul 27 06:51:40 PM PDT 24 |
Finished | Jul 27 06:51:40 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-a4fcd288-b577-45c2-9525-f0ff1b9de3c6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977648548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3977648548 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.1928444174 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 539753353114 ps |
CPU time | 2203.1 seconds |
Started | Jul 27 06:51:33 PM PDT 24 |
Finished | Jul 27 07:28:16 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-3941a02a-87b1-4dac-a7da-883e6fcd4ba9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928444174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .1928444174 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.2664003764 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 28661591552 ps |
CPU time | 763.96 seconds |
Started | Jul 27 06:51:32 PM PDT 24 |
Finished | Jul 27 07:04:16 PM PDT 24 |
Peak memory | 378024 kb |
Host | smart-19b67900-1b92-4d92-9f41-d4a1e906ed89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664003764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.2664003764 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.3007621259 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 12951627866 ps |
CPU time | 70.69 seconds |
Started | Jul 27 06:51:34 PM PDT 24 |
Finished | Jul 27 06:52:44 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-84aae668-7dbe-4032-b23d-acc2cb4711f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007621259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.3007621259 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.2264089706 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 2177914493 ps |
CPU time | 48.12 seconds |
Started | Jul 27 06:51:33 PM PDT 24 |
Finished | Jul 27 06:52:22 PM PDT 24 |
Peak memory | 292144 kb |
Host | smart-02c2e1f8-30d8-4cea-82bd-dfe06c681412 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264089706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.2264089706 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.109149196 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 2623970516 ps |
CPU time | 82.84 seconds |
Started | Jul 27 06:51:30 PM PDT 24 |
Finished | Jul 27 06:52:53 PM PDT 24 |
Peak memory | 219572 kb |
Host | smart-d28757ce-7fc0-44eb-aa01-ae1c4f301292 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109149196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_mem_partial_access.109149196 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.2974463529 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 28791225224 ps |
CPU time | 165.14 seconds |
Started | Jul 27 06:51:31 PM PDT 24 |
Finished | Jul 27 06:54:16 PM PDT 24 |
Peak memory | 204088 kb |
Host | smart-afee64b3-467c-437f-8b0f-2a399d672004 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974463529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.2974463529 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.116247411 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 3663718971 ps |
CPU time | 192.16 seconds |
Started | Jul 27 06:51:30 PM PDT 24 |
Finished | Jul 27 06:54:43 PM PDT 24 |
Peak memory | 332968 kb |
Host | smart-47362902-9925-484e-9aea-6714f43dada3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116247411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multip le_keys.116247411 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.2769696656 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 2780982778 ps |
CPU time | 145.43 seconds |
Started | Jul 27 06:51:32 PM PDT 24 |
Finished | Jul 27 06:53:58 PM PDT 24 |
Peak memory | 367756 kb |
Host | smart-cef76d8b-d12c-4d10-bcf5-cfe76a76cbb5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769696656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.2769696656 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4071314135 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 82441038179 ps |
CPU time | 548.86 seconds |
Started | Jul 27 06:51:29 PM PDT 24 |
Finished | Jul 27 07:00:38 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-f761279a-35cd-4126-9e8b-5bc4bf82f388 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071314135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.4071314135 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.3118720076 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 2574049502 ps |
CPU time | 3.4 seconds |
Started | Jul 27 06:51:32 PM PDT 24 |
Finished | Jul 27 06:51:35 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-65897f2a-2724-42d3-8734-fc603aa8ce90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118720076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3118720076 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.4036371090 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 210116014285 ps |
CPU time | 1206.61 seconds |
Started | Jul 27 06:51:33 PM PDT 24 |
Finished | Jul 27 07:11:40 PM PDT 24 |
Peak memory | 381108 kb |
Host | smart-10eb261f-04c2-4d53-8da7-faf20ef0991f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036371090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.4036371090 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.3078935438 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 824056589 ps |
CPU time | 15.77 seconds |
Started | Jul 27 06:51:31 PM PDT 24 |
Finished | Jul 27 06:51:47 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-031a7558-e7a9-4def-9090-af2d6b1d18b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078935438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3078935438 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.2411803137 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 95055492722 ps |
CPU time | 3324.49 seconds |
Started | Jul 27 06:51:39 PM PDT 24 |
Finished | Jul 27 07:47:04 PM PDT 24 |
Peak memory | 379164 kb |
Host | smart-6788dd60-cb25-49a4-ac9c-cab0cbf5d750 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411803137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.2411803137 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2976019881 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 837385010 ps |
CPU time | 24.3 seconds |
Started | Jul 27 06:51:38 PM PDT 24 |
Finished | Jul 27 06:52:02 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-3e3db983-9418-40ec-8650-0cb3d3d5b92c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2976019881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2976019881 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.639165652 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 2843145406 ps |
CPU time | 166.29 seconds |
Started | Jul 27 06:51:34 PM PDT 24 |
Finished | Jul 27 06:54:20 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-9a2f67c2-2a9e-4f9c-b812-72fbd92a0570 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639165652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_stress_pipeline.639165652 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.466322211 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 3703717249 ps |
CPU time | 115.32 seconds |
Started | Jul 27 06:51:31 PM PDT 24 |
Finished | Jul 27 06:53:26 PM PDT 24 |
Peak memory | 366872 kb |
Host | smart-a39332ff-c539-4cbd-b1b5-8241a1e65691 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466322211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.466322211 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3000783364 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 16879208820 ps |
CPU time | 639.21 seconds |
Started | Jul 27 06:45:19 PM PDT 24 |
Finished | Jul 27 06:55:59 PM PDT 24 |
Peak memory | 374988 kb |
Host | smart-6dd195fa-ccb9-4755-be8d-80d05b11ebeb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000783364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.3000783364 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.2933612837 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 13024684 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:45:21 PM PDT 24 |
Finished | Jul 27 06:45:21 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-849bd207-bca0-4f25-a851-dba404176f28 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933612837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2933612837 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.712799716 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 313505919048 ps |
CPU time | 1834.32 seconds |
Started | Jul 27 06:45:20 PM PDT 24 |
Finished | Jul 27 07:15:55 PM PDT 24 |
Peak memory | 203796 kb |
Host | smart-46e32462-3ba7-4773-a837-6a40a3df5bfe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712799716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.712799716 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.1660251268 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 50207762317 ps |
CPU time | 1643.16 seconds |
Started | Jul 27 06:45:20 PM PDT 24 |
Finished | Jul 27 07:12:43 PM PDT 24 |
Peak memory | 379872 kb |
Host | smart-ae4a3515-e5d5-498b-816d-d27153bfaa9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660251268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.1660251268 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.1046322415 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 11032962047 ps |
CPU time | 21.86 seconds |
Started | Jul 27 06:45:19 PM PDT 24 |
Finished | Jul 27 06:45:41 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-faf87b00-bb00-49ae-a4da-b1cad13dd787 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046322415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.1046322415 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.3396944132 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 3012914112 ps |
CPU time | 42.56 seconds |
Started | Jul 27 06:45:22 PM PDT 24 |
Finished | Jul 27 06:46:04 PM PDT 24 |
Peak memory | 301312 kb |
Host | smart-0d5f9964-fe26-4491-a8e0-765fd3ca44c3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396944132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.3396944132 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3500398653 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 29640472982 ps |
CPU time | 87.68 seconds |
Started | Jul 27 06:45:20 PM PDT 24 |
Finished | Jul 27 06:46:48 PM PDT 24 |
Peak memory | 212008 kb |
Host | smart-9ebf462c-d7d9-4b8d-b6eb-c6bcf65ad2d8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500398653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.3500398653 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.3050521674 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 77993703377 ps |
CPU time | 351.02 seconds |
Started | Jul 27 06:45:25 PM PDT 24 |
Finished | Jul 27 06:51:16 PM PDT 24 |
Peak memory | 211340 kb |
Host | smart-3dd71a22-c1aa-49ed-a54e-6a972e9a4c83 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050521674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.3050521674 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.1759558139 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 6820544479 ps |
CPU time | 1188.02 seconds |
Started | Jul 27 06:45:20 PM PDT 24 |
Finished | Jul 27 07:05:08 PM PDT 24 |
Peak memory | 375936 kb |
Host | smart-0029b515-83a8-4a5f-8049-13ded0ba7335 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759558139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.1759558139 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.4042783218 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 1730481912 ps |
CPU time | 65.98 seconds |
Started | Jul 27 06:45:19 PM PDT 24 |
Finished | Jul 27 06:46:25 PM PDT 24 |
Peak memory | 334152 kb |
Host | smart-ffd164e2-8d7c-444e-afb8-b8f3d6ce2365 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042783218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.4042783218 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3142778988 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 3759848462 ps |
CPU time | 207.53 seconds |
Started | Jul 27 06:45:17 PM PDT 24 |
Finished | Jul 27 06:48:45 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-ea844592-b9d6-4a48-af87-9c2d9c4694e2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142778988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.3142778988 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.4046195754 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 1251185975 ps |
CPU time | 3.09 seconds |
Started | Jul 27 06:45:21 PM PDT 24 |
Finished | Jul 27 06:45:24 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-79542129-4008-4994-bf6e-13a315e578c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046195754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.4046195754 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.663196453 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 11425686117 ps |
CPU time | 561.54 seconds |
Started | Jul 27 06:45:18 PM PDT 24 |
Finished | Jul 27 06:54:40 PM PDT 24 |
Peak memory | 373996 kb |
Host | smart-6765ce51-b13e-49f4-aba7-a198d5a214ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663196453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.663196453 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.1441366803 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 957797051 ps |
CPU time | 3.16 seconds |
Started | Jul 27 06:45:18 PM PDT 24 |
Finished | Jul 27 06:45:22 PM PDT 24 |
Peak memory | 223040 kb |
Host | smart-0a533807-20dc-4bfd-9e56-ef33fca4fa64 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441366803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1441366803 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.4070103525 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 2385811949 ps |
CPU time | 152.26 seconds |
Started | Jul 27 06:45:24 PM PDT 24 |
Finished | Jul 27 06:47:56 PM PDT 24 |
Peak memory | 370676 kb |
Host | smart-0d37582c-7add-4f1b-856b-20853aad4e9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070103525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.4070103525 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.333975140 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 138017577169 ps |
CPU time | 3393.17 seconds |
Started | Jul 27 06:45:22 PM PDT 24 |
Finished | Jul 27 07:41:56 PM PDT 24 |
Peak memory | 385224 kb |
Host | smart-411f8e20-1fc7-4e65-baba-6845e6028fcb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333975140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_stress_all.333975140 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3096945791 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 2949106421 ps |
CPU time | 20.78 seconds |
Started | Jul 27 06:45:20 PM PDT 24 |
Finished | Jul 27 06:45:41 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-a6535598-cc9f-43fb-b167-bfa758075f84 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3096945791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3096945791 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.486195446 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 8593592072 ps |
CPU time | 295.54 seconds |
Started | Jul 27 06:45:20 PM PDT 24 |
Finished | Jul 27 06:50:16 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-8694687b-3882-4253-8438-706198357a8d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486195446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. sram_ctrl_stress_pipeline.486195446 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2314497958 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 3313892066 ps |
CPU time | 79.6 seconds |
Started | Jul 27 06:45:19 PM PDT 24 |
Finished | Jul 27 06:46:39 PM PDT 24 |
Peak memory | 345312 kb |
Host | smart-341e4423-6600-4922-bae0-f7452db2ece5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314497958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.2314497958 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2451355163 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 3066879061 ps |
CPU time | 146.77 seconds |
Started | Jul 27 06:51:43 PM PDT 24 |
Finished | Jul 27 06:54:10 PM PDT 24 |
Peak memory | 305400 kb |
Host | smart-7dcc3743-d922-4e1c-b691-f37c145c3a88 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451355163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.2451355163 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.3644952505 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 36034736 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:51:46 PM PDT 24 |
Finished | Jul 27 06:51:47 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-16ec7659-0462-47db-817b-6c98eaaf9eb7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644952505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.3644952505 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.3585020469 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 116881653021 ps |
CPU time | 1996.12 seconds |
Started | Jul 27 06:51:38 PM PDT 24 |
Finished | Jul 27 07:24:54 PM PDT 24 |
Peak memory | 203492 kb |
Host | smart-9d2d394f-6aad-473b-8ea3-d1d264f1a5cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585020469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .3585020469 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.3817947403 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 43725187457 ps |
CPU time | 1149.37 seconds |
Started | Jul 27 06:51:40 PM PDT 24 |
Finished | Jul 27 07:10:50 PM PDT 24 |
Peak memory | 380088 kb |
Host | smart-0b6e3305-e5f6-41a2-b753-0e3f3a533266 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817947403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.3817947403 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.2513269108 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 13686288367 ps |
CPU time | 74.44 seconds |
Started | Jul 27 06:51:43 PM PDT 24 |
Finished | Jul 27 06:52:58 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-c23dccdf-bc56-40eb-8def-80568f160c3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513269108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.2513269108 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.2115547316 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 9144453028 ps |
CPU time | 69.29 seconds |
Started | Jul 27 06:51:42 PM PDT 24 |
Finished | Jul 27 06:52:51 PM PDT 24 |
Peak memory | 315584 kb |
Host | smart-42ed4a3b-a40c-4bee-b10b-f67b5e953c1a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115547316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.2115547316 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.884635498 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 37721542451 ps |
CPU time | 161.32 seconds |
Started | Jul 27 06:51:49 PM PDT 24 |
Finished | Jul 27 06:54:30 PM PDT 24 |
Peak memory | 211680 kb |
Host | smart-115ac70c-7478-4d7f-8d57-82e9ee834672 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884635498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sram_ctrl_mem_partial_access.884635498 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.1419889794 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 10953066625 ps |
CPU time | 152.54 seconds |
Started | Jul 27 06:51:48 PM PDT 24 |
Finished | Jul 27 06:54:20 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-f4715121-9080-4674-8e26-5cd826b2da0d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419889794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.1419889794 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.387340479 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 53389364649 ps |
CPU time | 473.93 seconds |
Started | Jul 27 06:51:37 PM PDT 24 |
Finished | Jul 27 06:59:31 PM PDT 24 |
Peak memory | 372888 kb |
Host | smart-2cf1ef89-5ea4-4ca5-be9c-8e20fbe73e6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387340479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multip le_keys.387340479 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.1638712398 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 636535584 ps |
CPU time | 20.42 seconds |
Started | Jul 27 06:51:38 PM PDT 24 |
Finished | Jul 27 06:51:58 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-70956e65-db35-46b8-9ce8-5bb1390785bb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638712398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.1638712398 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2571280774 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 29604501225 ps |
CPU time | 666.76 seconds |
Started | Jul 27 06:51:38 PM PDT 24 |
Finished | Jul 27 07:02:44 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-73caae36-8a03-42a7-a91c-78c0816f8574 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571280774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.2571280774 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.4117682038 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 1347968841 ps |
CPU time | 3.59 seconds |
Started | Jul 27 06:51:45 PM PDT 24 |
Finished | Jul 27 06:51:49 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-7c27a1bc-cca4-4d35-98e5-14bcca1463ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117682038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.4117682038 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.759704334 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 2350646563 ps |
CPU time | 350.15 seconds |
Started | Jul 27 06:51:39 PM PDT 24 |
Finished | Jul 27 06:57:29 PM PDT 24 |
Peak memory | 378964 kb |
Host | smart-374493fe-228a-41e7-8992-d02febf29778 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759704334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.759704334 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.3045144542 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 3272788837 ps |
CPU time | 38.06 seconds |
Started | Jul 27 06:51:37 PM PDT 24 |
Finished | Jul 27 06:52:15 PM PDT 24 |
Peak memory | 287456 kb |
Host | smart-95c7457d-7360-4ec5-810c-0b743f443f9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045144542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3045144542 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.1176050843 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 173089348582 ps |
CPU time | 2914.17 seconds |
Started | Jul 27 06:51:46 PM PDT 24 |
Finished | Jul 27 07:40:21 PM PDT 24 |
Peak memory | 382452 kb |
Host | smart-11d56873-b109-41b9-b9a2-8007fa3c5d2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176050843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.1176050843 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3556021970 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 285593185 ps |
CPU time | 11.07 seconds |
Started | Jul 27 06:51:46 PM PDT 24 |
Finished | Jul 27 06:51:57 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-09b4c968-9730-4fe1-83b3-e7dea1410176 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3556021970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.3556021970 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1143093700 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 4366064479 ps |
CPU time | 241.66 seconds |
Started | Jul 27 06:51:38 PM PDT 24 |
Finished | Jul 27 06:55:40 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-6b77dcc6-c3ea-4e91-a179-4a156a23b3df |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143093700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.1143093700 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1864426605 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 730277593 ps |
CPU time | 14.83 seconds |
Started | Jul 27 06:51:38 PM PDT 24 |
Finished | Jul 27 06:51:53 PM PDT 24 |
Peak memory | 245112 kb |
Host | smart-d307bcc5-6cac-488b-b34c-459b9e852132 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864426605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1864426605 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2207877254 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 21718128398 ps |
CPU time | 875.61 seconds |
Started | Jul 27 06:51:45 PM PDT 24 |
Finished | Jul 27 07:06:20 PM PDT 24 |
Peak memory | 381128 kb |
Host | smart-e1470387-42c8-4c87-a8fa-ccfbe6ff35d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207877254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.2207877254 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.3725528173 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 14778371 ps |
CPU time | 0.69 seconds |
Started | Jul 27 06:51:56 PM PDT 24 |
Finished | Jul 27 06:51:56 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-8a7a6f36-2904-4ce0-8182-1d825f306d63 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725528173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.3725528173 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.689490256 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 49858322856 ps |
CPU time | 1702.89 seconds |
Started | Jul 27 06:51:48 PM PDT 24 |
Finished | Jul 27 07:20:11 PM PDT 24 |
Peak memory | 203968 kb |
Host | smart-48eb829d-4281-4a45-9608-6b944e36dc76 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689490256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection. 689490256 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.2641943196 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 9576029366 ps |
CPU time | 519.21 seconds |
Started | Jul 27 06:51:55 PM PDT 24 |
Finished | Jul 27 07:00:34 PM PDT 24 |
Peak memory | 376900 kb |
Host | smart-c7b76931-6637-4150-9536-ef925211fb3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641943196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.2641943196 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.150037667 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 12563241126 ps |
CPU time | 75.51 seconds |
Started | Jul 27 06:51:46 PM PDT 24 |
Finished | Jul 27 06:53:01 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-b3413858-9733-4862-aad9-449c6d52a757 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150037667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_esc alation.150037667 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.123681108 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 741031941 ps |
CPU time | 61.29 seconds |
Started | Jul 27 06:51:46 PM PDT 24 |
Finished | Jul 27 06:52:48 PM PDT 24 |
Peak memory | 305408 kb |
Host | smart-5ed88edf-be86-41c0-8194-c40284dc5b2d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123681108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.sram_ctrl_max_throughput.123681108 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2729779598 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 1421195731 ps |
CPU time | 71.47 seconds |
Started | Jul 27 06:51:54 PM PDT 24 |
Finished | Jul 27 06:53:05 PM PDT 24 |
Peak memory | 211328 kb |
Host | smart-b7677259-910f-4db4-90d1-57758fbf788c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729779598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.2729779598 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.1033883375 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 10937971126 ps |
CPU time | 309.1 seconds |
Started | Jul 27 06:51:53 PM PDT 24 |
Finished | Jul 27 06:57:02 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-ffcd271b-7328-4dc7-a3e1-e38bba5fdee0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033883375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.1033883375 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.2557964588 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 67288552926 ps |
CPU time | 437.32 seconds |
Started | Jul 27 06:51:47 PM PDT 24 |
Finished | Jul 27 06:59:04 PM PDT 24 |
Peak memory | 371772 kb |
Host | smart-e02fe2e9-4553-48df-a366-e12cdce50fe6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557964588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.2557964588 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.661975108 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 3054459995 ps |
CPU time | 53.75 seconds |
Started | Jul 27 06:51:45 PM PDT 24 |
Finished | Jul 27 06:52:39 PM PDT 24 |
Peak memory | 303376 kb |
Host | smart-9fbcec9b-1d06-4c9e-8bac-d65c0ce9fa83 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661975108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s ram_ctrl_partial_access.661975108 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3003234648 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 3365090832 ps |
CPU time | 188.2 seconds |
Started | Jul 27 06:51:46 PM PDT 24 |
Finished | Jul 27 06:54:54 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-a6cd55e5-ecb0-445c-9d7a-977e3ddb33fc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003234648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.3003234648 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.874349667 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 744921235 ps |
CPU time | 3.08 seconds |
Started | Jul 27 06:51:55 PM PDT 24 |
Finished | Jul 27 06:51:58 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-6512614d-87f9-4b85-b8ac-72be6466d6e2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874349667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.874349667 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.1548567575 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 25324606326 ps |
CPU time | 689.82 seconds |
Started | Jul 27 06:51:58 PM PDT 24 |
Finished | Jul 27 07:03:28 PM PDT 24 |
Peak memory | 370888 kb |
Host | smart-b9e1d68f-f899-4eb5-bd80-783a194135db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548567575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1548567575 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.3448160498 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 1580117699 ps |
CPU time | 8.44 seconds |
Started | Jul 27 06:51:46 PM PDT 24 |
Finished | Jul 27 06:51:54 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-60db6849-37c1-4822-bd21-b0afa603c867 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448160498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3448160498 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.1369758851 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 104839814093 ps |
CPU time | 3557.69 seconds |
Started | Jul 27 06:51:55 PM PDT 24 |
Finished | Jul 27 07:51:14 PM PDT 24 |
Peak memory | 381184 kb |
Host | smart-ec099561-6cd9-487f-8750-14aebfcbfa14 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369758851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.1369758851 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.856541841 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 10660705685 ps |
CPU time | 338.42 seconds |
Started | Jul 27 06:51:45 PM PDT 24 |
Finished | Jul 27 06:57:24 PM PDT 24 |
Peak memory | 203432 kb |
Host | smart-304032be-25a9-4b06-a8bc-df00036edbc2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856541841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_stress_pipeline.856541841 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3230743757 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 767615408 ps |
CPU time | 59.96 seconds |
Started | Jul 27 06:51:47 PM PDT 24 |
Finished | Jul 27 06:52:47 PM PDT 24 |
Peak memory | 345256 kb |
Host | smart-050891d3-7746-4f24-8c17-2dbd9e490d9f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230743757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3230743757 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.482350067 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 10579362031 ps |
CPU time | 902.79 seconds |
Started | Jul 27 06:52:04 PM PDT 24 |
Finished | Jul 27 07:07:07 PM PDT 24 |
Peak memory | 375012 kb |
Host | smart-518953d7-c6af-410a-8fbf-82a08c32734e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482350067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 42.sram_ctrl_access_during_key_req.482350067 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.20303100 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 22279001 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:52:12 PM PDT 24 |
Finished | Jul 27 06:52:13 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-06148b3b-f168-4bee-a993-f8d91e43f546 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20303100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_alert_test.20303100 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.3860266562 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 95922024081 ps |
CPU time | 2190.85 seconds |
Started | Jul 27 06:52:04 PM PDT 24 |
Finished | Jul 27 07:28:35 PM PDT 24 |
Peak memory | 203884 kb |
Host | smart-b19e8330-1b2e-4324-a220-1109989436b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860266562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .3860266562 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.2803509581 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 14296576438 ps |
CPU time | 710.35 seconds |
Started | Jul 27 06:52:03 PM PDT 24 |
Finished | Jul 27 07:03:53 PM PDT 24 |
Peak memory | 375976 kb |
Host | smart-7ebd11b7-5a95-4e57-829d-9dbeee49e823 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803509581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.2803509581 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.3015014755 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 16533540966 ps |
CPU time | 102.19 seconds |
Started | Jul 27 06:52:02 PM PDT 24 |
Finished | Jul 27 06:53:45 PM PDT 24 |
Peak memory | 215244 kb |
Host | smart-b86740f8-7412-442e-9db3-a7bcc4d527d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015014755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.3015014755 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.3376018293 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 754263376 ps |
CPU time | 31.7 seconds |
Started | Jul 27 06:52:03 PM PDT 24 |
Finished | Jul 27 06:52:35 PM PDT 24 |
Peak memory | 286928 kb |
Host | smart-24f0820e-4651-4e6f-8468-309a0d2be2c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376018293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.3376018293 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4230457742 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 11748095971 ps |
CPU time | 160.87 seconds |
Started | Jul 27 06:52:05 PM PDT 24 |
Finished | Jul 27 06:54:45 PM PDT 24 |
Peak memory | 211340 kb |
Host | smart-b4ca7387-a8c0-4946-b182-0ff6290ddcda |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230457742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.4230457742 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.2718916643 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 28222753671 ps |
CPU time | 327.37 seconds |
Started | Jul 27 06:52:03 PM PDT 24 |
Finished | Jul 27 06:57:31 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-b4964403-d81b-45dc-b2af-1b1d6f9fea58 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718916643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.2718916643 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.2040932696 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 11304296110 ps |
CPU time | 730.07 seconds |
Started | Jul 27 06:51:57 PM PDT 24 |
Finished | Jul 27 07:04:07 PM PDT 24 |
Peak memory | 366936 kb |
Host | smart-e9bfb818-6fdc-4eec-a090-76836f621fda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040932696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.2040932696 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.1667899620 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 3499582059 ps |
CPU time | 11.61 seconds |
Started | Jul 27 06:52:03 PM PDT 24 |
Finished | Jul 27 06:52:15 PM PDT 24 |
Peak memory | 229840 kb |
Host | smart-2fd0c2c7-c896-4939-a2da-e583d5578455 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667899620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.1667899620 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.221552181 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 27887883533 ps |
CPU time | 250.23 seconds |
Started | Jul 27 06:52:04 PM PDT 24 |
Finished | Jul 27 06:56:15 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-1c0b8cc5-e1e1-49dc-b1e7-9a6c5ea6b8c1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221552181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.sram_ctrl_partial_access_b2b.221552181 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.3411503840 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 1875584536 ps |
CPU time | 3.63 seconds |
Started | Jul 27 06:52:04 PM PDT 24 |
Finished | Jul 27 06:52:07 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-763929a6-55bb-491a-b30c-b7f5c71bfcbe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411503840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3411503840 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.3100007151 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 19114313392 ps |
CPU time | 911.08 seconds |
Started | Jul 27 06:52:04 PM PDT 24 |
Finished | Jul 27 07:07:15 PM PDT 24 |
Peak memory | 373844 kb |
Host | smart-e22ee501-7b89-43dc-a920-0fda0d746fb4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100007151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3100007151 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.2945390327 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 672864644 ps |
CPU time | 5.99 seconds |
Started | Jul 27 06:51:57 PM PDT 24 |
Finished | Jul 27 06:52:03 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-5e573aa2-be54-43e2-a86b-b7493b970773 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945390327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2945390327 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.3646207860 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 55816618712 ps |
CPU time | 1871.98 seconds |
Started | Jul 27 06:52:12 PM PDT 24 |
Finished | Jul 27 07:23:24 PM PDT 24 |
Peak memory | 381116 kb |
Host | smart-9392dbd3-d86f-4058-bbac-d794d10ccfd5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646207860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.3646207860 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.394934477 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 2139878353 ps |
CPU time | 30.57 seconds |
Started | Jul 27 06:52:10 PM PDT 24 |
Finished | Jul 27 06:52:41 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-0537c6c2-6dff-4ae9-8555-9150fe8aa6b3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=394934477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.394934477 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1505932372 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 5715607798 ps |
CPU time | 190.46 seconds |
Started | Jul 27 06:52:03 PM PDT 24 |
Finished | Jul 27 06:55:13 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-96dd7840-90d6-47b6-bc2d-79535c1f0d6b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505932372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.1505932372 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.374521481 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 775524000 ps |
CPU time | 37.88 seconds |
Started | Jul 27 06:52:04 PM PDT 24 |
Finished | Jul 27 06:52:42 PM PDT 24 |
Peak memory | 290924 kb |
Host | smart-6e91ea09-b8b4-4b93-8344-8d01648550c4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374521481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.374521481 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3475283369 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 8008080476 ps |
CPU time | 533.02 seconds |
Started | Jul 27 06:52:23 PM PDT 24 |
Finished | Jul 27 07:01:16 PM PDT 24 |
Peak memory | 376052 kb |
Host | smart-8dc9a455-db3d-40c9-ae74-5347edd52fd7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475283369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.3475283369 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.635732932 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 11884762 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:52:32 PM PDT 24 |
Finished | Jul 27 06:52:32 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-2fc8fd82-a714-4e84-b906-29d6fafd3ab5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635732932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.635732932 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.4164764737 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 56079561548 ps |
CPU time | 988.69 seconds |
Started | Jul 27 06:52:12 PM PDT 24 |
Finished | Jul 27 07:08:41 PM PDT 24 |
Peak memory | 203944 kb |
Host | smart-1f306326-842e-4813-9d5c-dde6efb37fad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164764737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .4164764737 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.3609237719 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 105606172034 ps |
CPU time | 861.67 seconds |
Started | Jul 27 06:52:22 PM PDT 24 |
Finished | Jul 27 07:06:44 PM PDT 24 |
Peak memory | 379032 kb |
Host | smart-932b26ad-57d2-4a90-ac76-9b0679b8bc02 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609237719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.3609237719 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.1351940829 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 13029325081 ps |
CPU time | 62.13 seconds |
Started | Jul 27 06:52:22 PM PDT 24 |
Finished | Jul 27 06:53:24 PM PDT 24 |
Peak memory | 216612 kb |
Host | smart-85a1265b-79a5-4dda-bc64-d14ae413c5a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351940829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.1351940829 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.3507392812 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 3040165113 ps |
CPU time | 32.95 seconds |
Started | Jul 27 06:52:11 PM PDT 24 |
Finished | Jul 27 06:52:44 PM PDT 24 |
Peak memory | 289056 kb |
Host | smart-dacce84d-5699-4f4e-9b73-b17bbe18682b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507392812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.3507392812 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3404588079 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 9896229296 ps |
CPU time | 87.72 seconds |
Started | Jul 27 06:52:22 PM PDT 24 |
Finished | Jul 27 06:53:50 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-4fa92ce8-a488-4cd6-8f9f-d3d184fb94a9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404588079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.3404588079 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.809911900 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 41422220026 ps |
CPU time | 176.16 seconds |
Started | Jul 27 06:52:25 PM PDT 24 |
Finished | Jul 27 06:55:21 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-36653120-a7fe-4573-89d1-8372728979be |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809911900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _mem_walk.809911900 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.1369494613 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 19678549910 ps |
CPU time | 597.92 seconds |
Started | Jul 27 06:52:11 PM PDT 24 |
Finished | Jul 27 07:02:09 PM PDT 24 |
Peak memory | 377548 kb |
Host | smart-740e77c1-ac78-4a73-977c-8c1053558476 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369494613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.1369494613 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.263658573 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1565357186 ps |
CPU time | 3.9 seconds |
Started | Jul 27 06:52:12 PM PDT 24 |
Finished | Jul 27 06:52:16 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-9de5bbf8-a791-40b2-afe8-f881054522f2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263658573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s ram_ctrl_partial_access.263658573 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3079881330 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 27687432032 ps |
CPU time | 365.07 seconds |
Started | Jul 27 06:52:12 PM PDT 24 |
Finished | Jul 27 06:58:17 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-8adfef28-8e61-4bfb-89a6-7c166b10ccff |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079881330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3079881330 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.345764356 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 716165053 ps |
CPU time | 3.18 seconds |
Started | Jul 27 06:52:23 PM PDT 24 |
Finished | Jul 27 06:52:26 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-0006bfbe-0c3d-4c20-b0df-9ad6c04d78eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345764356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.345764356 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.2635245580 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 83452635209 ps |
CPU time | 2183.35 seconds |
Started | Jul 27 06:52:22 PM PDT 24 |
Finished | Jul 27 07:28:45 PM PDT 24 |
Peak memory | 382144 kb |
Host | smart-3ac7683c-164f-4b9d-9047-ca19a434bcd1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635245580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2635245580 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.1895104330 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 824412492 ps |
CPU time | 171.01 seconds |
Started | Jul 27 06:52:11 PM PDT 24 |
Finished | Jul 27 06:55:02 PM PDT 24 |
Peak memory | 368712 kb |
Host | smart-8af2a849-de3f-4887-8b26-a126c5000441 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895104330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1895104330 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.3891725559 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 1547141216423 ps |
CPU time | 6071.78 seconds |
Started | Jul 27 06:52:33 PM PDT 24 |
Finished | Jul 27 08:33:45 PM PDT 24 |
Peak memory | 379032 kb |
Host | smart-740db6b7-68cf-4126-9d90-bf50e451fefc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891725559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.3891725559 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.662046166 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 337868472 ps |
CPU time | 8.24 seconds |
Started | Jul 27 06:52:23 PM PDT 24 |
Finished | Jul 27 06:52:31 PM PDT 24 |
Peak memory | 218168 kb |
Host | smart-2de6acf7-40d2-4e50-abde-458f9c38a933 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=662046166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.662046166 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2991493960 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 3056344545 ps |
CPU time | 141.26 seconds |
Started | Jul 27 06:52:12 PM PDT 24 |
Finished | Jul 27 06:54:33 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-9540516c-fddc-42a5-900a-f8e90d79393d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991493960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.2991493960 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1910259287 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 3111635311 ps |
CPU time | 69.4 seconds |
Started | Jul 27 06:52:11 PM PDT 24 |
Finished | Jul 27 06:53:21 PM PDT 24 |
Peak memory | 363644 kb |
Host | smart-4cfdd18b-0875-4415-abda-f076a74f6d06 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910259287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1910259287 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1312378450 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 170102262093 ps |
CPU time | 1821.83 seconds |
Started | Jul 27 06:52:32 PM PDT 24 |
Finished | Jul 27 07:22:54 PM PDT 24 |
Peak memory | 380116 kb |
Host | smart-5b6c65e9-0734-40a8-b501-5aaa3377b51c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312378450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.1312378450 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.3549705118 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 30202322 ps |
CPU time | 0.69 seconds |
Started | Jul 27 06:52:52 PM PDT 24 |
Finished | Jul 27 06:52:53 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-ae4174bd-9296-4969-8e7c-1dd57e36b4b0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549705118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.3549705118 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.95707116 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 34949425470 ps |
CPU time | 1930.62 seconds |
Started | Jul 27 06:52:33 PM PDT 24 |
Finished | Jul 27 07:24:44 PM PDT 24 |
Peak memory | 203372 kb |
Host | smart-3d133fdf-305d-44b9-8c7b-318712ac3375 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95707116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.95707116 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.2868323767 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 15626643196 ps |
CPU time | 277.84 seconds |
Started | Jul 27 06:52:30 PM PDT 24 |
Finished | Jul 27 06:57:09 PM PDT 24 |
Peak memory | 352292 kb |
Host | smart-2c5be2ac-f078-4af3-a845-d790f73166f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868323767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.2868323767 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.180939743 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 40869299116 ps |
CPU time | 77.44 seconds |
Started | Jul 27 06:52:32 PM PDT 24 |
Finished | Jul 27 06:53:50 PM PDT 24 |
Peak memory | 215580 kb |
Host | smart-f3da368f-05dd-4292-a52d-65e04cca33a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180939743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_esc alation.180939743 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.1156742612 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 880295251 ps |
CPU time | 126.69 seconds |
Started | Jul 27 06:52:31 PM PDT 24 |
Finished | Jul 27 06:54:38 PM PDT 24 |
Peak memory | 358720 kb |
Host | smart-8530d2b8-4240-4fe4-83f8-c287072a712b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156742612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.1156742612 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1560783649 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 5113709188 ps |
CPU time | 167.79 seconds |
Started | Jul 27 06:52:41 PM PDT 24 |
Finished | Jul 27 06:55:29 PM PDT 24 |
Peak memory | 219568 kb |
Host | smart-44625e32-4ba9-49ce-b584-ce39812792c8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560783649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.1560783649 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.3964340450 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 38256370281 ps |
CPU time | 168.15 seconds |
Started | Jul 27 06:52:52 PM PDT 24 |
Finished | Jul 27 06:55:41 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-f6506d96-a028-437f-8ddd-adb9172759f1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964340450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.3964340450 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.106977988 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 88307377263 ps |
CPU time | 1115.03 seconds |
Started | Jul 27 06:52:32 PM PDT 24 |
Finished | Jul 27 07:11:07 PM PDT 24 |
Peak memory | 375980 kb |
Host | smart-601ea44d-c869-4672-b088-264071f21c42 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106977988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multip le_keys.106977988 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.835969702 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 5692592484 ps |
CPU time | 24.74 seconds |
Started | Jul 27 06:52:33 PM PDT 24 |
Finished | Jul 27 06:52:57 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-5dfd7fbf-a73f-4c18-994f-5fc77c1d6f58 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835969702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s ram_ctrl_partial_access.835969702 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1423853423 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 21780936891 ps |
CPU time | 515.93 seconds |
Started | Jul 27 06:52:32 PM PDT 24 |
Finished | Jul 27 07:01:08 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-c10f7534-7194-4571-b6f7-9035086f8f40 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423853423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.1423853423 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.427051474 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1001177642 ps |
CPU time | 3.27 seconds |
Started | Jul 27 06:52:52 PM PDT 24 |
Finished | Jul 27 06:52:56 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-f89640d9-e23e-4325-b9c1-63e97c8a107a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427051474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.427051474 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.3442284297 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 15642633842 ps |
CPU time | 613.48 seconds |
Started | Jul 27 06:52:33 PM PDT 24 |
Finished | Jul 27 07:02:47 PM PDT 24 |
Peak memory | 379052 kb |
Host | smart-0facff5f-f693-413a-afdc-636c242bf1d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442284297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3442284297 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.324917465 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 4634742514 ps |
CPU time | 18.99 seconds |
Started | Jul 27 06:52:32 PM PDT 24 |
Finished | Jul 27 06:52:51 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-daccdba2-eedd-472d-a92c-e6d5446ad7b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324917465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.324917465 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.787332040 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 189900653815 ps |
CPU time | 4206.04 seconds |
Started | Jul 27 06:52:40 PM PDT 24 |
Finished | Jul 27 08:02:46 PM PDT 24 |
Peak memory | 377392 kb |
Host | smart-08238ed7-5cae-4623-9ecf-949052ebf46d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787332040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_stress_all.787332040 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.360538766 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 1334778243 ps |
CPU time | 32.94 seconds |
Started | Jul 27 06:52:52 PM PDT 24 |
Finished | Jul 27 06:53:25 PM PDT 24 |
Peak memory | 211428 kb |
Host | smart-cc3f4025-58b5-410d-9f7f-acece7eaea64 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=360538766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.360538766 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2738039456 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 13490708232 ps |
CPU time | 141.68 seconds |
Started | Jul 27 06:52:32 PM PDT 24 |
Finished | Jul 27 06:54:54 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-2ba66ca8-acc0-4e6e-a8a2-ae15ef4e3524 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738039456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.2738039456 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1228638587 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 805470408 ps |
CPU time | 74.11 seconds |
Started | Jul 27 06:52:33 PM PDT 24 |
Finished | Jul 27 06:53:47 PM PDT 24 |
Peak memory | 314488 kb |
Host | smart-31eb7a31-ff5d-409a-825d-0fd085ea3471 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228638587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1228638587 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3729736492 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 11857651506 ps |
CPU time | 814.07 seconds |
Started | Jul 27 06:52:47 PM PDT 24 |
Finished | Jul 27 07:06:22 PM PDT 24 |
Peak memory | 380044 kb |
Host | smart-284326ba-1dfb-49d2-84ef-8c378055508b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729736492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.3729736492 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.3657362109 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 14181102 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:52:57 PM PDT 24 |
Finished | Jul 27 06:52:58 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-a2771441-4b3d-46aa-b2b3-34568bb38c4d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657362109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.3657362109 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.3190868438 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 126880209166 ps |
CPU time | 1289.82 seconds |
Started | Jul 27 06:52:40 PM PDT 24 |
Finished | Jul 27 07:14:10 PM PDT 24 |
Peak memory | 203808 kb |
Host | smart-04be09fc-85f0-4de6-aca5-e3adec2903cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190868438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .3190868438 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.2945173772 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 79217036864 ps |
CPU time | 722.34 seconds |
Started | Jul 27 06:52:49 PM PDT 24 |
Finished | Jul 27 07:04:52 PM PDT 24 |
Peak memory | 372180 kb |
Host | smart-e2ae7c64-bd4a-4314-bc70-507b8d22881b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945173772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.2945173772 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.1284934026 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 2559809329 ps |
CPU time | 17.14 seconds |
Started | Jul 27 06:52:49 PM PDT 24 |
Finished | Jul 27 06:53:06 PM PDT 24 |
Peak memory | 211640 kb |
Host | smart-ad514593-d926-43f0-8656-ee15ba9efe59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284934026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.1284934026 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.1280357146 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 2853197349 ps |
CPU time | 12.47 seconds |
Started | Jul 27 06:52:40 PM PDT 24 |
Finished | Jul 27 06:52:52 PM PDT 24 |
Peak memory | 235916 kb |
Host | smart-995b0e0a-2da0-4a54-b9e1-4d25e3252a3c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280357146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.1280357146 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3031416684 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 5529666261 ps |
CPU time | 72.69 seconds |
Started | Jul 27 06:52:57 PM PDT 24 |
Finished | Jul 27 06:54:10 PM PDT 24 |
Peak memory | 219576 kb |
Host | smart-14f29c02-67fd-4bd5-8e8c-c96ddc78c1d9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031416684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.3031416684 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.104273274 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 14580785391 ps |
CPU time | 334.11 seconds |
Started | Jul 27 06:52:55 PM PDT 24 |
Finished | Jul 27 06:58:29 PM PDT 24 |
Peak memory | 212200 kb |
Host | smart-590fb9f9-98cd-4677-b3b8-385be0fbd43d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104273274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _mem_walk.104273274 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.3165105343 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 37131179996 ps |
CPU time | 1104.61 seconds |
Started | Jul 27 06:52:40 PM PDT 24 |
Finished | Jul 27 07:11:05 PM PDT 24 |
Peak memory | 380088 kb |
Host | smart-35da2510-2dbc-4b62-9ca6-5754adb49639 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165105343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.3165105343 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.2630246040 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 2158537998 ps |
CPU time | 32.11 seconds |
Started | Jul 27 06:52:39 PM PDT 24 |
Finished | Jul 27 06:53:11 PM PDT 24 |
Peak memory | 285900 kb |
Host | smart-bd80e43e-f47a-44a5-bae1-749c9f481493 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630246040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.2630246040 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2899889093 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 5318219445 ps |
CPU time | 278.45 seconds |
Started | Jul 27 06:52:53 PM PDT 24 |
Finished | Jul 27 06:57:31 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-4a6ccbf9-db41-421a-93d7-83293fdf9559 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899889093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.2899889093 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.32356912 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 357727772 ps |
CPU time | 3.08 seconds |
Started | Jul 27 06:52:55 PM PDT 24 |
Finished | Jul 27 06:52:58 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-61efa29b-b044-42a4-9b9c-429f9e8df154 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.32356912 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.2358690532 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 13653789445 ps |
CPU time | 1207.49 seconds |
Started | Jul 27 06:52:48 PM PDT 24 |
Finished | Jul 27 07:12:55 PM PDT 24 |
Peak memory | 381180 kb |
Host | smart-262e598e-8b7c-4da4-9d3f-5def2ab5ce3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358690532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2358690532 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.2177232533 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 2376216169 ps |
CPU time | 15.67 seconds |
Started | Jul 27 06:52:41 PM PDT 24 |
Finished | Jul 27 06:52:57 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-0d43775f-f2f9-4863-9f3f-05100154815b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177232533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2177232533 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1054263024 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 212428992 ps |
CPU time | 9.24 seconds |
Started | Jul 27 06:52:57 PM PDT 24 |
Finished | Jul 27 06:53:06 PM PDT 24 |
Peak memory | 211372 kb |
Host | smart-66544595-c4fb-4e34-815c-151641fcc35b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1054263024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1054263024 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1604024718 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 2989670151 ps |
CPU time | 169.88 seconds |
Started | Jul 27 06:52:53 PM PDT 24 |
Finished | Jul 27 06:55:43 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-33f8ec08-fb94-487e-b9e9-0acf9f96abd3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604024718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.1604024718 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.613059531 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 3128420346 ps |
CPU time | 152.31 seconds |
Started | Jul 27 06:52:48 PM PDT 24 |
Finished | Jul 27 06:55:21 PM PDT 24 |
Peak memory | 371888 kb |
Host | smart-220accc3-3dc0-464b-b7e8-b9ec1071e02f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613059531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_throughput_w_partial_write.613059531 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.310754953 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 19331422068 ps |
CPU time | 517.75 seconds |
Started | Jul 27 06:53:05 PM PDT 24 |
Finished | Jul 27 07:01:43 PM PDT 24 |
Peak memory | 373380 kb |
Host | smart-910ca250-fc67-44ab-a0db-0bf721ab2b14 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310754953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 46.sram_ctrl_access_during_key_req.310754953 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.353556841 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 14484516 ps |
CPU time | 0.68 seconds |
Started | Jul 27 06:53:12 PM PDT 24 |
Finished | Jul 27 06:53:12 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-9d2c5b21-2582-4bdf-9590-b29bae2b0b90 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353556841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.353556841 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.1854824415 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 191944827318 ps |
CPU time | 2211.28 seconds |
Started | Jul 27 06:53:04 PM PDT 24 |
Finished | Jul 27 07:29:56 PM PDT 24 |
Peak memory | 203708 kb |
Host | smart-d73504f6-67ea-4fa3-94a3-f7d7ebce0a2d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854824415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .1854824415 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.441481775 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 19549027923 ps |
CPU time | 1172.19 seconds |
Started | Jul 27 06:53:04 PM PDT 24 |
Finished | Jul 27 07:12:37 PM PDT 24 |
Peak memory | 375436 kb |
Host | smart-10a258d7-cc3c-4a9a-b05e-7974536acb4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441481775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executabl e.441481775 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.3068530694 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 42333054366 ps |
CPU time | 57.47 seconds |
Started | Jul 27 06:53:07 PM PDT 24 |
Finished | Jul 27 06:54:05 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-e68fd428-e3ca-46ce-b792-d99134f90f07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068530694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.3068530694 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.2570022399 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 2887904600 ps |
CPU time | 39.96 seconds |
Started | Jul 27 06:53:04 PM PDT 24 |
Finished | Jul 27 06:53:44 PM PDT 24 |
Peak memory | 294884 kb |
Host | smart-b67e5614-f324-4097-8bdc-9072d3e3d967 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570022399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.2570022399 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.947532520 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 973666918 ps |
CPU time | 64.62 seconds |
Started | Jul 27 06:53:13 PM PDT 24 |
Finished | Jul 27 06:54:18 PM PDT 24 |
Peak memory | 211372 kb |
Host | smart-42b096a7-6fa1-4cc0-9ad4-be27c9c4fef8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947532520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sram_ctrl_mem_partial_access.947532520 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.120808912 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 23047530363 ps |
CPU time | 157.26 seconds |
Started | Jul 27 06:53:12 PM PDT 24 |
Finished | Jul 27 06:55:50 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-aaf74d6c-00a2-4170-9a70-aeabeff41d3c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120808912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _mem_walk.120808912 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.128122746 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 24758102862 ps |
CPU time | 656.28 seconds |
Started | Jul 27 06:52:55 PM PDT 24 |
Finished | Jul 27 07:03:51 PM PDT 24 |
Peak memory | 358600 kb |
Host | smart-1726a907-2903-4ac7-8c00-0a586a0bd82d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128122746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip le_keys.128122746 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.1156070123 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 1656703074 ps |
CPU time | 9.02 seconds |
Started | Jul 27 06:53:06 PM PDT 24 |
Finished | Jul 27 06:53:15 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-901b461c-07e9-4c85-a320-651c0cdb19b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156070123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.1156070123 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3033181611 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 66105967134 ps |
CPU time | 545.01 seconds |
Started | Jul 27 06:53:06 PM PDT 24 |
Finished | Jul 27 07:02:11 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-62205c6e-6c79-46a0-8595-826be98b31c4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033181611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.3033181611 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.3831791164 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 703668107 ps |
CPU time | 3.43 seconds |
Started | Jul 27 06:53:13 PM PDT 24 |
Finished | Jul 27 06:53:17 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-8bd654e7-11c1-4cea-85c8-c621e6275f4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831791164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3831791164 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.2814673217 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 18026903050 ps |
CPU time | 988.14 seconds |
Started | Jul 27 06:53:12 PM PDT 24 |
Finished | Jul 27 07:09:40 PM PDT 24 |
Peak memory | 378136 kb |
Host | smart-ff604317-d767-47be-a870-d39363406d01 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814673217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2814673217 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.2540605549 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 2712305874 ps |
CPU time | 138.01 seconds |
Started | Jul 27 06:52:56 PM PDT 24 |
Finished | Jul 27 06:55:14 PM PDT 24 |
Peak memory | 370800 kb |
Host | smart-bdcdce5e-d4f4-4790-a00c-4d21fe734ae8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540605549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2540605549 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.2591067547 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 929408994587 ps |
CPU time | 7370.73 seconds |
Started | Jul 27 06:53:13 PM PDT 24 |
Finished | Jul 27 08:56:04 PM PDT 24 |
Peak memory | 383188 kb |
Host | smart-353eb57d-ffab-449b-b58a-f9bbc732d1b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591067547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.2591067547 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.968747913 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 1201730470 ps |
CPU time | 13.26 seconds |
Started | Jul 27 06:53:12 PM PDT 24 |
Finished | Jul 27 06:53:26 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-6a3f24a0-0c1b-456b-9525-a74948e6b2e4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=968747913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.968747913 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3342574369 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 12111811983 ps |
CPU time | 208.46 seconds |
Started | Jul 27 06:53:05 PM PDT 24 |
Finished | Jul 27 06:56:34 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-7cba4a9e-fea2-48e6-be2a-b43936ca4f6a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342574369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.3342574369 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3910860607 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 3029732176 ps |
CPU time | 14.31 seconds |
Started | Jul 27 06:53:04 PM PDT 24 |
Finished | Jul 27 06:53:19 PM PDT 24 |
Peak memory | 243956 kb |
Host | smart-64ea9046-b105-48a9-b305-6b64a57966ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910860607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3910860607 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.794336714 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 35483125754 ps |
CPU time | 422.35 seconds |
Started | Jul 27 06:53:20 PM PDT 24 |
Finished | Jul 27 07:00:22 PM PDT 24 |
Peak memory | 377988 kb |
Host | smart-5a9a7b06-83ee-4b05-aa0d-2a1bfcba3624 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794336714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 47.sram_ctrl_access_during_key_req.794336714 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.1595824526 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 23232561 ps |
CPU time | 0.62 seconds |
Started | Jul 27 06:53:31 PM PDT 24 |
Finished | Jul 27 06:53:32 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-ef16475d-5353-4f9e-91a5-79707ede7ea9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595824526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1595824526 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.2447756017 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 113126285184 ps |
CPU time | 1633.4 seconds |
Started | Jul 27 06:53:22 PM PDT 24 |
Finished | Jul 27 07:20:36 PM PDT 24 |
Peak memory | 203808 kb |
Host | smart-9ccf309d-e715-40cf-8ca4-fba9521d6a90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447756017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .2447756017 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.1274598630 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 19916363163 ps |
CPU time | 1159.29 seconds |
Started | Jul 27 06:53:20 PM PDT 24 |
Finished | Jul 27 07:12:39 PM PDT 24 |
Peak memory | 379032 kb |
Host | smart-b140fb04-091a-4c26-abac-981c36c20605 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274598630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.1274598630 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.2435207504 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 41206360061 ps |
CPU time | 74.57 seconds |
Started | Jul 27 06:53:20 PM PDT 24 |
Finished | Jul 27 06:54:34 PM PDT 24 |
Peak memory | 211408 kb |
Host | smart-89983dee-d4dc-41d0-bd9f-c89b60d4519d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435207504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.2435207504 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.4128635934 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 1482933948 ps |
CPU time | 89.75 seconds |
Started | Jul 27 06:53:23 PM PDT 24 |
Finished | Jul 27 06:54:53 PM PDT 24 |
Peak memory | 330888 kb |
Host | smart-2dd380c8-0d72-4473-8e97-77b2b50e0131 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128635934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.4128635934 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3219782523 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 6558707874 ps |
CPU time | 84.79 seconds |
Started | Jul 27 06:53:30 PM PDT 24 |
Finished | Jul 27 06:54:55 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-cebd343b-bc1d-45ed-aa0b-44ec41564fe8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219782523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.3219782523 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.1192829206 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 114932692539 ps |
CPU time | 179.72 seconds |
Started | Jul 27 06:53:30 PM PDT 24 |
Finished | Jul 27 06:56:30 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-487e069b-0654-480e-913b-b26de34b80b2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192829206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.1192829206 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.215766057 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 6463151633 ps |
CPU time | 474.77 seconds |
Started | Jul 27 06:53:21 PM PDT 24 |
Finished | Jul 27 07:01:16 PM PDT 24 |
Peak memory | 374984 kb |
Host | smart-8844f306-682f-4a18-8d0b-eed5f219bd31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215766057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip le_keys.215766057 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.3198852003 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 13695579983 ps |
CPU time | 17.44 seconds |
Started | Jul 27 06:53:21 PM PDT 24 |
Finished | Jul 27 06:53:39 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-caacf3ae-421a-44ae-8b31-f4c7f4a0c294 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198852003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.3198852003 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1231676155 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 87290720865 ps |
CPU time | 594.37 seconds |
Started | Jul 27 06:53:21 PM PDT 24 |
Finished | Jul 27 07:03:16 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-7eac25c1-3db1-47a2-8c0b-7cb0ea561cc2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231676155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.1231676155 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.3563165865 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 1353117470 ps |
CPU time | 3.29 seconds |
Started | Jul 27 06:53:29 PM PDT 24 |
Finished | Jul 27 06:53:33 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-e96bbdf4-d9c9-4a21-bd47-1701b176182e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563165865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3563165865 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.548809184 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 34859508427 ps |
CPU time | 570.53 seconds |
Started | Jul 27 06:53:31 PM PDT 24 |
Finished | Jul 27 07:03:02 PM PDT 24 |
Peak memory | 368828 kb |
Host | smart-470b1da9-7409-4142-a3e6-c0c6fa58e09a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548809184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.548809184 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.711474480 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 1394380800 ps |
CPU time | 5.72 seconds |
Started | Jul 27 06:53:23 PM PDT 24 |
Finished | Jul 27 06:53:28 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-728fbcb8-0a31-46aa-975e-2fa0d12f907c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711474480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.711474480 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2435881717 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 9796057546 ps |
CPU time | 135.09 seconds |
Started | Jul 27 06:53:28 PM PDT 24 |
Finished | Jul 27 06:55:44 PM PDT 24 |
Peak memory | 244372 kb |
Host | smart-b66af042-67b4-4fea-9e70-6e0f36598c4c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2435881717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2435881717 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2675035361 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 4729670433 ps |
CPU time | 312.13 seconds |
Started | Jul 27 06:53:25 PM PDT 24 |
Finished | Jul 27 06:58:37 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-71c00f3f-0eac-4c15-b330-9e0a580f81fc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675035361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.2675035361 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3138321384 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 5590078462 ps |
CPU time | 106.65 seconds |
Started | Jul 27 06:53:23 PM PDT 24 |
Finished | Jul 27 06:55:10 PM PDT 24 |
Peak memory | 365528 kb |
Host | smart-a5d69ba6-d82f-47af-a41e-66b97b847f8f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138321384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.3138321384 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4050436560 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 19944596259 ps |
CPU time | 412.27 seconds |
Started | Jul 27 06:53:37 PM PDT 24 |
Finished | Jul 27 07:00:29 PM PDT 24 |
Peak memory | 378000 kb |
Host | smart-c8248829-1a09-49b0-90ec-279a5a9b42aa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050436560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.4050436560 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.3255967602 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 14804775 ps |
CPU time | 0.69 seconds |
Started | Jul 27 06:53:36 PM PDT 24 |
Finished | Jul 27 06:53:37 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-d9c937f0-0235-4e96-8910-c3b11c2ecc21 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255967602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3255967602 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.1565494090 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 364981784578 ps |
CPU time | 2048.86 seconds |
Started | Jul 27 06:53:29 PM PDT 24 |
Finished | Jul 27 07:27:39 PM PDT 24 |
Peak memory | 203864 kb |
Host | smart-85dab387-f67a-4aa3-8632-5209a02bca84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565494090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .1565494090 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.1135779663 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 96745470901 ps |
CPU time | 1532.13 seconds |
Started | Jul 27 06:53:37 PM PDT 24 |
Finished | Jul 27 07:19:09 PM PDT 24 |
Peak memory | 380108 kb |
Host | smart-1418034c-381e-4d08-bec8-e0ba23f8d649 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135779663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.1135779663 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.3280323027 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 10327383788 ps |
CPU time | 59.23 seconds |
Started | Jul 27 06:53:38 PM PDT 24 |
Finished | Jul 27 06:54:38 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-7f83d69a-4622-4fb4-a6f8-1748ee24c91f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280323027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.3280323027 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.149714276 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 5384466202 ps |
CPU time | 22.92 seconds |
Started | Jul 27 06:53:28 PM PDT 24 |
Finished | Jul 27 06:53:51 PM PDT 24 |
Peak memory | 259144 kb |
Host | smart-ca704242-6d8e-48e1-8883-053db3a19be6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149714276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.sram_ctrl_max_throughput.149714276 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2086734273 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 7304600888 ps |
CPU time | 83.24 seconds |
Started | Jul 27 06:53:38 PM PDT 24 |
Finished | Jul 27 06:55:02 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-5c698f8d-c436-4ab7-b0da-889161bf80b7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086734273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.2086734273 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.1475117026 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 10720169193 ps |
CPU time | 309.94 seconds |
Started | Jul 27 06:53:38 PM PDT 24 |
Finished | Jul 27 06:58:48 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-a1c0a921-6211-4da2-acce-aab33f0f22d9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475117026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.1475117026 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.3328373000 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 24073718592 ps |
CPU time | 889.58 seconds |
Started | Jul 27 06:53:29 PM PDT 24 |
Finished | Jul 27 07:08:19 PM PDT 24 |
Peak memory | 369824 kb |
Host | smart-d7d36aee-5491-416b-a6e1-38e183a10b32 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328373000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.3328373000 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.2196984064 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 10385626303 ps |
CPU time | 100.07 seconds |
Started | Jul 27 06:53:29 PM PDT 24 |
Finished | Jul 27 06:55:10 PM PDT 24 |
Peak memory | 338092 kb |
Host | smart-e2476f2f-909f-4274-b52d-f9300c676bd2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196984064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.2196984064 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1634711315 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 27546138794 ps |
CPU time | 385.08 seconds |
Started | Jul 27 06:53:28 PM PDT 24 |
Finished | Jul 27 06:59:53 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-45bbce63-11b2-4cf1-825f-e158b162d83c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634711315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.1634711315 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.845925103 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 715566545 ps |
CPU time | 3.21 seconds |
Started | Jul 27 06:53:36 PM PDT 24 |
Finished | Jul 27 06:53:39 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-fe389552-195a-44ce-8e07-5c1092789eba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845925103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.845925103 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.3145889061 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 7705902671 ps |
CPU time | 1463.96 seconds |
Started | Jul 27 06:53:37 PM PDT 24 |
Finished | Jul 27 07:18:01 PM PDT 24 |
Peak memory | 381092 kb |
Host | smart-a312f11e-761f-48d4-bcc5-872cd0711b32 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145889061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3145889061 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.4159157746 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 1781860273 ps |
CPU time | 11.33 seconds |
Started | Jul 27 06:53:28 PM PDT 24 |
Finished | Jul 27 06:53:40 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-e5ff9bed-3578-41d0-8de7-b0028f254174 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159157746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.4159157746 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.2318771382 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 128646323511 ps |
CPU time | 1790.19 seconds |
Started | Jul 27 06:53:36 PM PDT 24 |
Finished | Jul 27 07:23:26 PM PDT 24 |
Peak memory | 381052 kb |
Host | smart-a3d3436d-05fe-441b-b4a4-21a4e1207ed9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318771382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.2318771382 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4294589618 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 364183794 ps |
CPU time | 10.73 seconds |
Started | Jul 27 06:53:39 PM PDT 24 |
Finished | Jul 27 06:53:50 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-e775bf88-38f4-498e-92d4-bdb2f158385a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4294589618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.4294589618 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1532766558 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 23428456433 ps |
CPU time | 244.82 seconds |
Started | Jul 27 06:53:29 PM PDT 24 |
Finished | Jul 27 06:57:34 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-b11f9ff3-246d-494a-9b64-24c1eb58a351 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532766558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1532766558 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.781721866 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 1126347907 ps |
CPU time | 39.35 seconds |
Started | Jul 27 06:53:31 PM PDT 24 |
Finished | Jul 27 06:54:11 PM PDT 24 |
Peak memory | 291216 kb |
Host | smart-5a5aa37e-141c-4585-8e2d-357a27ff9c77 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781721866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.781721866 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2797036513 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 10873483114 ps |
CPU time | 1404.97 seconds |
Started | Jul 27 06:53:44 PM PDT 24 |
Finished | Jul 27 07:17:09 PM PDT 24 |
Peak memory | 379004 kb |
Host | smart-9ea93083-3394-4170-ae5f-417c2832b1a9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797036513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.2797036513 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.4268684994 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 22812555 ps |
CPU time | 0.67 seconds |
Started | Jul 27 06:53:55 PM PDT 24 |
Finished | Jul 27 06:53:56 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-f82d0659-a1f6-45bd-912a-b1428d523603 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268684994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.4268684994 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.887126823 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 62265711587 ps |
CPU time | 1029.05 seconds |
Started | Jul 27 06:53:36 PM PDT 24 |
Finished | Jul 27 07:10:46 PM PDT 24 |
Peak memory | 203316 kb |
Host | smart-232fffc1-6be6-4448-8488-e85f5cd36ebe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887126823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection. 887126823 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.3192402678 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 66685199740 ps |
CPU time | 929.43 seconds |
Started | Jul 27 06:53:46 PM PDT 24 |
Finished | Jul 27 07:09:16 PM PDT 24 |
Peak memory | 372948 kb |
Host | smart-368aa633-90b0-45a7-bab7-b0caab1aa7d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192402678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.3192402678 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.3718845360 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 45132637317 ps |
CPU time | 70.81 seconds |
Started | Jul 27 06:53:43 PM PDT 24 |
Finished | Jul 27 06:54:54 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-02d9ff9e-334b-4241-b0eb-6f89c817f7d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718845360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.3718845360 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.1340993647 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 1525136792 ps |
CPU time | 67.69 seconds |
Started | Jul 27 06:53:45 PM PDT 24 |
Finished | Jul 27 06:54:53 PM PDT 24 |
Peak memory | 330060 kb |
Host | smart-e83fdc0a-c218-424f-8104-8da34449b799 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340993647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.1340993647 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1988896087 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 4990741880 ps |
CPU time | 152.96 seconds |
Started | Jul 27 06:53:52 PM PDT 24 |
Finished | Jul 27 06:56:25 PM PDT 24 |
Peak memory | 219460 kb |
Host | smart-adc1915f-279b-41ae-b5dd-04fccb380423 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988896087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.1988896087 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.1377942617 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 41377182394 ps |
CPU time | 175.74 seconds |
Started | Jul 27 06:53:52 PM PDT 24 |
Finished | Jul 27 06:56:48 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-8b68086c-e862-45b8-aded-8c6bf8f3611f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377942617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.1377942617 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.3565450809 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 21239467654 ps |
CPU time | 1519.37 seconds |
Started | Jul 27 06:53:37 PM PDT 24 |
Finished | Jul 27 07:18:57 PM PDT 24 |
Peak memory | 380124 kb |
Host | smart-54694d7f-9940-41d3-81a4-c811263aa591 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565450809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.3565450809 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.2984249038 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 3980178450 ps |
CPU time | 34.74 seconds |
Started | Jul 27 06:53:46 PM PDT 24 |
Finished | Jul 27 06:54:21 PM PDT 24 |
Peak memory | 276280 kb |
Host | smart-53ba3ca7-4e6f-4ff5-a360-c9affe7768ba |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984249038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.2984249038 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3130466257 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 26070582319 ps |
CPU time | 277.54 seconds |
Started | Jul 27 06:53:44 PM PDT 24 |
Finished | Jul 27 06:58:22 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-bbe63014-7324-4b3b-9879-44b8019699d1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130466257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.3130466257 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.761965830 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 2176414710 ps |
CPU time | 3.18 seconds |
Started | Jul 27 06:53:55 PM PDT 24 |
Finished | Jul 27 06:53:58 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-3264e2bb-926a-409f-9f47-d2803cd4a127 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761965830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.761965830 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.1378726408 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 3590284971 ps |
CPU time | 415.39 seconds |
Started | Jul 27 06:53:54 PM PDT 24 |
Finished | Jul 27 07:00:49 PM PDT 24 |
Peak memory | 372184 kb |
Host | smart-aa47fcf3-235e-48e3-a56b-c98c0bf057f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378726408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1378726408 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.4260990030 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 3099961872 ps |
CPU time | 19.52 seconds |
Started | Jul 27 06:53:38 PM PDT 24 |
Finished | Jul 27 06:53:57 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-b57f5f0c-c974-46c1-86ee-6fef4fb9aecc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260990030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.4260990030 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.3161571545 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 321307847167 ps |
CPU time | 1973.22 seconds |
Started | Jul 27 06:53:53 PM PDT 24 |
Finished | Jul 27 07:26:46 PM PDT 24 |
Peak memory | 380136 kb |
Host | smart-7a1788f9-158d-4a9c-9154-235db0e4c34b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161571545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.3161571545 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.215413134 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 2320163217 ps |
CPU time | 106.11 seconds |
Started | Jul 27 06:53:53 PM PDT 24 |
Finished | Jul 27 06:55:39 PM PDT 24 |
Peak memory | 314172 kb |
Host | smart-daccc4d6-d4ec-47af-989d-4515950ba7c7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=215413134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.215413134 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1589071140 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 7756794290 ps |
CPU time | 275.44 seconds |
Started | Jul 27 06:53:43 PM PDT 24 |
Finished | Jul 27 06:58:19 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-cabae116-e634-420a-9175-60cb9d66a876 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589071140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.1589071140 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2668600557 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 1470562705 ps |
CPU time | 18.2 seconds |
Started | Jul 27 06:53:44 PM PDT 24 |
Finished | Jul 27 06:54:03 PM PDT 24 |
Peak memory | 257472 kb |
Host | smart-4a11e006-a97e-4604-9867-9b0e28f29a68 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668600557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2668600557 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.611246490 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 6391733643 ps |
CPU time | 339.57 seconds |
Started | Jul 27 06:45:19 PM PDT 24 |
Finished | Jul 27 06:50:58 PM PDT 24 |
Peak memory | 340212 kb |
Host | smart-cef36951-0ad9-4a12-a2c4-0c590e91c58b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611246490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_access_during_key_req.611246490 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.1012048341 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 18076852 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:45:29 PM PDT 24 |
Finished | Jul 27 06:45:30 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-fa30f29a-cdf4-4101-a102-9b6749a5f084 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012048341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.1012048341 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.2419927508 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 105891923387 ps |
CPU time | 2485.78 seconds |
Started | Jul 27 06:45:24 PM PDT 24 |
Finished | Jul 27 07:26:50 PM PDT 24 |
Peak memory | 203772 kb |
Host | smart-e565a803-1161-49e9-aa78-d772bf7a4a2d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419927508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 2419927508 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.685389464 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 8822494698 ps |
CPU time | 1263.16 seconds |
Started | Jul 27 06:45:22 PM PDT 24 |
Finished | Jul 27 07:06:25 PM PDT 24 |
Peak memory | 378080 kb |
Host | smart-3ae1fa1a-2f9e-4776-970c-420a4a4f17a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685389464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable .685389464 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.1690407388 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 27706033390 ps |
CPU time | 89.33 seconds |
Started | Jul 27 06:45:20 PM PDT 24 |
Finished | Jul 27 06:46:49 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-70c8bf17-138b-451c-9696-46043482e764 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690407388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.1690407388 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.241214800 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 744743912 ps |
CPU time | 51.35 seconds |
Started | Jul 27 06:45:20 PM PDT 24 |
Finished | Jul 27 06:46:11 PM PDT 24 |
Peak memory | 327920 kb |
Host | smart-a4eb0e53-f6f7-472f-9df0-90933bddb297 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241214800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_max_throughput.241214800 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2855533199 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 8784593326 ps |
CPU time | 146.7 seconds |
Started | Jul 27 06:45:30 PM PDT 24 |
Finished | Jul 27 06:47:56 PM PDT 24 |
Peak memory | 219412 kb |
Host | smart-5f9ec832-c754-4dc4-8eaf-f650cee60531 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855533199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.2855533199 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.26543433 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 10721611837 ps |
CPU time | 291.66 seconds |
Started | Jul 27 06:45:30 PM PDT 24 |
Finished | Jul 27 06:50:21 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-663e114d-7286-4493-bb8e-16bc17ee7de3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26543433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_m em_walk.26543433 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.3671590540 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 36083561145 ps |
CPU time | 1057.17 seconds |
Started | Jul 27 06:45:18 PM PDT 24 |
Finished | Jul 27 07:02:56 PM PDT 24 |
Peak memory | 382144 kb |
Host | smart-6ebab4f9-734b-4eee-9c80-e248ec3919e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671590540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.3671590540 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.40007165 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 805600722 ps |
CPU time | 26.63 seconds |
Started | Jul 27 06:45:18 PM PDT 24 |
Finished | Jul 27 06:45:45 PM PDT 24 |
Peak memory | 273364 kb |
Host | smart-19a1dd32-e92d-4bc7-9017-af34ec4c7db1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40007165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sra m_ctrl_partial_access.40007165 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2371988497 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 83256860213 ps |
CPU time | 532.01 seconds |
Started | Jul 27 06:45:20 PM PDT 24 |
Finished | Jul 27 06:54:13 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-7ea9395b-1d67-4aab-962b-337f61ee565d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371988497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.2371988497 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.616849493 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 2390616225 ps |
CPU time | 3.74 seconds |
Started | Jul 27 06:45:21 PM PDT 24 |
Finished | Jul 27 06:45:25 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-f1118e14-8998-489b-80ff-6bfb50772aa7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616849493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.616849493 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.682475541 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 22755378721 ps |
CPU time | 689.27 seconds |
Started | Jul 27 06:45:18 PM PDT 24 |
Finished | Jul 27 06:56:48 PM PDT 24 |
Peak memory | 378088 kb |
Host | smart-4161050c-c92c-4bed-a6a6-6eacc3162c9c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682475541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.682475541 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.1436385581 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 779275774 ps |
CPU time | 70.28 seconds |
Started | Jul 27 06:45:25 PM PDT 24 |
Finished | Jul 27 06:46:35 PM PDT 24 |
Peak memory | 312484 kb |
Host | smart-bee5cf28-db8b-44e4-8c63-ba028e767a70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436385581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1436385581 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.447088514 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 39751458408 ps |
CPU time | 2642.07 seconds |
Started | Jul 27 06:45:28 PM PDT 24 |
Finished | Jul 27 07:29:30 PM PDT 24 |
Peak memory | 320096 kb |
Host | smart-0855b679-faec-4e10-be48-ec7c5f3f5c9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447088514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_stress_all.447088514 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2364473770 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 871917448 ps |
CPU time | 9.11 seconds |
Started | Jul 27 06:45:36 PM PDT 24 |
Finished | Jul 27 06:45:45 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-ffa087a1-f7c5-4894-aee7-a96bae2a3e2a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2364473770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2364473770 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3917285945 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 8082921455 ps |
CPU time | 186.08 seconds |
Started | Jul 27 06:45:22 PM PDT 24 |
Finished | Jul 27 06:48:28 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-4887629d-c5a3-4f14-a3a4-6a94912e457c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917285945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.3917285945 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1317130573 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 824525277 ps |
CPU time | 109.09 seconds |
Started | Jul 27 06:45:22 PM PDT 24 |
Finished | Jul 27 06:47:12 PM PDT 24 |
Peak memory | 354336 kb |
Host | smart-be5f7f6f-346e-4667-b6db-354f1526cf8e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317130573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1317130573 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.4174213107 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 14342245572 ps |
CPU time | 1502.13 seconds |
Started | Jul 27 06:45:28 PM PDT 24 |
Finished | Jul 27 07:10:30 PM PDT 24 |
Peak memory | 379060 kb |
Host | smart-45987b35-6537-48ba-89ba-4124effc9c6c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174213107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.4174213107 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.1480109605 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 16213154 ps |
CPU time | 0.69 seconds |
Started | Jul 27 06:45:34 PM PDT 24 |
Finished | Jul 27 06:45:35 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-192f7872-566a-469e-a48b-962a13a43f7f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480109605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1480109605 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.2417847849 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 165836719837 ps |
CPU time | 1963.66 seconds |
Started | Jul 27 06:45:29 PM PDT 24 |
Finished | Jul 27 07:18:13 PM PDT 24 |
Peak memory | 203736 kb |
Host | smart-c96aa5ab-8f24-43ce-82fc-639ff99487f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417847849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 2417847849 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.1570480648 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 25255935813 ps |
CPU time | 1389.6 seconds |
Started | Jul 27 06:45:33 PM PDT 24 |
Finished | Jul 27 07:08:42 PM PDT 24 |
Peak memory | 380076 kb |
Host | smart-1c009dec-7bbf-43ba-a438-33a2e265d7aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570480648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.1570480648 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.110270848 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 12765533362 ps |
CPU time | 72.62 seconds |
Started | Jul 27 06:45:33 PM PDT 24 |
Finished | Jul 27 06:46:45 PM PDT 24 |
Peak memory | 211296 kb |
Host | smart-598d672a-2998-4e9a-84ff-c2fdbcee697b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110270848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esca lation.110270848 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.992095082 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 1577097585 ps |
CPU time | 39.57 seconds |
Started | Jul 27 06:45:28 PM PDT 24 |
Finished | Jul 27 06:46:08 PM PDT 24 |
Peak memory | 295372 kb |
Host | smart-4d242714-b6c3-4234-ad35-0bc1e79c00b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992095082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.sram_ctrl_max_throughput.992095082 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2253048767 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 10942284110 ps |
CPU time | 90.82 seconds |
Started | Jul 27 06:45:30 PM PDT 24 |
Finished | Jul 27 06:47:01 PM PDT 24 |
Peak memory | 219536 kb |
Host | smart-72673173-11a7-4217-8b65-b09d02f0cae7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253048767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.2253048767 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.2219785468 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 37335258247 ps |
CPU time | 178.6 seconds |
Started | Jul 27 06:45:31 PM PDT 24 |
Finished | Jul 27 06:48:29 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-8efcb408-dd06-4757-b8cb-48235769e5e7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219785468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.2219785468 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.1777986592 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 147449706891 ps |
CPU time | 1405.44 seconds |
Started | Jul 27 06:45:31 PM PDT 24 |
Finished | Jul 27 07:08:56 PM PDT 24 |
Peak memory | 380052 kb |
Host | smart-86f4a812-6021-4a6d-af0f-41224a65f36a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777986592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.1777986592 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.3438522721 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 1564013863 ps |
CPU time | 11.75 seconds |
Started | Jul 27 06:45:28 PM PDT 24 |
Finished | Jul 27 06:45:40 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-d89f6c5a-c352-4fad-9675-06940eabb3e9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438522721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.3438522721 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1974948444 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 84443744100 ps |
CPU time | 567.48 seconds |
Started | Jul 27 06:45:27 PM PDT 24 |
Finished | Jul 27 06:54:55 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-bc756666-b7c5-4011-9e32-fc727e9da325 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974948444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.1974948444 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.902550244 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 1881464760 ps |
CPU time | 3.19 seconds |
Started | Jul 27 06:45:29 PM PDT 24 |
Finished | Jul 27 06:45:33 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-b4977189-4a7b-45ce-be06-ebfe18cb3000 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902550244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.902550244 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2037763355 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 5593929560 ps |
CPU time | 394.5 seconds |
Started | Jul 27 06:45:32 PM PDT 24 |
Finished | Jul 27 06:52:06 PM PDT 24 |
Peak memory | 359616 kb |
Host | smart-9c710246-d569-41b4-bc84-f67b40935b0e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037763355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2037763355 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.3407896202 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 3205271828 ps |
CPU time | 9.59 seconds |
Started | Jul 27 06:45:28 PM PDT 24 |
Finished | Jul 27 06:45:38 PM PDT 24 |
Peak memory | 219504 kb |
Host | smart-ef6261f1-46e9-45f8-a3a7-eacbc0a89ae7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407896202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3407896202 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.3542548416 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 274025272176 ps |
CPU time | 4134.48 seconds |
Started | Jul 27 06:45:30 PM PDT 24 |
Finished | Jul 27 07:54:25 PM PDT 24 |
Peak memory | 377208 kb |
Host | smart-a46b49fc-295f-42bb-84de-714b6167ec4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542548416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.3542548416 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1037695014 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 4064882839 ps |
CPU time | 38.32 seconds |
Started | Jul 27 06:45:27 PM PDT 24 |
Finished | Jul 27 06:46:05 PM PDT 24 |
Peak memory | 211496 kb |
Host | smart-d5a1fd70-aef9-4ffd-a83f-ee25c2447916 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1037695014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1037695014 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3256552485 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 4259667854 ps |
CPU time | 263 seconds |
Started | Jul 27 06:45:30 PM PDT 24 |
Finished | Jul 27 06:49:53 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-72c18fb9-89ab-4914-8801-20488e20ddca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256552485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.3256552485 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.567377490 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 1459223447 ps |
CPU time | 37.48 seconds |
Started | Jul 27 06:45:30 PM PDT 24 |
Finished | Jul 27 06:46:07 PM PDT 24 |
Peak memory | 290968 kb |
Host | smart-f9b245b7-156b-480e-bf87-8e7b7e4cbc37 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567377490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.567377490 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1481515186 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 191846877528 ps |
CPU time | 1574.88 seconds |
Started | Jul 27 06:45:40 PM PDT 24 |
Finished | Jul 27 07:11:55 PM PDT 24 |
Peak memory | 380068 kb |
Host | smart-6ee6c57e-2f7d-4460-91bc-ce2e80a997c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481515186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.1481515186 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.3669824003 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 24358558 ps |
CPU time | 0.66 seconds |
Started | Jul 27 06:45:42 PM PDT 24 |
Finished | Jul 27 06:45:42 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-eb18a7eb-f71d-40e6-b3ae-e54caee22265 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669824003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3669824003 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.1148055349 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 119789163746 ps |
CPU time | 1982.2 seconds |
Started | Jul 27 06:45:30 PM PDT 24 |
Finished | Jul 27 07:18:32 PM PDT 24 |
Peak memory | 203980 kb |
Host | smart-93109499-3a5f-4d3c-885e-abe5ca386517 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148055349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 1148055349 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.752072162 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 96026097596 ps |
CPU time | 579 seconds |
Started | Jul 27 06:45:39 PM PDT 24 |
Finished | Jul 27 06:55:19 PM PDT 24 |
Peak memory | 353488 kb |
Host | smart-ccfc1735-cab3-41c0-918e-25a20b96c789 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752072162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable .752072162 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.3899502237 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 41630710150 ps |
CPU time | 63.97 seconds |
Started | Jul 27 06:45:38 PM PDT 24 |
Finished | Jul 27 06:46:42 PM PDT 24 |
Peak memory | 215556 kb |
Host | smart-4ac893de-19fb-4702-a55c-bc7520ade07c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899502237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.3899502237 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.702274567 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 741247021 ps |
CPU time | 59.07 seconds |
Started | Jul 27 06:45:29 PM PDT 24 |
Finished | Jul 27 06:46:28 PM PDT 24 |
Peak memory | 305404 kb |
Host | smart-fe34c09b-5d1c-4c35-9ce3-d70c3f00d7a5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702274567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.sram_ctrl_max_throughput.702274567 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2402909311 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 5160338409 ps |
CPU time | 79.23 seconds |
Started | Jul 27 06:45:43 PM PDT 24 |
Finished | Jul 27 06:47:03 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-927b870e-33ea-4aec-99b8-e97eff3c1da3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402909311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.2402909311 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.3119905078 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 65634234709 ps |
CPU time | 294.12 seconds |
Started | Jul 27 06:45:37 PM PDT 24 |
Finished | Jul 27 06:50:32 PM PDT 24 |
Peak memory | 212224 kb |
Host | smart-9ead91a5-cf2e-45d9-8ee3-9b1503cbaa26 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119905078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.3119905078 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.4238661561 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 18010748918 ps |
CPU time | 956.68 seconds |
Started | Jul 27 06:45:30 PM PDT 24 |
Finished | Jul 27 07:01:27 PM PDT 24 |
Peak memory | 379160 kb |
Host | smart-9bc42bf1-58f2-4b25-a8fb-39a18a034d64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238661561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.4238661561 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.3069427245 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 406590816 ps |
CPU time | 13.72 seconds |
Started | Jul 27 06:45:29 PM PDT 24 |
Finished | Jul 27 06:45:43 PM PDT 24 |
Peak memory | 254556 kb |
Host | smart-246da81d-c4ea-4398-8d8e-f84de00c482b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069427245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.3069427245 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.2453302418 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 694594585 ps |
CPU time | 3.27 seconds |
Started | Jul 27 06:45:40 PM PDT 24 |
Finished | Jul 27 06:45:43 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-82d2e5c0-4d56-43d7-95d7-4e4370eb0c69 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453302418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2453302418 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.1591664737 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 2709066548 ps |
CPU time | 761.05 seconds |
Started | Jul 27 06:45:39 PM PDT 24 |
Finished | Jul 27 06:58:20 PM PDT 24 |
Peak memory | 381148 kb |
Host | smart-45d82c78-bebe-4dda-b066-6b5d31b3b44d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591664737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1591664737 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.1138902681 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 2163116536 ps |
CPU time | 133.87 seconds |
Started | Jul 27 06:45:28 PM PDT 24 |
Finished | Jul 27 06:47:42 PM PDT 24 |
Peak memory | 371076 kb |
Host | smart-25e6ee23-3766-4027-8519-44b97d340702 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138902681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.1138902681 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.2248603440 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 230067251760 ps |
CPU time | 6321.13 seconds |
Started | Jul 27 06:45:39 PM PDT 24 |
Finished | Jul 27 08:31:01 PM PDT 24 |
Peak memory | 381168 kb |
Host | smart-96b3cd3d-e58d-4f16-bfc1-4f64fe94de50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248603440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.2248603440 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2410756014 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 421229215 ps |
CPU time | 15.93 seconds |
Started | Jul 27 06:45:40 PM PDT 24 |
Finished | Jul 27 06:45:56 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-d347291d-8d92-4dcf-88d9-2a8d45abab37 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2410756014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2410756014 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1307342318 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 4807086856 ps |
CPU time | 264.33 seconds |
Started | Jul 27 06:45:28 PM PDT 24 |
Finished | Jul 27 06:49:52 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-1db34781-150d-4ea0-a82e-0b21336332ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307342318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.1307342318 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2592144080 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 733386465 ps |
CPU time | 12.53 seconds |
Started | Jul 27 06:45:28 PM PDT 24 |
Finished | Jul 27 06:45:41 PM PDT 24 |
Peak memory | 237180 kb |
Host | smart-efcd57c5-e89f-4dad-bae5-cba4158039e7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592144080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2592144080 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2852499941 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 131376814675 ps |
CPU time | 1082.34 seconds |
Started | Jul 27 06:45:37 PM PDT 24 |
Finished | Jul 27 07:03:40 PM PDT 24 |
Peak memory | 380096 kb |
Host | smart-54a920a4-cd09-46b3-9ae1-6ed3f3ca7c8d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852499941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.2852499941 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.1058113572 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 25902998 ps |
CPU time | 0.65 seconds |
Started | Jul 27 06:45:49 PM PDT 24 |
Finished | Jul 27 06:45:50 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-3f7e4aba-8144-4f32-888c-998a3908be76 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058113572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.1058113572 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.2579832504 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 84654579093 ps |
CPU time | 1669.41 seconds |
Started | Jul 27 06:45:43 PM PDT 24 |
Finished | Jul 27 07:13:33 PM PDT 24 |
Peak memory | 203908 kb |
Host | smart-5da06b63-e6be-4cbe-9658-de0176bab17a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579832504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 2579832504 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.1388445928 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 22876447155 ps |
CPU time | 555.02 seconds |
Started | Jul 27 06:45:40 PM PDT 24 |
Finished | Jul 27 06:54:55 PM PDT 24 |
Peak memory | 370772 kb |
Host | smart-e72c4b51-50f0-4fd8-b294-c3fd253166c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388445928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.1388445928 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.351872343 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 51389162000 ps |
CPU time | 92.16 seconds |
Started | Jul 27 06:45:38 PM PDT 24 |
Finished | Jul 27 06:47:10 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-16a31999-dcc9-4fee-aa81-8ebfa7ddfddc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351872343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca lation.351872343 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.1518791840 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 1353649947 ps |
CPU time | 22.36 seconds |
Started | Jul 27 06:45:41 PM PDT 24 |
Finished | Jul 27 06:46:04 PM PDT 24 |
Peak memory | 261640 kb |
Host | smart-f4315f0c-7829-41a4-a5b9-1804de90c021 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518791840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.1518791840 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.4051102075 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 2685206178 ps |
CPU time | 73.72 seconds |
Started | Jul 27 06:45:57 PM PDT 24 |
Finished | Jul 27 06:47:11 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-6a053c66-4860-4ce4-96e4-e5f502217a4a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051102075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.4051102075 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.485925231 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 21875113025 ps |
CPU time | 313.69 seconds |
Started | Jul 27 06:45:52 PM PDT 24 |
Finished | Jul 27 06:51:06 PM PDT 24 |
Peak memory | 212352 kb |
Host | smart-59a08183-1abf-4952-b7cd-6dc30c8ed84a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485925231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ mem_walk.485925231 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.1015447632 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 13514546220 ps |
CPU time | 283.03 seconds |
Started | Jul 27 06:45:42 PM PDT 24 |
Finished | Jul 27 06:50:25 PM PDT 24 |
Peak memory | 346360 kb |
Host | smart-0f34f2ff-429d-4f8f-b893-4e3ea84251b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015447632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.1015447632 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.3499820706 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 987649033 ps |
CPU time | 11.13 seconds |
Started | Jul 27 06:45:39 PM PDT 24 |
Finished | Jul 27 06:45:51 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-3fb37c3a-68f5-4dbf-97fb-fc8ef23b8e23 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499820706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.3499820706 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2566300446 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 4182043979 ps |
CPU time | 239.7 seconds |
Started | Jul 27 06:45:38 PM PDT 24 |
Finished | Jul 27 06:49:38 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-61253c57-75b6-495e-8167-d7c989a64a0e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566300446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.2566300446 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.626473092 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 349074833 ps |
CPU time | 3.21 seconds |
Started | Jul 27 06:45:49 PM PDT 24 |
Finished | Jul 27 06:45:52 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-1671915d-3679-4b93-b1f2-e8ff4364d948 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626473092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.626473092 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.1092182373 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 3415931065 ps |
CPU time | 1101.98 seconds |
Started | Jul 27 06:45:38 PM PDT 24 |
Finished | Jul 27 07:04:00 PM PDT 24 |
Peak memory | 382060 kb |
Host | smart-68e699b2-6956-4e45-9948-d98666a6b205 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092182373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1092182373 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.1313682405 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 1020863078 ps |
CPU time | 18.9 seconds |
Started | Jul 27 06:45:38 PM PDT 24 |
Finished | Jul 27 06:45:57 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-9ac8322a-9f29-4ea3-8983-82d9e4a91c96 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313682405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1313682405 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.2280274230 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 949760022783 ps |
CPU time | 6817.91 seconds |
Started | Jul 27 06:45:50 PM PDT 24 |
Finished | Jul 27 08:39:28 PM PDT 24 |
Peak memory | 381144 kb |
Host | smart-75055a0d-32eb-4682-9f32-54c14dea3d02 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280274230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.2280274230 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1518413577 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 1077072394 ps |
CPU time | 50.37 seconds |
Started | Jul 27 06:45:49 PM PDT 24 |
Finished | Jul 27 06:46:39 PM PDT 24 |
Peak memory | 212856 kb |
Host | smart-4133a5bf-da6f-428b-acac-7626e1980cd7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1518413577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1518413577 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2196575836 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 81545912405 ps |
CPU time | 253.08 seconds |
Started | Jul 27 06:45:39 PM PDT 24 |
Finished | Jul 27 06:49:52 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-ff2fea27-24c0-4530-bd71-c533010e1f1d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196575836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.2196575836 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3719530351 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 757873606 ps |
CPU time | 35.92 seconds |
Started | Jul 27 06:45:41 PM PDT 24 |
Finished | Jul 27 06:46:17 PM PDT 24 |
Peak memory | 284948 kb |
Host | smart-0ece435a-cc87-467f-8706-736e8c901136 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719530351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.3719530351 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1830859040 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 11216330965 ps |
CPU time | 606.02 seconds |
Started | Jul 27 06:45:51 PM PDT 24 |
Finished | Jul 27 06:55:57 PM PDT 24 |
Peak memory | 367868 kb |
Host | smart-5901314d-7b3e-495d-a7b4-877a8af01bca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830859040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.1830859040 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.2821826426 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 45217116 ps |
CPU time | 0.62 seconds |
Started | Jul 27 06:45:59 PM PDT 24 |
Finished | Jul 27 06:46:00 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-9475a75f-c122-453d-9c28-1db0cd4ece94 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821826426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2821826426 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.653733607 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 280753656635 ps |
CPU time | 1519.85 seconds |
Started | Jul 27 06:45:49 PM PDT 24 |
Finished | Jul 27 07:11:10 PM PDT 24 |
Peak memory | 203864 kb |
Host | smart-3d3c9696-5423-4677-82d7-f6a8e36830f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653733607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.653733607 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.2154288879 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 20838420600 ps |
CPU time | 960.98 seconds |
Started | Jul 27 06:45:49 PM PDT 24 |
Finished | Jul 27 07:01:50 PM PDT 24 |
Peak memory | 375848 kb |
Host | smart-109eec70-c7f6-427e-80ae-3bc8212ebff4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154288879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.2154288879 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.4118607544 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 10319375594 ps |
CPU time | 60.55 seconds |
Started | Jul 27 06:45:49 PM PDT 24 |
Finished | Jul 27 06:46:49 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-72c83bdb-bcbb-4bb4-bd41-33349a43d6eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118607544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.4118607544 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.3585191031 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 2865245287 ps |
CPU time | 13.36 seconds |
Started | Jul 27 06:45:49 PM PDT 24 |
Finished | Jul 27 06:46:03 PM PDT 24 |
Peak memory | 238100 kb |
Host | smart-0547400e-b59b-4598-996d-cdb9256a0a19 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585191031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.3585191031 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1010889042 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 6288605641 ps |
CPU time | 131.34 seconds |
Started | Jul 27 06:45:49 PM PDT 24 |
Finished | Jul 27 06:48:00 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-836028aa-6783-4369-9af8-4e55cf5ef792 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010889042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.1010889042 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.3998904262 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 197213476669 ps |
CPU time | 408.83 seconds |
Started | Jul 27 06:45:51 PM PDT 24 |
Finished | Jul 27 06:52:40 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-66738c91-50cf-435b-89d9-5b34980ab664 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998904262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3998904262 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.3565840929 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 9874570978 ps |
CPU time | 269.37 seconds |
Started | Jul 27 06:45:52 PM PDT 24 |
Finished | Jul 27 06:50:22 PM PDT 24 |
Peak memory | 364148 kb |
Host | smart-d040fe05-74f3-4adc-9504-f4f3ed8a4c60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565840929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.3565840929 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.3179216405 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 2710523302 ps |
CPU time | 7.08 seconds |
Started | Jul 27 06:45:56 PM PDT 24 |
Finished | Jul 27 06:46:03 PM PDT 24 |
Peak memory | 205952 kb |
Host | smart-43f21e9c-2817-44a2-bdde-9c8219677234 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179216405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3179216405 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.218908964 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 5959287541 ps |
CPU time | 338.15 seconds |
Started | Jul 27 06:45:57 PM PDT 24 |
Finished | Jul 27 06:51:35 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-16fce489-4b06-4239-926d-d11c4d070b16 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218908964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 9.sram_ctrl_partial_access_b2b.218908964 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.987623214 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 696489103 ps |
CPU time | 3.25 seconds |
Started | Jul 27 06:45:48 PM PDT 24 |
Finished | Jul 27 06:45:52 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-f2ce3991-d9e6-4ddb-860e-3c0911acb027 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987623214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.987623214 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.3765389647 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 16198344896 ps |
CPU time | 1439.6 seconds |
Started | Jul 27 06:45:50 PM PDT 24 |
Finished | Jul 27 07:09:50 PM PDT 24 |
Peak memory | 381088 kb |
Host | smart-1812cb9b-1282-4b32-9c2b-23493dc6cc26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765389647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3765389647 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.2071980474 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 412064044 ps |
CPU time | 7.7 seconds |
Started | Jul 27 06:45:50 PM PDT 24 |
Finished | Jul 27 06:45:58 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-ed499644-f001-4372-a112-e62d78a6528a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071980474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2071980474 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.1014479943 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 1344214231981 ps |
CPU time | 7853.45 seconds |
Started | Jul 27 06:45:53 PM PDT 24 |
Finished | Jul 27 08:56:47 PM PDT 24 |
Peak memory | 383196 kb |
Host | smart-e64efa48-e5a5-40a2-9be7-55534e7eac55 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014479943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.1014479943 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1243206441 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1303597804 ps |
CPU time | 25.1 seconds |
Started | Jul 27 06:45:49 PM PDT 24 |
Finished | Jul 27 06:46:15 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-179f1802-579c-45ce-8c27-8522539ed599 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1243206441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1243206441 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1946456339 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 9412253053 ps |
CPU time | 258.13 seconds |
Started | Jul 27 06:45:57 PM PDT 24 |
Finished | Jul 27 06:50:15 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-60b839b4-6bb4-478e-8f36-89fc0cf6c15a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946456339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.1946456339 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1648320033 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 3104304159 ps |
CPU time | 150.49 seconds |
Started | Jul 27 06:45:51 PM PDT 24 |
Finished | Jul 27 06:48:21 PM PDT 24 |
Peak memory | 362672 kb |
Host | smart-e12e4abf-d520-4e56-a697-7fd6dbe20bb3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648320033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.1648320033 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |