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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.99 99.19 94.27 99.72 100.00 96.03 99.12 97.62


Total test records in report: 1033
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T794 /workspace/coverage/default/20.sram_ctrl_alert_test.1475109279 Jul 28 06:55:34 PM PDT 24 Jul 28 06:55:35 PM PDT 24 27482333 ps
T795 /workspace/coverage/default/37.sram_ctrl_executable.2129869599 Jul 28 06:59:19 PM PDT 24 Jul 28 07:21:15 PM PDT 24 19213263409 ps
T796 /workspace/coverage/default/13.sram_ctrl_smoke.3839980202 Jul 28 06:53:41 PM PDT 24 Jul 28 06:53:56 PM PDT 24 1572043918 ps
T797 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1049549079 Jul 28 06:57:12 PM PDT 24 Jul 28 07:08:35 PM PDT 24 32488244254 ps
T798 /workspace/coverage/default/39.sram_ctrl_stress_all.2665570369 Jul 28 06:59:53 PM PDT 24 Jul 28 07:47:48 PM PDT 24 75386392604 ps
T799 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3606356425 Jul 28 06:51:58 PM PDT 24 Jul 28 06:55:28 PM PDT 24 11019684017 ps
T800 /workspace/coverage/default/2.sram_ctrl_mem_walk.3722262786 Jul 28 06:51:27 PM PDT 24 Jul 28 06:54:24 PM PDT 24 43173737559 ps
T801 /workspace/coverage/default/37.sram_ctrl_smoke.747709501 Jul 28 06:59:16 PM PDT 24 Jul 28 06:59:29 PM PDT 24 3589367525 ps
T802 /workspace/coverage/default/1.sram_ctrl_stress_all.2633534849 Jul 28 06:51:11 PM PDT 24 Jul 28 07:52:40 PM PDT 24 37137753271 ps
T803 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.327173877 Jul 28 07:00:39 PM PDT 24 Jul 28 07:00:51 PM PDT 24 953096019 ps
T804 /workspace/coverage/default/25.sram_ctrl_ram_cfg.30969336 Jul 28 06:56:34 PM PDT 24 Jul 28 06:56:38 PM PDT 24 2385094688 ps
T805 /workspace/coverage/default/30.sram_ctrl_max_throughput.3603330630 Jul 28 06:57:41 PM PDT 24 Jul 28 06:58:32 PM PDT 24 2896724146 ps
T806 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2576404955 Jul 28 06:53:40 PM PDT 24 Jul 28 06:56:29 PM PDT 24 10004583496 ps
T807 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.417651053 Jul 28 06:51:25 PM PDT 24 Jul 28 06:52:43 PM PDT 24 1956507765 ps
T808 /workspace/coverage/default/23.sram_ctrl_max_throughput.3316628696 Jul 28 06:56:03 PM PDT 24 Jul 28 06:56:16 PM PDT 24 716368260 ps
T809 /workspace/coverage/default/42.sram_ctrl_bijection.3521536400 Jul 28 07:00:28 PM PDT 24 Jul 28 07:16:28 PM PDT 24 58322561429 ps
T810 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2653370674 Jul 28 06:55:57 PM PDT 24 Jul 28 07:02:11 PM PDT 24 60874305601 ps
T811 /workspace/coverage/default/42.sram_ctrl_lc_escalation.99769454 Jul 28 07:00:37 PM PDT 24 Jul 28 07:01:01 PM PDT 24 3590561516 ps
T812 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2689489854 Jul 28 06:57:47 PM PDT 24 Jul 28 06:58:10 PM PDT 24 1306869860 ps
T813 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.4090496527 Jul 28 06:53:40 PM PDT 24 Jul 28 07:01:55 PM PDT 24 11254275303 ps
T814 /workspace/coverage/default/35.sram_ctrl_multiple_keys.471625658 Jul 28 06:58:47 PM PDT 24 Jul 28 07:00:54 PM PDT 24 7356225039 ps
T815 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2767424622 Jul 28 06:57:53 PM PDT 24 Jul 28 07:00:42 PM PDT 24 9645874560 ps
T816 /workspace/coverage/default/44.sram_ctrl_max_throughput.3702156368 Jul 28 07:01:09 PM PDT 24 Jul 28 07:03:43 PM PDT 24 779552458 ps
T817 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3550380769 Jul 28 07:02:23 PM PDT 24 Jul 28 07:16:57 PM PDT 24 10703682371 ps
T818 /workspace/coverage/default/19.sram_ctrl_max_throughput.4169155050 Jul 28 06:55:04 PM PDT 24 Jul 28 06:56:31 PM PDT 24 3014472609 ps
T819 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.754482176 Jul 28 07:01:40 PM PDT 24 Jul 28 07:02:55 PM PDT 24 4473473944 ps
T820 /workspace/coverage/default/38.sram_ctrl_alert_test.2890104286 Jul 28 06:59:32 PM PDT 24 Jul 28 06:59:33 PM PDT 24 15587115 ps
T821 /workspace/coverage/default/33.sram_ctrl_multiple_keys.4189177895 Jul 28 06:58:15 PM PDT 24 Jul 28 07:15:55 PM PDT 24 87519611378 ps
T822 /workspace/coverage/default/21.sram_ctrl_ram_cfg.246075520 Jul 28 06:55:36 PM PDT 24 Jul 28 06:55:39 PM PDT 24 368633147 ps
T823 /workspace/coverage/default/37.sram_ctrl_bijection.597959868 Jul 28 06:59:11 PM PDT 24 Jul 28 07:29:40 PM PDT 24 215563308480 ps
T824 /workspace/coverage/default/28.sram_ctrl_executable.3505727156 Jul 28 06:57:13 PM PDT 24 Jul 28 07:12:10 PM PDT 24 80861253084 ps
T825 /workspace/coverage/default/28.sram_ctrl_multiple_keys.879980154 Jul 28 06:57:04 PM PDT 24 Jul 28 07:18:39 PM PDT 24 6861400381 ps
T826 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3610451062 Jul 28 06:51:35 PM PDT 24 Jul 28 06:52:50 PM PDT 24 2789598780 ps
T827 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3648592570 Jul 28 06:51:55 PM PDT 24 Jul 28 06:52:17 PM PDT 24 1052216764 ps
T828 /workspace/coverage/default/35.sram_ctrl_smoke.2810929592 Jul 28 06:58:40 PM PDT 24 Jul 28 06:58:55 PM PDT 24 3142107364 ps
T829 /workspace/coverage/default/8.sram_ctrl_partial_access.849617267 Jul 28 06:52:40 PM PDT 24 Jul 28 06:52:58 PM PDT 24 1164838509 ps
T830 /workspace/coverage/default/39.sram_ctrl_multiple_keys.883371938 Jul 28 06:59:40 PM PDT 24 Jul 28 07:10:54 PM PDT 24 42002042730 ps
T831 /workspace/coverage/default/25.sram_ctrl_mem_walk.4164489873 Jul 28 06:56:33 PM PDT 24 Jul 28 07:01:33 PM PDT 24 14429030638 ps
T832 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3105098022 Jul 28 07:02:01 PM PDT 24 Jul 28 07:02:30 PM PDT 24 1543169666 ps
T833 /workspace/coverage/default/19.sram_ctrl_lc_escalation.1004656863 Jul 28 06:55:10 PM PDT 24 Jul 28 06:56:02 PM PDT 24 8180055621 ps
T834 /workspace/coverage/default/22.sram_ctrl_partial_access.1357722092 Jul 28 06:55:46 PM PDT 24 Jul 28 06:57:13 PM PDT 24 2058626763 ps
T835 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1041489752 Jul 28 06:52:29 PM PDT 24 Jul 28 07:09:32 PM PDT 24 85320722371 ps
T836 /workspace/coverage/default/5.sram_ctrl_regwen.3906495401 Jul 28 06:52:02 PM PDT 24 Jul 28 07:01:56 PM PDT 24 12908231181 ps
T837 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2488455624 Jul 28 07:01:35 PM PDT 24 Jul 28 07:11:45 PM PDT 24 14211945967 ps
T838 /workspace/coverage/default/49.sram_ctrl_executable.2317030321 Jul 28 07:02:23 PM PDT 24 Jul 28 07:22:27 PM PDT 24 63081589244 ps
T839 /workspace/coverage/default/31.sram_ctrl_regwen.1374695398 Jul 28 06:57:51 PM PDT 24 Jul 28 07:03:16 PM PDT 24 39033069808 ps
T840 /workspace/coverage/default/43.sram_ctrl_multiple_keys.3126901585 Jul 28 07:00:48 PM PDT 24 Jul 28 07:15:33 PM PDT 24 60909980081 ps
T841 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2014106267 Jul 28 06:51:55 PM PDT 24 Jul 28 06:54:04 PM PDT 24 10623898911 ps
T842 /workspace/coverage/default/36.sram_ctrl_stress_all.2466195274 Jul 28 06:59:03 PM PDT 24 Jul 28 07:51:32 PM PDT 24 445870281833 ps
T843 /workspace/coverage/default/7.sram_ctrl_alert_test.124941886 Jul 28 06:52:38 PM PDT 24 Jul 28 06:52:38 PM PDT 24 79485718 ps
T844 /workspace/coverage/default/20.sram_ctrl_partial_access.1329280258 Jul 28 06:55:26 PM PDT 24 Jul 28 06:55:30 PM PDT 24 362111341 ps
T845 /workspace/coverage/default/36.sram_ctrl_ram_cfg.208409086 Jul 28 06:59:04 PM PDT 24 Jul 28 06:59:07 PM PDT 24 348508239 ps
T846 /workspace/coverage/default/44.sram_ctrl_stress_all.2973523286 Jul 28 07:01:17 PM PDT 24 Jul 28 07:58:57 PM PDT 24 55443929963 ps
T847 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2184867042 Jul 28 06:54:54 PM PDT 24 Jul 28 06:55:08 PM PDT 24 2901266249 ps
T848 /workspace/coverage/default/24.sram_ctrl_bijection.3060727998 Jul 28 06:56:12 PM PDT 24 Jul 28 07:40:27 PM PDT 24 112740979449 ps
T849 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.4153961096 Jul 28 07:01:02 PM PDT 24 Jul 28 07:06:48 PM PDT 24 4948204050 ps
T850 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.654267195 Jul 28 06:56:58 PM PDT 24 Jul 28 06:57:19 PM PDT 24 2096690517 ps
T851 /workspace/coverage/default/35.sram_ctrl_stress_all.2256554613 Jul 28 06:58:54 PM PDT 24 Jul 28 08:23:21 PM PDT 24 191192458120 ps
T852 /workspace/coverage/default/2.sram_ctrl_max_throughput.2614099527 Jul 28 06:51:16 PM PDT 24 Jul 28 06:51:35 PM PDT 24 739144860 ps
T853 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3140353145 Jul 28 06:59:32 PM PDT 24 Jul 28 07:00:56 PM PDT 24 3940266240 ps
T854 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3193076260 Jul 28 07:00:55 PM PDT 24 Jul 28 07:14:23 PM PDT 24 22160327023 ps
T855 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.4107032737 Jul 28 06:53:14 PM PDT 24 Jul 28 07:26:18 PM PDT 24 75500979483 ps
T856 /workspace/coverage/default/16.sram_ctrl_partial_access.2417842298 Jul 28 06:54:32 PM PDT 24 Jul 28 06:54:40 PM PDT 24 789907216 ps
T857 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2032300153 Jul 28 06:56:07 PM PDT 24 Jul 28 06:58:54 PM PDT 24 12120706741 ps
T858 /workspace/coverage/default/33.sram_ctrl_max_throughput.1377319482 Jul 28 06:58:20 PM PDT 24 Jul 28 07:00:03 PM PDT 24 2690035252 ps
T859 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1278242717 Jul 28 06:52:41 PM PDT 24 Jul 28 07:00:11 PM PDT 24 72234816704 ps
T860 /workspace/coverage/default/1.sram_ctrl_executable.3537643725 Jul 28 06:51:02 PM PDT 24 Jul 28 07:18:20 PM PDT 24 147032695720 ps
T861 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.45426756 Jul 28 06:54:55 PM PDT 24 Jul 28 06:59:40 PM PDT 24 22762535769 ps
T862 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1390015814 Jul 28 06:56:07 PM PDT 24 Jul 28 06:56:53 PM PDT 24 1493733960 ps
T863 /workspace/coverage/default/19.sram_ctrl_mem_walk.4108090932 Jul 28 06:55:09 PM PDT 24 Jul 28 06:58:07 PM PDT 24 37429766904 ps
T864 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1261863614 Jul 28 06:59:35 PM PDT 24 Jul 28 07:03:21 PM PDT 24 4235379496 ps
T865 /workspace/coverage/default/23.sram_ctrl_ram_cfg.907559272 Jul 28 06:56:06 PM PDT 24 Jul 28 06:56:09 PM PDT 24 1057893988 ps
T866 /workspace/coverage/default/39.sram_ctrl_lc_escalation.768099771 Jul 28 06:59:45 PM PDT 24 Jul 28 06:59:49 PM PDT 24 362507978 ps
T867 /workspace/coverage/default/30.sram_ctrl_partial_access.4232805971 Jul 28 06:57:41 PM PDT 24 Jul 28 06:58:01 PM PDT 24 959014446 ps
T868 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2162642623 Jul 28 06:58:32 PM PDT 24 Jul 28 07:04:33 PM PDT 24 172354691380 ps
T869 /workspace/coverage/default/25.sram_ctrl_smoke.3356654703 Jul 28 06:56:21 PM PDT 24 Jul 28 06:56:31 PM PDT 24 601668251 ps
T870 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1989782245 Jul 28 06:52:35 PM PDT 24 Jul 28 06:54:06 PM PDT 24 34027816218 ps
T871 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.959878391 Jul 28 06:50:47 PM PDT 24 Jul 28 06:51:55 PM PDT 24 2721739177 ps
T872 /workspace/coverage/default/34.sram_ctrl_partial_access.2504491714 Jul 28 06:58:27 PM PDT 24 Jul 28 06:58:53 PM PDT 24 1739267629 ps
T873 /workspace/coverage/default/33.sram_ctrl_alert_test.492105135 Jul 28 06:58:27 PM PDT 24 Jul 28 06:58:28 PM PDT 24 37438520 ps
T874 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.4178196884 Jul 28 06:56:34 PM PDT 24 Jul 28 07:14:07 PM PDT 24 29697778687 ps
T875 /workspace/coverage/default/5.sram_ctrl_max_throughput.315691976 Jul 28 06:52:03 PM PDT 24 Jul 28 06:52:10 PM PDT 24 1249022536 ps
T876 /workspace/coverage/default/46.sram_ctrl_ram_cfg.2334983922 Jul 28 07:01:39 PM PDT 24 Jul 28 07:01:43 PM PDT 24 1255072467 ps
T877 /workspace/coverage/default/45.sram_ctrl_lc_escalation.712917501 Jul 28 07:01:22 PM PDT 24 Jul 28 07:02:21 PM PDT 24 10283756395 ps
T878 /workspace/coverage/default/19.sram_ctrl_partial_access.3733175313 Jul 28 06:55:06 PM PDT 24 Jul 28 06:55:16 PM PDT 24 792171596 ps
T879 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3770332051 Jul 28 06:54:46 PM PDT 24 Jul 28 06:56:52 PM PDT 24 4310183352 ps
T880 /workspace/coverage/default/18.sram_ctrl_ram_cfg.3010684011 Jul 28 06:54:59 PM PDT 24 Jul 28 06:55:03 PM PDT 24 1295996859 ps
T881 /workspace/coverage/default/33.sram_ctrl_partial_access.1079663551 Jul 28 06:58:15 PM PDT 24 Jul 28 06:58:50 PM PDT 24 4449944367 ps
T882 /workspace/coverage/default/49.sram_ctrl_ram_cfg.3859781277 Jul 28 07:02:25 PM PDT 24 Jul 28 07:02:28 PM PDT 24 1404533544 ps
T883 /workspace/coverage/default/47.sram_ctrl_partial_access.2797396279 Jul 28 07:01:43 PM PDT 24 Jul 28 07:03:30 PM PDT 24 846434169 ps
T884 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2692043588 Jul 28 06:55:47 PM PDT 24 Jul 28 07:00:44 PM PDT 24 4705542307 ps
T885 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4075967025 Jul 28 06:53:30 PM PDT 24 Jul 28 07:03:47 PM PDT 24 28583543540 ps
T886 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3359287723 Jul 28 06:52:26 PM PDT 24 Jul 28 06:57:18 PM PDT 24 9402738570 ps
T887 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3986503145 Jul 28 07:00:48 PM PDT 24 Jul 28 07:04:41 PM PDT 24 11323810390 ps
T888 /workspace/coverage/default/25.sram_ctrl_bijection.3739811185 Jul 28 06:56:28 PM PDT 24 Jul 28 07:05:36 PM PDT 24 8299619190 ps
T889 /workspace/coverage/default/32.sram_ctrl_stress_all.2027754204 Jul 28 06:58:09 PM PDT 24 Jul 28 08:46:22 PM PDT 24 420563122602 ps
T890 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.682065730 Jul 28 06:59:59 PM PDT 24 Jul 28 07:05:44 PM PDT 24 22159615557 ps
T891 /workspace/coverage/default/11.sram_ctrl_partial_access.1898412331 Jul 28 06:53:16 PM PDT 24 Jul 28 06:53:30 PM PDT 24 3320379746 ps
T892 /workspace/coverage/default/36.sram_ctrl_lc_escalation.2728872352 Jul 28 06:58:59 PM PDT 24 Jul 28 06:59:50 PM PDT 24 37572243475 ps
T893 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4232850733 Jul 28 07:00:42 PM PDT 24 Jul 28 07:03:27 PM PDT 24 5411526312 ps
T894 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.389638677 Jul 28 07:01:17 PM PDT 24 Jul 28 07:02:34 PM PDT 24 2780410114 ps
T895 /workspace/coverage/default/36.sram_ctrl_executable.2952659996 Jul 28 06:58:59 PM PDT 24 Jul 28 07:04:22 PM PDT 24 15737889502 ps
T896 /workspace/coverage/default/38.sram_ctrl_partial_access.3795711921 Jul 28 06:59:26 PM PDT 24 Jul 28 07:01:16 PM PDT 24 3978664321 ps
T897 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1156315391 Jul 28 06:53:01 PM PDT 24 Jul 28 06:55:02 PM PDT 24 1632888355 ps
T898 /workspace/coverage/default/5.sram_ctrl_lc_escalation.800220439 Jul 28 06:52:02 PM PDT 24 Jul 28 06:52:57 PM PDT 24 9095736031 ps
T899 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2278499750 Jul 28 06:55:43 PM PDT 24 Jul 28 06:56:59 PM PDT 24 2484588259 ps
T900 /workspace/coverage/default/10.sram_ctrl_smoke.1365165720 Jul 28 06:53:03 PM PDT 24 Jul 28 06:53:32 PM PDT 24 410378094 ps
T901 /workspace/coverage/default/27.sram_ctrl_bijection.2610417591 Jul 28 06:56:52 PM PDT 24 Jul 28 07:12:06 PM PDT 24 148159011262 ps
T902 /workspace/coverage/default/44.sram_ctrl_bijection.2134237593 Jul 28 07:01:02 PM PDT 24 Jul 28 07:27:44 PM PDT 24 96663817038 ps
T903 /workspace/coverage/default/39.sram_ctrl_executable.4283209777 Jul 28 06:59:44 PM PDT 24 Jul 28 07:08:18 PM PDT 24 10760294683 ps
T904 /workspace/coverage/default/38.sram_ctrl_ram_cfg.3126851355 Jul 28 06:59:34 PM PDT 24 Jul 28 06:59:37 PM PDT 24 360053558 ps
T905 /workspace/coverage/default/31.sram_ctrl_bijection.4268777051 Jul 28 06:57:51 PM PDT 24 Jul 28 07:16:23 PM PDT 24 210793252094 ps
T906 /workspace/coverage/default/4.sram_ctrl_executable.979655005 Jul 28 06:51:47 PM PDT 24 Jul 28 07:14:05 PM PDT 24 26283221670 ps
T907 /workspace/coverage/default/23.sram_ctrl_partial_access.3739823128 Jul 28 06:55:57 PM PDT 24 Jul 28 06:56:22 PM PDT 24 1634596127 ps
T908 /workspace/coverage/default/44.sram_ctrl_smoke.3519391648 Jul 28 07:01:02 PM PDT 24 Jul 28 07:01:06 PM PDT 24 1502036532 ps
T909 /workspace/coverage/default/41.sram_ctrl_smoke.576270273 Jul 28 07:00:13 PM PDT 24 Jul 28 07:00:33 PM PDT 24 1089408401 ps
T910 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3957688103 Jul 28 07:01:24 PM PDT 24 Jul 28 07:09:32 PM PDT 24 62589415647 ps
T911 /workspace/coverage/default/24.sram_ctrl_max_throughput.570817848 Jul 28 06:56:16 PM PDT 24 Jul 28 06:56:44 PM PDT 24 2949133977 ps
T912 /workspace/coverage/default/20.sram_ctrl_executable.3155831573 Jul 28 06:55:22 PM PDT 24 Jul 28 07:09:30 PM PDT 24 66537432519 ps
T913 /workspace/coverage/default/5.sram_ctrl_ram_cfg.3545991090 Jul 28 06:52:02 PM PDT 24 Jul 28 06:52:05 PM PDT 24 2805089233 ps
T914 /workspace/coverage/default/17.sram_ctrl_executable.2166251963 Jul 28 06:54:47 PM PDT 24 Jul 28 07:17:56 PM PDT 24 71104240867 ps
T915 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2902943484 Jul 28 06:53:17 PM PDT 24 Jul 28 06:58:05 PM PDT 24 38443761853 ps
T916 /workspace/coverage/default/6.sram_ctrl_bijection.2226978301 Jul 28 06:52:07 PM PDT 24 Jul 28 07:29:51 PM PDT 24 631133429959 ps
T917 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.646359041 Jul 28 06:52:49 PM PDT 24 Jul 28 06:53:13 PM PDT 24 5017317415 ps
T918 /workspace/coverage/default/46.sram_ctrl_smoke.2628909902 Jul 28 07:01:29 PM PDT 24 Jul 28 07:01:50 PM PDT 24 875556943 ps
T919 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.923767670 Jul 28 06:52:08 PM PDT 24 Jul 28 06:52:26 PM PDT 24 571754276 ps
T920 /workspace/coverage/default/17.sram_ctrl_max_throughput.3417322825 Jul 28 06:54:44 PM PDT 24 Jul 28 06:56:20 PM PDT 24 4419120757 ps
T921 /workspace/coverage/default/23.sram_ctrl_stress_all.204955153 Jul 28 06:56:06 PM PDT 24 Jul 28 07:20:01 PM PDT 24 25149962322 ps
T922 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1173794531 Jul 28 06:56:22 PM PDT 24 Jul 28 06:56:48 PM PDT 24 1408239702 ps
T923 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3705019945 Jul 28 06:53:24 PM PDT 24 Jul 28 07:02:38 PM PDT 24 8286328184 ps
T924 /workspace/coverage/default/13.sram_ctrl_stress_all.2579202664 Jul 28 06:53:50 PM PDT 24 Jul 28 07:10:12 PM PDT 24 25124921178 ps
T925 /workspace/coverage/default/43.sram_ctrl_lc_escalation.145366324 Jul 28 07:00:54 PM PDT 24 Jul 28 07:02:06 PM PDT 24 23179868642 ps
T926 /workspace/coverage/default/7.sram_ctrl_smoke.3647959137 Jul 28 06:52:22 PM PDT 24 Jul 28 06:53:45 PM PDT 24 934781287 ps
T927 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1983826421 Jul 28 06:56:33 PM PDT 24 Jul 28 06:59:00 PM PDT 24 4447630356 ps
T928 /workspace/coverage/default/29.sram_ctrl_alert_test.3246082079 Jul 28 06:57:34 PM PDT 24 Jul 28 06:57:35 PM PDT 24 22471317 ps
T929 /workspace/coverage/default/2.sram_ctrl_partial_access.4241771164 Jul 28 06:51:16 PM PDT 24 Jul 28 06:51:26 PM PDT 24 486917992 ps
T930 /workspace/coverage/default/10.sram_ctrl_lc_escalation.2954060383 Jul 28 06:53:14 PM PDT 24 Jul 28 06:54:25 PM PDT 24 40288379058 ps
T931 /workspace/coverage/default/27.sram_ctrl_stress_all.137578720 Jul 28 06:57:02 PM PDT 24 Jul 28 07:44:52 PM PDT 24 75179910349 ps
T932 /workspace/coverage/default/9.sram_ctrl_regwen.676260912 Jul 28 06:53:01 PM PDT 24 Jul 28 07:08:55 PM PDT 24 23024270642 ps
T933 /workspace/coverage/default/18.sram_ctrl_bijection.3844397170 Jul 28 06:54:50 PM PDT 24 Jul 28 07:25:19 PM PDT 24 104051958873 ps
T934 /workspace/coverage/default/24.sram_ctrl_ram_cfg.4206790977 Jul 28 06:56:16 PM PDT 24 Jul 28 06:56:20 PM PDT 24 3724489887 ps
T935 /workspace/coverage/default/8.sram_ctrl_mem_walk.1855608263 Jul 28 06:52:45 PM PDT 24 Jul 28 06:58:02 PM PDT 24 18948263522 ps
T936 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2095226317 Jul 28 06:57:56 PM PDT 24 Jul 28 07:02:45 PM PDT 24 26574524546 ps
T937 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3379036658 Jul 28 07:00:20 PM PDT 24 Jul 28 07:03:29 PM PDT 24 19565743916 ps
T938 /workspace/coverage/default/13.sram_ctrl_bijection.828116918 Jul 28 06:53:41 PM PDT 24 Jul 28 07:10:48 PM PDT 24 529275725666 ps
T939 /workspace/coverage/default/28.sram_ctrl_max_throughput.2549224062 Jul 28 06:57:13 PM PDT 24 Jul 28 06:58:49 PM PDT 24 1296362092 ps
T940 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.36331303 Jul 28 06:53:51 PM PDT 24 Jul 28 06:56:24 PM PDT 24 2532119057 ps
T941 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3271815651 Jul 28 06:57:41 PM PDT 24 Jul 28 06:57:50 PM PDT 24 2720110950 ps
T942 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.239999698 Jul 28 06:57:02 PM PDT 24 Jul 28 06:57:25 PM PDT 24 5046119682 ps
T943 /workspace/coverage/default/43.sram_ctrl_bijection.1260640659 Jul 28 07:00:48 PM PDT 24 Jul 28 07:18:18 PM PDT 24 47746584349 ps
T73 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.146354513 Jul 28 05:16:06 PM PDT 24 Jul 28 05:16:07 PM PDT 24 37291285 ps
T74 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1156515713 Jul 28 05:16:20 PM PDT 24 Jul 28 05:16:52 PM PDT 24 16730649152 ps
T75 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1825611088 Jul 28 05:16:12 PM PDT 24 Jul 28 05:16:13 PM PDT 24 109102075 ps
T68 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1610901885 Jul 28 05:16:43 PM PDT 24 Jul 28 05:16:45 PM PDT 24 435659750 ps
T944 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2012300802 Jul 28 05:16:22 PM PDT 24 Jul 28 05:16:26 PM PDT 24 1474854558 ps
T105 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1224154466 Jul 28 05:16:09 PM PDT 24 Jul 28 05:16:11 PM PDT 24 48090371 ps
T945 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1359680939 Jul 28 05:16:06 PM PDT 24 Jul 28 05:16:10 PM PDT 24 370603475 ps
T946 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1542854020 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:23 PM PDT 24 351183303 ps
T115 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1718158395 Jul 28 05:16:05 PM PDT 24 Jul 28 05:16:05 PM PDT 24 88145697 ps
T69 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4289975792 Jul 28 05:16:08 PM PDT 24 Jul 28 05:16:10 PM PDT 24 336645516 ps
T947 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2167155935 Jul 28 05:16:01 PM PDT 24 Jul 28 05:16:05 PM PDT 24 31808122 ps
T83 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3151810092 Jul 28 05:16:04 PM PDT 24 Jul 28 05:16:04 PM PDT 24 19515950 ps
T84 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2602097480 Jul 28 05:16:13 PM PDT 24 Jul 28 05:16:14 PM PDT 24 41845656 ps
T70 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4227930282 Jul 28 05:16:26 PM PDT 24 Jul 28 05:16:29 PM PDT 24 1488126655 ps
T948 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3069826413 Jul 28 05:16:11 PM PDT 24 Jul 28 05:16:16 PM PDT 24 2692494779 ps
T949 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3945633032 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:21 PM PDT 24 38309889 ps
T85 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3775119799 Jul 28 05:16:24 PM PDT 24 Jul 28 05:16:24 PM PDT 24 44196966 ps
T106 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1439891094 Jul 28 05:16:25 PM PDT 24 Jul 28 05:16:26 PM PDT 24 78374348 ps
T86 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.318797890 Jul 28 05:16:09 PM PDT 24 Jul 28 05:16:10 PM PDT 24 21332705 ps
T129 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3413488868 Jul 28 05:16:18 PM PDT 24 Jul 28 05:16:20 PM PDT 24 349283400 ps
T87 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3575395256 Jul 28 05:16:21 PM PDT 24 Jul 28 05:16:22 PM PDT 24 37231862 ps
T950 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2611220518 Jul 28 05:16:20 PM PDT 24 Jul 28 05:16:21 PM PDT 24 58428519 ps
T107 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2105106778 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:20 PM PDT 24 15005682 ps
T951 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.127156868 Jul 28 05:16:13 PM PDT 24 Jul 28 05:16:14 PM PDT 24 17202221 ps
T952 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2878469524 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:23 PM PDT 24 301761725 ps
T133 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.176794463 Jul 28 05:16:18 PM PDT 24 Jul 28 05:16:20 PM PDT 24 94645324 ps
T88 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3784883052 Jul 28 05:16:07 PM PDT 24 Jul 28 05:16:08 PM PDT 24 45449107 ps
T953 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3432465452 Jul 28 05:16:15 PM PDT 24 Jul 28 05:16:18 PM PDT 24 443924813 ps
T954 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3264328180 Jul 28 05:16:22 PM PDT 24 Jul 28 05:16:24 PM PDT 24 45088869 ps
T89 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2865794178 Jul 28 05:16:05 PM PDT 24 Jul 28 05:16:06 PM PDT 24 20011490 ps
T90 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.734320 Jul 28 05:16:18 PM PDT 24 Jul 28 05:16:19 PM PDT 24 14385377 ps
T955 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.484506020 Jul 28 05:16:17 PM PDT 24 Jul 28 05:16:20 PM PDT 24 88255920 ps
T956 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1483832797 Jul 28 05:16:07 PM PDT 24 Jul 28 05:16:11 PM PDT 24 134238976 ps
T125 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1961352762 Jul 28 05:16:00 PM PDT 24 Jul 28 05:16:02 PM PDT 24 255869828 ps
T108 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.103439358 Jul 28 05:16:03 PM PDT 24 Jul 28 05:16:03 PM PDT 24 19324748 ps
T957 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3228891823 Jul 28 05:16:16 PM PDT 24 Jul 28 05:16:18 PM PDT 24 839616200 ps
T958 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3422091521 Jul 28 05:16:06 PM PDT 24 Jul 28 05:16:07 PM PDT 24 15946138 ps
T134 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.101539347 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:21 PM PDT 24 475459761 ps
T959 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1637860748 Jul 28 05:16:00 PM PDT 24 Jul 28 05:16:03 PM PDT 24 365778196 ps
T91 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1491324814 Jul 28 05:16:01 PM PDT 24 Jul 28 05:17:01 PM PDT 24 64010603045 ps
T960 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4246233571 Jul 28 05:16:24 PM PDT 24 Jul 28 05:16:25 PM PDT 24 40957400 ps
T961 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.803512683 Jul 28 05:16:12 PM PDT 24 Jul 28 05:16:16 PM PDT 24 362614883 ps
T92 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3884131028 Jul 28 05:16:19 PM PDT 24 Jul 28 05:17:11 PM PDT 24 28242336217 ps
T962 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.649530949 Jul 28 05:16:24 PM PDT 24 Jul 28 05:16:27 PM PDT 24 92588087 ps
T135 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3814323235 Jul 28 05:16:01 PM PDT 24 Jul 28 05:16:04 PM PDT 24 759799609 ps
T93 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1898120348 Jul 28 05:16:18 PM PDT 24 Jul 28 05:17:11 PM PDT 24 24308557689 ps
T94 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2686118766 Jul 28 05:16:17 PM PDT 24 Jul 28 05:16:48 PM PDT 24 11901900033 ps
T126 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3966916363 Jul 28 05:16:16 PM PDT 24 Jul 28 05:16:19 PM PDT 24 824890356 ps
T963 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1210040784 Jul 28 05:16:38 PM PDT 24 Jul 28 05:16:42 PM PDT 24 1357488395 ps
T964 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2338419321 Jul 28 05:16:16 PM PDT 24 Jul 28 05:16:17 PM PDT 24 13024352 ps
T965 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3526907317 Jul 28 05:16:21 PM PDT 24 Jul 28 05:16:22 PM PDT 24 16877778 ps
T966 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.330540626 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:20 PM PDT 24 17809483 ps
T967 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1811289886 Jul 28 05:16:20 PM PDT 24 Jul 28 05:16:21 PM PDT 24 29706587 ps
T968 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3735982885 Jul 28 05:16:09 PM PDT 24 Jul 28 05:16:11 PM PDT 24 216122188 ps
T969 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1151969 Jul 28 05:16:14 PM PDT 24 Jul 28 05:16:15 PM PDT 24 12777063 ps
T95 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1445369580 Jul 28 05:16:20 PM PDT 24 Jul 28 05:16:46 PM PDT 24 3781688214 ps
T970 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3488645010 Jul 28 05:16:18 PM PDT 24 Jul 28 05:16:22 PM PDT 24 2177021313 ps
T96 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.169478678 Jul 28 05:16:20 PM PDT 24 Jul 28 05:17:10 PM PDT 24 7209536945 ps
T971 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3595599366 Jul 28 05:16:20 PM PDT 24 Jul 28 05:16:21 PM PDT 24 45989240 ps
T130 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.114044763 Jul 28 05:16:30 PM PDT 24 Jul 28 05:16:32 PM PDT 24 116118517 ps
T972 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2132396886 Jul 28 05:16:14 PM PDT 24 Jul 28 05:16:17 PM PDT 24 589640581 ps
T973 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.132141307 Jul 28 05:16:16 PM PDT 24 Jul 28 05:16:17 PM PDT 24 23414857 ps
T974 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4179933844 Jul 28 05:15:58 PM PDT 24 Jul 28 05:16:24 PM PDT 24 3851523122 ps
T975 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3056512614 Jul 28 05:16:13 PM PDT 24 Jul 28 05:16:42 PM PDT 24 3806110066 ps
T976 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1884178382 Jul 28 05:16:17 PM PDT 24 Jul 28 05:16:18 PM PDT 24 14796604 ps
T977 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3559345764 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:23 PM PDT 24 2670566126 ps
T978 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1550815908 Jul 28 05:16:21 PM PDT 24 Jul 28 05:16:21 PM PDT 24 55116366 ps
T100 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4213432023 Jul 28 05:16:05 PM PDT 24 Jul 28 05:17:00 PM PDT 24 141303351114 ps
T979 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.385907861 Jul 28 05:16:07 PM PDT 24 Jul 28 05:16:09 PM PDT 24 75431728 ps
T980 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.383345312 Jul 28 05:16:04 PM PDT 24 Jul 28 05:16:09 PM PDT 24 1753210594 ps
T99 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3639830132 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:48 PM PDT 24 15398797460 ps
T981 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.779686805 Jul 28 05:15:57 PM PDT 24 Jul 28 05:15:58 PM PDT 24 74179149 ps
T131 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.790515675 Jul 28 05:16:14 PM PDT 24 Jul 28 05:16:16 PM PDT 24 372329592 ps
T982 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2441860461 Jul 28 05:16:14 PM PDT 24 Jul 28 05:16:16 PM PDT 24 53359653 ps
T983 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1766732135 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:20 PM PDT 24 14243099 ps
T984 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.204204264 Jul 28 05:16:16 PM PDT 24 Jul 28 05:16:17 PM PDT 24 62253528 ps
T985 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1286460583 Jul 28 05:16:36 PM PDT 24 Jul 28 05:16:40 PM PDT 24 75525909 ps
T986 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1461359854 Jul 28 05:16:07 PM PDT 24 Jul 28 05:16:07 PM PDT 24 70271181 ps
T136 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.254713176 Jul 28 05:16:04 PM PDT 24 Jul 28 05:16:07 PM PDT 24 530196234 ps
T987 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1988102950 Jul 28 05:16:02 PM PDT 24 Jul 28 05:16:06 PM PDT 24 1491526665 ps
T132 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1320139728 Jul 28 05:16:16 PM PDT 24 Jul 28 05:16:19 PM PDT 24 800008087 ps
T988 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2763964274 Jul 28 05:16:16 PM PDT 24 Jul 28 05:16:20 PM PDT 24 402280253 ps
T989 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4193907564 Jul 28 05:16:17 PM PDT 24 Jul 28 05:16:18 PM PDT 24 18657754 ps
T990 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4189651205 Jul 28 05:16:20 PM PDT 24 Jul 28 05:16:24 PM PDT 24 45029480 ps
T991 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.195240540 Jul 28 05:16:15 PM PDT 24 Jul 28 05:16:16 PM PDT 24 21454551 ps
T992 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3728426559 Jul 28 05:16:07 PM PDT 24 Jul 28 05:16:08 PM PDT 24 30070130 ps
T993 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1847521087 Jul 28 05:16:20 PM PDT 24 Jul 28 05:16:21 PM PDT 24 111140747 ps
T101 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2571783795 Jul 28 05:16:05 PM PDT 24 Jul 28 05:16:59 PM PDT 24 28131594189 ps
T994 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.212976680 Jul 28 05:16:10 PM PDT 24 Jul 28 05:16:11 PM PDT 24 43499984 ps
T995 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2730840078 Jul 28 05:16:02 PM PDT 24 Jul 28 05:16:03 PM PDT 24 95195708 ps
T996 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.88675609 Jul 28 05:16:27 PM PDT 24 Jul 28 05:16:31 PM PDT 24 1341058797 ps
T997 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4122627608 Jul 28 05:16:20 PM PDT 24 Jul 28 05:16:24 PM PDT 24 359316867 ps
T998 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.786452379 Jul 28 05:16:19 PM PDT 24 Jul 28 05:16:22 PM PDT 24 356960161 ps
T999 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2874028006 Jul 28 05:16:08 PM PDT 24 Jul 28 05:16:35 PM PDT 24 7684353963 ps
T1000 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2670196029 Jul 28 05:16:02 PM PDT 24 Jul 28 05:16:03 PM PDT 24 33311604 ps
T1001 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.979463963 Jul 28 05:16:18 PM PDT 24 Jul 28 05:16:47 PM PDT 24 7701283822 ps
T1002 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2608589316 Jul 28 05:16:06 PM PDT 24 Jul 28 05:16:06 PM PDT 24 31793302 ps
T1003 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1913891493 Jul 28 05:16:08 PM PDT 24 Jul 28 05:16:10 PM PDT 24 45538052 ps
T1004 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.551698855 Jul 28 05:16:02 PM PDT 24 Jul 28 05:16:05 PM PDT 24 348657532 ps
T1005 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.838326711 Jul 28 05:16:29 PM PDT 24 Jul 28 05:16:30 PM PDT 24 38150503 ps
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