SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.99 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.62 |
T1006 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1458332921 | Jul 28 05:16:15 PM PDT 24 | Jul 28 05:16:19 PM PDT 24 | 1227844638 ps | ||
T102 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3600083688 | Jul 28 05:16:41 PM PDT 24 | Jul 28 05:16:42 PM PDT 24 | 15188907 ps | ||
T1007 | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.584006097 | Jul 28 05:16:23 PM PDT 24 | Jul 28 05:16:24 PM PDT 24 | 24910639 ps | ||
T1008 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3778661395 | Jul 28 05:16:06 PM PDT 24 | Jul 28 05:16:10 PM PDT 24 | 699239263 ps | ||
T1009 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2509954905 | Jul 28 05:16:15 PM PDT 24 | Jul 28 05:16:17 PM PDT 24 | 168414744 ps | ||
T1010 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.820549941 | Jul 28 05:16:09 PM PDT 24 | Jul 28 05:16:10 PM PDT 24 | 25225301 ps | ||
T127 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2239522171 | Jul 28 05:16:26 PM PDT 24 | Jul 28 05:16:28 PM PDT 24 | 517299098 ps | ||
T1011 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2054032962 | Jul 28 05:16:18 PM PDT 24 | Jul 28 05:16:21 PM PDT 24 | 277972464 ps | ||
T1012 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4047503124 | Jul 28 05:16:04 PM PDT 24 | Jul 28 05:16:06 PM PDT 24 | 67018528 ps | ||
T1013 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3580820651 | Jul 28 05:16:20 PM PDT 24 | Jul 28 05:16:22 PM PDT 24 | 175534284 ps | ||
T1014 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.630322124 | Jul 28 05:16:21 PM PDT 24 | Jul 28 05:16:23 PM PDT 24 | 105888007 ps | ||
T1015 | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3698407423 | Jul 28 05:16:20 PM PDT 24 | Jul 28 05:16:49 PM PDT 24 | 3699991579 ps | ||
T103 | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2493963063 | Jul 28 05:16:21 PM PDT 24 | Jul 28 05:16:46 PM PDT 24 | 7725268794 ps | ||
T1016 | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3590626765 | Jul 28 05:16:28 PM PDT 24 | Jul 28 05:16:34 PM PDT 24 | 15696521 ps | ||
T1017 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3693088510 | Jul 28 05:16:12 PM PDT 24 | Jul 28 05:16:13 PM PDT 24 | 33582769 ps | ||
T1018 | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1879791751 | Jul 28 05:16:19 PM PDT 24 | Jul 28 05:16:20 PM PDT 24 | 54517402 ps | ||
T1019 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4182647960 | Jul 28 05:16:27 PM PDT 24 | Jul 28 05:16:33 PM PDT 24 | 1485162465 ps | ||
T1020 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2557962896 | Jul 28 05:16:18 PM PDT 24 | Jul 28 05:16:19 PM PDT 24 | 14717898 ps | ||
T1021 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4149779107 | Jul 28 05:16:01 PM PDT 24 | Jul 28 05:16:03 PM PDT 24 | 75452936 ps | ||
T1022 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2017026076 | Jul 28 05:16:21 PM PDT 24 | Jul 28 05:16:22 PM PDT 24 | 15284975 ps | ||
T1023 | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.605746693 | Jul 28 05:16:21 PM PDT 24 | Jul 28 05:17:23 PM PDT 24 | 44135797259 ps | ||
T104 | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1527707900 | Jul 28 05:16:11 PM PDT 24 | Jul 28 05:17:05 PM PDT 24 | 10232493170 ps | ||
T1024 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2254262206 | Jul 28 05:16:02 PM PDT 24 | Jul 28 05:16:05 PM PDT 24 | 64523191 ps | ||
T1025 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.882133946 | Jul 28 05:16:18 PM PDT 24 | Jul 28 05:16:19 PM PDT 24 | 12754266 ps | ||
T1026 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2612910743 | Jul 28 05:16:25 PM PDT 24 | Jul 28 05:16:28 PM PDT 24 | 704049757 ps | ||
T1027 | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1627226924 | Jul 28 05:16:05 PM PDT 24 | Jul 28 05:16:05 PM PDT 24 | 65918296 ps | ||
T1028 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1773117722 | Jul 28 05:16:40 PM PDT 24 | Jul 28 05:16:49 PM PDT 24 | 149226252 ps | ||
T1029 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1367226787 | Jul 28 05:16:04 PM PDT 24 | Jul 28 05:16:04 PM PDT 24 | 27430621 ps | ||
T1030 | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2070766948 | Jul 28 05:16:22 PM PDT 24 | Jul 28 05:17:19 PM PDT 24 | 28160731658 ps | ||
T1031 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4120453830 | Jul 28 05:16:21 PM PDT 24 | Jul 28 05:16:25 PM PDT 24 | 1387873081 ps | ||
T1032 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3839345768 | Jul 28 05:16:39 PM PDT 24 | Jul 28 05:16:42 PM PDT 24 | 28271726 ps | ||
T1033 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3595364827 | Jul 28 05:16:20 PM PDT 24 | Jul 28 05:16:25 PM PDT 24 | 1399820524 ps | ||
T128 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2489524251 | Jul 28 05:16:03 PM PDT 24 | Jul 28 05:16:06 PM PDT 24 | 400772214 ps |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2510991479 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1473427435 ps |
CPU time | 21.11 seconds |
Started | Jul 28 06:57:52 PM PDT 24 |
Finished | Jul 28 06:58:14 PM PDT 24 |
Peak memory | 211468 kb |
Host | smart-0f85c531-2cb1-4b6a-adf1-e8e3c0c66481 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2510991479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2510991479 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2044383310 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 4789400154 ps |
CPU time | 70.55 seconds |
Started | Jul 28 07:02:06 PM PDT 24 |
Finished | Jul 28 07:03:17 PM PDT 24 |
Peak memory | 288800 kb |
Host | smart-90d3ddc2-3714-492f-bd45-3c4f42a3a506 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2044383310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2044383310 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.2875378901 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 36292405091 ps |
CPU time | 65.36 seconds |
Started | Jul 28 07:01:39 PM PDT 24 |
Finished | Jul 28 07:02:45 PM PDT 24 |
Peak memory | 211316 kb |
Host | smart-dc6932f2-59e3-4303-b318-c0da17876a24 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875378901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.2875378901 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.3583016728 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 62689832513 ps |
CPU time | 365.78 seconds |
Started | Jul 28 07:00:05 PM PDT 24 |
Finished | Jul 28 07:06:11 PM PDT 24 |
Peak memory | 211492 kb |
Host | smart-62119c3d-0c53-4c63-8507-0e2a912a49ae |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583016728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.3583016728 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.523850910 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 41018361168 ps |
CPU time | 4759.59 seconds |
Started | Jul 28 06:51:59 PM PDT 24 |
Finished | Jul 28 08:11:19 PM PDT 24 |
Peak memory | 388288 kb |
Host | smart-3c4d6d36-4aa2-4f5c-9542-7e26d376eb00 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523850910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_stress_all.523850910 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1610901885 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 435659750 ps |
CPU time | 2.1 seconds |
Started | Jul 28 05:16:43 PM PDT 24 |
Finished | Jul 28 05:16:45 PM PDT 24 |
Peak memory | 211224 kb |
Host | smart-d3214345-55d1-4573-a90f-ddc09fd72378 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610901885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.1610901885 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1195803539 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 50812966652 ps |
CPU time | 334.31 seconds |
Started | Jul 28 06:54:14 PM PDT 24 |
Finished | Jul 28 06:59:48 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-587d7769-e23a-4e96-ac7c-608bc4dfb8e6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195803539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.1195803539 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.307083654 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 859832040 ps |
CPU time | 3.11 seconds |
Started | Jul 28 06:51:58 PM PDT 24 |
Finished | Jul 28 06:52:01 PM PDT 24 |
Peak memory | 222380 kb |
Host | smart-6b6680cc-52c3-4018-8153-8d01b5484d9d |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307083654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_sec_cm.307083654 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.907746037 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 17149985592 ps |
CPU time | 647.48 seconds |
Started | Jul 28 06:56:58 PM PDT 24 |
Finished | Jul 28 07:07:45 PM PDT 24 |
Peak memory | 356524 kb |
Host | smart-43816e7d-c9aa-4815-a2b5-f81ddf315565 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907746037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executabl e.907746037 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1157533352 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 8416658053 ps |
CPU time | 51.53 seconds |
Started | Jul 28 06:51:45 PM PDT 24 |
Finished | Jul 28 06:52:37 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-acba6450-2a8b-4898-996c-416ef226af57 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1157533352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1157533352 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1156515713 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 16730649152 ps |
CPU time | 31.51 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:52 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-3991b7a2-ccf4-404e-b4bb-9f18b167bba5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156515713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1156515713 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.483923400 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 2400088963 ps |
CPU time | 3.45 seconds |
Started | Jul 28 06:50:47 PM PDT 24 |
Finished | Jul 28 06:50:50 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-02d73543-4ea4-463e-8994-102713dea309 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483923400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.483923400 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3041428509 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 2379649381 ps |
CPU time | 76.34 seconds |
Started | Jul 28 06:51:08 PM PDT 24 |
Finished | Jul 28 06:52:24 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-2a666780-488f-488a-9071-569bc48c8150 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041428509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.3041428509 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2239522171 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 517299098 ps |
CPU time | 2.19 seconds |
Started | Jul 28 05:16:26 PM PDT 24 |
Finished | Jul 28 05:16:28 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-87ca1f0a-de2d-4737-8280-b008106657c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239522171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.2239522171 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4227930282 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 1488126655 ps |
CPU time | 2.78 seconds |
Started | Jul 28 05:16:26 PM PDT 24 |
Finished | Jul 28 05:16:29 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-8f81a39d-fbe7-4903-9e9d-b6c35ad886e2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227930282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.4227930282 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.4203055143 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 328144718159 ps |
CPU time | 4394.94 seconds |
Started | Jul 28 06:53:25 PM PDT 24 |
Finished | Jul 28 08:06:40 PM PDT 24 |
Peak memory | 382164 kb |
Host | smart-f0c90cee-394c-4dde-a1b4-20d3c747b504 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203055143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.4203055143 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2284073079 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 31869432529 ps |
CPU time | 347.93 seconds |
Started | Jul 28 07:01:02 PM PDT 24 |
Finished | Jul 28 07:06:50 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-5fd2eba5-c873-4878-86eb-09ccbdf28f69 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284073079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.2284073079 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.1772751181 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 11830700 ps |
CPU time | 0.66 seconds |
Started | Jul 28 06:51:12 PM PDT 24 |
Finished | Jul 28 06:51:12 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-1e71c9bf-3ec8-4896-8702-929edc71d723 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772751181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1772751181 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.1659697876 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 592265128958 ps |
CPU time | 6225.7 seconds |
Started | Jul 28 06:54:36 PM PDT 24 |
Finished | Jul 28 08:38:22 PM PDT 24 |
Peak memory | 378844 kb |
Host | smart-7e6f781f-cd94-44ec-a2e4-7fcdafd3fd4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659697876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.1659697876 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1961352762 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 255869828 ps |
CPU time | 2.06 seconds |
Started | Jul 28 05:16:00 PM PDT 24 |
Finished | Jul 28 05:16:02 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-83fa5189-0c1e-47b6-860c-a0f13c537503 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961352762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1961352762 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3639830132 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 15398797460 ps |
CPU time | 29.26 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:48 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-a308cf9d-3e2c-42e6-82c9-7c9463feac95 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639830132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3639830132 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.890853806 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 70712340664 ps |
CPU time | 5323.2 seconds |
Started | Jul 28 06:53:12 PM PDT 24 |
Finished | Jul 28 08:21:56 PM PDT 24 |
Peak memory | 381316 kb |
Host | smart-0086b3bb-a69b-4e2e-84f7-faee7c7d5582 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890853806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_stress_all.890853806 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.779686805 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 74179149 ps |
CPU time | 0.66 seconds |
Started | Jul 28 05:15:57 PM PDT 24 |
Finished | Jul 28 05:15:58 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-820843ec-395b-4be6-8f79-d9a11f840b44 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779686805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_aliasing.779686805 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1913891493 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 45538052 ps |
CPU time | 1.86 seconds |
Started | Jul 28 05:16:08 PM PDT 24 |
Finished | Jul 28 05:16:10 PM PDT 24 |
Peak memory | 203008 kb |
Host | smart-4c2f034d-fc36-4474-ac77-7c17344cd92f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913891493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.1913891493 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1825611088 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 109102075 ps |
CPU time | 0.71 seconds |
Started | Jul 28 05:16:12 PM PDT 24 |
Finished | Jul 28 05:16:13 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-65b0b1bf-a4aa-47d0-8d11-1a796776a035 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825611088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.1825611088 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1988102950 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 1491526665 ps |
CPU time | 4.5 seconds |
Started | Jul 28 05:16:02 PM PDT 24 |
Finished | Jul 28 05:16:06 PM PDT 24 |
Peak memory | 211172 kb |
Host | smart-670f7311-32de-4b95-8976-e9e0d0b69d93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988102950 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1988102950 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1884178382 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 14796604 ps |
CPU time | 0.7 seconds |
Started | Jul 28 05:16:17 PM PDT 24 |
Finished | Jul 28 05:16:18 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-3030d5e2-7101-4884-a2bb-1feb1a02c126 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884178382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.1884178382 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1491324814 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 64010603045 ps |
CPU time | 59.45 seconds |
Started | Jul 28 05:16:01 PM PDT 24 |
Finished | Jul 28 05:17:01 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-ed77954a-0598-4919-9b59-2fc6be648ec3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491324814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1491324814 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2730840078 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 95195708 ps |
CPU time | 0.86 seconds |
Started | Jul 28 05:16:02 PM PDT 24 |
Finished | Jul 28 05:16:03 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-d56018eb-e216-4f9d-befc-f2b6b43e4e58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730840078 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2730840078 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2167155935 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 31808122 ps |
CPU time | 3.39 seconds |
Started | Jul 28 05:16:01 PM PDT 24 |
Finished | Jul 28 05:16:05 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-8f2d8ee9-b4a6-44a4-8f5d-41b2ce9646bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167155935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.2167155935 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.254713176 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 530196234 ps |
CPU time | 2.75 seconds |
Started | Jul 28 05:16:04 PM PDT 24 |
Finished | Jul 28 05:16:07 PM PDT 24 |
Peak memory | 211156 kb |
Host | smart-33ecab30-9f5c-46e2-89cd-c8d1fec1511e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254713176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.sram_ctrl_tl_intg_err.254713176 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3151810092 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 19515950 ps |
CPU time | 0.69 seconds |
Started | Jul 28 05:16:04 PM PDT 24 |
Finished | Jul 28 05:16:04 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-ea2119a4-b170-4d59-b97c-eb97eee7ee63 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151810092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.3151810092 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4047503124 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 67018528 ps |
CPU time | 1.45 seconds |
Started | Jul 28 05:16:04 PM PDT 24 |
Finished | Jul 28 05:16:06 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-b07d715c-6df6-41c7-a159-8e93855cae6b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047503124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.4047503124 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1718158395 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 88145697 ps |
CPU time | 0.71 seconds |
Started | Jul 28 05:16:05 PM PDT 24 |
Finished | Jul 28 05:16:05 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-3df727bd-1109-48a2-8ad8-ef7344c0caa7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718158395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.1718158395 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.383345312 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 1753210594 ps |
CPU time | 4.34 seconds |
Started | Jul 28 05:16:04 PM PDT 24 |
Finished | Jul 28 05:16:09 PM PDT 24 |
Peak memory | 212840 kb |
Host | smart-6c23d838-abfc-4da3-94c5-7d813931cc0c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383345312 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.383345312 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2670196029 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 33311604 ps |
CPU time | 0.63 seconds |
Started | Jul 28 05:16:02 PM PDT 24 |
Finished | Jul 28 05:16:03 PM PDT 24 |
Peak memory | 202576 kb |
Host | smart-a7153108-3eb1-490d-a402-59fff6403e37 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670196029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2670196029 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4179933844 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 3851523122 ps |
CPU time | 26.55 seconds |
Started | Jul 28 05:15:58 PM PDT 24 |
Finished | Jul 28 05:16:24 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-f6e3e0e8-3bd9-4b7b-9c6c-9faf7bf70839 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179933844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.4179933844 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1627226924 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 65918296 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:16:05 PM PDT 24 |
Finished | Jul 28 05:16:05 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-599eea54-283c-4a86-8af3-39a6dcb1c2db |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627226924 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1627226924 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1637860748 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 365778196 ps |
CPU time | 2.9 seconds |
Started | Jul 28 05:16:00 PM PDT 24 |
Finished | Jul 28 05:16:03 PM PDT 24 |
Peak memory | 203012 kb |
Host | smart-d93626cb-b7a2-40e2-bb2e-f15d836717ae |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637860748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.1637860748 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1542854020 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 351183303 ps |
CPU time | 3.46 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:23 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-2907debd-ac5c-41f7-bf86-eeefedb81ffe |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542854020 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1542854020 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1766732135 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 14243099 ps |
CPU time | 0.65 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:20 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-4c4dd4d2-6b78-48f2-adfc-b4d15cf9e29c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766732135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.1766732135 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2686118766 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 11901900033 ps |
CPU time | 30.58 seconds |
Started | Jul 28 05:16:17 PM PDT 24 |
Finished | Jul 28 05:16:48 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-65db6246-97c3-4ac2-bbee-b332f3814b53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686118766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2686118766 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.132141307 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 23414857 ps |
CPU time | 0.76 seconds |
Started | Jul 28 05:16:16 PM PDT 24 |
Finished | Jul 28 05:16:17 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-8cd67279-d4c7-4397-93c2-22bf90f5376e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132141307 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.132141307 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4189651205 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 45029480 ps |
CPU time | 4.07 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:24 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-fe1b2282-4e82-4d6b-8dfb-f75561888bf6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189651205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.4189651205 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3413488868 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 349283400 ps |
CPU time | 1.56 seconds |
Started | Jul 28 05:16:18 PM PDT 24 |
Finished | Jul 28 05:16:20 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-7d056a62-3ddc-410f-b6d8-e5b7f8474520 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413488868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.3413488868 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2105106778 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 15005682 ps |
CPU time | 0.66 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:20 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-b302c7fb-9997-4d80-9e6d-e675976691b3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105106778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.2105106778 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2493963063 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 7725268794 ps |
CPU time | 25.43 seconds |
Started | Jul 28 05:16:21 PM PDT 24 |
Finished | Jul 28 05:16:46 PM PDT 24 |
Peak memory | 203092 kb |
Host | smart-19ec34e6-e995-498f-8369-4d76e3995a95 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493963063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.2493963063 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1879791751 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 54517402 ps |
CPU time | 0.8 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:20 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-edce6c82-bd4e-4ebe-9861-ae36397e0fb5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879791751 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1879791751 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.195240540 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 21454551 ps |
CPU time | 1.79 seconds |
Started | Jul 28 05:16:15 PM PDT 24 |
Finished | Jul 28 05:16:16 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-66547860-a604-4a2b-a6b4-17136df2e2b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195240540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.195240540 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3966916363 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 824890356 ps |
CPU time | 2.39 seconds |
Started | Jul 28 05:16:16 PM PDT 24 |
Finished | Jul 28 05:16:19 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-78f731d9-7f00-4df2-bedd-448aa170b2a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966916363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.3966916363 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2763964274 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 402280253 ps |
CPU time | 3.6 seconds |
Started | Jul 28 05:16:16 PM PDT 24 |
Finished | Jul 28 05:16:20 PM PDT 24 |
Peak memory | 211220 kb |
Host | smart-38567dff-77b2-4454-8627-c6365bd271d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763964274 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2763964274 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.204204264 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 62253528 ps |
CPU time | 0.67 seconds |
Started | Jul 28 05:16:16 PM PDT 24 |
Finished | Jul 28 05:16:17 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-71b0f8c6-9db7-40ca-98dc-c744fbd6feca |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204204264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_csr_rw.204204264 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1445369580 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 3781688214 ps |
CPU time | 25.78 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:46 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-32ffeff8-191b-4945-b9a7-5ae30e2757c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445369580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1445369580 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.734320 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 14385377 ps |
CPU time | 0.68 seconds |
Started | Jul 28 05:16:18 PM PDT 24 |
Finished | Jul 28 05:16:19 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-16ffe4e0-a6ab-4943-8e3a-fac8db503161 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.734320 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3264328180 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 45088869 ps |
CPU time | 1.96 seconds |
Started | Jul 28 05:16:22 PM PDT 24 |
Finished | Jul 28 05:16:24 PM PDT 24 |
Peak memory | 203012 kb |
Host | smart-c3c3398e-3cf1-4ff6-bbc7-fbe3a12c3f4a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264328180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.3264328180 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1320139728 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 800008087 ps |
CPU time | 2.58 seconds |
Started | Jul 28 05:16:16 PM PDT 24 |
Finished | Jul 28 05:16:19 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-76b0ef6d-3e55-44a2-a258-819ff2d90d47 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320139728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.1320139728 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3559345764 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 2670566126 ps |
CPU time | 3.72 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:23 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-46a33b8b-f15a-427b-b839-569247f109de |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559345764 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.3559345764 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1847521087 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 111140747 ps |
CPU time | 0.64 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:21 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-b03c1766-394d-4d09-9f88-077c0e38be4d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847521087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.1847521087 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3595599366 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 45989240 ps |
CPU time | 0.78 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:21 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-e4a5ba35-685d-41b7-a023-380905471bb4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595599366 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3595599366 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2878469524 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 301761725 ps |
CPU time | 2.93 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:23 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-b9e6b8a7-19f4-498a-b94b-7621126a6e2f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878469524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.2878469524 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.101539347 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 475459761 ps |
CPU time | 2.03 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:21 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-8d72bb4c-faff-4d45-a324-d66cb9640637 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101539347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.sram_ctrl_tl_intg_err.101539347 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3595364827 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 1399820524 ps |
CPU time | 4.55 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:25 PM PDT 24 |
Peak memory | 211172 kb |
Host | smart-650b58a3-4ed5-4adb-98bd-e5b9db1f93d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595364827 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3595364827 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2611220518 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 58428519 ps |
CPU time | 0.65 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:21 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-c38c8ce0-37f7-42e8-bd69-7ce641ec2491 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611220518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.2611220518 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3775119799 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 44196966 ps |
CPU time | 0.72 seconds |
Started | Jul 28 05:16:24 PM PDT 24 |
Finished | Jul 28 05:16:24 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-e14a5f04-d94e-4508-ae22-93333629f7ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775119799 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.3775119799 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3945633032 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 38309889 ps |
CPU time | 1.59 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:21 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-9e06957c-fd4c-4a31-b849-9b15950be0ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945633032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3945633032 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.176794463 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 94645324 ps |
CPU time | 1.55 seconds |
Started | Jul 28 05:16:18 PM PDT 24 |
Finished | Jul 28 05:16:20 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-f6539276-d3ef-428e-960d-d037cf2c5422 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176794463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.sram_ctrl_tl_intg_err.176794463 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2612910743 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 704049757 ps |
CPU time | 3.28 seconds |
Started | Jul 28 05:16:25 PM PDT 24 |
Finished | Jul 28 05:16:28 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-a053f6e2-6117-463b-8194-0f5927a867e2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612910743 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2612910743 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2017026076 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 15284975 ps |
CPU time | 0.68 seconds |
Started | Jul 28 05:16:21 PM PDT 24 |
Finished | Jul 28 05:16:22 PM PDT 24 |
Peak memory | 202576 kb |
Host | smart-018e9d73-e303-473c-aaac-3bbd9b1938f5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017026076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.2017026076 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2070766948 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 28160731658 ps |
CPU time | 56.1 seconds |
Started | Jul 28 05:16:22 PM PDT 24 |
Finished | Jul 28 05:17:19 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-0565ae6c-f5c0-45b4-8525-39060ddfb212 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070766948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2070766948 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3575395256 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 37231862 ps |
CPU time | 0.67 seconds |
Started | Jul 28 05:16:21 PM PDT 24 |
Finished | Jul 28 05:16:22 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-b370ba3b-2507-4f13-afbd-2592e645cc7e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575395256 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.3575395256 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3839345768 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 28271726 ps |
CPU time | 2.38 seconds |
Started | Jul 28 05:16:39 PM PDT 24 |
Finished | Jul 28 05:16:42 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-a8324e8f-324f-4f20-bff3-2ac56ad0f3e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839345768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.3839345768 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4182647960 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 1485162465 ps |
CPU time | 5.32 seconds |
Started | Jul 28 05:16:27 PM PDT 24 |
Finished | Jul 28 05:16:33 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-af446dbf-d990-40d8-a9b7-6d277a3ce226 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182647960 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.4182647960 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1439891094 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 78374348 ps |
CPU time | 0.67 seconds |
Started | Jul 28 05:16:25 PM PDT 24 |
Finished | Jul 28 05:16:26 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-6e2ef89e-0038-4f43-9b6b-1758fb577fc3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439891094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.1439891094 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.605746693 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 44135797259 ps |
CPU time | 61.29 seconds |
Started | Jul 28 05:16:21 PM PDT 24 |
Finished | Jul 28 05:17:23 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-e0d939f9-2c94-4017-82b1-7899fa4049e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605746693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.605746693 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1811289886 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 29706587 ps |
CPU time | 0.86 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:21 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-f73213bf-7c4f-4501-802e-cd7260722201 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811289886 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.1811289886 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4122627608 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 359316867 ps |
CPU time | 3.95 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:24 PM PDT 24 |
Peak memory | 211208 kb |
Host | smart-d864d37a-5ae2-490b-95f3-5023f12bd2e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122627608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.4122627608 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3580820651 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 175534284 ps |
CPU time | 2.35 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:22 PM PDT 24 |
Peak memory | 211168 kb |
Host | smart-115ced17-3b82-41c8-b85d-5b64f8554541 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580820651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.3580820651 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2012300802 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 1474854558 ps |
CPU time | 4.05 seconds |
Started | Jul 28 05:16:22 PM PDT 24 |
Finished | Jul 28 05:16:26 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-9adbed52-1017-4adb-a943-3fd81fc3bfda |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012300802 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.2012300802 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3600083688 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 15188907 ps |
CPU time | 0.7 seconds |
Started | Jul 28 05:16:41 PM PDT 24 |
Finished | Jul 28 05:16:42 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-453fd803-f172-4845-9b81-5e19dd74ffee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600083688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.3600083688 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.169478678 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 7209536945 ps |
CPU time | 49.51 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:17:10 PM PDT 24 |
Peak memory | 203316 kb |
Host | smart-5cb83689-4e33-4978-bc22-cf600a91d3df |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169478678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.169478678 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1550815908 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 55116366 ps |
CPU time | 0.77 seconds |
Started | Jul 28 05:16:21 PM PDT 24 |
Finished | Jul 28 05:16:21 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-c7718406-d764-4435-971c-121652797475 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550815908 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1550815908 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.649530949 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 92588087 ps |
CPU time | 2.47 seconds |
Started | Jul 28 05:16:24 PM PDT 24 |
Finished | Jul 28 05:16:27 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-eef189f6-69e4-4440-adad-4b2d45b3bebe |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649530949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.649530949 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.114044763 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 116118517 ps |
CPU time | 1.67 seconds |
Started | Jul 28 05:16:30 PM PDT 24 |
Finished | Jul 28 05:16:32 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-0f2deefe-d193-4f71-8c5f-e2e7eb021c2b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114044763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.sram_ctrl_tl_intg_err.114044763 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.88675609 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 1341058797 ps |
CPU time | 3.77 seconds |
Started | Jul 28 05:16:27 PM PDT 24 |
Finished | Jul 28 05:16:31 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-aac55bf8-82be-425d-85c7-92fb45ab615d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88675609 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.88675609 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4246233571 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 40957400 ps |
CPU time | 0.64 seconds |
Started | Jul 28 05:16:24 PM PDT 24 |
Finished | Jul 28 05:16:25 PM PDT 24 |
Peak memory | 202612 kb |
Host | smart-1bc268b0-92f0-40e0-9d7f-7607e9683ece |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246233571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.4246233571 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.584006097 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 24910639 ps |
CPU time | 0.8 seconds |
Started | Jul 28 05:16:23 PM PDT 24 |
Finished | Jul 28 05:16:24 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-64188b44-766e-41e7-9aa8-064ec1638668 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584006097 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.584006097 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1286460583 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 75525909 ps |
CPU time | 3.71 seconds |
Started | Jul 28 05:16:36 PM PDT 24 |
Finished | Jul 28 05:16:40 PM PDT 24 |
Peak memory | 211232 kb |
Host | smart-950a1842-70e2-4980-a012-ee4db6046cde |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286460583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.1286460583 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1210040784 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 1357488395 ps |
CPU time | 3.35 seconds |
Started | Jul 28 05:16:38 PM PDT 24 |
Finished | Jul 28 05:16:42 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-3c47bf10-f85f-4d43-a517-c90fecb6b905 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210040784 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1210040784 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.838326711 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 38150503 ps |
CPU time | 0.68 seconds |
Started | Jul 28 05:16:29 PM PDT 24 |
Finished | Jul 28 05:16:30 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-ec7776a8-f7aa-4735-8c07-087735909778 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838326711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_csr_rw.838326711 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3698407423 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 3699991579 ps |
CPU time | 29.35 seconds |
Started | Jul 28 05:16:20 PM PDT 24 |
Finished | Jul 28 05:16:49 PM PDT 24 |
Peak memory | 203052 kb |
Host | smart-f0d82b6b-2f64-4002-9449-50083e0208d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698407423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.3698407423 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3590626765 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 15696521 ps |
CPU time | 0.79 seconds |
Started | Jul 28 05:16:28 PM PDT 24 |
Finished | Jul 28 05:16:34 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-20f15e38-19a2-4acd-993d-f7b5606124f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590626765 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3590626765 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1773117722 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 149226252 ps |
CPU time | 3.85 seconds |
Started | Jul 28 05:16:40 PM PDT 24 |
Finished | Jul 28 05:16:49 PM PDT 24 |
Peak memory | 211276 kb |
Host | smart-a78389ed-5036-4329-bab4-4a480e2fd188 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773117722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.1773117722 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2865794178 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 20011490 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:16:05 PM PDT 24 |
Finished | Jul 28 05:16:06 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-13a7b38c-875e-4cc7-b3ff-b361011584ec |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865794178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.2865794178 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3728426559 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 30070130 ps |
CPU time | 1.21 seconds |
Started | Jul 28 05:16:07 PM PDT 24 |
Finished | Jul 28 05:16:08 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-60f84a7c-74d4-4de3-ba77-b0567285f45e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728426559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.3728426559 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.820549941 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 25225301 ps |
CPU time | 0.7 seconds |
Started | Jul 28 05:16:09 PM PDT 24 |
Finished | Jul 28 05:16:10 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-18290f59-9a6f-4532-96cb-07757c8749a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820549941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_reset.820549941 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.551698855 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 348657532 ps |
CPU time | 3.05 seconds |
Started | Jul 28 05:16:02 PM PDT 24 |
Finished | Jul 28 05:16:05 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-10be0b26-42dc-406b-80c5-d456134a1c6b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551698855 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.551698855 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3422091521 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 15946138 ps |
CPU time | 0.68 seconds |
Started | Jul 28 05:16:06 PM PDT 24 |
Finished | Jul 28 05:16:07 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-23074086-1420-4d6a-acf7-189d1d0a2028 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422091521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.3422091521 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2571783795 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 28131594189 ps |
CPU time | 53.4 seconds |
Started | Jul 28 05:16:05 PM PDT 24 |
Finished | Jul 28 05:16:59 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-3807980b-875c-4a56-a96e-3fe33d192a4a |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571783795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.2571783795 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.103439358 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 19324748 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:16:03 PM PDT 24 |
Finished | Jul 28 05:16:03 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-b1ea8d86-076a-489c-b940-e032f12c7a16 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103439358 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.103439358 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.385907861 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 75431728 ps |
CPU time | 1.96 seconds |
Started | Jul 28 05:16:07 PM PDT 24 |
Finished | Jul 28 05:16:09 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-6865a644-b743-4b12-8d96-5275a75f031d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385907861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.385907861 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2489524251 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 400772214 ps |
CPU time | 2.32 seconds |
Started | Jul 28 05:16:03 PM PDT 24 |
Finished | Jul 28 05:16:06 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-ddcb7c37-5355-49da-b828-4904fd559d2e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489524251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.2489524251 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1461359854 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 70271181 ps |
CPU time | 0.68 seconds |
Started | Jul 28 05:16:07 PM PDT 24 |
Finished | Jul 28 05:16:07 PM PDT 24 |
Peak memory | 202552 kb |
Host | smart-c7cc7652-10f4-4a60-9973-52bbc394843d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461359854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.1461359854 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2441860461 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 53359653 ps |
CPU time | 1.3 seconds |
Started | Jul 28 05:16:14 PM PDT 24 |
Finished | Jul 28 05:16:16 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-5fd1c17b-97c9-4aeb-b836-e5afc9f1f669 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441860461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.2441860461 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1367226787 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 27430621 ps |
CPU time | 0.68 seconds |
Started | Jul 28 05:16:04 PM PDT 24 |
Finished | Jul 28 05:16:04 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-56be1c0a-96cc-4e04-a1a0-73fcac2b7dd9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367226787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1367226787 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3778661395 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 699239263 ps |
CPU time | 3.33 seconds |
Started | Jul 28 05:16:06 PM PDT 24 |
Finished | Jul 28 05:16:10 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-6daa3c1a-e937-4d14-bc98-eda3414dc4b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778661395 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3778661395 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2608589316 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 31793302 ps |
CPU time | 0.64 seconds |
Started | Jul 28 05:16:06 PM PDT 24 |
Finished | Jul 28 05:16:06 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-744975dd-a338-4f0c-a758-646635a10832 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608589316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.2608589316 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4213432023 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 141303351114 ps |
CPU time | 54.74 seconds |
Started | Jul 28 05:16:05 PM PDT 24 |
Finished | Jul 28 05:17:00 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-3d936556-4222-47bc-8691-dbb84853b8d2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213432023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.4213432023 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.146354513 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 37291285 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:16:06 PM PDT 24 |
Finished | Jul 28 05:16:07 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-65805dff-3a64-4680-8e69-12f0561d14de |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146354513 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.146354513 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2254262206 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 64523191 ps |
CPU time | 2.56 seconds |
Started | Jul 28 05:16:02 PM PDT 24 |
Finished | Jul 28 05:16:05 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-67034907-cf19-4ddf-805b-505f944b7b12 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254262206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.2254262206 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3814323235 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 759799609 ps |
CPU time | 2.46 seconds |
Started | Jul 28 05:16:01 PM PDT 24 |
Finished | Jul 28 05:16:04 PM PDT 24 |
Peak memory | 211364 kb |
Host | smart-c01a74d5-c032-4b6c-b023-b19d219f1425 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814323235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.3814323235 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.127156868 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 17202221 ps |
CPU time | 0.71 seconds |
Started | Jul 28 05:16:13 PM PDT 24 |
Finished | Jul 28 05:16:14 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-d154fd8e-3d8c-48ca-acd7-bd147ab92900 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127156868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_aliasing.127156868 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2132396886 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 589640581 ps |
CPU time | 2.38 seconds |
Started | Jul 28 05:16:14 PM PDT 24 |
Finished | Jul 28 05:16:17 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-29e36a78-3931-42f0-b8cc-1898976dea09 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132396886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.2132396886 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2602097480 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 41845656 ps |
CPU time | 0.72 seconds |
Started | Jul 28 05:16:13 PM PDT 24 |
Finished | Jul 28 05:16:14 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-b6520841-5bf5-43fc-99eb-33cc5e8e0f73 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602097480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.2602097480 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1359680939 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 370603475 ps |
CPU time | 3.77 seconds |
Started | Jul 28 05:16:06 PM PDT 24 |
Finished | Jul 28 05:16:10 PM PDT 24 |
Peak memory | 211276 kb |
Host | smart-ad75a5ee-35bf-4091-9f58-6dc4c1975bcc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359680939 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1359680939 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.882133946 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 12754266 ps |
CPU time | 0.66 seconds |
Started | Jul 28 05:16:18 PM PDT 24 |
Finished | Jul 28 05:16:19 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-b5d219d3-6d84-4d4a-8869-71b034a2be07 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882133946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.sram_ctrl_csr_rw.882133946 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2874028006 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 7684353963 ps |
CPU time | 26.79 seconds |
Started | Jul 28 05:16:08 PM PDT 24 |
Finished | Jul 28 05:16:35 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-2b0ebb9a-592f-41d4-acc0-b2050fc51afd |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874028006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2874028006 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.318797890 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 21332705 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:16:09 PM PDT 24 |
Finished | Jul 28 05:16:10 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-9962d580-8116-489a-801f-a61211cdae6e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318797890 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.318797890 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1483832797 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 134238976 ps |
CPU time | 3.35 seconds |
Started | Jul 28 05:16:07 PM PDT 24 |
Finished | Jul 28 05:16:11 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-50d5909e-70ab-48fd-b873-4dc5e2ce33c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483832797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.1483832797 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4149779107 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 75452936 ps |
CPU time | 1.4 seconds |
Started | Jul 28 05:16:01 PM PDT 24 |
Finished | Jul 28 05:16:03 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-5ca178d5-bf87-4c2a-94d4-5f0f01986218 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149779107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.4149779107 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4120453830 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 1387873081 ps |
CPU time | 3.49 seconds |
Started | Jul 28 05:16:21 PM PDT 24 |
Finished | Jul 28 05:16:25 PM PDT 24 |
Peak memory | 210924 kb |
Host | smart-f18d9ace-2cd7-441b-b886-6db2da9dec17 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120453830 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.4120453830 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2557962896 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 14717898 ps |
CPU time | 0.65 seconds |
Started | Jul 28 05:16:18 PM PDT 24 |
Finished | Jul 28 05:16:19 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-ea2a69e4-6528-4c27-b425-7d571d2e6355 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557962896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.2557962896 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3884131028 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 28242336217 ps |
CPU time | 51.97 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:17:11 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-407def38-f4a3-4f24-94bf-60f7220b7097 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884131028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3884131028 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.212976680 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 43499984 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:16:10 PM PDT 24 |
Finished | Jul 28 05:16:11 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-2d179306-8d05-43f4-bb6e-162948204a46 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212976680 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.212976680 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.484506020 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 88255920 ps |
CPU time | 3.23 seconds |
Started | Jul 28 05:16:17 PM PDT 24 |
Finished | Jul 28 05:16:20 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-be2edcf8-523f-4c5f-ab8e-cfbb2e67b20a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484506020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.484506020 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4289975792 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 336645516 ps |
CPU time | 2.04 seconds |
Started | Jul 28 05:16:08 PM PDT 24 |
Finished | Jul 28 05:16:10 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-57e2b046-14a4-48fc-949e-6b4f7c023666 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289975792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.4289975792 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.803512683 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 362614883 ps |
CPU time | 3.51 seconds |
Started | Jul 28 05:16:12 PM PDT 24 |
Finished | Jul 28 05:16:16 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-b8b2546f-9210-4990-b244-915ecbdbd120 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803512683 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.803512683 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3784883052 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 45449107 ps |
CPU time | 0.65 seconds |
Started | Jul 28 05:16:07 PM PDT 24 |
Finished | Jul 28 05:16:08 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-7c4402d6-0755-45fe-8321-28b7d3abbd28 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784883052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.3784883052 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1898120348 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 24308557689 ps |
CPU time | 53.46 seconds |
Started | Jul 28 05:16:18 PM PDT 24 |
Finished | Jul 28 05:17:11 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-d1a075ce-a205-4bcc-aca7-9b395581b43d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898120348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.1898120348 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3526907317 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 16877778 ps |
CPU time | 0.78 seconds |
Started | Jul 28 05:16:21 PM PDT 24 |
Finished | Jul 28 05:16:22 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-342b93d6-9eee-4548-81ff-1dab7eb343ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526907317 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3526907317 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3432465452 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 443924813 ps |
CPU time | 3.85 seconds |
Started | Jul 28 05:16:15 PM PDT 24 |
Finished | Jul 28 05:16:18 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-551e4231-6b32-4046-bcb4-fc4ee3a23d78 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432465452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.3432465452 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3735982885 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 216122188 ps |
CPU time | 1.52 seconds |
Started | Jul 28 05:16:09 PM PDT 24 |
Finished | Jul 28 05:16:11 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-7ac4ceeb-a1d6-4279-b09e-752a3faadfa8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735982885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.3735982885 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3488645010 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 2177021313 ps |
CPU time | 4.16 seconds |
Started | Jul 28 05:16:18 PM PDT 24 |
Finished | Jul 28 05:16:22 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-f054590f-1e3a-4f6f-8255-6117154e9554 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488645010 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3488645010 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.330540626 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 17809483 ps |
CPU time | 0.65 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:20 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-cd8da7ab-73be-4a23-a8ef-3b97f6fa8c90 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330540626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_csr_rw.330540626 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3056512614 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 3806110066 ps |
CPU time | 28.76 seconds |
Started | Jul 28 05:16:13 PM PDT 24 |
Finished | Jul 28 05:16:42 PM PDT 24 |
Peak memory | 202988 kb |
Host | smart-014365c3-16d9-4c49-b538-a6c00d9cbc0c |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056512614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3056512614 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1151969 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 12777063 ps |
CPU time | 0.72 seconds |
Started | Jul 28 05:16:14 PM PDT 24 |
Finished | Jul 28 05:16:15 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-e33a8437-cb92-46d3-a42e-381e5412b580 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151969 -assert nopostproc +UVM_TESTNAME=sram_ctrl _base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1151969 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2509954905 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 168414744 ps |
CPU time | 2.18 seconds |
Started | Jul 28 05:16:15 PM PDT 24 |
Finished | Jul 28 05:16:17 PM PDT 24 |
Peak memory | 202988 kb |
Host | smart-b66ebe69-8a2f-40d1-910d-f1c66eae1ca7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509954905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.2509954905 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.790515675 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 372329592 ps |
CPU time | 2.33 seconds |
Started | Jul 28 05:16:14 PM PDT 24 |
Finished | Jul 28 05:16:16 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-42c73b42-e217-488d-8e24-6ca541d20d61 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790515675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.sram_ctrl_tl_intg_err.790515675 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3069826413 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 2692494779 ps |
CPU time | 5.06 seconds |
Started | Jul 28 05:16:11 PM PDT 24 |
Finished | Jul 28 05:16:16 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-0e839df4-3a8c-4c33-865c-0cf737120986 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069826413 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3069826413 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3693088510 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 33582769 ps |
CPU time | 0.66 seconds |
Started | Jul 28 05:16:12 PM PDT 24 |
Finished | Jul 28 05:16:13 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-75b5ebb5-78c3-426a-9e83-8b1558744744 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693088510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.3693088510 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1527707900 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 10232493170 ps |
CPU time | 54.01 seconds |
Started | Jul 28 05:16:11 PM PDT 24 |
Finished | Jul 28 05:17:05 PM PDT 24 |
Peak memory | 203312 kb |
Host | smart-492ccd76-5853-4319-9e63-a3a1b7cafdc2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527707900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.1527707900 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4193907564 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 18657754 ps |
CPU time | 0.77 seconds |
Started | Jul 28 05:16:17 PM PDT 24 |
Finished | Jul 28 05:16:18 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-76c2c163-5967-43b6-846b-3a63d2f7231d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193907564 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.4193907564 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.630322124 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 105888007 ps |
CPU time | 2.34 seconds |
Started | Jul 28 05:16:21 PM PDT 24 |
Finished | Jul 28 05:16:23 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-3fd44c8a-3237-4419-851c-363be94678db |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630322124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.630322124 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.786452379 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 356960161 ps |
CPU time | 2.35 seconds |
Started | Jul 28 05:16:19 PM PDT 24 |
Finished | Jul 28 05:16:22 PM PDT 24 |
Peak memory | 211200 kb |
Host | smart-d6dc7c97-02ba-4091-a030-4b1b96ec4474 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786452379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.sram_ctrl_tl_intg_err.786452379 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1458332921 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 1227844638 ps |
CPU time | 3.73 seconds |
Started | Jul 28 05:16:15 PM PDT 24 |
Finished | Jul 28 05:16:19 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-901f4f9a-a630-4a53-b73d-8fb972fcb5dc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458332921 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1458332921 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2338419321 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 13024352 ps |
CPU time | 0.7 seconds |
Started | Jul 28 05:16:16 PM PDT 24 |
Finished | Jul 28 05:16:17 PM PDT 24 |
Peak memory | 202548 kb |
Host | smart-55488098-8d95-4df0-9ada-d3dc3511a1c3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338419321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.2338419321 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.979463963 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 7701283822 ps |
CPU time | 29.15 seconds |
Started | Jul 28 05:16:18 PM PDT 24 |
Finished | Jul 28 05:16:47 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-f79422f7-c9cf-4b74-a494-697d51fcfe14 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979463963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.979463963 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1224154466 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 48090371 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:16:09 PM PDT 24 |
Finished | Jul 28 05:16:11 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-89e23b03-f58d-4863-88f6-d4275e59d56c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224154466 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1224154466 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2054032962 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 277972464 ps |
CPU time | 2.8 seconds |
Started | Jul 28 05:16:18 PM PDT 24 |
Finished | Jul 28 05:16:21 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-aa0ebd18-8db2-4ce6-97d7-24bdc1eef454 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054032962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.2054032962 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3228891823 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 839616200 ps |
CPU time | 2.47 seconds |
Started | Jul 28 05:16:16 PM PDT 24 |
Finished | Jul 28 05:16:18 PM PDT 24 |
Peak memory | 211324 kb |
Host | smart-e5f2e34a-4cc5-436e-a6ed-cf4565caafed |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228891823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.3228891823 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3739295668 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 30563566586 ps |
CPU time | 280.2 seconds |
Started | Jul 28 06:50:49 PM PDT 24 |
Finished | Jul 28 06:55:29 PM PDT 24 |
Peak memory | 370728 kb |
Host | smart-2e2dff00-a8aa-4e0f-a19c-e54e4ba7d4ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739295668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.3739295668 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.3026459812 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 34705377 ps |
CPU time | 0.64 seconds |
Started | Jul 28 06:50:52 PM PDT 24 |
Finished | Jul 28 06:50:53 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-c211bee5-6211-4d33-8cb9-f3adbb772787 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026459812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3026459812 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.3495334429 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 75313146736 ps |
CPU time | 2031.22 seconds |
Started | Jul 28 06:50:43 PM PDT 24 |
Finished | Jul 28 07:24:35 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-d752004c-1a5e-4918-9be8-4e3f739ced13 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495334429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 3495334429 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.3349876336 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 17026156026 ps |
CPU time | 626.47 seconds |
Started | Jul 28 06:50:48 PM PDT 24 |
Finished | Jul 28 07:01:14 PM PDT 24 |
Peak memory | 369772 kb |
Host | smart-c2fa1611-ed49-44b4-9922-7d176d86d77d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349876336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.3349876336 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.3940458310 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 11131281381 ps |
CPU time | 66.93 seconds |
Started | Jul 28 06:50:48 PM PDT 24 |
Finished | Jul 28 06:51:55 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-c2eb6654-88d7-4b4b-a785-8d0db88e283d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940458310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.3940458310 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.4192223959 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 10059327349 ps |
CPU time | 23.1 seconds |
Started | Jul 28 06:50:44 PM PDT 24 |
Finished | Jul 28 06:51:07 PM PDT 24 |
Peak memory | 272740 kb |
Host | smart-20be60d2-be32-44ac-a8fa-a7f1f5dac95e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192223959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.4192223959 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.959878391 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 2721739177 ps |
CPU time | 67.99 seconds |
Started | Jul 28 06:50:47 PM PDT 24 |
Finished | Jul 28 06:51:55 PM PDT 24 |
Peak memory | 211344 kb |
Host | smart-8015c7c4-1625-4e3b-82eb-91e0e63c0d88 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959878391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_mem_partial_access.959878391 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.3117044035 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 86139533212 ps |
CPU time | 350.55 seconds |
Started | Jul 28 06:50:47 PM PDT 24 |
Finished | Jul 28 06:56:38 PM PDT 24 |
Peak memory | 211596 kb |
Host | smart-5a9230ac-952c-4783-a1e5-f4539d184ec2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117044035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.3117044035 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.3808162431 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 6830004395 ps |
CPU time | 766.73 seconds |
Started | Jul 28 06:50:44 PM PDT 24 |
Finished | Jul 28 07:03:31 PM PDT 24 |
Peak memory | 374912 kb |
Host | smart-e9d693db-5716-4180-8f04-e668b2f4dcf4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808162431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.3808162431 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.2185038362 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 2223679859 ps |
CPU time | 84.88 seconds |
Started | Jul 28 06:50:44 PM PDT 24 |
Finished | Jul 28 06:52:09 PM PDT 24 |
Peak memory | 359696 kb |
Host | smart-7fa57499-401b-427e-a4e7-fa298f7b6e6d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185038362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.2185038362 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1671433770 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 93074407885 ps |
CPU time | 405.46 seconds |
Started | Jul 28 06:50:43 PM PDT 24 |
Finished | Jul 28 06:57:29 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-b587df59-446c-4fa3-a0c6-de2018474578 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671433770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.1671433770 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.2731740275 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 20592360990 ps |
CPU time | 573.94 seconds |
Started | Jul 28 06:50:48 PM PDT 24 |
Finished | Jul 28 07:00:22 PM PDT 24 |
Peak memory | 378080 kb |
Host | smart-8d36c5fd-23aa-4a1e-b18e-2e0691642abb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731740275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2731740275 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.2666764921 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 189412465 ps |
CPU time | 1.79 seconds |
Started | Jul 28 06:50:53 PM PDT 24 |
Finished | Jul 28 06:50:55 PM PDT 24 |
Peak memory | 222604 kb |
Host | smart-a39c2566-5cea-4fc4-8638-cca901667ae6 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666764921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2666764921 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.1556642929 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 515799362 ps |
CPU time | 13.77 seconds |
Started | Jul 28 06:50:39 PM PDT 24 |
Finished | Jul 28 06:50:53 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-eabd8f9b-9095-46c7-9d91-a3d61e5abf21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556642929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1556642929 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.2394242217 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 40422243746 ps |
CPU time | 2906.55 seconds |
Started | Jul 28 06:50:52 PM PDT 24 |
Finished | Jul 28 07:39:19 PM PDT 24 |
Peak memory | 382104 kb |
Host | smart-58fb0289-3e61-49c7-b3ef-d87aa3a279c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394242217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.2394242217 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2666438252 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 425184410 ps |
CPU time | 11.04 seconds |
Started | Jul 28 06:50:54 PM PDT 24 |
Finished | Jul 28 06:51:05 PM PDT 24 |
Peak memory | 211532 kb |
Host | smart-6f2d1276-14e4-42ac-b5f2-58f95b440186 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2666438252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.2666438252 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3317927497 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 23914091701 ps |
CPU time | 385.38 seconds |
Started | Jul 28 06:50:44 PM PDT 24 |
Finished | Jul 28 06:57:09 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-38edaeec-fa1d-4651-aeb8-d104a4bd4368 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317927497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.3317927497 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2464167335 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1596520827 ps |
CPU time | 99.12 seconds |
Started | Jul 28 06:50:48 PM PDT 24 |
Finished | Jul 28 06:52:27 PM PDT 24 |
Peak memory | 364580 kb |
Host | smart-6c5d30ea-cdf9-4c72-a156-3b15fe25ef24 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464167335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.2464167335 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2284673617 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 1752634252 ps |
CPU time | 94.82 seconds |
Started | Jul 28 06:51:02 PM PDT 24 |
Finished | Jul 28 06:52:37 PM PDT 24 |
Peak memory | 346140 kb |
Host | smart-dc82deb4-0037-40f7-8b5f-2bb835f7ba38 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284673617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.2284673617 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.3170870328 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 32483834600 ps |
CPU time | 735.01 seconds |
Started | Jul 28 06:50:57 PM PDT 24 |
Finished | Jul 28 07:03:12 PM PDT 24 |
Peak memory | 203820 kb |
Host | smart-529cd3c6-70f8-4287-ae03-e8e369eab200 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170870328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 3170870328 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.3537643725 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 147032695720 ps |
CPU time | 1637.59 seconds |
Started | Jul 28 06:51:02 PM PDT 24 |
Finished | Jul 28 07:18:20 PM PDT 24 |
Peak memory | 381040 kb |
Host | smart-a64cacab-a8b4-4e35-9dfd-df6b95bbed45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537643725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.3537643725 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.3782545501 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 23565132092 ps |
CPU time | 72.29 seconds |
Started | Jul 28 06:51:02 PM PDT 24 |
Finished | Jul 28 06:52:14 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-6338f7cb-2e5b-42c9-a5e9-12c77c4f13f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782545501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.3782545501 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.344727818 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 1413508977 ps |
CPU time | 14.63 seconds |
Started | Jul 28 06:51:02 PM PDT 24 |
Finished | Jul 28 06:51:17 PM PDT 24 |
Peak memory | 252164 kb |
Host | smart-687176c8-044d-48b4-8337-0af39cc5f64c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344727818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.sram_ctrl_max_throughput.344727818 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.1315773190 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 20735641643 ps |
CPU time | 242.64 seconds |
Started | Jul 28 06:51:07 PM PDT 24 |
Finished | Jul 28 06:55:09 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-d1fc3ac5-ca47-4426-b99e-757a51e4999b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315773190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.1315773190 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.4023283812 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 5818028916 ps |
CPU time | 475.87 seconds |
Started | Jul 28 06:50:57 PM PDT 24 |
Finished | Jul 28 06:58:54 PM PDT 24 |
Peak memory | 375952 kb |
Host | smart-c91ba61f-29bc-4ba9-8cbc-7cf11508a820 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023283812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.4023283812 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.1476351021 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1934239834 ps |
CPU time | 22.55 seconds |
Started | Jul 28 06:51:02 PM PDT 24 |
Finished | Jul 28 06:51:25 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-243714f9-d544-4544-a4e4-3a669758cd50 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476351021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.1476351021 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1155840453 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 37660013737 ps |
CPU time | 291.83 seconds |
Started | Jul 28 06:51:02 PM PDT 24 |
Finished | Jul 28 06:55:54 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-2953f2f7-09b3-4962-8aea-b7d1ef7b671e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155840453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.1155840453 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.2629983097 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 680075290 ps |
CPU time | 3.59 seconds |
Started | Jul 28 06:51:06 PM PDT 24 |
Finished | Jul 28 06:51:09 PM PDT 24 |
Peak memory | 203064 kb |
Host | smart-24546549-1891-4c60-98b5-dfda434f5ddb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629983097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2629983097 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.817492168 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 25926615434 ps |
CPU time | 1933.83 seconds |
Started | Jul 28 06:51:06 PM PDT 24 |
Finished | Jul 28 07:23:20 PM PDT 24 |
Peak memory | 374964 kb |
Host | smart-13678fc4-d213-4a42-a8b2-437c9b39ff7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817492168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.817492168 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.2147354758 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 129730520 ps |
CPU time | 1.82 seconds |
Started | Jul 28 06:51:11 PM PDT 24 |
Finished | Jul 28 06:51:13 PM PDT 24 |
Peak memory | 222532 kb |
Host | smart-e6a87f0a-975f-4fc8-97ba-2fe96178cf03 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147354758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2147354758 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.1434617131 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 4184548144 ps |
CPU time | 13.38 seconds |
Started | Jul 28 06:50:54 PM PDT 24 |
Finished | Jul 28 06:51:07 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-52cd71ec-9d9f-459c-a1b8-1e5ff68b7e42 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434617131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1434617131 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.2633534849 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 37137753271 ps |
CPU time | 3688.71 seconds |
Started | Jul 28 06:51:11 PM PDT 24 |
Finished | Jul 28 07:52:40 PM PDT 24 |
Peak memory | 379088 kb |
Host | smart-8a2c3a14-bc62-4b70-8891-97447390d288 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633534849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.2633534849 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.194014074 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 1352734929 ps |
CPU time | 36.94 seconds |
Started | Jul 28 06:51:11 PM PDT 24 |
Finished | Jul 28 06:51:48 PM PDT 24 |
Peak memory | 219552 kb |
Host | smart-adbf9612-fbd6-4a00-9a30-7d5fb0f34ff3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=194014074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.194014074 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2845790679 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 5251565080 ps |
CPU time | 330.08 seconds |
Started | Jul 28 06:50:58 PM PDT 24 |
Finished | Jul 28 06:56:28 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-c8f7669b-6b14-4efd-8b75-f0b74b017189 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845790679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.2845790679 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3828440323 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 2831181375 ps |
CPU time | 18.7 seconds |
Started | Jul 28 06:51:02 PM PDT 24 |
Finished | Jul 28 06:51:20 PM PDT 24 |
Peak memory | 257136 kb |
Host | smart-df4c8463-e5e4-49bb-9ec9-f71b14de8d45 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828440323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3828440323 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.4107032737 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 75500979483 ps |
CPU time | 1984.15 seconds |
Started | Jul 28 06:53:14 PM PDT 24 |
Finished | Jul 28 07:26:18 PM PDT 24 |
Peak memory | 380040 kb |
Host | smart-6f1af562-22f9-415a-8889-20a07dd0a853 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107032737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.4107032737 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.4204048293 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 27894922 ps |
CPU time | 0.65 seconds |
Started | Jul 28 06:53:13 PM PDT 24 |
Finished | Jul 28 06:53:14 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-15b547e2-66f1-4c05-856f-73cb561a1683 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204048293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.4204048293 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.2015151295 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 216044783162 ps |
CPU time | 1018.67 seconds |
Started | Jul 28 06:53:02 PM PDT 24 |
Finished | Jul 28 07:10:01 PM PDT 24 |
Peak memory | 203900 kb |
Host | smart-764dfbde-43d1-436a-9e94-656470070cfb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015151295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .2015151295 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.1087149448 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 6440938245 ps |
CPU time | 127.84 seconds |
Started | Jul 28 06:53:14 PM PDT 24 |
Finished | Jul 28 06:55:22 PM PDT 24 |
Peak memory | 347876 kb |
Host | smart-dbf94676-7c41-4c45-a0eb-f0d329d353f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087149448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.1087149448 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.2954060383 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 40288379058 ps |
CPU time | 71.04 seconds |
Started | Jul 28 06:53:14 PM PDT 24 |
Finished | Jul 28 06:54:25 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-c55e4566-02f9-4ffd-90bf-9e977ff52ce6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954060383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.2954060383 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.3193732787 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 3302347590 ps |
CPU time | 37.29 seconds |
Started | Jul 28 06:53:12 PM PDT 24 |
Finished | Jul 28 06:53:49 PM PDT 24 |
Peak memory | 304328 kb |
Host | smart-3a23546e-a71d-49b7-a6cb-8d0ba0c565d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193732787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.3193732787 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3349827439 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 20337117748 ps |
CPU time | 82.47 seconds |
Started | Jul 28 06:53:11 PM PDT 24 |
Finished | Jul 28 06:54:34 PM PDT 24 |
Peak memory | 211668 kb |
Host | smart-c2bf41af-b26c-469d-a22b-53b95f0a2c8b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349827439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.3349827439 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.2550990076 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 8587919112 ps |
CPU time | 126.12 seconds |
Started | Jul 28 06:53:13 PM PDT 24 |
Finished | Jul 28 06:55:19 PM PDT 24 |
Peak memory | 212408 kb |
Host | smart-26436733-c98f-4d4f-85ce-bad02c30a0a6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550990076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.2550990076 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.1961054706 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 44885730344 ps |
CPU time | 1049.75 seconds |
Started | Jul 28 06:53:05 PM PDT 24 |
Finished | Jul 28 07:10:35 PM PDT 24 |
Peak memory | 381132 kb |
Host | smart-e696abaf-c596-4299-aeeb-c357097d6672 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961054706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.1961054706 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.3062200360 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 1555613591 ps |
CPU time | 3.85 seconds |
Started | Jul 28 06:53:08 PM PDT 24 |
Finished | Jul 28 06:53:12 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-91e6154a-58e5-4550-8559-c6ce0d5361ea |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062200360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.3062200360 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.101495272 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 65234322072 ps |
CPU time | 230.63 seconds |
Started | Jul 28 06:53:08 PM PDT 24 |
Finished | Jul 28 06:56:59 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-245494ed-8c03-4178-8067-012d4bd83046 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101495272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.sram_ctrl_partial_access_b2b.101495272 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.898582851 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 465409725 ps |
CPU time | 3.36 seconds |
Started | Jul 28 06:53:12 PM PDT 24 |
Finished | Jul 28 06:53:16 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-fc4b73d7-bab4-4141-bd20-e87ac301acb2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898582851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.898582851 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.2985811652 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 10945546528 ps |
CPU time | 572.39 seconds |
Started | Jul 28 06:53:12 PM PDT 24 |
Finished | Jul 28 07:02:44 PM PDT 24 |
Peak memory | 365684 kb |
Host | smart-a0b30d33-1761-4ec3-af3e-21f0a85869a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985811652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2985811652 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.1365165720 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 410378094 ps |
CPU time | 28.81 seconds |
Started | Jul 28 06:53:03 PM PDT 24 |
Finished | Jul 28 06:53:32 PM PDT 24 |
Peak memory | 286908 kb |
Host | smart-79bd7423-a76e-4586-a408-da292bc61ac2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365165720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1365165720 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.463375755 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 1486801467 ps |
CPU time | 11.93 seconds |
Started | Jul 28 06:53:12 PM PDT 24 |
Finished | Jul 28 06:53:24 PM PDT 24 |
Peak memory | 211364 kb |
Host | smart-441ef3a8-c093-4149-9967-5ae4014f2fee |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=463375755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.463375755 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3449595944 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 5103082836 ps |
CPU time | 313.97 seconds |
Started | Jul 28 06:53:08 PM PDT 24 |
Finished | Jul 28 06:58:22 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-bb248ed0-b85e-4599-9953-f1c55f1fcb20 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449595944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.3449595944 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2185664386 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 682694997 ps |
CPU time | 8.02 seconds |
Started | Jul 28 06:53:14 PM PDT 24 |
Finished | Jul 28 06:53:22 PM PDT 24 |
Peak memory | 219480 kb |
Host | smart-0f995da9-dddd-4ee2-852a-93f00f31ac4a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185664386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2185664386 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3705019945 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 8286328184 ps |
CPU time | 553.24 seconds |
Started | Jul 28 06:53:24 PM PDT 24 |
Finished | Jul 28 07:02:38 PM PDT 24 |
Peak memory | 370800 kb |
Host | smart-a6f9b11b-2253-4ea6-a689-a1c0bcb068c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705019945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3705019945 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.1261641370 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 14397219 ps |
CPU time | 0.65 seconds |
Started | Jul 28 06:53:25 PM PDT 24 |
Finished | Jul 28 06:53:26 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-57b44cb0-89ef-41fd-be06-c4e724dd625f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261641370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1261641370 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.2751065724 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 441468678009 ps |
CPU time | 2004.63 seconds |
Started | Jul 28 06:53:18 PM PDT 24 |
Finished | Jul 28 07:26:42 PM PDT 24 |
Peak memory | 204152 kb |
Host | smart-b4c99092-5414-43f1-9904-f3b48684dab0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751065724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .2751065724 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.944417389 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 31088771369 ps |
CPU time | 1469.25 seconds |
Started | Jul 28 06:53:21 PM PDT 24 |
Finished | Jul 28 07:17:50 PM PDT 24 |
Peak memory | 379016 kb |
Host | smart-d8148743-6873-4843-b8cd-725abd0a4a4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944417389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executabl e.944417389 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1016430641 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 28033136812 ps |
CPU time | 37.27 seconds |
Started | Jul 28 06:53:21 PM PDT 24 |
Finished | Jul 28 06:53:59 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-2337d9b6-1c05-412a-8348-87811b83d4bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016430641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1016430641 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.2126509397 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 3025252474 ps |
CPU time | 39.34 seconds |
Started | Jul 28 06:53:20 PM PDT 24 |
Finished | Jul 28 06:54:00 PM PDT 24 |
Peak memory | 301300 kb |
Host | smart-2f4bb477-40b8-4e5d-ab5a-249fca74fc91 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126509397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.2126509397 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3938875048 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 5060534230 ps |
CPU time | 159.65 seconds |
Started | Jul 28 06:53:25 PM PDT 24 |
Finished | Jul 28 06:56:05 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-0f218462-9d6a-4b8a-b3bd-7cb96acf7cc0 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938875048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.3938875048 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.3944554374 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 82657270150 ps |
CPU time | 383.88 seconds |
Started | Jul 28 06:53:25 PM PDT 24 |
Finished | Jul 28 06:59:49 PM PDT 24 |
Peak memory | 211328 kb |
Host | smart-b9387fd1-b4bf-40fd-9b5e-6bb42d005005 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944554374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.3944554374 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.4266677448 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 19108876757 ps |
CPU time | 976.22 seconds |
Started | Jul 28 06:53:16 PM PDT 24 |
Finished | Jul 28 07:09:33 PM PDT 24 |
Peak memory | 378036 kb |
Host | smart-e89161c6-0fa5-40cb-9e56-764614f4fde1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266677448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.4266677448 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.1898412331 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 3320379746 ps |
CPU time | 14.06 seconds |
Started | Jul 28 06:53:16 PM PDT 24 |
Finished | Jul 28 06:53:30 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-1c5b3008-0474-4137-afe4-062ffb90a69f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898412331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.1898412331 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3880551746 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 7782157095 ps |
CPU time | 229.56 seconds |
Started | Jul 28 06:53:20 PM PDT 24 |
Finished | Jul 28 06:57:10 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-bee58e0d-7173-4bec-9350-83e380885dd5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880551746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.3880551746 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.176417418 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 695935514 ps |
CPU time | 3.48 seconds |
Started | Jul 28 06:53:22 PM PDT 24 |
Finished | Jul 28 06:53:25 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-8726d0ac-89a6-45b3-8a70-0176e74aff41 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176417418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.176417418 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.2133879207 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 2789359496 ps |
CPU time | 151.54 seconds |
Started | Jul 28 06:53:20 PM PDT 24 |
Finished | Jul 28 06:55:52 PM PDT 24 |
Peak memory | 365492 kb |
Host | smart-c170c894-660f-43d8-b6d7-27697179bc48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133879207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2133879207 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.54483181 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 422337804 ps |
CPU time | 6.53 seconds |
Started | Jul 28 06:53:12 PM PDT 24 |
Finished | Jul 28 06:53:19 PM PDT 24 |
Peak memory | 216420 kb |
Host | smart-02df5b78-9a1d-4d03-b05c-00997a2ddfa8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54483181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.54483181 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2303388969 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 1807704217 ps |
CPU time | 53.1 seconds |
Started | Jul 28 06:53:25 PM PDT 24 |
Finished | Jul 28 06:54:18 PM PDT 24 |
Peak memory | 211844 kb |
Host | smart-140d3b8a-9383-42cf-9f61-db674c5de2cf |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2303388969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2303388969 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2902943484 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 38443761853 ps |
CPU time | 287.9 seconds |
Started | Jul 28 06:53:17 PM PDT 24 |
Finished | Jul 28 06:58:05 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-653d7721-f045-4b8e-8e28-7b66a82d5c16 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902943484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.2902943484 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1344661614 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 2758937664 ps |
CPU time | 61.42 seconds |
Started | Jul 28 06:53:21 PM PDT 24 |
Finished | Jul 28 06:54:23 PM PDT 24 |
Peak memory | 307008 kb |
Host | smart-5dd63781-dfaf-4db0-ad96-d375a49a5aa7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344661614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1344661614 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.4090496527 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 11254275303 ps |
CPU time | 495.03 seconds |
Started | Jul 28 06:53:40 PM PDT 24 |
Finished | Jul 28 07:01:55 PM PDT 24 |
Peak memory | 378468 kb |
Host | smart-37224093-3704-4f43-9293-b4cc4703fc1e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090496527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.4090496527 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.206559212 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 13382027 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:53:39 PM PDT 24 |
Finished | Jul 28 06:53:39 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-596ac1d8-dc20-4c67-a817-d6cdd3fd9d44 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206559212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.206559212 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.2543696700 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 151806254427 ps |
CPU time | 2504.87 seconds |
Started | Jul 28 06:53:30 PM PDT 24 |
Finished | Jul 28 07:35:15 PM PDT 24 |
Peak memory | 204004 kb |
Host | smart-1d81adab-f557-4591-b272-6f0a42cd6bf3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543696700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .2543696700 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.2218400165 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 217443130373 ps |
CPU time | 2331.66 seconds |
Started | Jul 28 06:53:36 PM PDT 24 |
Finished | Jul 28 07:32:28 PM PDT 24 |
Peak memory | 380280 kb |
Host | smart-2476143d-c24c-4086-8e16-7506d5a3703f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218400165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.2218400165 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.832186145 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 43154994719 ps |
CPU time | 74.84 seconds |
Started | Jul 28 06:53:35 PM PDT 24 |
Finished | Jul 28 06:54:50 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-4a556187-7ae5-4aab-abb8-38487a130472 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832186145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_esc alation.832186145 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.1676521218 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 5212134412 ps |
CPU time | 52.65 seconds |
Started | Jul 28 06:53:32 PM PDT 24 |
Finished | Jul 28 06:54:25 PM PDT 24 |
Peak memory | 309184 kb |
Host | smart-5f79cc08-d4ca-4665-bfad-7f972840c43d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676521218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.1676521218 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2843815842 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 20513979670 ps |
CPU time | 147.74 seconds |
Started | Jul 28 06:53:36 PM PDT 24 |
Finished | Jul 28 06:56:04 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-355a0c24-84fc-4230-8662-03d40ca53fb7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843815842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.2843815842 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.2929600177 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 6928503252 ps |
CPU time | 154.81 seconds |
Started | Jul 28 06:53:35 PM PDT 24 |
Finished | Jul 28 06:56:10 PM PDT 24 |
Peak memory | 204048 kb |
Host | smart-4b0a49b3-e3f2-496f-8daa-1082cd4c2fa9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929600177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.2929600177 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.2166970740 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 12065974139 ps |
CPU time | 291.39 seconds |
Started | Jul 28 06:53:31 PM PDT 24 |
Finished | Jul 28 06:58:23 PM PDT 24 |
Peak memory | 354468 kb |
Host | smart-827f6b74-3119-441b-a617-de19299f7280 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166970740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.2166970740 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.1973193197 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 2695506811 ps |
CPU time | 20.6 seconds |
Started | Jul 28 06:53:33 PM PDT 24 |
Finished | Jul 28 06:53:53 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-c014529e-b197-42fc-942e-5c2b96308f38 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973193197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.1973193197 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4075967025 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 28583543540 ps |
CPU time | 616.36 seconds |
Started | Jul 28 06:53:30 PM PDT 24 |
Finished | Jul 28 07:03:47 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-b02dc3bf-0150-44f3-adb0-b1b7f6a591be |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075967025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.4075967025 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.3213332111 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 1675850104 ps |
CPU time | 3.32 seconds |
Started | Jul 28 06:53:37 PM PDT 24 |
Finished | Jul 28 06:53:41 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-6f5bded7-375c-4830-b245-ef2357a83187 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213332111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3213332111 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.1138266247 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 48005294925 ps |
CPU time | 646.22 seconds |
Started | Jul 28 06:53:39 PM PDT 24 |
Finished | Jul 28 07:04:25 PM PDT 24 |
Peak memory | 343240 kb |
Host | smart-4c1fa0d4-362b-482c-9fd5-bcb31e33b909 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138266247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1138266247 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.1858022493 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 1231433433 ps |
CPU time | 123.97 seconds |
Started | Jul 28 06:53:26 PM PDT 24 |
Finished | Jul 28 06:55:30 PM PDT 24 |
Peak memory | 348200 kb |
Host | smart-c2006186-8850-4530-9369-28799fd3201b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858022493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1858022493 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.2632371827 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 2264648647194 ps |
CPU time | 6754.54 seconds |
Started | Jul 28 06:53:36 PM PDT 24 |
Finished | Jul 28 08:46:11 PM PDT 24 |
Peak memory | 381104 kb |
Host | smart-c6ff3eb0-34d3-4552-ab8d-17acfbc6e5da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632371827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.2632371827 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3613437851 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 5723047235 ps |
CPU time | 35.28 seconds |
Started | Jul 28 06:53:39 PM PDT 24 |
Finished | Jul 28 06:54:14 PM PDT 24 |
Peak memory | 219036 kb |
Host | smart-e37376e7-4f14-4a01-a5d3-b539dce603ef |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3613437851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3613437851 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3949409145 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 10451968649 ps |
CPU time | 257.4 seconds |
Started | Jul 28 06:53:30 PM PDT 24 |
Finished | Jul 28 06:57:48 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-3f045170-629b-4cb7-bd27-d7c4da11cd45 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949409145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.3949409145 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4278191765 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 765987210 ps |
CPU time | 44.03 seconds |
Started | Jul 28 06:53:33 PM PDT 24 |
Finished | Jul 28 06:54:17 PM PDT 24 |
Peak memory | 302320 kb |
Host | smart-afc0c207-44d3-4401-a492-70adfae5dc53 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278191765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.4278191765 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3857241641 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 13300426835 ps |
CPU time | 1283.02 seconds |
Started | Jul 28 06:53:45 PM PDT 24 |
Finished | Jul 28 07:15:08 PM PDT 24 |
Peak memory | 380088 kb |
Host | smart-62ade785-f11e-44f8-888d-d635e4979318 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857241641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.3857241641 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.4146177694 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 19248974 ps |
CPU time | 0.66 seconds |
Started | Jul 28 06:53:54 PM PDT 24 |
Finished | Jul 28 06:53:55 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-aa51293e-706e-412d-995f-fc2be2cab3b8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146177694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.4146177694 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.828116918 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 529275725666 ps |
CPU time | 1027.02 seconds |
Started | Jul 28 06:53:41 PM PDT 24 |
Finished | Jul 28 07:10:48 PM PDT 24 |
Peak memory | 203724 kb |
Host | smart-044254cb-b90e-460b-8191-a43c54fb498d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828116918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection. 828116918 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.456111243 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 24806585220 ps |
CPU time | 1048.53 seconds |
Started | Jul 28 06:53:46 PM PDT 24 |
Finished | Jul 28 07:11:14 PM PDT 24 |
Peak memory | 376940 kb |
Host | smart-6cb874aa-583b-45e6-ba80-e015ae46b31f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456111243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executabl e.456111243 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.4019030930 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 9673224097 ps |
CPU time | 62.56 seconds |
Started | Jul 28 06:53:45 PM PDT 24 |
Finished | Jul 28 06:54:47 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-8db82339-4faa-4577-b0c8-53b1345f28d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019030930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.4019030930 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.2493145454 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 736765415 ps |
CPU time | 47.95 seconds |
Started | Jul 28 06:53:47 PM PDT 24 |
Finished | Jul 28 06:54:35 PM PDT 24 |
Peak memory | 310604 kb |
Host | smart-6465d0ab-be54-43d2-93f9-11316c53c885 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493145454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.2493145454 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.36331303 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 2532119057 ps |
CPU time | 153.16 seconds |
Started | Jul 28 06:53:51 PM PDT 24 |
Finished | Jul 28 06:56:24 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-a809ceff-c915-4d6a-9449-b727a68316b6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36331303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_mem_partial_access.36331303 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.1482138136 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 4029504778 ps |
CPU time | 254.2 seconds |
Started | Jul 28 06:53:51 PM PDT 24 |
Finished | Jul 28 06:58:05 PM PDT 24 |
Peak memory | 211296 kb |
Host | smart-b4673a45-a18f-42ce-9055-c7e00b9578a2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482138136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.1482138136 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.914438973 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 8388083646 ps |
CPU time | 1198.91 seconds |
Started | Jul 28 06:53:42 PM PDT 24 |
Finished | Jul 28 07:13:41 PM PDT 24 |
Peak memory | 380020 kb |
Host | smart-21e4574f-1102-4e43-84d2-470f1b28d604 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914438973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip le_keys.914438973 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.1483866192 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 1661957691 ps |
CPU time | 16.18 seconds |
Started | Jul 28 06:53:45 PM PDT 24 |
Finished | Jul 28 06:54:01 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-6a0024c7-540f-48cd-a106-b1f746d6ee8f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483866192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.1483866192 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.475833891 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 11760966352 ps |
CPU time | 350.27 seconds |
Started | Jul 28 06:53:45 PM PDT 24 |
Finished | Jul 28 06:59:36 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-0a1984f4-066e-4ca9-b986-3636cfa6f285 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475833891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.sram_ctrl_partial_access_b2b.475833891 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.1129370206 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 344214432 ps |
CPU time | 3.22 seconds |
Started | Jul 28 06:53:44 PM PDT 24 |
Finished | Jul 28 06:53:47 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-b6b29e7c-e3a3-4104-87dc-e35d6e65f7c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129370206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1129370206 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.3127022575 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 11994954280 ps |
CPU time | 700.8 seconds |
Started | Jul 28 06:53:44 PM PDT 24 |
Finished | Jul 28 07:05:25 PM PDT 24 |
Peak memory | 377984 kb |
Host | smart-d99fbe96-52eb-4daa-aebd-55d1003d7d74 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127022575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3127022575 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.3839980202 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 1572043918 ps |
CPU time | 14.69 seconds |
Started | Jul 28 06:53:41 PM PDT 24 |
Finished | Jul 28 06:53:56 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-0f307ed1-9059-4fd1-8cd0-2cb1b901cd4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839980202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3839980202 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.2579202664 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 25124921178 ps |
CPU time | 981.95 seconds |
Started | Jul 28 06:53:50 PM PDT 24 |
Finished | Jul 28 07:10:12 PM PDT 24 |
Peak memory | 381180 kb |
Host | smart-e866c9c7-8ced-4407-a3d1-cdd6447c4704 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579202664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.2579202664 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2508534738 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 1064688224 ps |
CPU time | 38.12 seconds |
Started | Jul 28 06:53:51 PM PDT 24 |
Finished | Jul 28 06:54:30 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-ca4c90ab-d789-4f2e-b419-d12af045bba7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2508534738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2508534738 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2576404955 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 10004583496 ps |
CPU time | 169.02 seconds |
Started | Jul 28 06:53:40 PM PDT 24 |
Finished | Jul 28 06:56:29 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-104c00cf-1f7b-41ce-975e-19ad5e511704 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576404955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.2576404955 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3494798737 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 1496314880 ps |
CPU time | 33.02 seconds |
Started | Jul 28 06:53:46 PM PDT 24 |
Finished | Jul 28 06:54:19 PM PDT 24 |
Peak memory | 295884 kb |
Host | smart-44fb371d-1b30-4bb0-930b-ffad75a125c2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494798737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3494798737 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.542684853 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 4422498644 ps |
CPU time | 75.55 seconds |
Started | Jul 28 06:54:04 PM PDT 24 |
Finished | Jul 28 06:55:20 PM PDT 24 |
Peak memory | 311500 kb |
Host | smart-55c00b24-be8e-452c-b18a-8a221c2fe125 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542684853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_access_during_key_req.542684853 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.1966956314 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 42972888 ps |
CPU time | 0.63 seconds |
Started | Jul 28 06:54:09 PM PDT 24 |
Finished | Jul 28 06:54:10 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-0fd6c699-1920-4d85-84a8-89bf84878073 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966956314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1966956314 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.979543761 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 179451604286 ps |
CPU time | 2294.1 seconds |
Started | Jul 28 06:53:54 PM PDT 24 |
Finished | Jul 28 07:32:09 PM PDT 24 |
Peak memory | 203832 kb |
Host | smart-08a87887-9c9f-4b76-870b-717014c1c244 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979543761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection. 979543761 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.4019792420 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 7470082504 ps |
CPU time | 446.94 seconds |
Started | Jul 28 06:54:04 PM PDT 24 |
Finished | Jul 28 07:01:31 PM PDT 24 |
Peak memory | 376956 kb |
Host | smart-9ff5acdd-6982-41f3-b807-3422eb3ee856 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019792420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.4019792420 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.572405888 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 8917385441 ps |
CPU time | 58.32 seconds |
Started | Jul 28 06:53:59 PM PDT 24 |
Finished | Jul 28 06:54:57 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-cedee2ec-1145-4208-afe0-4bbb57e9e3db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572405888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_esc alation.572405888 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.4069891385 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 6798701061 ps |
CPU time | 84.91 seconds |
Started | Jul 28 06:53:58 PM PDT 24 |
Finished | Jul 28 06:55:23 PM PDT 24 |
Peak memory | 334024 kb |
Host | smart-6965d86b-596f-4c2f-8ff8-46c72d063077 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069891385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.4069891385 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.921285715 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 5362378225 ps |
CPU time | 92.03 seconds |
Started | Jul 28 06:54:04 PM PDT 24 |
Finished | Jul 28 06:55:37 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-69fa198a-047b-4378-91e5-62b7f9ebf512 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921285715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14 .sram_ctrl_mem_partial_access.921285715 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.1471238763 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 5419116259 ps |
CPU time | 301.21 seconds |
Started | Jul 28 06:54:06 PM PDT 24 |
Finished | Jul 28 06:59:08 PM PDT 24 |
Peak memory | 211324 kb |
Host | smart-80995bb0-2caf-4e73-8801-c37a198ad9a8 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471238763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.1471238763 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.3196996838 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 9255506650 ps |
CPU time | 1179.4 seconds |
Started | Jul 28 06:53:54 PM PDT 24 |
Finished | Jul 28 07:13:34 PM PDT 24 |
Peak memory | 381048 kb |
Host | smart-1ebcadef-83a4-4f3c-872f-197eab60d824 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196996838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3196996838 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.2290506203 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 3332403280 ps |
CPU time | 96.03 seconds |
Started | Jul 28 06:54:00 PM PDT 24 |
Finished | Jul 28 06:55:36 PM PDT 24 |
Peak memory | 359616 kb |
Host | smart-51b0a948-914a-484b-b769-9941561f47de |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290506203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.2290506203 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1278563809 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 67010332910 ps |
CPU time | 377.2 seconds |
Started | Jul 28 06:54:00 PM PDT 24 |
Finished | Jul 28 07:00:17 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-aad5ba40-b2d8-4134-b3c0-a86869b1bfb4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278563809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.1278563809 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.1874382977 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 403257599 ps |
CPU time | 3.18 seconds |
Started | Jul 28 06:54:05 PM PDT 24 |
Finished | Jul 28 06:54:08 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-7eb17fa0-2526-4f14-b957-75bf70434a82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874382977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1874382977 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.1617197525 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 14790179943 ps |
CPU time | 427.25 seconds |
Started | Jul 28 06:54:04 PM PDT 24 |
Finished | Jul 28 07:01:12 PM PDT 24 |
Peak memory | 379052 kb |
Host | smart-bcbbea35-7cba-472e-9fc1-9190a70442a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617197525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1617197525 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.3431516346 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 824648844 ps |
CPU time | 126.89 seconds |
Started | Jul 28 06:53:54 PM PDT 24 |
Finished | Jul 28 06:56:01 PM PDT 24 |
Peak memory | 367624 kb |
Host | smart-97913868-ab5d-448f-b8b9-1b95ec598c46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431516346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3431516346 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.4090560871 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 191987585332 ps |
CPU time | 1912.14 seconds |
Started | Jul 28 06:54:05 PM PDT 24 |
Finished | Jul 28 07:25:58 PM PDT 24 |
Peak memory | 381088 kb |
Host | smart-ad7616d3-fcae-41b6-8af3-bd39cf3abe92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090560871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.4090560871 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3318061389 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 1625184914 ps |
CPU time | 55.87 seconds |
Started | Jul 28 06:54:04 PM PDT 24 |
Finished | Jul 28 06:55:00 PM PDT 24 |
Peak memory | 278584 kb |
Host | smart-b7e94b0c-8e9c-483f-86e6-a705dc26e3e1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3318061389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3318061389 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2960567276 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 2958071698 ps |
CPU time | 201.25 seconds |
Started | Jul 28 06:54:00 PM PDT 24 |
Finished | Jul 28 06:57:21 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-04898141-1279-4c1d-9c81-07e90d806c9f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960567276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.2960567276 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1678792670 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 721298302 ps |
CPU time | 16.74 seconds |
Started | Jul 28 06:53:58 PM PDT 24 |
Finished | Jul 28 06:54:15 PM PDT 24 |
Peak memory | 259616 kb |
Host | smart-f3861fc9-8551-41f2-bdb0-fde764fa9aaf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678792670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1678792670 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3529581712 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 43531632706 ps |
CPU time | 966.76 seconds |
Started | Jul 28 06:54:23 PM PDT 24 |
Finished | Jul 28 07:10:30 PM PDT 24 |
Peak memory | 377956 kb |
Host | smart-ed8d5f26-399e-4252-a965-8cadd8a46889 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529581712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.3529581712 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.3042287761 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 14342695 ps |
CPU time | 0.68 seconds |
Started | Jul 28 06:54:29 PM PDT 24 |
Finished | Jul 28 06:54:30 PM PDT 24 |
Peak memory | 202612 kb |
Host | smart-e991a788-b0ea-4e33-a28b-ea662173cace |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042287761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.3042287761 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.4074724850 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 248992499649 ps |
CPU time | 1111.08 seconds |
Started | Jul 28 06:54:10 PM PDT 24 |
Finished | Jul 28 07:12:41 PM PDT 24 |
Peak memory | 203856 kb |
Host | smart-2efb5900-58bc-45fb-967a-d670c922cad8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074724850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .4074724850 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.12427574 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 11971193335 ps |
CPU time | 1148.23 seconds |
Started | Jul 28 06:54:22 PM PDT 24 |
Finished | Jul 28 07:13:30 PM PDT 24 |
Peak memory | 381044 kb |
Host | smart-896b143d-4018-404c-976a-01869034e790 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12427574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable .12427574 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.701608178 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 25751018006 ps |
CPU time | 41.7 seconds |
Started | Jul 28 06:54:23 PM PDT 24 |
Finished | Jul 28 06:55:04 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-566e109c-beda-4369-981a-1eba32b64825 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701608178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_esc alation.701608178 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.1792953403 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 770074398 ps |
CPU time | 82.34 seconds |
Started | Jul 28 06:54:19 PM PDT 24 |
Finished | Jul 28 06:55:41 PM PDT 24 |
Peak memory | 320660 kb |
Host | smart-5c6f63a7-a60c-43a0-8185-9fe95f2d9df6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792953403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.1792953403 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.4171243259 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 38341513351 ps |
CPU time | 84.25 seconds |
Started | Jul 28 06:54:27 PM PDT 24 |
Finished | Jul 28 06:55:51 PM PDT 24 |
Peak memory | 212092 kb |
Host | smart-5f18e555-5f09-4658-b35a-ff24ddd6f4fd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171243259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.4171243259 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.2079187143 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 115211154136 ps |
CPU time | 351.54 seconds |
Started | Jul 28 06:54:21 PM PDT 24 |
Finished | Jul 28 07:00:13 PM PDT 24 |
Peak memory | 211552 kb |
Host | smart-ee2bcc24-2f49-403d-a2c4-4138d3054e82 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079187143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.2079187143 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.1321159592 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 102225217112 ps |
CPU time | 1078.55 seconds |
Started | Jul 28 06:54:07 PM PDT 24 |
Finished | Jul 28 07:12:06 PM PDT 24 |
Peak memory | 376944 kb |
Host | smart-f28ce58f-cc9a-45df-8710-e54b34e23761 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321159592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.1321159592 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.2876336426 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 764838103 ps |
CPU time | 36.45 seconds |
Started | Jul 28 06:54:13 PM PDT 24 |
Finished | Jul 28 06:54:50 PM PDT 24 |
Peak memory | 281788 kb |
Host | smart-570ca2cd-5ee0-4359-a4ce-01a78e038f4b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876336426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.2876336426 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.1897365394 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 688083267 ps |
CPU time | 3.16 seconds |
Started | Jul 28 06:54:21 PM PDT 24 |
Finished | Jul 28 06:54:24 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-3271697b-651b-4893-8a65-b7a32f4af7ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897365394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1897365394 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.1451956100 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 16957465590 ps |
CPU time | 942.52 seconds |
Started | Jul 28 06:54:21 PM PDT 24 |
Finished | Jul 28 07:10:04 PM PDT 24 |
Peak memory | 370824 kb |
Host | smart-41853a55-0c0d-43a2-b347-25928c3760d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451956100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1451956100 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.4055030772 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 814658811 ps |
CPU time | 10.51 seconds |
Started | Jul 28 06:54:08 PM PDT 24 |
Finished | Jul 28 06:54:19 PM PDT 24 |
Peak memory | 226372 kb |
Host | smart-8c808f52-63a7-459c-93f9-077566d44477 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055030772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.4055030772 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3364184058 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 1164131105 ps |
CPU time | 41.97 seconds |
Started | Jul 28 06:54:27 PM PDT 24 |
Finished | Jul 28 06:55:09 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-2a29bd0f-b536-4e89-ab8a-a587dca95ea7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3364184058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3364184058 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.4039676749 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 3334142276 ps |
CPU time | 195.31 seconds |
Started | Jul 28 06:54:13 PM PDT 24 |
Finished | Jul 28 06:57:29 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-d6802ebb-9413-4f75-b2d0-b34fec439568 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039676749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.4039676749 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2688123081 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 1404806148 ps |
CPU time | 9.62 seconds |
Started | Jul 28 06:54:18 PM PDT 24 |
Finished | Jul 28 06:54:28 PM PDT 24 |
Peak memory | 226496 kb |
Host | smart-c7fe6ab9-79a0-445f-bf73-4c73ea879b9b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688123081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2688123081 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.4165742006 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 4683318983 ps |
CPU time | 389.98 seconds |
Started | Jul 28 06:54:31 PM PDT 24 |
Finished | Jul 28 07:01:01 PM PDT 24 |
Peak memory | 362704 kb |
Host | smart-6828a3fd-7870-4e05-b8e1-cd2a7026f001 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165742006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.4165742006 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.3528424655 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 14212416 ps |
CPU time | 0.65 seconds |
Started | Jul 28 06:54:36 PM PDT 24 |
Finished | Jul 28 06:54:37 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-45043f63-7117-4a0a-b49b-8ad482116e75 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528424655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3528424655 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.2004545923 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 63511235825 ps |
CPU time | 2230.65 seconds |
Started | Jul 28 06:54:27 PM PDT 24 |
Finished | Jul 28 07:31:38 PM PDT 24 |
Peak memory | 203908 kb |
Host | smart-0706f47e-02f2-4269-912b-7221c1558ead |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004545923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .2004545923 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.3886346416 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 62120927750 ps |
CPU time | 291.29 seconds |
Started | Jul 28 06:54:31 PM PDT 24 |
Finished | Jul 28 06:59:22 PM PDT 24 |
Peak memory | 337072 kb |
Host | smart-5978229c-3617-4ecf-94b9-947723e1f0dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886346416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.3886346416 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.1673935135 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 8063585819 ps |
CPU time | 48.86 seconds |
Started | Jul 28 06:54:32 PM PDT 24 |
Finished | Jul 28 06:55:21 PM PDT 24 |
Peak memory | 215984 kb |
Host | smart-aac7d984-f9c5-44c4-95ea-70b246c1d709 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673935135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.1673935135 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.296416228 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 794118086 ps |
CPU time | 80.56 seconds |
Started | Jul 28 06:54:34 PM PDT 24 |
Finished | Jul 28 06:55:55 PM PDT 24 |
Peak memory | 332152 kb |
Host | smart-c0d83691-804c-4836-b33b-7f5f70edc897 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296416228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.sram_ctrl_max_throughput.296416228 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1034655416 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 2783865664 ps |
CPU time | 74.55 seconds |
Started | Jul 28 06:54:35 PM PDT 24 |
Finished | Jul 28 06:55:49 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-bb905303-d9cb-4c28-b0da-72fbcdaedcdc |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034655416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.1034655416 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.2223854648 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 32864303810 ps |
CPU time | 159.95 seconds |
Started | Jul 28 06:54:36 PM PDT 24 |
Finished | Jul 28 06:57:16 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-b74a29c5-72f4-40b7-89a3-4747a5037578 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223854648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.2223854648 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.3517334410 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 60875613197 ps |
CPU time | 721.93 seconds |
Started | Jul 28 06:54:25 PM PDT 24 |
Finished | Jul 28 07:06:27 PM PDT 24 |
Peak memory | 371828 kb |
Host | smart-8f6efee2-f164-4ffb-abe8-51b9b562bc13 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517334410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.3517334410 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.2417842298 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 789907216 ps |
CPU time | 7.79 seconds |
Started | Jul 28 06:54:32 PM PDT 24 |
Finished | Jul 28 06:54:40 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-a0e13e42-2d82-4aa9-9e7e-5a4424ba2e49 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417842298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.2417842298 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1793801373 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 5117963927 ps |
CPU time | 167.08 seconds |
Started | Jul 28 06:54:34 PM PDT 24 |
Finished | Jul 28 06:57:21 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-6b64ffcf-7bcf-4093-911c-da5a38538c41 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793801373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.1793801373 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.1037647569 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 367013855 ps |
CPU time | 3.36 seconds |
Started | Jul 28 06:54:36 PM PDT 24 |
Finished | Jul 28 06:54:40 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-a3589e91-ae07-43ca-b817-060b83c513a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037647569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1037647569 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.2894765286 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 19411635425 ps |
CPU time | 1663.82 seconds |
Started | Jul 28 06:54:32 PM PDT 24 |
Finished | Jul 28 07:22:16 PM PDT 24 |
Peak memory | 378036 kb |
Host | smart-8fa7c3ec-bb8d-4c0e-a6c9-a842cad9bc62 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894765286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2894765286 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.4211729599 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 1798544804 ps |
CPU time | 18.4 seconds |
Started | Jul 28 06:54:27 PM PDT 24 |
Finished | Jul 28 06:54:45 PM PDT 24 |
Peak memory | 248020 kb |
Host | smart-7aa748b9-20c8-4ee9-95c0-3aac0f46007c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211729599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.4211729599 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1379266196 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 25848465760 ps |
CPU time | 193.21 seconds |
Started | Jul 28 06:54:36 PM PDT 24 |
Finished | Jul 28 06:57:50 PM PDT 24 |
Peak memory | 363772 kb |
Host | smart-cb0054a8-761b-4987-9f6f-dd2fbd64f2e0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1379266196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1379266196 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.4291671148 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 3351344872 ps |
CPU time | 202.35 seconds |
Started | Jul 28 06:54:27 PM PDT 24 |
Finished | Jul 28 06:57:49 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-5077525c-3a2e-4948-86b3-01dd80f720e1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291671148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.4291671148 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.53122295 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 945668057 ps |
CPU time | 70.12 seconds |
Started | Jul 28 06:54:32 PM PDT 24 |
Finished | Jul 28 06:55:42 PM PDT 24 |
Peak memory | 330960 kb |
Host | smart-aaeb2e39-d06c-46d7-bc2d-dbae0bdc298a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53122295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.sram_ctrl_throughput_w_partial_write.53122295 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.844726438 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 11756084439 ps |
CPU time | 1174.2 seconds |
Started | Jul 28 06:54:45 PM PDT 24 |
Finished | Jul 28 07:14:20 PM PDT 24 |
Peak memory | 380144 kb |
Host | smart-bd648a08-2ab8-48a5-9934-3a21430632c2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844726438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_access_during_key_req.844726438 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.2746530782 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 14519504 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:54:49 PM PDT 24 |
Finished | Jul 28 06:54:50 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-ce43f83c-162e-4bbf-bd95-992c68cf3ab9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746530782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2746530782 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.1387541248 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 53789245379 ps |
CPU time | 970.53 seconds |
Started | Jul 28 06:54:43 PM PDT 24 |
Finished | Jul 28 07:10:53 PM PDT 24 |
Peak memory | 204056 kb |
Host | smart-2a9dc7e6-b6f5-4de3-81aa-f639e55149b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387541248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .1387541248 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.2166251963 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 71104240867 ps |
CPU time | 1389.22 seconds |
Started | Jul 28 06:54:47 PM PDT 24 |
Finished | Jul 28 07:17:56 PM PDT 24 |
Peak memory | 379036 kb |
Host | smart-903170ed-43e8-4d88-89cc-1cd7f3853fb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166251963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.2166251963 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.2135323655 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 8905169026 ps |
CPU time | 45.62 seconds |
Started | Jul 28 06:54:46 PM PDT 24 |
Finished | Jul 28 06:55:32 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-0fe389e1-f1c4-45a8-9859-e1ac0c614ac2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135323655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.2135323655 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.3417322825 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 4419120757 ps |
CPU time | 96.66 seconds |
Started | Jul 28 06:54:44 PM PDT 24 |
Finished | Jul 28 06:56:20 PM PDT 24 |
Peak memory | 349772 kb |
Host | smart-0dc12121-a6f3-498f-8350-c97e0cfddc13 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417322825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.3417322825 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3770332051 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 4310183352 ps |
CPU time | 125.48 seconds |
Started | Jul 28 06:54:46 PM PDT 24 |
Finished | Jul 28 06:56:52 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-40e51f0d-3e45-44b6-be40-51b00b8930b8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770332051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.3770332051 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.1119000554 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 8452096683 ps |
CPU time | 158.92 seconds |
Started | Jul 28 06:54:46 PM PDT 24 |
Finished | Jul 28 06:57:25 PM PDT 24 |
Peak memory | 211864 kb |
Host | smart-b861135b-4352-4bd4-961c-81f76319f50b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119000554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.1119000554 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.2279129767 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 13310749832 ps |
CPU time | 1023.16 seconds |
Started | Jul 28 06:54:44 PM PDT 24 |
Finished | Jul 28 07:11:47 PM PDT 24 |
Peak memory | 381532 kb |
Host | smart-cc1be243-0873-4f67-bd12-4e2063bcbf64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279129767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.2279129767 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.2230705927 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 814587301 ps |
CPU time | 50.21 seconds |
Started | Jul 28 06:54:43 PM PDT 24 |
Finished | Jul 28 06:55:33 PM PDT 24 |
Peak memory | 318616 kb |
Host | smart-24ce0a97-ea91-41f9-8920-f3144222cbc7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230705927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.2230705927 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3748915947 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 32876125847 ps |
CPU time | 173.51 seconds |
Started | Jul 28 06:54:41 PM PDT 24 |
Finished | Jul 28 06:57:34 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-18b2bc90-4f24-4141-88a6-0d8319fd666b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748915947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.3748915947 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.923797276 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 1473996834 ps |
CPU time | 3.75 seconds |
Started | Jul 28 06:54:46 PM PDT 24 |
Finished | Jul 28 06:54:50 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-bb59f242-9243-4003-87d2-be23a47bd9f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923797276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.923797276 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.1629901447 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 74554700813 ps |
CPU time | 1447.26 seconds |
Started | Jul 28 06:54:47 PM PDT 24 |
Finished | Jul 28 07:18:54 PM PDT 24 |
Peak memory | 376868 kb |
Host | smart-3fa0955d-f433-4214-ab7e-fbeee1eb04e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629901447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1629901447 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.3869883667 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 2639900457 ps |
CPU time | 18.9 seconds |
Started | Jul 28 06:54:41 PM PDT 24 |
Finished | Jul 28 06:55:00 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-a3b0fe40-9a33-497b-9c24-02a004ce62d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869883667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3869883667 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.2307368651 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 64206528268 ps |
CPU time | 4454.06 seconds |
Started | Jul 28 06:54:50 PM PDT 24 |
Finished | Jul 28 08:09:05 PM PDT 24 |
Peak memory | 379056 kb |
Host | smart-550a9844-2437-4829-9428-31a677958fe0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307368651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.2307368651 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2776500450 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 2368293913 ps |
CPU time | 297.06 seconds |
Started | Jul 28 06:54:51 PM PDT 24 |
Finished | Jul 28 06:59:48 PM PDT 24 |
Peak memory | 387240 kb |
Host | smart-28d1d376-d767-4c9e-a45b-c6539c42d159 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2776500450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2776500450 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1363504639 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 22258451496 ps |
CPU time | 369.24 seconds |
Started | Jul 28 06:54:40 PM PDT 24 |
Finished | Jul 28 07:00:49 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-4e19bcf5-86fa-4bd6-8c47-895d4a5dc786 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363504639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.1363504639 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3148677561 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 773410200 ps |
CPU time | 64.68 seconds |
Started | Jul 28 06:54:42 PM PDT 24 |
Finished | Jul 28 06:55:46 PM PDT 24 |
Peak memory | 315992 kb |
Host | smart-c67e169b-301a-4277-bf67-4be41d53c5c8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148677561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.3148677561 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3943136526 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 2511245715 ps |
CPU time | 24.94 seconds |
Started | Jul 28 06:54:59 PM PDT 24 |
Finished | Jul 28 06:55:24 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-c500c8e0-b04f-4643-916e-abebe0bde9ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943136526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.3943136526 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.580870128 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 23059022 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:54:59 PM PDT 24 |
Finished | Jul 28 06:55:00 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-8af46c12-949c-4b91-8033-02a8099f1d08 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580870128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.580870128 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.3844397170 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 104051958873 ps |
CPU time | 1829.05 seconds |
Started | Jul 28 06:54:50 PM PDT 24 |
Finished | Jul 28 07:25:19 PM PDT 24 |
Peak memory | 204036 kb |
Host | smart-996cc29b-8110-4b40-9269-7f5ed11fa142 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844397170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .3844397170 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.3336458336 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 39828082214 ps |
CPU time | 531.19 seconds |
Started | Jul 28 06:55:02 PM PDT 24 |
Finished | Jul 28 07:03:53 PM PDT 24 |
Peak memory | 375964 kb |
Host | smart-bc510cb0-4cdd-4493-b896-c997e2e8463e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336458336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.3336458336 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.1393899000 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 43256959998 ps |
CPU time | 77.78 seconds |
Started | Jul 28 06:54:54 PM PDT 24 |
Finished | Jul 28 06:56:12 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-7664a812-b28d-40dd-a3d6-cdda0e0acb7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393899000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.1393899000 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.3475838914 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 756168272 ps |
CPU time | 93.38 seconds |
Started | Jul 28 06:54:54 PM PDT 24 |
Finished | Jul 28 06:56:27 PM PDT 24 |
Peak memory | 354384 kb |
Host | smart-6fdfc0df-6263-4b32-9e4f-e6022010b7f1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475838914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.3475838914 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2424576452 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 4902377112 ps |
CPU time | 166.72 seconds |
Started | Jul 28 06:55:03 PM PDT 24 |
Finished | Jul 28 06:57:50 PM PDT 24 |
Peak memory | 219476 kb |
Host | smart-e9839cea-9e92-4861-9b7c-fa8ed6586455 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424576452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.2424576452 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.2725218225 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 14188051495 ps |
CPU time | 296.67 seconds |
Started | Jul 28 06:55:02 PM PDT 24 |
Finished | Jul 28 06:59:59 PM PDT 24 |
Peak memory | 211220 kb |
Host | smart-65da6e74-aa51-4ca4-a82c-a2a9c455009c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725218225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.2725218225 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.471959550 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 9403513745 ps |
CPU time | 702.83 seconds |
Started | Jul 28 06:54:49 PM PDT 24 |
Finished | Jul 28 07:06:33 PM PDT 24 |
Peak memory | 377980 kb |
Host | smart-516a7c62-8cd9-47d3-a6d2-a610f3643b66 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471959550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip le_keys.471959550 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.1945174076 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1715894872 ps |
CPU time | 25.85 seconds |
Started | Jul 28 06:54:50 PM PDT 24 |
Finished | Jul 28 06:55:16 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-901b66f7-0ab6-45fd-9b77-5e6a5db7ccf6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945174076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.1945174076 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.45426756 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 22762535769 ps |
CPU time | 285.51 seconds |
Started | Jul 28 06:54:55 PM PDT 24 |
Finished | Jul 28 06:59:40 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-edae4512-0d4f-413a-99e4-3529034d4d01 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45426756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_partial_access_b2b.45426756 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.3010684011 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 1295996859 ps |
CPU time | 3.31 seconds |
Started | Jul 28 06:54:59 PM PDT 24 |
Finished | Jul 28 06:55:03 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-31bf8ed5-29a1-4ecd-ba8b-f216e93ec8a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010684011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.3010684011 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.1058477101 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 2797515380 ps |
CPU time | 442.39 seconds |
Started | Jul 28 06:55:00 PM PDT 24 |
Finished | Jul 28 07:02:22 PM PDT 24 |
Peak memory | 353480 kb |
Host | smart-c28331fc-0d12-410e-9e6a-158c6c25e93f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058477101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1058477101 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.2360184799 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 4559457044 ps |
CPU time | 35.44 seconds |
Started | Jul 28 06:54:50 PM PDT 24 |
Finished | Jul 28 06:55:26 PM PDT 24 |
Peak memory | 289692 kb |
Host | smart-db93f32b-65b6-43c4-a8a0-d5f4fc96fc9a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360184799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2360184799 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.3071188152 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 441023317726 ps |
CPU time | 3426.64 seconds |
Started | Jul 28 06:54:59 PM PDT 24 |
Finished | Jul 28 07:52:06 PM PDT 24 |
Peak memory | 383244 kb |
Host | smart-1b03f45c-e3a8-4815-aa18-0ce862479bd7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071188152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.3071188152 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.609480828 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 2820115816 ps |
CPU time | 120.05 seconds |
Started | Jul 28 06:55:02 PM PDT 24 |
Finished | Jul 28 06:57:02 PM PDT 24 |
Peak memory | 216232 kb |
Host | smart-30c7c081-ed2c-468d-af8c-b50cab4b06bd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=609480828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.609480828 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3152686332 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 23823345880 ps |
CPU time | 357.23 seconds |
Started | Jul 28 06:54:51 PM PDT 24 |
Finished | Jul 28 07:00:48 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-dd0374b0-46ac-4b26-993b-b06c9c7126b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152686332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.3152686332 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2184867042 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 2901266249 ps |
CPU time | 13.32 seconds |
Started | Jul 28 06:54:54 PM PDT 24 |
Finished | Jul 28 06:55:08 PM PDT 24 |
Peak memory | 240272 kb |
Host | smart-e0e90177-d096-4592-bfc5-9f6ae8097963 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184867042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.2184867042 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.489227105 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 58318945797 ps |
CPU time | 1144.63 seconds |
Started | Jul 28 06:55:08 PM PDT 24 |
Finished | Jul 28 07:14:13 PM PDT 24 |
Peak memory | 378052 kb |
Host | smart-015adea7-fd9d-42d3-86d1-0f1133b637f3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489227105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_access_during_key_req.489227105 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.1602127792 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 13082049 ps |
CPU time | 0.65 seconds |
Started | Jul 28 06:55:15 PM PDT 24 |
Finished | Jul 28 06:55:15 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-87d45b4a-a402-4a51-8211-83892ea6b7dc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602127792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1602127792 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.2572415077 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 62685048038 ps |
CPU time | 1165.11 seconds |
Started | Jul 28 06:55:04 PM PDT 24 |
Finished | Jul 28 07:14:29 PM PDT 24 |
Peak memory | 203772 kb |
Host | smart-98b4a2c3-1627-46db-a7cc-e362f20466c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572415077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .2572415077 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.1869707248 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 28649852497 ps |
CPU time | 2400.38 seconds |
Started | Jul 28 06:55:09 PM PDT 24 |
Finished | Jul 28 07:35:09 PM PDT 24 |
Peak memory | 380080 kb |
Host | smart-5011bb90-7710-4fe0-89b1-7a1e9ff65303 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869707248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.1869707248 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.1004656863 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 8180055621 ps |
CPU time | 52.15 seconds |
Started | Jul 28 06:55:10 PM PDT 24 |
Finished | Jul 28 06:56:02 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-0c4b1565-9868-4fdc-a03d-f6b7003b41e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004656863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.1004656863 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.4169155050 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 3014472609 ps |
CPU time | 87.07 seconds |
Started | Jul 28 06:55:04 PM PDT 24 |
Finished | Jul 28 06:56:31 PM PDT 24 |
Peak memory | 357568 kb |
Host | smart-062e3ba8-5250-41e7-a727-3b4a38569d48 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169155050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.4169155050 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.21295501 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 2703913086 ps |
CPU time | 94.05 seconds |
Started | Jul 28 06:55:09 PM PDT 24 |
Finished | Jul 28 06:56:44 PM PDT 24 |
Peak memory | 219568 kb |
Host | smart-a262d484-4f47-4737-9562-cda6d991da87 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21295501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_mem_partial_access.21295501 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.4108090932 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 37429766904 ps |
CPU time | 177.62 seconds |
Started | Jul 28 06:55:09 PM PDT 24 |
Finished | Jul 28 06:58:07 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-8e4469f2-fd89-4d75-993d-e3937e058f19 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108090932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.4108090932 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.279193161 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 3754880445 ps |
CPU time | 131.84 seconds |
Started | Jul 28 06:55:02 PM PDT 24 |
Finished | Jul 28 06:57:14 PM PDT 24 |
Peak memory | 348084 kb |
Host | smart-8babe471-7914-4d04-b1db-103e40ebb8d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279193161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip le_keys.279193161 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.3733175313 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 792171596 ps |
CPU time | 10.43 seconds |
Started | Jul 28 06:55:06 PM PDT 24 |
Finished | Jul 28 06:55:16 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-786c3adb-8c22-4326-a43c-e994c1472970 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733175313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.3733175313 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3822959756 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 13391235450 ps |
CPU time | 270.77 seconds |
Started | Jul 28 06:55:05 PM PDT 24 |
Finished | Jul 28 06:59:35 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-fa255e24-ed62-4fe2-aca2-57676faff998 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822959756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.3822959756 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.3030165653 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 1408930942 ps |
CPU time | 3.44 seconds |
Started | Jul 28 06:55:10 PM PDT 24 |
Finished | Jul 28 06:55:14 PM PDT 24 |
Peak memory | 203064 kb |
Host | smart-4bab0463-f733-41f0-9f62-14fe806d76f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030165653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3030165653 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.1407135091 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 40266420064 ps |
CPU time | 704.18 seconds |
Started | Jul 28 06:55:09 PM PDT 24 |
Finished | Jul 28 07:06:53 PM PDT 24 |
Peak memory | 379004 kb |
Host | smart-2bf7f430-493d-41b3-ad2c-19ac8b6bd5be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407135091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1407135091 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.1517639821 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 2001479567 ps |
CPU time | 13.33 seconds |
Started | Jul 28 06:55:00 PM PDT 24 |
Finished | Jul 28 06:55:13 PM PDT 24 |
Peak memory | 232564 kb |
Host | smart-0f441335-07df-4ed3-9a2c-2b9d97682f1d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517639821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.1517639821 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.3515112532 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 43615211618 ps |
CPU time | 2408.67 seconds |
Started | Jul 28 06:55:14 PM PDT 24 |
Finished | Jul 28 07:35:23 PM PDT 24 |
Peak memory | 382220 kb |
Host | smart-948367a3-4a1a-45bd-9467-92743062f268 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515112532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.3515112532 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.953384945 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 273684630 ps |
CPU time | 9.01 seconds |
Started | Jul 28 06:55:15 PM PDT 24 |
Finished | Jul 28 06:55:24 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-5cafeb6d-86c1-42bd-baf5-4a9a864fe05f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=953384945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.953384945 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2270238548 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 4503329651 ps |
CPU time | 141.58 seconds |
Started | Jul 28 06:55:04 PM PDT 24 |
Finished | Jul 28 06:57:25 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-ffcd64db-aa9f-4ea2-84d2-ade4e854533f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270238548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.2270238548 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3769930037 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 719470774 ps |
CPU time | 11.6 seconds |
Started | Jul 28 06:55:04 PM PDT 24 |
Finished | Jul 28 06:55:15 PM PDT 24 |
Peak memory | 235872 kb |
Host | smart-23df2d02-dcd0-419e-b24a-3e397de9c16b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769930037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3769930037 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2539355548 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 18374516571 ps |
CPU time | 39.75 seconds |
Started | Jul 28 06:51:21 PM PDT 24 |
Finished | Jul 28 06:52:01 PM PDT 24 |
Peak memory | 258360 kb |
Host | smart-f9c2a9aa-a089-40f9-a7b5-b99da04469b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539355548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.2539355548 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.3624841404 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 175081325 ps |
CPU time | 0.66 seconds |
Started | Jul 28 06:51:26 PM PDT 24 |
Finished | Jul 28 06:51:27 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-e42eed8f-f975-4122-b698-05c4aa4a9358 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624841404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3624841404 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.4114764186 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 42065287859 ps |
CPU time | 794.7 seconds |
Started | Jul 28 06:51:18 PM PDT 24 |
Finished | Jul 28 07:04:33 PM PDT 24 |
Peak memory | 203880 kb |
Host | smart-1100cf08-f990-44fc-b2e1-e14ea6c26621 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114764186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 4114764186 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.1966429205 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 5512699881 ps |
CPU time | 400.72 seconds |
Started | Jul 28 06:51:26 PM PDT 24 |
Finished | Jul 28 06:58:07 PM PDT 24 |
Peak memory | 326264 kb |
Host | smart-f9bfe47b-bcd4-43b8-935c-bcb00ab9a393 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966429205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.1966429205 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.4136419451 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 3348595705 ps |
CPU time | 18.93 seconds |
Started | Jul 28 06:51:21 PM PDT 24 |
Finished | Jul 28 06:51:40 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-1d72e2d7-7afd-4aa1-9bed-5a853009ff1d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136419451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.4136419451 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.2614099527 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 739144860 ps |
CPU time | 18.57 seconds |
Started | Jul 28 06:51:16 PM PDT 24 |
Finished | Jul 28 06:51:35 PM PDT 24 |
Peak memory | 268524 kb |
Host | smart-1991efaf-9205-4761-b537-ce3c48330a2e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614099527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.2614099527 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.664623137 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 11221692332 ps |
CPU time | 82.31 seconds |
Started | Jul 28 06:51:26 PM PDT 24 |
Finished | Jul 28 06:52:48 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-ad6c2cd0-10f9-4d35-8bd4-36f1bd620e50 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664623137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. sram_ctrl_mem_partial_access.664623137 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.3722262786 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 43173737559 ps |
CPU time | 176.79 seconds |
Started | Jul 28 06:51:27 PM PDT 24 |
Finished | Jul 28 06:54:24 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-5ca9b728-54a0-440f-a100-56fc3121780c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722262786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.3722262786 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.212007073 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 15740644577 ps |
CPU time | 417.97 seconds |
Started | Jul 28 06:51:11 PM PDT 24 |
Finished | Jul 28 06:58:09 PM PDT 24 |
Peak memory | 350384 kb |
Host | smart-5b171dd0-963a-4c94-bce0-32388370fbe1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212007073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multipl e_keys.212007073 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.4241771164 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 486917992 ps |
CPU time | 10.65 seconds |
Started | Jul 28 06:51:16 PM PDT 24 |
Finished | Jul 28 06:51:26 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-fb533edc-ee83-4f3f-8d12-d1215c92b451 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241771164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.4241771164 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1674935928 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 18589180930 ps |
CPU time | 349.65 seconds |
Started | Jul 28 06:51:16 PM PDT 24 |
Finished | Jul 28 06:57:06 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-4dcecdea-f3be-40da-ade1-140dd97cfe4d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674935928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.1674935928 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.1411495633 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 344089565 ps |
CPU time | 3.14 seconds |
Started | Jul 28 06:51:24 PM PDT 24 |
Finished | Jul 28 06:51:28 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-ebf1b070-d669-42da-b7f4-62af270fed0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411495633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1411495633 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.4016664794 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 4363185328 ps |
CPU time | 1699.96 seconds |
Started | Jul 28 06:51:25 PM PDT 24 |
Finished | Jul 28 07:19:45 PM PDT 24 |
Peak memory | 380072 kb |
Host | smart-7572b0fc-ee5b-40fd-af66-b53615bc7b60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016664794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.4016664794 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.1674899505 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 342808857 ps |
CPU time | 2.7 seconds |
Started | Jul 28 06:51:26 PM PDT 24 |
Finished | Jul 28 06:51:29 PM PDT 24 |
Peak memory | 222492 kb |
Host | smart-c69caaa2-e496-44e6-9c1c-2605f97e2f38 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674899505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1674899505 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.2984744435 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 1511902875 ps |
CPU time | 8.1 seconds |
Started | Jul 28 06:51:11 PM PDT 24 |
Finished | Jul 28 06:51:19 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-fce8cdec-db20-4000-8623-03f27abf8095 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984744435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2984744435 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.914795693 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 679256857521 ps |
CPU time | 8869.86 seconds |
Started | Jul 28 06:51:25 PM PDT 24 |
Finished | Jul 28 09:19:16 PM PDT 24 |
Peak memory | 383176 kb |
Host | smart-5d7bb0f9-8632-4575-ba47-82c2ec263bd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914795693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_stress_all.914795693 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.417651053 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 1956507765 ps |
CPU time | 77.96 seconds |
Started | Jul 28 06:51:25 PM PDT 24 |
Finished | Jul 28 06:52:43 PM PDT 24 |
Peak memory | 212424 kb |
Host | smart-cc5ccb2f-6fcd-43a3-ba36-e4a6b0205294 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=417651053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.417651053 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3266939677 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 2348455173 ps |
CPU time | 162.47 seconds |
Started | Jul 28 06:51:16 PM PDT 24 |
Finished | Jul 28 06:53:58 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-bc85c070-edad-4070-8113-222ea2671ac5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266939677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.3266939677 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3385361076 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 5126175486 ps |
CPU time | 6.21 seconds |
Started | Jul 28 06:51:34 PM PDT 24 |
Finished | Jul 28 06:51:40 PM PDT 24 |
Peak memory | 211212 kb |
Host | smart-d27cfc73-4bcb-41d5-b013-df1c38440bef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385361076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3385361076 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1347346008 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 45836433709 ps |
CPU time | 897.24 seconds |
Started | Jul 28 06:55:27 PM PDT 24 |
Finished | Jul 28 07:10:24 PM PDT 24 |
Peak memory | 378024 kb |
Host | smart-616e8e7a-32b4-4b89-a8f1-2fb6e515d552 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347346008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.1347346008 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.1475109279 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 27482333 ps |
CPU time | 0.65 seconds |
Started | Jul 28 06:55:34 PM PDT 24 |
Finished | Jul 28 06:55:35 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-b6481892-ce8d-4433-9655-b9ce09d1f85a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475109279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1475109279 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.3119950996 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 17425814338 ps |
CPU time | 1192.21 seconds |
Started | Jul 28 06:55:19 PM PDT 24 |
Finished | Jul 28 07:15:12 PM PDT 24 |
Peak memory | 203984 kb |
Host | smart-d2a7ff09-f51e-48e9-b444-4107db00956f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119950996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .3119950996 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.3155831573 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 66537432519 ps |
CPU time | 847.04 seconds |
Started | Jul 28 06:55:22 PM PDT 24 |
Finished | Jul 28 07:09:30 PM PDT 24 |
Peak memory | 370912 kb |
Host | smart-c321d660-ce3e-4d7e-a485-1a4ad2b72975 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155831573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.3155831573 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.1285169952 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 3915906175 ps |
CPU time | 18.49 seconds |
Started | Jul 28 06:55:22 PM PDT 24 |
Finished | Jul 28 06:55:41 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-01c9b048-c7fb-4cb4-bfaf-999088fd8ba3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285169952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.1285169952 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.2201821650 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 4108095117 ps |
CPU time | 21.74 seconds |
Started | Jul 28 06:55:22 PM PDT 24 |
Finished | Jul 28 06:55:44 PM PDT 24 |
Peak memory | 258096 kb |
Host | smart-51ed6347-a16c-424e-aca9-513ff301e10c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201821650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.2201821650 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2124413215 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 3075966203 ps |
CPU time | 87.05 seconds |
Started | Jul 28 06:55:26 PM PDT 24 |
Finished | Jul 28 06:56:54 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-272124c8-3473-4e71-8227-015499504a50 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124413215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2124413215 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.3104220666 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 7080866954 ps |
CPU time | 156.95 seconds |
Started | Jul 28 06:55:26 PM PDT 24 |
Finished | Jul 28 06:58:03 PM PDT 24 |
Peak memory | 211336 kb |
Host | smart-004ca57e-ed59-4d8f-9399-cb1b010e865c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104220666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.3104220666 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.207281651 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 42722550805 ps |
CPU time | 1563.11 seconds |
Started | Jul 28 06:55:19 PM PDT 24 |
Finished | Jul 28 07:21:23 PM PDT 24 |
Peak memory | 377016 kb |
Host | smart-721035bf-73fe-44f7-9f48-50c43bdcb31e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207281651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip le_keys.207281651 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.1329280258 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 362111341 ps |
CPU time | 3.74 seconds |
Started | Jul 28 06:55:26 PM PDT 24 |
Finished | Jul 28 06:55:30 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-9acc43bb-ab1e-4ff6-ad03-0aa371cfb8a8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329280258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.1329280258 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2125090848 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 50895539916 ps |
CPU time | 306.32 seconds |
Started | Jul 28 06:55:27 PM PDT 24 |
Finished | Jul 28 07:00:33 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-bf022ea0-5744-451e-8de7-83bf6d637ace |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125090848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.2125090848 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.615236381 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 2798051586 ps |
CPU time | 3.65 seconds |
Started | Jul 28 06:55:27 PM PDT 24 |
Finished | Jul 28 06:55:30 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-bff398cf-97bf-4de6-aac2-44ecd43d8dae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615236381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.615236381 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.1495018056 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 54327641436 ps |
CPU time | 542.68 seconds |
Started | Jul 28 06:55:24 PM PDT 24 |
Finished | Jul 28 07:04:27 PM PDT 24 |
Peak memory | 368704 kb |
Host | smart-8f360020-c5ff-42d0-940c-05331f8f175d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495018056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1495018056 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.3883921545 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1967536182 ps |
CPU time | 17.11 seconds |
Started | Jul 28 06:55:15 PM PDT 24 |
Finished | Jul 28 06:55:32 PM PDT 24 |
Peak memory | 203056 kb |
Host | smart-88c230ca-87f7-4f6e-a2f0-16fa866eeb2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883921545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3883921545 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.24480455 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 316604051211 ps |
CPU time | 5547.7 seconds |
Started | Jul 28 06:55:28 PM PDT 24 |
Finished | Jul 28 08:27:56 PM PDT 24 |
Peak memory | 378100 kb |
Host | smart-d05348f6-29b2-4935-9e0e-cd7719a92343 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24480455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.sram_ctrl_stress_all.24480455 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2756405992 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 3604424362 ps |
CPU time | 23.58 seconds |
Started | Jul 28 06:55:29 PM PDT 24 |
Finished | Jul 28 06:55:53 PM PDT 24 |
Peak memory | 211556 kb |
Host | smart-55a673a8-5133-480e-bfad-b4003b6864eb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2756405992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.2756405992 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1592502089 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 19454831320 ps |
CPU time | 300.92 seconds |
Started | Jul 28 06:55:26 PM PDT 24 |
Finished | Jul 28 07:00:27 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-6185ef8c-5616-40a0-9112-c6db2d55f786 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592502089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.1592502089 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.769990890 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 814130574 ps |
CPU time | 84.04 seconds |
Started | Jul 28 06:55:25 PM PDT 24 |
Finished | Jul 28 06:56:49 PM PDT 24 |
Peak memory | 324776 kb |
Host | smart-ce6139d9-6e4d-439e-ae67-961c8ec34f3b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769990890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.769990890 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.322946425 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 24087556059 ps |
CPU time | 650.49 seconds |
Started | Jul 28 06:55:35 PM PDT 24 |
Finished | Jul 28 07:06:26 PM PDT 24 |
Peak memory | 378996 kb |
Host | smart-3736dc22-19ca-406f-bbe5-2ab395ceb4a0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322946425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 21.sram_ctrl_access_during_key_req.322946425 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.2067704043 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 17276207 ps |
CPU time | 0.66 seconds |
Started | Jul 28 06:55:41 PM PDT 24 |
Finished | Jul 28 06:55:42 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-35588a45-be3d-4a5c-aa5e-49a729727f79 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067704043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2067704043 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.2360109260 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 103700057733 ps |
CPU time | 1719.87 seconds |
Started | Jul 28 06:55:33 PM PDT 24 |
Finished | Jul 28 07:24:13 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-5d7c46d3-4044-45bb-89e2-a609f5960170 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360109260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .2360109260 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.226936498 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 26542973896 ps |
CPU time | 1915.86 seconds |
Started | Jul 28 06:55:37 PM PDT 24 |
Finished | Jul 28 07:27:33 PM PDT 24 |
Peak memory | 379052 kb |
Host | smart-b7742207-dd1d-47ae-bad4-d8833dad5304 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226936498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executabl e.226936498 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.1367485450 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 21771700911 ps |
CPU time | 29.46 seconds |
Started | Jul 28 06:55:36 PM PDT 24 |
Finished | Jul 28 06:56:05 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-46dbbdac-e224-46d3-82db-abebb0649379 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367485450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.1367485450 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.1098953297 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 749117113 ps |
CPU time | 55.5 seconds |
Started | Jul 28 06:55:35 PM PDT 24 |
Finished | Jul 28 06:56:31 PM PDT 24 |
Peak memory | 319584 kb |
Host | smart-2a260a15-6f2f-41df-8869-a64257e564eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098953297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.1098953297 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2278499750 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 2484588259 ps |
CPU time | 75.65 seconds |
Started | Jul 28 06:55:43 PM PDT 24 |
Finished | Jul 28 06:56:59 PM PDT 24 |
Peak memory | 211272 kb |
Host | smart-972e7745-1bc8-4f81-99c2-3fbeb9f8022b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278499750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.2278499750 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.1462759902 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 39395812464 ps |
CPU time | 275.89 seconds |
Started | Jul 28 06:55:41 PM PDT 24 |
Finished | Jul 28 07:00:18 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-72a59cd1-8692-4467-b0ae-f131703c26df |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462759902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.1462759902 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.1937457955 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 38116097020 ps |
CPU time | 743.66 seconds |
Started | Jul 28 06:55:33 PM PDT 24 |
Finished | Jul 28 07:07:57 PM PDT 24 |
Peak memory | 379860 kb |
Host | smart-0616ea21-7377-40da-bf0f-47bace563d8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937457955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.1937457955 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.692580650 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 2912774809 ps |
CPU time | 7.27 seconds |
Started | Jul 28 06:55:32 PM PDT 24 |
Finished | Jul 28 06:55:39 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-1175a4df-feb6-4c80-b1df-4945352da1e5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692580650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.s ram_ctrl_partial_access.692580650 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3562727358 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 4909694316 ps |
CPU time | 291.21 seconds |
Started | Jul 28 06:55:33 PM PDT 24 |
Finished | Jul 28 07:00:25 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-09415fca-e0b9-4fe9-9fa5-398c8709e57e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562727358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.3562727358 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.246075520 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 368633147 ps |
CPU time | 3.51 seconds |
Started | Jul 28 06:55:36 PM PDT 24 |
Finished | Jul 28 06:55:39 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-7427d381-c919-4e23-8820-c7d7cf931e82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246075520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.246075520 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.351679170 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 7507411656 ps |
CPU time | 593.7 seconds |
Started | Jul 28 06:55:38 PM PDT 24 |
Finished | Jul 28 07:05:32 PM PDT 24 |
Peak memory | 373064 kb |
Host | smart-50f5c708-f6b9-4454-851c-f35a77a56a99 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351679170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.351679170 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.2339574776 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 701603721 ps |
CPU time | 15.33 seconds |
Started | Jul 28 06:55:33 PM PDT 24 |
Finished | Jul 28 06:55:49 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-b182c070-2173-4b41-ac4d-d964432def1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339574776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2339574776 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.907961796 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 275233042069 ps |
CPU time | 5447.92 seconds |
Started | Jul 28 06:55:43 PM PDT 24 |
Finished | Jul 28 08:26:32 PM PDT 24 |
Peak memory | 381096 kb |
Host | smart-0e3a2fbe-73f1-460c-85ce-3c489daa336c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907961796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_stress_all.907961796 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2103411541 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 731281312 ps |
CPU time | 18.28 seconds |
Started | Jul 28 06:55:43 PM PDT 24 |
Finished | Jul 28 06:56:02 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-4d5dffb5-18aa-4374-abfd-7ef68a123dae |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2103411541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2103411541 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.4091265846 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 3523781229 ps |
CPU time | 193.02 seconds |
Started | Jul 28 06:55:33 PM PDT 24 |
Finished | Jul 28 06:58:46 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-a5cdf39f-c2c2-4085-aab6-c6dc147bb77c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091265846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.4091265846 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1353240886 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 1405655265 ps |
CPU time | 96.3 seconds |
Started | Jul 28 06:55:35 PM PDT 24 |
Finished | Jul 28 06:57:11 PM PDT 24 |
Peak memory | 350328 kb |
Host | smart-1253282f-aade-45f7-8ea3-5f71a11c94ac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353240886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.1353240886 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3106117255 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 9862297095 ps |
CPU time | 972.35 seconds |
Started | Jul 28 06:55:52 PM PDT 24 |
Finished | Jul 28 07:12:05 PM PDT 24 |
Peak memory | 379024 kb |
Host | smart-4482574f-4471-44ae-85cb-de4bb0121814 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106117255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.3106117255 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.2307411866 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 120513258 ps |
CPU time | 0.69 seconds |
Started | Jul 28 06:55:57 PM PDT 24 |
Finished | Jul 28 06:55:58 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-a721177b-460e-41b8-a21f-3bf6222e2e3b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307411866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.2307411866 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.3915789630 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 601515633171 ps |
CPU time | 843.16 seconds |
Started | Jul 28 06:55:43 PM PDT 24 |
Finished | Jul 28 07:09:46 PM PDT 24 |
Peak memory | 203776 kb |
Host | smart-de6b5533-9c7c-404d-b8a0-05902ccd1875 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915789630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .3915789630 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.369897156 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 32348252495 ps |
CPU time | 883.24 seconds |
Started | Jul 28 06:55:52 PM PDT 24 |
Finished | Jul 28 07:10:36 PM PDT 24 |
Peak memory | 379012 kb |
Host | smart-d8f8a188-a576-41f8-9e4c-12c05e2bf1fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369897156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl e.369897156 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.3573416490 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 21001709937 ps |
CPU time | 34.29 seconds |
Started | Jul 28 06:55:52 PM PDT 24 |
Finished | Jul 28 06:56:27 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-a3c7b7ea-859d-48d5-8e0b-6359b852e96a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573416490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.3573416490 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.1261576474 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 754250463 ps |
CPU time | 97.99 seconds |
Started | Jul 28 06:55:47 PM PDT 24 |
Finished | Jul 28 06:57:25 PM PDT 24 |
Peak memory | 342128 kb |
Host | smart-44dcf3df-43de-4834-aca6-e64ef106877a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261576474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.1261576474 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3258453911 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 4838723892 ps |
CPU time | 75.79 seconds |
Started | Jul 28 06:55:53 PM PDT 24 |
Finished | Jul 28 06:57:09 PM PDT 24 |
Peak memory | 219552 kb |
Host | smart-5c372374-df4d-43bc-a615-bdf390a5f6d6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258453911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.3258453911 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.3998123094 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 14553630947 ps |
CPU time | 301.85 seconds |
Started | Jul 28 06:55:55 PM PDT 24 |
Finished | Jul 28 07:00:57 PM PDT 24 |
Peak memory | 211324 kb |
Host | smart-c2a625f4-06c0-4d8f-9a93-2f30f201b9aa |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998123094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.3998123094 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.3090190748 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 144892695224 ps |
CPU time | 1317.1 seconds |
Started | Jul 28 06:55:41 PM PDT 24 |
Finished | Jul 28 07:17:39 PM PDT 24 |
Peak memory | 381044 kb |
Host | smart-49df5f7d-cf30-4aca-a6d2-55a85106434a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090190748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.3090190748 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.1357722092 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 2058626763 ps |
CPU time | 86.63 seconds |
Started | Jul 28 06:55:46 PM PDT 24 |
Finished | Jul 28 06:57:13 PM PDT 24 |
Peak memory | 362456 kb |
Host | smart-f9bf3c51-986e-4c9b-bef5-2663ec2220e9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357722092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.1357722092 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1038335715 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 58093287982 ps |
CPU time | 292.4 seconds |
Started | Jul 28 06:55:46 PM PDT 24 |
Finished | Jul 28 07:00:39 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-45319ee5-6c49-4a81-ad98-b81eb4d0ff84 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038335715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.1038335715 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.2836679359 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 360428501 ps |
CPU time | 3.56 seconds |
Started | Jul 28 06:55:53 PM PDT 24 |
Finished | Jul 28 06:55:57 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-3fc54e96-d94d-4cff-9c98-b82c429178e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836679359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2836679359 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.2302665964 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 2033983431 ps |
CPU time | 867.69 seconds |
Started | Jul 28 06:55:52 PM PDT 24 |
Finished | Jul 28 07:10:20 PM PDT 24 |
Peak memory | 370792 kb |
Host | smart-91ea0ade-7421-4fe5-8cd7-4df30f119434 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302665964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2302665964 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.2946139402 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 1892667099 ps |
CPU time | 5.8 seconds |
Started | Jul 28 06:55:43 PM PDT 24 |
Finished | Jul 28 06:55:50 PM PDT 24 |
Peak memory | 203008 kb |
Host | smart-2d3b0169-c1ce-47b8-b351-e928b15e70af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946139402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2946139402 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.3668039410 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 63843249475 ps |
CPU time | 4103.85 seconds |
Started | Jul 28 06:55:57 PM PDT 24 |
Finished | Jul 28 08:04:22 PM PDT 24 |
Peak memory | 383224 kb |
Host | smart-58713c6d-13c8-4704-8ad3-ba75736c4592 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668039410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.3668039410 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2478471601 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 1165490686 ps |
CPU time | 20 seconds |
Started | Jul 28 06:55:58 PM PDT 24 |
Finished | Jul 28 06:56:18 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-6e44dd1a-f706-4df7-8608-5ab034fa319e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2478471601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2478471601 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2692043588 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 4705542307 ps |
CPU time | 296.75 seconds |
Started | Jul 28 06:55:47 PM PDT 24 |
Finished | Jul 28 07:00:44 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-9750efb4-a755-44e6-bc60-bde2d53a6578 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692043588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.2692043588 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.27825974 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 3273452195 ps |
CPU time | 115.97 seconds |
Started | Jul 28 06:55:53 PM PDT 24 |
Finished | Jul 28 06:57:49 PM PDT 24 |
Peak memory | 372084 kb |
Host | smart-c36cc248-6aba-4b3b-beaf-e217123ff851 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27825974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.sram_ctrl_throughput_w_partial_write.27825974 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2952936507 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 59054683978 ps |
CPU time | 1211.97 seconds |
Started | Jul 28 06:56:01 PM PDT 24 |
Finished | Jul 28 07:16:14 PM PDT 24 |
Peak memory | 380044 kb |
Host | smart-d6f248f2-6512-472b-9f41-13d26ca01dd6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952936507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.2952936507 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.3857184522 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 27007463 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:56:06 PM PDT 24 |
Finished | Jul 28 06:56:07 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-d7db7f92-ccae-40f9-a17e-a44737bf8861 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857184522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3857184522 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.1776533055 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 32801030135 ps |
CPU time | 1127.55 seconds |
Started | Jul 28 06:55:57 PM PDT 24 |
Finished | Jul 28 07:14:45 PM PDT 24 |
Peak memory | 203796 kb |
Host | smart-19e31d3f-51b1-4db5-a73f-850ee9292095 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776533055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .1776533055 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.2753870257 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 4772812339 ps |
CPU time | 443.57 seconds |
Started | Jul 28 06:56:06 PM PDT 24 |
Finished | Jul 28 07:03:30 PM PDT 24 |
Peak memory | 352480 kb |
Host | smart-9aeb143f-9a06-486e-a7e4-9290b3fddeb6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753870257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.2753870257 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.1230736885 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 10821348347 ps |
CPU time | 63.82 seconds |
Started | Jul 28 06:56:03 PM PDT 24 |
Finished | Jul 28 06:57:07 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-4216fea7-1757-4eb7-ab7b-cb2a33068125 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230736885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.1230736885 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.3316628696 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 716368260 ps |
CPU time | 13.02 seconds |
Started | Jul 28 06:56:03 PM PDT 24 |
Finished | Jul 28 06:56:16 PM PDT 24 |
Peak memory | 242808 kb |
Host | smart-318024a6-6fb7-4971-ae4d-62620e13f2ca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316628696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.3316628696 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2032300153 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 12120706741 ps |
CPU time | 166.72 seconds |
Started | Jul 28 06:56:07 PM PDT 24 |
Finished | Jul 28 06:58:54 PM PDT 24 |
Peak memory | 219720 kb |
Host | smart-85761fb3-256e-4daa-84ec-c500207351e6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032300153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.2032300153 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.2568149545 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 35002516338 ps |
CPU time | 288.44 seconds |
Started | Jul 28 06:56:06 PM PDT 24 |
Finished | Jul 28 07:00:55 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-29438dc6-c1e7-41ba-b2af-1c2b89668b9b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568149545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.2568149545 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.1359883761 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 15579438618 ps |
CPU time | 263.74 seconds |
Started | Jul 28 06:55:56 PM PDT 24 |
Finished | Jul 28 07:00:19 PM PDT 24 |
Peak memory | 373040 kb |
Host | smart-191fa33d-c14e-4160-ab8b-82916439d9b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359883761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.1359883761 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.3739823128 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 1634596127 ps |
CPU time | 25.15 seconds |
Started | Jul 28 06:55:57 PM PDT 24 |
Finished | Jul 28 06:56:22 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-fc922b57-fc0f-4186-82bc-a868a70b5885 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739823128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.3739823128 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2653370674 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 60874305601 ps |
CPU time | 374.43 seconds |
Started | Jul 28 06:55:57 PM PDT 24 |
Finished | Jul 28 07:02:11 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-4a8f8d50-78b1-4a9c-bbb1-08c567de8624 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653370674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.2653370674 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.907559272 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 1057893988 ps |
CPU time | 3.08 seconds |
Started | Jul 28 06:56:06 PM PDT 24 |
Finished | Jul 28 06:56:09 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-754e96a8-059b-4ed1-a868-e03526908c59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907559272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.907559272 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.2647322938 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 118293934059 ps |
CPU time | 935.37 seconds |
Started | Jul 28 06:56:07 PM PDT 24 |
Finished | Jul 28 07:11:43 PM PDT 24 |
Peak memory | 380048 kb |
Host | smart-58ca4d97-026d-4fb1-81c1-5094d4e73eb6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647322938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2647322938 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.3757058827 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 712470628 ps |
CPU time | 13.18 seconds |
Started | Jul 28 06:55:58 PM PDT 24 |
Finished | Jul 28 06:56:11 PM PDT 24 |
Peak memory | 241520 kb |
Host | smart-cbf52782-fa46-434c-a3bc-f012b102f1ca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757058827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3757058827 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.204955153 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 25149962322 ps |
CPU time | 1434.71 seconds |
Started | Jul 28 06:56:06 PM PDT 24 |
Finished | Jul 28 07:20:01 PM PDT 24 |
Peak memory | 367700 kb |
Host | smart-6b76e11a-0b9b-46db-9ad7-10cbf00d294b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204955153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_stress_all.204955153 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1390015814 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 1493733960 ps |
CPU time | 45.9 seconds |
Started | Jul 28 06:56:07 PM PDT 24 |
Finished | Jul 28 06:56:53 PM PDT 24 |
Peak memory | 246432 kb |
Host | smart-648d23aa-441f-4ad6-b1a9-fc43741b9309 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1390015814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1390015814 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3621079832 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 5588528356 ps |
CPU time | 365.85 seconds |
Started | Jul 28 06:55:58 PM PDT 24 |
Finished | Jul 28 07:02:04 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-f2304b26-b2c9-402e-9556-74691d5ace31 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621079832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3621079832 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1132759325 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 1579889739 ps |
CPU time | 99.19 seconds |
Started | Jul 28 06:56:03 PM PDT 24 |
Finished | Jul 28 06:57:42 PM PDT 24 |
Peak memory | 357016 kb |
Host | smart-ba5e2c29-f457-47e1-8776-ddb1a8ac1cb5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132759325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1132759325 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.575862795 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 11315924392 ps |
CPU time | 872.27 seconds |
Started | Jul 28 06:56:16 PM PDT 24 |
Finished | Jul 28 07:10:49 PM PDT 24 |
Peak memory | 380084 kb |
Host | smart-8d9216cb-9215-4a0f-b5bf-468dc041c431 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575862795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 24.sram_ctrl_access_during_key_req.575862795 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.728200126 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 15277629 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:56:22 PM PDT 24 |
Finished | Jul 28 06:56:23 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-ea2033bd-7715-4850-abce-95a46f61e5f6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728200126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.728200126 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.3060727998 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 112740979449 ps |
CPU time | 2654.68 seconds |
Started | Jul 28 06:56:12 PM PDT 24 |
Finished | Jul 28 07:40:27 PM PDT 24 |
Peak memory | 203988 kb |
Host | smart-e1b07e65-13aa-4394-b9a6-5c7fc2b56a09 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060727998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .3060727998 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.3443469485 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 173780915962 ps |
CPU time | 1211.04 seconds |
Started | Jul 28 06:56:16 PM PDT 24 |
Finished | Jul 28 07:16:27 PM PDT 24 |
Peak memory | 380016 kb |
Host | smart-9c8347e2-7f44-4049-9dd3-2a94f5ea2ccd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443469485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.3443469485 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.963118403 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 136455839528 ps |
CPU time | 78.25 seconds |
Started | Jul 28 06:56:16 PM PDT 24 |
Finished | Jul 28 06:57:35 PM PDT 24 |
Peak memory | 211344 kb |
Host | smart-7e4ff453-fa7c-48c9-b078-e5695da1d917 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963118403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esc alation.963118403 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.570817848 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 2949133977 ps |
CPU time | 28.28 seconds |
Started | Jul 28 06:56:16 PM PDT 24 |
Finished | Jul 28 06:56:44 PM PDT 24 |
Peak memory | 268696 kb |
Host | smart-ed78ba9c-8cf3-4c1f-84ee-28c73755d18a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570817848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.sram_ctrl_max_throughput.570817848 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3737354533 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 5005525113 ps |
CPU time | 154.81 seconds |
Started | Jul 28 06:56:21 PM PDT 24 |
Finished | Jul 28 06:58:56 PM PDT 24 |
Peak memory | 211592 kb |
Host | smart-bf833741-e97b-4e94-96a1-3e56be11775e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737354533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.3737354533 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.1131974578 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 7212796245 ps |
CPU time | 162.8 seconds |
Started | Jul 28 06:56:17 PM PDT 24 |
Finished | Jul 28 06:59:00 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-f6a5e4c7-72b7-49fc-8478-2ba398d71b83 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131974578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.1131974578 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.1046496521 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 44761825289 ps |
CPU time | 1129.99 seconds |
Started | Jul 28 06:56:12 PM PDT 24 |
Finished | Jul 28 07:15:02 PM PDT 24 |
Peak memory | 381088 kb |
Host | smart-4dc8c547-c004-4226-a37f-91a4b465301f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046496521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.1046496521 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.1303247344 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 3950016676 ps |
CPU time | 151.44 seconds |
Started | Jul 28 06:56:11 PM PDT 24 |
Finished | Jul 28 06:58:43 PM PDT 24 |
Peak memory | 367748 kb |
Host | smart-1495afbe-79bb-4950-997e-3371a3bd6ac7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303247344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.1303247344 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2673245440 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 14194034372 ps |
CPU time | 226.44 seconds |
Started | Jul 28 06:56:13 PM PDT 24 |
Finished | Jul 28 07:00:00 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-9ae7653c-497f-4be9-823a-3be41b6c1ffb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673245440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.2673245440 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.4206790977 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 3724489887 ps |
CPU time | 3.94 seconds |
Started | Jul 28 06:56:16 PM PDT 24 |
Finished | Jul 28 06:56:20 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-902ff2e1-b7c6-450f-bd14-f8e75f8fdadb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206790977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.4206790977 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.3468595383 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 3478924131 ps |
CPU time | 59.84 seconds |
Started | Jul 28 06:56:17 PM PDT 24 |
Finished | Jul 28 06:57:17 PM PDT 24 |
Peak memory | 230000 kb |
Host | smart-e1e35345-e9cf-446f-aefd-97af7aff8584 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468595383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3468595383 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.1341871859 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 807009236 ps |
CPU time | 12.85 seconds |
Started | Jul 28 06:56:12 PM PDT 24 |
Finished | Jul 28 06:56:25 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-ad378c3b-873c-4892-97dc-a832c9ee143e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341871859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1341871859 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.3890545467 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 230706336245 ps |
CPU time | 5750.03 seconds |
Started | Jul 28 06:56:21 PM PDT 24 |
Finished | Jul 28 08:32:12 PM PDT 24 |
Peak memory | 381320 kb |
Host | smart-4b188096-11fa-4d83-beaf-bb52d8ce6a91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890545467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.3890545467 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1173794531 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 1408239702 ps |
CPU time | 26.48 seconds |
Started | Jul 28 06:56:22 PM PDT 24 |
Finished | Jul 28 06:56:48 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-e34994e1-0c6f-4d9d-ae65-6a3e39044159 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1173794531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.1173794531 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3581936812 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 16608198164 ps |
CPU time | 218.76 seconds |
Started | Jul 28 06:56:13 PM PDT 24 |
Finished | Jul 28 06:59:51 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-53362aa5-a33b-4635-b718-652514746edf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581936812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.3581936812 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2249550311 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 5872887111 ps |
CPU time | 18.22 seconds |
Started | Jul 28 06:56:16 PM PDT 24 |
Finished | Jul 28 06:56:35 PM PDT 24 |
Peak memory | 255304 kb |
Host | smart-2cdfd013-2912-4a0f-86b4-3bd837ee8a33 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249550311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.2249550311 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.4178196884 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 29697778687 ps |
CPU time | 1053.55 seconds |
Started | Jul 28 06:56:34 PM PDT 24 |
Finished | Jul 28 07:14:07 PM PDT 24 |
Peak memory | 374048 kb |
Host | smart-8dca4f44-09a4-4791-b7de-a4ae76e2e512 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178196884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.4178196884 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.84109605 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 55146309 ps |
CPU time | 0.65 seconds |
Started | Jul 28 06:56:37 PM PDT 24 |
Finished | Jul 28 06:56:38 PM PDT 24 |
Peak memory | 202612 kb |
Host | smart-739b5080-ee2c-40b4-9bf3-58eb637f3623 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84109605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_alert_test.84109605 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.3739811185 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 8299619190 ps |
CPU time | 547.84 seconds |
Started | Jul 28 06:56:28 PM PDT 24 |
Finished | Jul 28 07:05:36 PM PDT 24 |
Peak memory | 203944 kb |
Host | smart-4ee23e4b-3272-4685-acbe-1d5613e40e1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739811185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .3739811185 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.4138793368 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 44261377807 ps |
CPU time | 1417.93 seconds |
Started | Jul 28 06:56:32 PM PDT 24 |
Finished | Jul 28 07:20:10 PM PDT 24 |
Peak memory | 380180 kb |
Host | smart-72337923-148a-4e63-bda9-13764d76c3c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138793368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.4138793368 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.1777702478 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 21553924572 ps |
CPU time | 66.13 seconds |
Started | Jul 28 06:56:33 PM PDT 24 |
Finished | Jul 28 06:57:39 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-819b2326-b680-4778-bca2-1be59776f33f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777702478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.1777702478 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.1305060934 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 786664280 ps |
CPU time | 85.03 seconds |
Started | Jul 28 06:56:28 PM PDT 24 |
Finished | Jul 28 06:57:53 PM PDT 24 |
Peak memory | 348180 kb |
Host | smart-01a461f7-8bf7-4336-acde-5e6608b621cb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305060934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.1305060934 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1983826421 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 4447630356 ps |
CPU time | 147.22 seconds |
Started | Jul 28 06:56:33 PM PDT 24 |
Finished | Jul 28 06:59:00 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-7d6f7b62-8efc-496d-a442-7b53538e6fe9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983826421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.1983826421 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.4164489873 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 14429030638 ps |
CPU time | 299.91 seconds |
Started | Jul 28 06:56:33 PM PDT 24 |
Finished | Jul 28 07:01:33 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-62d2cb41-6c8c-4b0a-8512-14c1b4d6f25e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164489873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.4164489873 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.2017652659 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 25927599729 ps |
CPU time | 1683.98 seconds |
Started | Jul 28 06:56:21 PM PDT 24 |
Finished | Jul 28 07:24:25 PM PDT 24 |
Peak memory | 376956 kb |
Host | smart-026e4058-2aa3-4d91-9f8c-f82e3d8680cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017652659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.2017652659 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.327708634 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 9904714757 ps |
CPU time | 12.4 seconds |
Started | Jul 28 06:56:25 PM PDT 24 |
Finished | Jul 28 06:56:38 PM PDT 24 |
Peak memory | 238032 kb |
Host | smart-9c02a559-d3cc-4712-80a0-4af297b69872 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327708634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s ram_ctrl_partial_access.327708634 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3234596595 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 14498951110 ps |
CPU time | 300.81 seconds |
Started | Jul 28 06:56:25 PM PDT 24 |
Finished | Jul 28 07:01:26 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-71745372-c763-4644-b0da-2d97e7148d8c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234596595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3234596595 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.30969336 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 2385094688 ps |
CPU time | 3.79 seconds |
Started | Jul 28 06:56:34 PM PDT 24 |
Finished | Jul 28 06:56:38 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-bdc2cdf1-e574-45ef-b690-bf109571b09e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.30969336 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.3464650709 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 17045773932 ps |
CPU time | 1007.01 seconds |
Started | Jul 28 06:56:34 PM PDT 24 |
Finished | Jul 28 07:13:21 PM PDT 24 |
Peak memory | 380048 kb |
Host | smart-481b6701-ca46-4e57-9299-aab3e928e4aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464650709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3464650709 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.3356654703 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 601668251 ps |
CPU time | 9.85 seconds |
Started | Jul 28 06:56:21 PM PDT 24 |
Finished | Jul 28 06:56:31 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-06f17c7b-5046-4a86-8234-4bece2472b20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356654703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3356654703 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.2876738630 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 501173534445 ps |
CPU time | 7762.12 seconds |
Started | Jul 28 06:56:38 PM PDT 24 |
Finished | Jul 28 09:06:01 PM PDT 24 |
Peak memory | 381156 kb |
Host | smart-8d8c7214-9530-4569-a09a-9476e1bc5ce9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876738630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.2876738630 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3696826506 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 1767549326 ps |
CPU time | 15.35 seconds |
Started | Jul 28 06:56:37 PM PDT 24 |
Finished | Jul 28 06:56:53 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-14c699dd-2ea4-4ec1-af8b-7233f89624fc |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3696826506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3696826506 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.611750378 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 14673141229 ps |
CPU time | 244.93 seconds |
Started | Jul 28 06:56:26 PM PDT 24 |
Finished | Jul 28 07:00:31 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-f8af8c43-f36b-4996-8872-4a49223959f1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611750378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_stress_pipeline.611750378 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1668031709 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 1631919590 ps |
CPU time | 119.64 seconds |
Started | Jul 28 06:56:26 PM PDT 24 |
Finished | Jul 28 06:58:26 PM PDT 24 |
Peak memory | 372804 kb |
Host | smart-143ac811-b501-456f-a18c-d3addee8ca60 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668031709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1668031709 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1089209551 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 25952270264 ps |
CPU time | 941.98 seconds |
Started | Jul 28 06:56:41 PM PDT 24 |
Finished | Jul 28 07:12:24 PM PDT 24 |
Peak memory | 366780 kb |
Host | smart-224613aa-a2df-4526-b4f5-d3cac8500115 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089209551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.1089209551 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.2275718569 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 41535091 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:56:51 PM PDT 24 |
Finished | Jul 28 06:56:52 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-528adae7-7087-4031-9fca-ea0d267d441e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275718569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2275718569 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.2440132895 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 882018413592 ps |
CPU time | 2625.23 seconds |
Started | Jul 28 06:56:37 PM PDT 24 |
Finished | Jul 28 07:40:22 PM PDT 24 |
Peak memory | 204220 kb |
Host | smart-a40cbc17-6dde-4d4f-a374-7710cfc428fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440132895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .2440132895 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.3740253378 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 196813792176 ps |
CPU time | 798.63 seconds |
Started | Jul 28 06:56:44 PM PDT 24 |
Finished | Jul 28 07:10:03 PM PDT 24 |
Peak memory | 379056 kb |
Host | smart-0ec9b7a4-9c6d-43fc-aa6b-8742a4d13fd0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740253378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.3740253378 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.371404282 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 5786194333 ps |
CPU time | 38.08 seconds |
Started | Jul 28 06:56:42 PM PDT 24 |
Finished | Jul 28 06:57:20 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-6afeb099-6276-486e-a6a2-0622a3cbd65a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371404282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esc alation.371404282 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.4107257521 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 1535806018 ps |
CPU time | 109.81 seconds |
Started | Jul 28 06:56:43 PM PDT 24 |
Finished | Jul 28 06:58:33 PM PDT 24 |
Peak memory | 346152 kb |
Host | smart-2e335b9e-c89a-43bf-8eb8-0228029e7049 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107257521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.4107257521 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2097436462 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 25761403412 ps |
CPU time | 156.42 seconds |
Started | Jul 28 06:56:46 PM PDT 24 |
Finished | Jul 28 06:59:23 PM PDT 24 |
Peak memory | 219492 kb |
Host | smart-6a5789fc-d674-4712-a0a6-3d32468bede8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097436462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.2097436462 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.2820655561 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 28815684003 ps |
CPU time | 171.96 seconds |
Started | Jul 28 06:56:52 PM PDT 24 |
Finished | Jul 28 06:59:44 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-1dd1e49c-c77d-40c4-a8d7-8fe395c7e231 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820655561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.2820655561 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.329815209 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 12506170662 ps |
CPU time | 555.01 seconds |
Started | Jul 28 06:56:38 PM PDT 24 |
Finished | Jul 28 07:05:53 PM PDT 24 |
Peak memory | 371320 kb |
Host | smart-6b40a0bf-986e-4cbd-8d0e-84543b0ed7bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329815209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip le_keys.329815209 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.2664386939 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 2683744717 ps |
CPU time | 17.09 seconds |
Started | Jul 28 06:56:38 PM PDT 24 |
Finished | Jul 28 06:56:55 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-e4c8a43c-f051-46aa-832b-cb17ae35f642 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664386939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.2664386939 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2797702074 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 17947147805 ps |
CPU time | 453.89 seconds |
Started | Jul 28 06:56:43 PM PDT 24 |
Finished | Jul 28 07:04:17 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-905a2334-4c5c-49a9-bc3e-ed49837ac489 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797702074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.2797702074 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.3773796725 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 708389392 ps |
CPU time | 3.5 seconds |
Started | Jul 28 06:56:46 PM PDT 24 |
Finished | Jul 28 06:56:50 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-54a73b13-bd7d-4de2-bbf5-83318676fa27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773796725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3773796725 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.4072861844 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 8836423459 ps |
CPU time | 150.65 seconds |
Started | Jul 28 06:56:42 PM PDT 24 |
Finished | Jul 28 06:59:13 PM PDT 24 |
Peak memory | 376852 kb |
Host | smart-23781614-84e4-49c8-b875-f1e99721e007 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072861844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.4072861844 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.1075911291 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 953105053 ps |
CPU time | 12.59 seconds |
Started | Jul 28 06:56:37 PM PDT 24 |
Finished | Jul 28 06:56:50 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-ebada795-9b52-42e2-adba-1e5293e08b2b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075911291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1075911291 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.137936859 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 204139194682 ps |
CPU time | 5120.01 seconds |
Started | Jul 28 06:56:52 PM PDT 24 |
Finished | Jul 28 08:22:12 PM PDT 24 |
Peak memory | 389316 kb |
Host | smart-505ce738-5fc3-4f12-9122-f7a307f67742 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137936859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_stress_all.137936859 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1419549121 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 3882096906 ps |
CPU time | 15.64 seconds |
Started | Jul 28 06:56:46 PM PDT 24 |
Finished | Jul 28 06:57:02 PM PDT 24 |
Peak memory | 211496 kb |
Host | smart-e564a635-dec0-4c1c-8937-1b324ff583c5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1419549121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1419549121 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2793020185 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 11772980355 ps |
CPU time | 232.68 seconds |
Started | Jul 28 06:56:37 PM PDT 24 |
Finished | Jul 28 07:00:30 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-e3c6ef3e-5808-403f-bb32-7476f9e4c45a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793020185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.2793020185 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.976536002 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 786662360 ps |
CPU time | 123.31 seconds |
Started | Jul 28 06:56:42 PM PDT 24 |
Finished | Jul 28 06:58:46 PM PDT 24 |
Peak memory | 372744 kb |
Host | smart-ea555630-cf3a-4d66-9c1b-888515f78fc2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976536002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.976536002 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.4236076627 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 25201939297 ps |
CPU time | 804.58 seconds |
Started | Jul 28 06:56:59 PM PDT 24 |
Finished | Jul 28 07:10:24 PM PDT 24 |
Peak memory | 360620 kb |
Host | smart-4437976b-eabd-4ce4-9799-acc986789273 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236076627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.4236076627 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.313523594 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 32902371 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:57:03 PM PDT 24 |
Finished | Jul 28 06:57:04 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-9c346ad9-405a-47b2-931f-1894ed6af7c7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313523594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.313523594 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.2610417591 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 148159011262 ps |
CPU time | 913.83 seconds |
Started | Jul 28 06:56:52 PM PDT 24 |
Finished | Jul 28 07:12:06 PM PDT 24 |
Peak memory | 203424 kb |
Host | smart-f440a6c5-2fb3-4f03-b230-6a657eeabcab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610417591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .2610417591 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.55659764 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 1332736208 ps |
CPU time | 5.62 seconds |
Started | Jul 28 06:56:59 PM PDT 24 |
Finished | Jul 28 06:57:05 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-5faa8fd4-4faf-451a-a91c-b8c29084e318 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55659764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_esca lation.55659764 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.1468710782 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 1539050547 ps |
CPU time | 162.91 seconds |
Started | Jul 28 06:56:57 PM PDT 24 |
Finished | Jul 28 06:59:41 PM PDT 24 |
Peak memory | 372824 kb |
Host | smart-3e81be42-83cf-4887-91e7-0a21d083a7c1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468710782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.1468710782 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3024531813 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 5774195629 ps |
CPU time | 74.68 seconds |
Started | Jul 28 06:57:04 PM PDT 24 |
Finished | Jul 28 06:58:19 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-c3d0f152-b024-402a-a337-d3efecee5a98 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024531813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.3024531813 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.2488052821 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 20999517612 ps |
CPU time | 293.32 seconds |
Started | Jul 28 06:57:04 PM PDT 24 |
Finished | Jul 28 07:01:57 PM PDT 24 |
Peak memory | 211324 kb |
Host | smart-eb56d223-7144-4b77-b2fb-bc599fa4e414 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488052821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.2488052821 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.3924467419 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 17640883909 ps |
CPU time | 837.58 seconds |
Started | Jul 28 06:56:52 PM PDT 24 |
Finished | Jul 28 07:10:50 PM PDT 24 |
Peak memory | 372204 kb |
Host | smart-6c2815e5-7934-45b1-ae6e-18aa00f1a9da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924467419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.3924467419 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.9512722 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 2592148986 ps |
CPU time | 26.05 seconds |
Started | Jul 28 06:56:59 PM PDT 24 |
Finished | Jul 28 06:57:25 PM PDT 24 |
Peak memory | 269644 kb |
Host | smart-6bda19ae-3cf5-4bf1-8314-6526dd7f8b9d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9512722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sra m_ctrl_partial_access.9512722 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3019374701 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 20497734182 ps |
CPU time | 455.61 seconds |
Started | Jul 28 06:56:58 PM PDT 24 |
Finished | Jul 28 07:04:34 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-55a8e411-da4c-4021-8547-c449501b9df1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019374701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.3019374701 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.976561541 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 707288629 ps |
CPU time | 3.22 seconds |
Started | Jul 28 06:57:04 PM PDT 24 |
Finished | Jul 28 06:57:07 PM PDT 24 |
Peak memory | 203064 kb |
Host | smart-3508d4d8-68ea-40ba-836f-dc53a7ff8e6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976561541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.976561541 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.1349432566 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 12153049921 ps |
CPU time | 497.19 seconds |
Started | Jul 28 06:57:04 PM PDT 24 |
Finished | Jul 28 07:05:22 PM PDT 24 |
Peak memory | 356484 kb |
Host | smart-b3487e90-74b1-4f03-8555-b7c788ef9680 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349432566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1349432566 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.4245639100 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 6782091515 ps |
CPU time | 18.83 seconds |
Started | Jul 28 06:56:56 PM PDT 24 |
Finished | Jul 28 06:57:15 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-e77da478-3cfe-423b-88d1-4d62ac9f2cea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245639100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.4245639100 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.137578720 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 75179910349 ps |
CPU time | 2868.94 seconds |
Started | Jul 28 06:57:02 PM PDT 24 |
Finished | Jul 28 07:44:52 PM PDT 24 |
Peak memory | 380052 kb |
Host | smart-7053f4f9-f341-4511-9731-709cbc3bcf60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137578720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_stress_all.137578720 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.239999698 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 5046119682 ps |
CPU time | 22.55 seconds |
Started | Jul 28 06:57:02 PM PDT 24 |
Finished | Jul 28 06:57:25 PM PDT 24 |
Peak memory | 211484 kb |
Host | smart-baacb20c-4287-4290-8ed9-7094eb509cb3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=239999698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.239999698 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.4101863906 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 22560127477 ps |
CPU time | 320.8 seconds |
Started | Jul 28 06:56:57 PM PDT 24 |
Finished | Jul 28 07:02:18 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-ad8d7d6e-b02b-4ea8-8acd-94172c1313f5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101863906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.4101863906 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.654267195 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 2096690517 ps |
CPU time | 20.75 seconds |
Started | Jul 28 06:56:58 PM PDT 24 |
Finished | Jul 28 06:57:19 PM PDT 24 |
Peak memory | 268496 kb |
Host | smart-fc3f52be-00b5-4e8f-b0ad-e0b4c5c7d8ed |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654267195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_throughput_w_partial_write.654267195 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1049549079 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 32488244254 ps |
CPU time | 683.03 seconds |
Started | Jul 28 06:57:12 PM PDT 24 |
Finished | Jul 28 07:08:35 PM PDT 24 |
Peak memory | 357516 kb |
Host | smart-8fc53e3b-3aec-4556-956a-3f0a7c9e8f79 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049549079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.1049549079 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.1726381567 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 14389003 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:57:16 PM PDT 24 |
Finished | Jul 28 06:57:17 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-58ccead5-337e-4d57-8978-6da2ec7f07e2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726381567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1726381567 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.2916087933 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 71932986108 ps |
CPU time | 1378.79 seconds |
Started | Jul 28 06:57:03 PM PDT 24 |
Finished | Jul 28 07:20:02 PM PDT 24 |
Peak memory | 203316 kb |
Host | smart-c9df6116-8e2c-437d-93db-ceabf0c6816b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916087933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .2916087933 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.3505727156 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 80861253084 ps |
CPU time | 897.6 seconds |
Started | Jul 28 06:57:13 PM PDT 24 |
Finished | Jul 28 07:12:10 PM PDT 24 |
Peak memory | 373944 kb |
Host | smart-84325265-d2b4-4647-a0a5-91449a30a371 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505727156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.3505727156 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.818051916 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 16221983789 ps |
CPU time | 86.71 seconds |
Started | Jul 28 06:57:11 PM PDT 24 |
Finished | Jul 28 06:58:38 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-a36d4d1c-da90-4f74-9ce0-7bfd35e94ede |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818051916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc alation.818051916 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.2549224062 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 1296362092 ps |
CPU time | 96.05 seconds |
Started | Jul 28 06:57:13 PM PDT 24 |
Finished | Jul 28 06:58:49 PM PDT 24 |
Peak memory | 348684 kb |
Host | smart-e9866352-0743-412f-a472-952114c3ebe8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549224062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.2549224062 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.611019495 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 29764240426 ps |
CPU time | 96.12 seconds |
Started | Jul 28 06:57:16 PM PDT 24 |
Finished | Jul 28 06:58:52 PM PDT 24 |
Peak memory | 211868 kb |
Host | smart-25f971a5-0668-449b-9f51-e23936a38426 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611019495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .sram_ctrl_mem_partial_access.611019495 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.3968124670 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 6918284294 ps |
CPU time | 157.28 seconds |
Started | Jul 28 06:57:15 PM PDT 24 |
Finished | Jul 28 06:59:52 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-99f3fe94-2547-4a66-bac1-a79fce2daa79 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968124670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.3968124670 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.879980154 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 6861400381 ps |
CPU time | 1294.28 seconds |
Started | Jul 28 06:57:04 PM PDT 24 |
Finished | Jul 28 07:18:39 PM PDT 24 |
Peak memory | 381120 kb |
Host | smart-cd04201d-14b6-40ad-82f7-ab6ff7506e6e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879980154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip le_keys.879980154 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.2643428179 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 3987351932 ps |
CPU time | 14.71 seconds |
Started | Jul 28 06:57:04 PM PDT 24 |
Finished | Jul 28 06:57:19 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-257c2cd1-80df-4d27-befc-0eb7ebdab22f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643428179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.2643428179 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2803258592 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 6499502894 ps |
CPU time | 333.09 seconds |
Started | Jul 28 06:57:11 PM PDT 24 |
Finished | Jul 28 07:02:45 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-21d99b8f-6507-408b-b18c-e4dc6385cd09 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803258592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.2803258592 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.3947142661 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 1353344675 ps |
CPU time | 3.42 seconds |
Started | Jul 28 06:57:12 PM PDT 24 |
Finished | Jul 28 06:57:16 PM PDT 24 |
Peak memory | 203064 kb |
Host | smart-b43aee47-2d9e-4691-b24f-ed84af0a3acb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947142661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3947142661 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.2521613409 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 14894658933 ps |
CPU time | 31.06 seconds |
Started | Jul 28 06:57:12 PM PDT 24 |
Finished | Jul 28 06:57:43 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-6df471c9-6543-4b82-9e78-1142fe572e25 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521613409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2521613409 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.565974254 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 1512423307 ps |
CPU time | 90.66 seconds |
Started | Jul 28 06:57:03 PM PDT 24 |
Finished | Jul 28 06:58:34 PM PDT 24 |
Peak memory | 340412 kb |
Host | smart-a2e82a8e-6e3a-45b0-90ca-0fe307e4dc9b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565974254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.565974254 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.2061542237 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 66749092083 ps |
CPU time | 1300.51 seconds |
Started | Jul 28 06:57:15 PM PDT 24 |
Finished | Jul 28 07:18:56 PM PDT 24 |
Peak memory | 373976 kb |
Host | smart-5dc4d0b1-e044-463e-a23c-b985d767f6ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061542237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.2061542237 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.778627182 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 808355514 ps |
CPU time | 22.18 seconds |
Started | Jul 28 06:57:16 PM PDT 24 |
Finished | Jul 28 06:57:38 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-9b3990c0-d3a7-4ad9-8c11-b1515f8830cf |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=778627182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.778627182 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1820338162 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 3417586520 ps |
CPU time | 163.52 seconds |
Started | Jul 28 06:57:04 PM PDT 24 |
Finished | Jul 28 06:59:48 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-a767a27e-6d59-479f-bd55-49d0549a9c3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820338162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.1820338162 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1666491982 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 3100202280 ps |
CPU time | 134.92 seconds |
Started | Jul 28 06:57:10 PM PDT 24 |
Finished | Jul 28 06:59:25 PM PDT 24 |
Peak memory | 364644 kb |
Host | smart-39091ea3-0650-4424-87c2-7d36cb516ba2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666491982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1666491982 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.548916432 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 12686065804 ps |
CPU time | 759.67 seconds |
Started | Jul 28 06:57:26 PM PDT 24 |
Finished | Jul 28 07:10:05 PM PDT 24 |
Peak memory | 372768 kb |
Host | smart-f1dd6099-9c05-4385-b5a4-d2dde507a6fd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548916432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 29.sram_ctrl_access_during_key_req.548916432 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.3246082079 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 22471317 ps |
CPU time | 0.74 seconds |
Started | Jul 28 06:57:34 PM PDT 24 |
Finished | Jul 28 06:57:35 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-bac7a17b-3a81-451b-817a-e909aed176af |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246082079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.3246082079 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.2742152712 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 278459438762 ps |
CPU time | 632.07 seconds |
Started | Jul 28 06:57:20 PM PDT 24 |
Finished | Jul 28 07:07:52 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-f0118722-a12e-47f3-816f-b5e6d1928ade |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742152712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .2742152712 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.4170100410 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 27985415483 ps |
CPU time | 637.53 seconds |
Started | Jul 28 06:57:26 PM PDT 24 |
Finished | Jul 28 07:08:03 PM PDT 24 |
Peak memory | 379060 kb |
Host | smart-be7c3af2-1909-48fb-9fdb-8f4b91fa0967 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170100410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.4170100410 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.2159839762 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 9594887518 ps |
CPU time | 59.09 seconds |
Started | Jul 28 06:57:26 PM PDT 24 |
Finished | Jul 28 06:58:25 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-15ddceec-d517-4428-9538-31b01e353e25 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159839762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.2159839762 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.1816096245 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 769618949 ps |
CPU time | 73.82 seconds |
Started | Jul 28 06:57:26 PM PDT 24 |
Finished | Jul 28 06:58:40 PM PDT 24 |
Peak memory | 344224 kb |
Host | smart-bfae7501-b8a9-41ec-8951-55fe151914b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816096245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.1816096245 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1463820465 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 15472651244 ps |
CPU time | 78.61 seconds |
Started | Jul 28 06:57:32 PM PDT 24 |
Finished | Jul 28 06:58:51 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-b0548f56-227a-4601-8ed8-8e1ae7848f45 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463820465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.1463820465 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.2866053262 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 4023577987 ps |
CPU time | 242.63 seconds |
Started | Jul 28 06:57:26 PM PDT 24 |
Finished | Jul 28 07:01:29 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-191a4b56-61e7-42fb-8856-7a4c5bf42064 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866053262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.2866053262 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.2903229999 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 48995397855 ps |
CPU time | 1433.55 seconds |
Started | Jul 28 06:57:21 PM PDT 24 |
Finished | Jul 28 07:21:15 PM PDT 24 |
Peak memory | 379064 kb |
Host | smart-15f2b2c7-31ce-472c-8750-5946894b24e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903229999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.2903229999 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.1510906859 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 696926398 ps |
CPU time | 3.72 seconds |
Started | Jul 28 06:57:27 PM PDT 24 |
Finished | Jul 28 06:57:31 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-522d5c15-a4ad-445b-87e3-01a33393fff9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510906859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.1510906859 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2175953460 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 6826793133 ps |
CPU time | 358.29 seconds |
Started | Jul 28 06:57:26 PM PDT 24 |
Finished | Jul 28 07:03:24 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-cf2457b6-b607-405b-b300-6770a19ba6d1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175953460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.2175953460 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.1479365003 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 1410122135 ps |
CPU time | 3.82 seconds |
Started | Jul 28 06:57:26 PM PDT 24 |
Finished | Jul 28 06:57:30 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-6c41c413-4c56-493c-b90b-0428e3040615 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479365003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1479365003 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.4129825246 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 3829216852 ps |
CPU time | 594.31 seconds |
Started | Jul 28 06:57:25 PM PDT 24 |
Finished | Jul 28 07:07:20 PM PDT 24 |
Peak memory | 375008 kb |
Host | smart-e8aafe41-7c2d-4caf-a4a3-55e5b9628e72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129825246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.4129825246 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.2291740840 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 691256553 ps |
CPU time | 11.9 seconds |
Started | Jul 28 06:57:16 PM PDT 24 |
Finished | Jul 28 06:57:28 PM PDT 24 |
Peak memory | 203308 kb |
Host | smart-3d815c5d-6e15-49e2-af27-261aa607e187 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291740840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2291740840 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.3280989725 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 611918971438 ps |
CPU time | 5238.08 seconds |
Started | Jul 28 06:57:32 PM PDT 24 |
Finished | Jul 28 08:24:51 PM PDT 24 |
Peak memory | 389408 kb |
Host | smart-956991b1-ee68-4e64-a72d-03d266fa33dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280989725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.3280989725 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2328887147 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 3845942231 ps |
CPU time | 26.1 seconds |
Started | Jul 28 06:57:34 PM PDT 24 |
Finished | Jul 28 06:58:00 PM PDT 24 |
Peak memory | 211968 kb |
Host | smart-739d3166-2054-4c4a-b186-5047cf680199 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2328887147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.2328887147 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2866827433 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 17084846452 ps |
CPU time | 256.32 seconds |
Started | Jul 28 06:57:21 PM PDT 24 |
Finished | Jul 28 07:01:38 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-476ed470-a5fb-4b3f-9634-429fded0a165 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866827433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.2866827433 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.373758290 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 6501207623 ps |
CPU time | 23.7 seconds |
Started | Jul 28 06:57:26 PM PDT 24 |
Finished | Jul 28 06:57:50 PM PDT 24 |
Peak memory | 277684 kb |
Host | smart-38739814-142a-4bc6-bfef-7889775b0c0f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373758290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_throughput_w_partial_write.373758290 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1642985193 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 64351360537 ps |
CPU time | 1152.85 seconds |
Started | Jul 28 06:51:39 PM PDT 24 |
Finished | Jul 28 07:10:53 PM PDT 24 |
Peak memory | 381112 kb |
Host | smart-c86c33fe-6cee-4ab1-969a-36a4770fd46f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642985193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.1642985193 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.1063987429 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 25918048 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:51:45 PM PDT 24 |
Finished | Jul 28 06:51:46 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-0d99616e-3645-4bb9-b85f-e7112b48f88b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063987429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1063987429 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.3739889442 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 61246297357 ps |
CPU time | 1331.25 seconds |
Started | Jul 28 06:51:31 PM PDT 24 |
Finished | Jul 28 07:13:42 PM PDT 24 |
Peak memory | 203408 kb |
Host | smart-79bf526c-dffa-4e37-bdca-1ded5bba750c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739889442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 3739889442 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.4157433191 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 43459629646 ps |
CPU time | 235.9 seconds |
Started | Jul 28 06:51:39 PM PDT 24 |
Finished | Jul 28 06:55:35 PM PDT 24 |
Peak memory | 356736 kb |
Host | smart-d8ce06f2-47fe-47b3-acca-6f861bf0cefe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157433191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.4157433191 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.1314469968 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 19363180801 ps |
CPU time | 53.52 seconds |
Started | Jul 28 06:51:34 PM PDT 24 |
Finished | Jul 28 06:52:28 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-bde28e1f-cca7-4538-b188-ba7d910d45b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314469968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.1314469968 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.3862448604 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 2787388587 ps |
CPU time | 15.8 seconds |
Started | Jul 28 06:51:34 PM PDT 24 |
Finished | Jul 28 06:51:50 PM PDT 24 |
Peak memory | 253268 kb |
Host | smart-314bb676-50cb-40bd-a14a-3955b78e892a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862448604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.3862448604 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3307828898 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 5351306471 ps |
CPU time | 146.35 seconds |
Started | Jul 28 06:51:40 PM PDT 24 |
Finished | Jul 28 06:54:06 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-27baf2b2-deab-4bac-834b-9cf435fc6782 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307828898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.3307828898 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.1646540646 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 14122501005 ps |
CPU time | 316.77 seconds |
Started | Jul 28 06:51:39 PM PDT 24 |
Finished | Jul 28 06:56:56 PM PDT 24 |
Peak memory | 203608 kb |
Host | smart-9844789c-1cd9-441c-91b3-ac6ce018305f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646540646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.1646540646 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.2285227911 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 13032480203 ps |
CPU time | 225.33 seconds |
Started | Jul 28 06:51:30 PM PDT 24 |
Finished | Jul 28 06:55:16 PM PDT 24 |
Peak memory | 335252 kb |
Host | smart-373e1463-8e2a-445e-9a9c-42b15ddf2cc0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285227911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.2285227911 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.2967292128 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 2145926887 ps |
CPU time | 34.83 seconds |
Started | Jul 28 06:51:29 PM PDT 24 |
Finished | Jul 28 06:52:04 PM PDT 24 |
Peak memory | 288924 kb |
Host | smart-7d27c340-638e-4e92-a105-a2ba8ea1109f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967292128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.2967292128 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2473692800 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 16309602755 ps |
CPU time | 205.66 seconds |
Started | Jul 28 06:51:35 PM PDT 24 |
Finished | Jul 28 06:55:01 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-ea82212a-6afe-4c0d-a7f0-4b15716cdcc6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473692800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.2473692800 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.3660659953 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 349777699 ps |
CPU time | 3.45 seconds |
Started | Jul 28 06:51:40 PM PDT 24 |
Finished | Jul 28 06:51:44 PM PDT 24 |
Peak memory | 203048 kb |
Host | smart-6c82251c-c9e0-4c1b-8411-27a97ccacb01 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660659953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3660659953 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.4138669647 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 3911177211 ps |
CPU time | 63.46 seconds |
Started | Jul 28 06:51:45 PM PDT 24 |
Finished | Jul 28 06:52:49 PM PDT 24 |
Peak memory | 250976 kb |
Host | smart-be759e2a-721b-43c3-a192-a45ce156f507 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138669647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.4138669647 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.2115768638 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 133397728 ps |
CPU time | 1.84 seconds |
Started | Jul 28 06:51:46 PM PDT 24 |
Finished | Jul 28 06:51:48 PM PDT 24 |
Peak memory | 222308 kb |
Host | smart-4df64466-d49c-4784-a97e-619661e9c3fd |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115768638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.2115768638 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.1619544463 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 3023958705 ps |
CPU time | 7.66 seconds |
Started | Jul 28 06:51:29 PM PDT 24 |
Finished | Jul 28 06:51:37 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-092e6983-dac8-4dbc-90e5-d21ed8e6d656 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619544463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1619544463 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.4217434412 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 213300818985 ps |
CPU time | 6777.13 seconds |
Started | Jul 28 06:51:40 PM PDT 24 |
Finished | Jul 28 08:44:38 PM PDT 24 |
Peak memory | 383196 kb |
Host | smart-7f0c0241-b437-4d72-899a-c3c57879ef5b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217434412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.4217434412 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.349731377 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 10509532233 ps |
CPU time | 183.38 seconds |
Started | Jul 28 06:51:29 PM PDT 24 |
Finished | Jul 28 06:54:33 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-6e9e969a-30ac-4b52-b74a-541315d8e1bf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349731377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_stress_pipeline.349731377 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3610451062 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 2789598780 ps |
CPU time | 74.68 seconds |
Started | Jul 28 06:51:35 PM PDT 24 |
Finished | Jul 28 06:52:50 PM PDT 24 |
Peak memory | 326876 kb |
Host | smart-816eb4ea-c4d8-4b19-9395-f258bd2b7d73 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610451062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.3610451062 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1468581745 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 13641021392 ps |
CPU time | 760.15 seconds |
Started | Jul 28 06:57:47 PM PDT 24 |
Finished | Jul 28 07:10:27 PM PDT 24 |
Peak memory | 374948 kb |
Host | smart-40d1a51c-3766-4448-873f-ce4f84c12746 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468581745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.1468581745 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.4149026357 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 42284046 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:57:47 PM PDT 24 |
Finished | Jul 28 06:57:48 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-2007ec67-fac5-46f9-915a-b39b4f9ec175 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149026357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.4149026357 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.4259116535 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 462195193526 ps |
CPU time | 1270.08 seconds |
Started | Jul 28 06:57:41 PM PDT 24 |
Finished | Jul 28 07:18:51 PM PDT 24 |
Peak memory | 203832 kb |
Host | smart-dee27e30-098c-49af-84ea-76665544ba18 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259116535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .4259116535 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.4219063019 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 4765882940 ps |
CPU time | 468.17 seconds |
Started | Jul 28 06:57:49 PM PDT 24 |
Finished | Jul 28 07:05:37 PM PDT 24 |
Peak memory | 377924 kb |
Host | smart-cc7012b2-eea8-4531-8313-4f7852bb3a71 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219063019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.4219063019 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.3077227407 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 49584333697 ps |
CPU time | 74.88 seconds |
Started | Jul 28 06:57:41 PM PDT 24 |
Finished | Jul 28 06:58:56 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-8eaa86af-d015-4f53-b201-07882be90ac3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077227407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.3077227407 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.3603330630 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 2896724146 ps |
CPU time | 50.87 seconds |
Started | Jul 28 06:57:41 PM PDT 24 |
Finished | Jul 28 06:58:32 PM PDT 24 |
Peak memory | 301344 kb |
Host | smart-0e06c481-0ff4-488a-9bb4-bd17ee280931 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603330630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.3603330630 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3912402653 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 18237806404 ps |
CPU time | 163.84 seconds |
Started | Jul 28 06:57:48 PM PDT 24 |
Finished | Jul 28 07:00:32 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-6e635328-a96b-4ff0-8401-3db9cc1a9140 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912402653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.3912402653 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.4030147869 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 4109118888 ps |
CPU time | 260.21 seconds |
Started | Jul 28 06:57:46 PM PDT 24 |
Finished | Jul 28 07:02:06 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-0002cb21-1ac9-4ad8-946f-7be3a230d019 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030147869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.4030147869 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.3703516511 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 52898988138 ps |
CPU time | 460.72 seconds |
Started | Jul 28 06:57:41 PM PDT 24 |
Finished | Jul 28 07:05:22 PM PDT 24 |
Peak memory | 366560 kb |
Host | smart-e8ca900b-b23e-4693-a89a-9530ad53ef1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703516511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.3703516511 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.4232805971 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 959014446 ps |
CPU time | 20.64 seconds |
Started | Jul 28 06:57:41 PM PDT 24 |
Finished | Jul 28 06:58:01 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-2dcff066-37cc-49b4-9e11-200bb9fb1987 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232805971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.4232805971 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1874280469 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 14075141659 ps |
CPU time | 296 seconds |
Started | Jul 28 06:57:40 PM PDT 24 |
Finished | Jul 28 07:02:36 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-17c8edbe-23b9-40ed-b410-841b93b5fb80 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874280469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.1874280469 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.2691372077 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 1876479828 ps |
CPU time | 3.31 seconds |
Started | Jul 28 06:57:47 PM PDT 24 |
Finished | Jul 28 06:57:51 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-a32994ba-ea23-4515-b68b-a4deabe103e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691372077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2691372077 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.726111012 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 5701859335 ps |
CPU time | 927.93 seconds |
Started | Jul 28 06:57:48 PM PDT 24 |
Finished | Jul 28 07:13:16 PM PDT 24 |
Peak memory | 375004 kb |
Host | smart-73d03d7b-ca87-416d-a4a1-65980facbeea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726111012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.726111012 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.4021707803 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 4382284178 ps |
CPU time | 16.05 seconds |
Started | Jul 28 06:57:41 PM PDT 24 |
Finished | Jul 28 06:57:57 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-93fa687d-88f0-49be-9282-99ffa0b1a036 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021707803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.4021707803 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.4237741924 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 125015090120 ps |
CPU time | 5369.95 seconds |
Started | Jul 28 06:57:48 PM PDT 24 |
Finished | Jul 28 08:27:19 PM PDT 24 |
Peak memory | 382136 kb |
Host | smart-8d8feaec-0b08-4914-b4ad-5736812eb855 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237741924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.4237741924 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2689489854 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 1306869860 ps |
CPU time | 23.17 seconds |
Started | Jul 28 06:57:47 PM PDT 24 |
Finished | Jul 28 06:58:10 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-7498fa66-b4b3-4e71-b456-7e58f3cd72f7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2689489854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2689489854 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2077246433 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 2631921999 ps |
CPU time | 197.51 seconds |
Started | Jul 28 06:57:43 PM PDT 24 |
Finished | Jul 28 07:01:00 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-3df3c28d-f69a-4f69-9b60-424d1f01d55d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077246433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.2077246433 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3271815651 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 2720110950 ps |
CPU time | 8.62 seconds |
Started | Jul 28 06:57:41 PM PDT 24 |
Finished | Jul 28 06:57:50 PM PDT 24 |
Peak memory | 221160 kb |
Host | smart-7e23102c-3140-4cf0-acf2-ebed37f96eb5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271815651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3271815651 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2826229605 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 16144728732 ps |
CPU time | 1190.97 seconds |
Started | Jul 28 06:57:53 PM PDT 24 |
Finished | Jul 28 07:17:44 PM PDT 24 |
Peak memory | 379876 kb |
Host | smart-d6723bac-cd94-492e-96e3-85993e16e123 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826229605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.2826229605 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.3350654217 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 38090381 ps |
CPU time | 0.68 seconds |
Started | Jul 28 06:58:01 PM PDT 24 |
Finished | Jul 28 06:58:01 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-580da0ad-9e60-4286-9245-a4e72a3ebeb5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350654217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3350654217 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.4268777051 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 210793252094 ps |
CPU time | 1111.76 seconds |
Started | Jul 28 06:57:51 PM PDT 24 |
Finished | Jul 28 07:16:23 PM PDT 24 |
Peak memory | 203292 kb |
Host | smart-f3ed67fc-557c-4835-a28f-14b5127ef5d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268777051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .4268777051 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.1490960242 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 6536189673 ps |
CPU time | 26.06 seconds |
Started | Jul 28 06:57:54 PM PDT 24 |
Finished | Jul 28 06:58:20 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-444754e3-7ca4-49ff-9634-c8028d0aa30b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490960242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.1490960242 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.1545350452 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 18025252718 ps |
CPU time | 25.87 seconds |
Started | Jul 28 06:57:52 PM PDT 24 |
Finished | Jul 28 06:58:18 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-b311ff4a-fe61-4bfe-9e9e-46c6d618491a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545350452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.1545350452 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.626802103 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 716160123 ps |
CPU time | 28.99 seconds |
Started | Jul 28 06:57:53 PM PDT 24 |
Finished | Jul 28 06:58:22 PM PDT 24 |
Peak memory | 277708 kb |
Host | smart-3f7062b8-1e8b-4263-926e-338ca9632fab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626802103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.sram_ctrl_max_throughput.626802103 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2767424622 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 9645874560 ps |
CPU time | 169.13 seconds |
Started | Jul 28 06:57:53 PM PDT 24 |
Finished | Jul 28 07:00:42 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-820e2db5-ac84-4cc5-b6cf-70a6e8eed470 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767424622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.2767424622 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.4161705872 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 8045165747 ps |
CPU time | 255.85 seconds |
Started | Jul 28 06:57:53 PM PDT 24 |
Finished | Jul 28 07:02:09 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-70a548d5-2884-43b1-97a7-824307f12a11 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161705872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.4161705872 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.2551665162 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 18176774590 ps |
CPU time | 1033.79 seconds |
Started | Jul 28 06:57:52 PM PDT 24 |
Finished | Jul 28 07:15:06 PM PDT 24 |
Peak memory | 378748 kb |
Host | smart-56fab872-ddce-4799-8dfb-d7a327cc044d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551665162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.2551665162 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.3320705940 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 8179444776 ps |
CPU time | 23.82 seconds |
Started | Jul 28 06:57:54 PM PDT 24 |
Finished | Jul 28 06:58:18 PM PDT 24 |
Peak memory | 272944 kb |
Host | smart-2ca6ede5-7533-4324-a004-3e4c0b13382f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320705940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.3320705940 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2095226317 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 26574524546 ps |
CPU time | 289.27 seconds |
Started | Jul 28 06:57:56 PM PDT 24 |
Finished | Jul 28 07:02:45 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-f54f120a-526e-46cd-8ea6-f8d57629405e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095226317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2095226317 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.2564702918 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 487875141 ps |
CPU time | 3.17 seconds |
Started | Jul 28 06:57:56 PM PDT 24 |
Finished | Jul 28 06:57:59 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-cc3bf265-91ac-4168-911b-7710f8955652 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564702918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2564702918 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.1374695398 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 39033069808 ps |
CPU time | 324.21 seconds |
Started | Jul 28 06:57:51 PM PDT 24 |
Finished | Jul 28 07:03:16 PM PDT 24 |
Peak memory | 378976 kb |
Host | smart-454f5304-d372-4325-996e-6550b04e88dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374695398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1374695398 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.1591025209 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 777354186 ps |
CPU time | 146.36 seconds |
Started | Jul 28 06:57:48 PM PDT 24 |
Finished | Jul 28 07:00:15 PM PDT 24 |
Peak memory | 369708 kb |
Host | smart-2ca5c228-fc57-49ed-9456-399c2a75bafb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591025209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1591025209 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.2588095444 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 206312003899 ps |
CPU time | 5179.62 seconds |
Started | Jul 28 06:58:02 PM PDT 24 |
Finished | Jul 28 08:24:22 PM PDT 24 |
Peak memory | 380332 kb |
Host | smart-6b36310b-0456-491d-b316-e624026e6560 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588095444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.2588095444 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3051802801 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 3301128578 ps |
CPU time | 166.53 seconds |
Started | Jul 28 06:57:52 PM PDT 24 |
Finished | Jul 28 07:00:39 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-97f73a07-efa3-4625-81a5-6434f2cee370 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051802801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.3051802801 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.841901307 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 736727255 ps |
CPU time | 42.13 seconds |
Started | Jul 28 06:57:52 PM PDT 24 |
Finished | Jul 28 06:58:34 PM PDT 24 |
Peak memory | 295724 kb |
Host | smart-9331d5b1-545a-4ac6-8856-9df88c0cdf1a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841901307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.841901307 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1228386771 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 20604477622 ps |
CPU time | 1576.37 seconds |
Started | Jul 28 06:58:08 PM PDT 24 |
Finished | Jul 28 07:24:25 PM PDT 24 |
Peak memory | 379060 kb |
Host | smart-262a144f-0ba9-4194-bd0a-959f92d4fa05 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228386771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.1228386771 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.1379316989 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 45719838 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:58:16 PM PDT 24 |
Finished | Jul 28 06:58:16 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-d161bfca-ed52-48f3-9f54-25cac7a901d0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379316989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1379316989 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.2922074342 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 174245016450 ps |
CPU time | 1031.28 seconds |
Started | Jul 28 06:57:59 PM PDT 24 |
Finished | Jul 28 07:15:11 PM PDT 24 |
Peak memory | 203980 kb |
Host | smart-55abbde6-612c-4a41-a23f-c194dc3d094e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922074342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .2922074342 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.3984804004 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 6734981874 ps |
CPU time | 239.97 seconds |
Started | Jul 28 06:58:09 PM PDT 24 |
Finished | Jul 28 07:02:09 PM PDT 24 |
Peak memory | 355380 kb |
Host | smart-2e03f9c0-90e1-42c5-8613-252d4207f895 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984804004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.3984804004 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.4184418929 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 4341652503 ps |
CPU time | 26.53 seconds |
Started | Jul 28 06:58:05 PM PDT 24 |
Finished | Jul 28 06:58:32 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-0a3d33b1-6125-46d2-b591-0ea77732fe50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184418929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.4184418929 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.2003624912 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 2536391279 ps |
CPU time | 8.38 seconds |
Started | Jul 28 06:57:59 PM PDT 24 |
Finished | Jul 28 06:58:08 PM PDT 24 |
Peak memory | 221788 kb |
Host | smart-5a2f3bbf-0c4c-4d7f-8e8e-288610366cdf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003624912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.2003624912 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.928331319 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 8492061489 ps |
CPU time | 150.24 seconds |
Started | Jul 28 06:58:08 PM PDT 24 |
Finished | Jul 28 07:00:38 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-5fdfc63a-e8d1-4f40-95c5-638df12106eb |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928331319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .sram_ctrl_mem_partial_access.928331319 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.365685384 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 14398216032 ps |
CPU time | 159.07 seconds |
Started | Jul 28 06:58:06 PM PDT 24 |
Finished | Jul 28 07:00:45 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-42de690d-0fc4-4de6-bdf6-b506c4071de7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365685384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl _mem_walk.365685384 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.3599572424 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 32808834749 ps |
CPU time | 994.42 seconds |
Started | Jul 28 06:57:59 PM PDT 24 |
Finished | Jul 28 07:14:34 PM PDT 24 |
Peak memory | 372852 kb |
Host | smart-da12229b-7ccb-4414-9562-35ab493f6441 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599572424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.3599572424 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1187217139 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 623551565 ps |
CPU time | 13.83 seconds |
Started | Jul 28 06:58:01 PM PDT 24 |
Finished | Jul 28 06:58:15 PM PDT 24 |
Peak memory | 239528 kb |
Host | smart-4db01a50-8a7b-4a4e-9772-229b6d3c3ed2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187217139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1187217139 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3449865707 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 66589605493 ps |
CPU time | 429.09 seconds |
Started | Jul 28 06:58:02 PM PDT 24 |
Finished | Jul 28 07:05:11 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-15daf13c-e382-4499-be2b-76678cc314e8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449865707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.3449865707 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.3989188429 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 682537241 ps |
CPU time | 3.49 seconds |
Started | Jul 28 06:58:06 PM PDT 24 |
Finished | Jul 28 06:58:10 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-f1479d1b-c5f6-472d-ac08-324b93f475aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989188429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3989188429 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.2383872118 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 7583753755 ps |
CPU time | 255.19 seconds |
Started | Jul 28 06:58:09 PM PDT 24 |
Finished | Jul 28 07:02:24 PM PDT 24 |
Peak memory | 333968 kb |
Host | smart-30e6d0ad-cc8d-4e11-a12f-ae4b4dcbcfc7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383872118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2383872118 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.1084013980 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 2745643023 ps |
CPU time | 15.77 seconds |
Started | Jul 28 06:58:00 PM PDT 24 |
Finished | Jul 28 06:58:16 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-f5a9f1a3-a565-45da-b329-5da2de110682 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084013980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1084013980 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.2027754204 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 420563122602 ps |
CPU time | 6492.64 seconds |
Started | Jul 28 06:58:09 PM PDT 24 |
Finished | Jul 28 08:46:22 PM PDT 24 |
Peak memory | 374944 kb |
Host | smart-ffed8f39-0a1f-437d-95b0-0fe09e5ad818 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027754204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.2027754204 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3621814580 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 275115609 ps |
CPU time | 8.55 seconds |
Started | Jul 28 06:58:08 PM PDT 24 |
Finished | Jul 28 06:58:17 PM PDT 24 |
Peak memory | 213200 kb |
Host | smart-2fcca493-a25e-4761-835c-1e6c453369d0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3621814580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3621814580 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.355436653 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 22488783509 ps |
CPU time | 168.93 seconds |
Started | Jul 28 06:58:01 PM PDT 24 |
Finished | Jul 28 07:00:50 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-9636e979-5d95-4b2d-b36b-ecc42ac3d8d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355436653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .sram_ctrl_stress_pipeline.355436653 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1365419216 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 1759995911 ps |
CPU time | 71.85 seconds |
Started | Jul 28 06:58:02 PM PDT 24 |
Finished | Jul 28 06:59:14 PM PDT 24 |
Peak memory | 335968 kb |
Host | smart-f7502019-478e-4afb-9f8e-3c5f9731f5a2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365419216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1365419216 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3272544162 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 17463835763 ps |
CPU time | 548.2 seconds |
Started | Jul 28 06:58:21 PM PDT 24 |
Finished | Jul 28 07:07:30 PM PDT 24 |
Peak memory | 375948 kb |
Host | smart-82659584-76ef-490a-9620-1566eb48ac81 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272544162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.3272544162 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.492105135 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 37438520 ps |
CPU time | 0.64 seconds |
Started | Jul 28 06:58:27 PM PDT 24 |
Finished | Jul 28 06:58:28 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-7aecea3c-90e8-48db-92a7-b3231a668d33 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492105135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.492105135 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.1346904550 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 739790952467 ps |
CPU time | 1752.98 seconds |
Started | Jul 28 06:58:15 PM PDT 24 |
Finished | Jul 28 07:27:28 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-14991e60-8236-4d4f-a8e3-582c305b795f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346904550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .1346904550 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.2003896443 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 5779818154 ps |
CPU time | 49.49 seconds |
Started | Jul 28 06:58:21 PM PDT 24 |
Finished | Jul 28 06:59:10 PM PDT 24 |
Peak memory | 283948 kb |
Host | smart-cb809f18-1cd7-4a61-9345-bbf4ebffe67b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003896443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.2003896443 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.1476094143 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 85604871477 ps |
CPU time | 104.01 seconds |
Started | Jul 28 06:58:19 PM PDT 24 |
Finished | Jul 28 07:00:03 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-91a852c9-742e-486e-9a4b-f1db3292c92b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476094143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.1476094143 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.1377319482 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 2690035252 ps |
CPU time | 102.67 seconds |
Started | Jul 28 06:58:20 PM PDT 24 |
Finished | Jul 28 07:00:03 PM PDT 24 |
Peak memory | 354536 kb |
Host | smart-4d0972cb-c91f-483e-a33f-1c881ae5ed32 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377319482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.1377319482 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1334886161 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 2450595905 ps |
CPU time | 138.81 seconds |
Started | Jul 28 06:58:26 PM PDT 24 |
Finished | Jul 28 07:00:45 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-50c87765-63ec-49ca-bcb4-7310897a8dd2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334886161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.1334886161 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.1265060313 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 38353188464 ps |
CPU time | 179.01 seconds |
Started | Jul 28 06:58:29 PM PDT 24 |
Finished | Jul 28 07:01:28 PM PDT 24 |
Peak memory | 203408 kb |
Host | smart-0923fb7a-3870-495e-bbfb-151559f056d4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265060313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.1265060313 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.4189177895 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 87519611378 ps |
CPU time | 1059.12 seconds |
Started | Jul 28 06:58:15 PM PDT 24 |
Finished | Jul 28 07:15:55 PM PDT 24 |
Peak memory | 380744 kb |
Host | smart-eca57416-2e14-4351-8184-3bd4212fb961 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189177895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.4189177895 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.1079663551 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 4449944367 ps |
CPU time | 34.92 seconds |
Started | Jul 28 06:58:15 PM PDT 24 |
Finished | Jul 28 06:58:50 PM PDT 24 |
Peak memory | 276680 kb |
Host | smart-31ffb6bd-ca88-43ac-8494-a43e6f1dbc73 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079663551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.1079663551 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.345576454 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 30416532220 ps |
CPU time | 361.63 seconds |
Started | Jul 28 06:58:21 PM PDT 24 |
Finished | Jul 28 07:04:22 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-e9cbf4ad-67c9-4faa-9f39-126829e8be62 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345576454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.sram_ctrl_partial_access_b2b.345576454 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.2056930057 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 690678021 ps |
CPU time | 3.53 seconds |
Started | Jul 28 06:58:18 PM PDT 24 |
Finished | Jul 28 06:58:22 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-cc5a0c8b-40b8-4af3-bee5-e9fdab6dd22b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056930057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2056930057 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.3720793103 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 73128488498 ps |
CPU time | 455.9 seconds |
Started | Jul 28 06:58:19 PM PDT 24 |
Finished | Jul 28 07:05:55 PM PDT 24 |
Peak memory | 351404 kb |
Host | smart-0c2090ad-c0e8-45ee-976b-923832f8b27e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720793103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3720793103 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.4198290778 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 1570528994 ps |
CPU time | 13.31 seconds |
Started | Jul 28 06:58:14 PM PDT 24 |
Finished | Jul 28 06:58:28 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-23600cbf-561b-484c-aa6c-053f016d635a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198290778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.4198290778 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.2144444716 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 178689805098 ps |
CPU time | 4259.53 seconds |
Started | Jul 28 06:58:27 PM PDT 24 |
Finished | Jul 28 08:09:27 PM PDT 24 |
Peak memory | 388240 kb |
Host | smart-267035d7-0518-4e8a-af58-ec43ef557722 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144444716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.2144444716 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1796567456 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 550248558 ps |
CPU time | 7.27 seconds |
Started | Jul 28 06:58:28 PM PDT 24 |
Finished | Jul 28 06:58:36 PM PDT 24 |
Peak memory | 211428 kb |
Host | smart-452372b5-858a-4be2-83b2-6250bf38d578 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1796567456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1796567456 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1577326481 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 5408194078 ps |
CPU time | 311.55 seconds |
Started | Jul 28 06:58:15 PM PDT 24 |
Finished | Jul 28 07:03:27 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-4f216484-294a-41d7-8d32-4febd6c61cc0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577326481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.1577326481 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3472392539 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 791749450 ps |
CPU time | 111.75 seconds |
Started | Jul 28 06:58:17 PM PDT 24 |
Finished | Jul 28 07:00:09 PM PDT 24 |
Peak memory | 364680 kb |
Host | smart-58de5c2f-a018-46a9-aa0a-331922b023c8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472392539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3472392539 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2294011289 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 18878833687 ps |
CPU time | 494.03 seconds |
Started | Jul 28 06:58:33 PM PDT 24 |
Finished | Jul 28 07:06:47 PM PDT 24 |
Peak memory | 373900 kb |
Host | smart-1ccd1146-b3df-416f-979e-87e73a8f1ba8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294011289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.2294011289 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.3969024150 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 20657471 ps |
CPU time | 0.7 seconds |
Started | Jul 28 06:58:39 PM PDT 24 |
Finished | Jul 28 06:58:40 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-e7e92089-92aa-4e3e-88a0-597b2e980e0d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969024150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3969024150 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.3426791988 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 87724932758 ps |
CPU time | 775.54 seconds |
Started | Jul 28 06:58:26 PM PDT 24 |
Finished | Jul 28 07:11:22 PM PDT 24 |
Peak memory | 204000 kb |
Host | smart-7a3762bf-d5b6-4b6f-8078-0956bc01564c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426791988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .3426791988 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.679609120 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 191606671826 ps |
CPU time | 1026.73 seconds |
Started | Jul 28 06:58:32 PM PDT 24 |
Finished | Jul 28 07:15:39 PM PDT 24 |
Peak memory | 356832 kb |
Host | smart-eecbba60-3e66-4ca8-8229-2373b9ef75ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679609120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executabl e.679609120 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.539615353 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 4771695582 ps |
CPU time | 31.3 seconds |
Started | Jul 28 06:58:31 PM PDT 24 |
Finished | Jul 28 06:59:03 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-77883ae5-6ff0-4146-a268-03f36e6d3676 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539615353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc alation.539615353 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.2463391868 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 2781102696 ps |
CPU time | 6.41 seconds |
Started | Jul 28 06:58:33 PM PDT 24 |
Finished | Jul 28 06:58:40 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-6aeda5d1-f0c4-4b54-a955-a78c264b9ad9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463391868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.2463391868 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2339086978 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 1449448731 ps |
CPU time | 74.32 seconds |
Started | Jul 28 06:58:39 PM PDT 24 |
Finished | Jul 28 06:59:53 PM PDT 24 |
Peak memory | 211336 kb |
Host | smart-0c421fad-3909-4b27-83c4-db04f103abd8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339086978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.2339086978 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.92269824 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 7679933136 ps |
CPU time | 161.02 seconds |
Started | Jul 28 06:58:40 PM PDT 24 |
Finished | Jul 28 07:01:21 PM PDT 24 |
Peak memory | 212276 kb |
Host | smart-227512d7-2bab-40c9-83ad-b287ace455fa |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92269824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ mem_walk.92269824 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.2144931955 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 17365663946 ps |
CPU time | 432.05 seconds |
Started | Jul 28 06:58:27 PM PDT 24 |
Finished | Jul 28 07:05:39 PM PDT 24 |
Peak memory | 376876 kb |
Host | smart-26decc79-e840-4f7b-887c-e8f486f10e72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144931955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.2144931955 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.2504491714 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 1739267629 ps |
CPU time | 25.6 seconds |
Started | Jul 28 06:58:27 PM PDT 24 |
Finished | Jul 28 06:58:53 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-ba67a549-9e4e-4dfa-bc26-9f3107077fb4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504491714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.2504491714 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2162642623 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 172354691380 ps |
CPU time | 360.66 seconds |
Started | Jul 28 06:58:32 PM PDT 24 |
Finished | Jul 28 07:04:33 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-3556356f-5671-4800-8986-5f75fd81a1d2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162642623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.2162642623 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.1735902203 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 1344155060 ps |
CPU time | 3.67 seconds |
Started | Jul 28 06:58:40 PM PDT 24 |
Finished | Jul 28 06:58:44 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-faff4fe0-bcb0-497f-aa4a-822fa3866b2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735902203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1735902203 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.2158201145 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 45808550285 ps |
CPU time | 1570.55 seconds |
Started | Jul 28 06:58:40 PM PDT 24 |
Finished | Jul 28 07:24:50 PM PDT 24 |
Peak memory | 380588 kb |
Host | smart-a604c287-405b-47fd-a1f9-71956eb0faa8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158201145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2158201145 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.485218759 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 972279374 ps |
CPU time | 111.07 seconds |
Started | Jul 28 06:58:24 PM PDT 24 |
Finished | Jul 28 07:00:15 PM PDT 24 |
Peak memory | 344056 kb |
Host | smart-ae07bee1-d04f-4a39-a12b-089bb892deac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485218759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.485218759 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.2792484458 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 75173113842 ps |
CPU time | 6513.22 seconds |
Started | Jul 28 06:58:40 PM PDT 24 |
Finished | Jul 28 08:47:14 PM PDT 24 |
Peak memory | 381128 kb |
Host | smart-e0dca935-b216-4b9e-88a6-1711e42427f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792484458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.2792484458 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4135127377 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 6229739838 ps |
CPU time | 234.44 seconds |
Started | Jul 28 06:58:26 PM PDT 24 |
Finished | Jul 28 07:02:20 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-dc090472-aaf5-4317-9f77-ae6820ed9bdc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135127377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.4135127377 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1889687042 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 754740555 ps |
CPU time | 58.93 seconds |
Started | Jul 28 06:58:33 PM PDT 24 |
Finished | Jul 28 06:59:33 PM PDT 24 |
Peak memory | 321660 kb |
Host | smart-0d2eb95a-316b-423a-b9a1-7f1b64c686ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889687042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1889687042 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.4037657152 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 54640659938 ps |
CPU time | 1441.02 seconds |
Started | Jul 28 06:58:47 PM PDT 24 |
Finished | Jul 28 07:22:48 PM PDT 24 |
Peak memory | 376680 kb |
Host | smart-aa14a6cd-fc7c-4dc6-bb77-a5523eb0448a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037657152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.4037657152 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.2461829461 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 10848581 ps |
CPU time | 0.66 seconds |
Started | Jul 28 06:58:56 PM PDT 24 |
Finished | Jul 28 06:58:57 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-10451885-fc7b-4f5c-9b02-ae87be10e64b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461829461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2461829461 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.654032551 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 10794218522 ps |
CPU time | 765.43 seconds |
Started | Jul 28 06:58:55 PM PDT 24 |
Finished | Jul 28 07:11:40 PM PDT 24 |
Peak memory | 374004 kb |
Host | smart-cbe13801-58ec-4f8e-bc38-1b40cbacb033 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654032551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executabl e.654032551 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.3840000657 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 3371304991 ps |
CPU time | 19.61 seconds |
Started | Jul 28 06:58:46 PM PDT 24 |
Finished | Jul 28 06:59:06 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-b2df7afa-b366-4c55-9a79-52e58998205c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840000657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.3840000657 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.3597366954 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 2734106689 ps |
CPU time | 6.56 seconds |
Started | Jul 28 06:58:47 PM PDT 24 |
Finished | Jul 28 06:58:54 PM PDT 24 |
Peak memory | 211296 kb |
Host | smart-2ea9d523-b34e-4a73-ba02-28f6a0102218 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597366954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.3597366954 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.532111304 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 12789927091 ps |
CPU time | 92.26 seconds |
Started | Jul 28 06:58:53 PM PDT 24 |
Finished | Jul 28 07:00:26 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-3aef38c1-3b75-4425-b7cf-a513ac5a60ff |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532111304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .sram_ctrl_mem_partial_access.532111304 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.74398645 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 86312511231 ps |
CPU time | 374.26 seconds |
Started | Jul 28 06:58:53 PM PDT 24 |
Finished | Jul 28 07:05:08 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-0eb88816-df89-4e45-8e7d-b0b0b1ebf5dc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74398645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ mem_walk.74398645 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.471625658 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 7356225039 ps |
CPU time | 126.62 seconds |
Started | Jul 28 06:58:47 PM PDT 24 |
Finished | Jul 28 07:00:54 PM PDT 24 |
Peak memory | 327912 kb |
Host | smart-f7be8f62-67ee-429e-a805-885d564ec64c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471625658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip le_keys.471625658 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.3651099330 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 1084225723 ps |
CPU time | 14.71 seconds |
Started | Jul 28 06:58:46 PM PDT 24 |
Finished | Jul 28 06:59:01 PM PDT 24 |
Peak memory | 203092 kb |
Host | smart-0819ddb9-cf3b-4396-9662-d7a051f556a6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651099330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3651099330 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1259602200 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 56051877160 ps |
CPU time | 303.47 seconds |
Started | Jul 28 06:58:49 PM PDT 24 |
Finished | Jul 28 07:03:52 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-5a072209-deef-445c-a630-fd7c38970458 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259602200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.1259602200 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.2610353571 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 351321102 ps |
CPU time | 3.36 seconds |
Started | Jul 28 06:58:55 PM PDT 24 |
Finished | Jul 28 06:58:58 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-83aa5005-931b-4000-9841-71f74bf83784 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610353571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2610353571 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.251920074 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 18054774730 ps |
CPU time | 282.91 seconds |
Started | Jul 28 06:58:56 PM PDT 24 |
Finished | Jul 28 07:03:39 PM PDT 24 |
Peak memory | 358548 kb |
Host | smart-96c1c7ed-81b5-4007-8e7f-64c5af007556 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251920074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.251920074 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.2810929592 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 3142107364 ps |
CPU time | 14.96 seconds |
Started | Jul 28 06:58:40 PM PDT 24 |
Finished | Jul 28 06:58:55 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-263947f2-28bf-47db-a390-ee95ab77c44b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810929592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2810929592 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.2256554613 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 191192458120 ps |
CPU time | 5066.06 seconds |
Started | Jul 28 06:58:54 PM PDT 24 |
Finished | Jul 28 08:23:21 PM PDT 24 |
Peak memory | 376948 kb |
Host | smart-51ca9c30-2177-46d0-88c7-bd255af0de4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256554613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.2256554613 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2370225560 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 546770454 ps |
CPU time | 10.91 seconds |
Started | Jul 28 06:58:53 PM PDT 24 |
Finished | Jul 28 06:59:04 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-7f6aa778-c607-475b-8317-914156ace16d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2370225560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2370225560 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1248757197 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 7378745548 ps |
CPU time | 216.7 seconds |
Started | Jul 28 06:58:44 PM PDT 24 |
Finished | Jul 28 07:02:21 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-1cda0dde-422d-4c37-bff6-ecce198858e3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248757197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1248757197 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2032325771 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 5857047117 ps |
CPU time | 68 seconds |
Started | Jul 28 06:58:49 PM PDT 24 |
Finished | Jul 28 06:59:57 PM PDT 24 |
Peak memory | 345312 kb |
Host | smart-9f256116-11ff-4fc3-9157-e71f828cd3fb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032325771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.2032325771 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3230250790 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 18644185978 ps |
CPU time | 846.8 seconds |
Started | Jul 28 06:59:00 PM PDT 24 |
Finished | Jul 28 07:13:07 PM PDT 24 |
Peak memory | 361468 kb |
Host | smart-256d5f34-590d-4b22-ba07-bea9bf1e02cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230250790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.3230250790 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.226128336 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 43571079 ps |
CPU time | 0.66 seconds |
Started | Jul 28 06:59:19 PM PDT 24 |
Finished | Jul 28 06:59:20 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-fa53168a-3f51-4e56-9beb-b18fcf1d8945 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226128336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.226128336 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.2952659996 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 15737889502 ps |
CPU time | 322.8 seconds |
Started | Jul 28 06:58:59 PM PDT 24 |
Finished | Jul 28 07:04:22 PM PDT 24 |
Peak memory | 358624 kb |
Host | smart-ad123297-ac84-4be9-9fad-28126a937f3d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952659996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.2952659996 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.2728872352 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 37572243475 ps |
CPU time | 51.23 seconds |
Started | Jul 28 06:58:59 PM PDT 24 |
Finished | Jul 28 06:59:50 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-1d4d29ed-cfbf-492c-947c-017aa272c9e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728872352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.2728872352 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.3421662592 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 761617308 ps |
CPU time | 61.04 seconds |
Started | Jul 28 06:58:58 PM PDT 24 |
Finished | Jul 28 06:59:59 PM PDT 24 |
Peak memory | 337964 kb |
Host | smart-f7b522c3-6a0d-49e4-a767-ad3cf48c86a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421662592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.3421662592 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2636944755 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 4025230502 ps |
CPU time | 66.56 seconds |
Started | Jul 28 06:59:14 PM PDT 24 |
Finished | Jul 28 07:00:21 PM PDT 24 |
Peak memory | 219564 kb |
Host | smart-7b827de6-a39c-42cb-9322-af0d17eb028e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636944755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.2636944755 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.161443336 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 15766467179 ps |
CPU time | 273.64 seconds |
Started | Jul 28 06:59:04 PM PDT 24 |
Finished | Jul 28 07:03:38 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-5e5ae606-6b43-496e-bd80-3d6f49f96c91 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161443336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl _mem_walk.161443336 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.1581952601 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 72337273168 ps |
CPU time | 895.77 seconds |
Started | Jul 28 06:58:55 PM PDT 24 |
Finished | Jul 28 07:13:51 PM PDT 24 |
Peak memory | 374900 kb |
Host | smart-10ef68bf-d724-440b-adcb-1fcad6679201 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581952601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.1581952601 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.1582324471 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 1482795576 ps |
CPU time | 21.03 seconds |
Started | Jul 28 06:58:57 PM PDT 24 |
Finished | Jul 28 06:59:18 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-b87835ef-1d4c-4abd-8483-654e0f4402a6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582324471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.1582324471 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1482564416 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 80140965108 ps |
CPU time | 407.43 seconds |
Started | Jul 28 06:58:59 PM PDT 24 |
Finished | Jul 28 07:05:47 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-dd819c96-8ab7-4810-b586-fd4fadce9092 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482564416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.1482564416 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.208409086 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 348508239 ps |
CPU time | 3.23 seconds |
Started | Jul 28 06:59:04 PM PDT 24 |
Finished | Jul 28 06:59:07 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-28e7fef2-2864-4f7c-a0af-1c7ac17d9572 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208409086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.208409086 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.3035685680 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 69301923832 ps |
CPU time | 737.14 seconds |
Started | Jul 28 06:59:01 PM PDT 24 |
Finished | Jul 28 07:11:18 PM PDT 24 |
Peak memory | 370788 kb |
Host | smart-8930982a-6241-487a-91cf-c99f471b658c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035685680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3035685680 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.2583748269 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 2090016442 ps |
CPU time | 15.53 seconds |
Started | Jul 28 06:58:56 PM PDT 24 |
Finished | Jul 28 06:59:11 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-1bdf3299-81fc-4838-85b7-213022b0b9ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583748269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2583748269 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.2466195274 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 445870281833 ps |
CPU time | 3148.53 seconds |
Started | Jul 28 06:59:03 PM PDT 24 |
Finished | Jul 28 07:51:32 PM PDT 24 |
Peak memory | 390308 kb |
Host | smart-af81e3e2-e4d2-4ef1-ac4c-756b760f87ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466195274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.2466195274 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3640702616 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 1014555097 ps |
CPU time | 8.79 seconds |
Started | Jul 28 06:59:03 PM PDT 24 |
Finished | Jul 28 06:59:12 PM PDT 24 |
Peak memory | 211344 kb |
Host | smart-e70d01f1-d50a-4167-b27d-db975333e712 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3640702616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3640702616 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.612008707 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 4920205058 ps |
CPU time | 329.84 seconds |
Started | Jul 28 06:58:58 PM PDT 24 |
Finished | Jul 28 07:04:28 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-ce905854-f2ee-4a58-9f27-3d20da06b77c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612008707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .sram_ctrl_stress_pipeline.612008707 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3404690263 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 1480567473 ps |
CPU time | 13.67 seconds |
Started | Jul 28 06:59:00 PM PDT 24 |
Finished | Jul 28 06:59:14 PM PDT 24 |
Peak memory | 238620 kb |
Host | smart-fd73a1d1-0c58-42b2-b323-bd3d95074ab1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404690263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.3404690263 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3721255912 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 36285579859 ps |
CPU time | 786.33 seconds |
Started | Jul 28 06:59:24 PM PDT 24 |
Finished | Jul 28 07:12:31 PM PDT 24 |
Peak memory | 363708 kb |
Host | smart-10fcf7ac-8303-4ac9-839e-7847aa370620 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721255912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.3721255912 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.926634813 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 29824771 ps |
CPU time | 0.68 seconds |
Started | Jul 28 06:59:27 PM PDT 24 |
Finished | Jul 28 06:59:28 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-aec318f2-bb95-43e0-a4e3-1c4d42322f52 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926634813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.926634813 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.597959868 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 215563308480 ps |
CPU time | 1828.92 seconds |
Started | Jul 28 06:59:11 PM PDT 24 |
Finished | Jul 28 07:29:40 PM PDT 24 |
Peak memory | 203756 kb |
Host | smart-365681dd-7e2f-4f5c-898f-36db5e664073 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597959868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection. 597959868 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.2129869599 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 19213263409 ps |
CPU time | 1315.99 seconds |
Started | Jul 28 06:59:19 PM PDT 24 |
Finished | Jul 28 07:21:15 PM PDT 24 |
Peak memory | 380000 kb |
Host | smart-52bc6655-c4ca-46b7-9475-c9ddb29b7e26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129869599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.2129869599 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.686649937 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 41532219933 ps |
CPU time | 59.97 seconds |
Started | Jul 28 06:59:17 PM PDT 24 |
Finished | Jul 28 07:00:17 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-2c9d791f-399d-4370-9380-cc7887bf6c5f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686649937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc alation.686649937 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.3984070036 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 2919382765 ps |
CPU time | 54.11 seconds |
Started | Jul 28 06:59:07 PM PDT 24 |
Finished | Jul 28 07:00:01 PM PDT 24 |
Peak memory | 307416 kb |
Host | smart-5a1fd06c-a93f-4204-aeaa-be667542a2c5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984070036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.3984070036 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.3966448467 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 6373156869 ps |
CPU time | 123.61 seconds |
Started | Jul 28 06:59:15 PM PDT 24 |
Finished | Jul 28 07:01:19 PM PDT 24 |
Peak memory | 211548 kb |
Host | smart-da3ccd4f-32ac-438f-a8f3-e0686adbccfa |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966448467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.3966448467 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.1885378058 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 21106475519 ps |
CPU time | 345.98 seconds |
Started | Jul 28 06:59:18 PM PDT 24 |
Finished | Jul 28 07:05:04 PM PDT 24 |
Peak memory | 203588 kb |
Host | smart-f36440a7-d157-4aba-8e4b-ecb8fe39dd55 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885378058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.1885378058 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.1670735191 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 25271522737 ps |
CPU time | 1663.9 seconds |
Started | Jul 28 06:59:10 PM PDT 24 |
Finished | Jul 28 07:26:54 PM PDT 24 |
Peak memory | 381108 kb |
Host | smart-d79367a8-d066-4be9-9c1e-fe5885d9c2fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670735191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.1670735191 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.2228927281 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 907048415 ps |
CPU time | 19.17 seconds |
Started | Jul 28 06:59:09 PM PDT 24 |
Finished | Jul 28 06:59:28 PM PDT 24 |
Peak memory | 203084 kb |
Host | smart-828ed7bb-e36a-4bd1-8a71-e312d0170704 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228927281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.2228927281 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3451422178 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 13568958150 ps |
CPU time | 304.17 seconds |
Started | Jul 28 06:59:10 PM PDT 24 |
Finished | Jul 28 07:04:15 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-7bf458ab-8bf1-4af1-9780-6ba9e9828e8d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451422178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.3451422178 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.2667386238 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 353863852 ps |
CPU time | 3.36 seconds |
Started | Jul 28 06:59:21 PM PDT 24 |
Finished | Jul 28 06:59:25 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-7c09fa32-1b3c-455e-9e23-67b8f7be12a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667386238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2667386238 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.802292303 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 3745699700 ps |
CPU time | 702.87 seconds |
Started | Jul 28 06:59:19 PM PDT 24 |
Finished | Jul 28 07:11:02 PM PDT 24 |
Peak memory | 370808 kb |
Host | smart-2d186101-817e-4aca-bbf1-3e6cf465788d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802292303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.802292303 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.747709501 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 3589367525 ps |
CPU time | 12.85 seconds |
Started | Jul 28 06:59:16 PM PDT 24 |
Finished | Jul 28 06:59:29 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-6cbf173d-1c52-4865-8489-5c5991f9f6ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747709501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.747709501 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.2401469359 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 110720829897 ps |
CPU time | 3278.16 seconds |
Started | Jul 28 06:59:26 PM PDT 24 |
Finished | Jul 28 07:54:04 PM PDT 24 |
Peak memory | 382108 kb |
Host | smart-1e6a6f40-1354-4840-ba6b-0c0c5dffeb43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401469359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.2401469359 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.4175395447 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 1190573211 ps |
CPU time | 30.7 seconds |
Started | Jul 28 06:59:20 PM PDT 24 |
Finished | Jul 28 06:59:51 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-8a9f6338-95c4-4da8-8d9b-dd86615ea8ee |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4175395447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.4175395447 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3430798428 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 38629918047 ps |
CPU time | 180.86 seconds |
Started | Jul 28 06:59:09 PM PDT 24 |
Finished | Jul 28 07:02:10 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-ee39556d-5f43-4881-ace7-8860c4376220 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430798428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.3430798428 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1984428890 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 1516725622 ps |
CPU time | 36.66 seconds |
Started | Jul 28 06:59:17 PM PDT 24 |
Finished | Jul 28 06:59:54 PM PDT 24 |
Peak memory | 294040 kb |
Host | smart-91855f12-000d-4a77-b147-73f13c7183b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984428890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1984428890 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2870904750 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 30054554984 ps |
CPU time | 683.07 seconds |
Started | Jul 28 06:59:33 PM PDT 24 |
Finished | Jul 28 07:10:56 PM PDT 24 |
Peak memory | 372548 kb |
Host | smart-97ef59db-5bd4-425d-b553-bb13bb24e614 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870904750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.2870904750 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.2890104286 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 15587115 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:59:32 PM PDT 24 |
Finished | Jul 28 06:59:33 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-716bc40c-184d-451e-b708-a84d2fe4db73 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890104286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.2890104286 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.2141230208 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 36173375263 ps |
CPU time | 587.47 seconds |
Started | Jul 28 06:59:25 PM PDT 24 |
Finished | Jul 28 07:09:13 PM PDT 24 |
Peak memory | 203688 kb |
Host | smart-dd4f54aa-ad5f-45ea-ab86-915b340ecb0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141230208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2141230208 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.1702860314 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 90506034961 ps |
CPU time | 128.67 seconds |
Started | Jul 28 06:59:26 PM PDT 24 |
Finished | Jul 28 07:01:35 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-47843958-f6b6-4fc8-9d2c-d042fcc101b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702860314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.1702860314 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.2139664528 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 747900627 ps |
CPU time | 40.86 seconds |
Started | Jul 28 06:59:25 PM PDT 24 |
Finished | Jul 28 07:00:06 PM PDT 24 |
Peak memory | 295484 kb |
Host | smart-6d014426-2a95-41ca-acb5-021c412fa359 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139664528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.2139664528 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3140353145 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 3940266240 ps |
CPU time | 83.87 seconds |
Started | Jul 28 06:59:32 PM PDT 24 |
Finished | Jul 28 07:00:56 PM PDT 24 |
Peak memory | 211372 kb |
Host | smart-ab8cbd55-f4da-4ed7-89cf-457578002b70 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140353145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.3140353145 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.833016053 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 2085836512 ps |
CPU time | 119.49 seconds |
Started | Jul 28 06:59:31 PM PDT 24 |
Finished | Jul 28 07:01:31 PM PDT 24 |
Peak memory | 211292 kb |
Host | smart-2925500c-bf5a-4f3d-9b55-14e4d7c76f9a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833016053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _mem_walk.833016053 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.3950999891 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 150067553868 ps |
CPU time | 1569.51 seconds |
Started | Jul 28 06:59:26 PM PDT 24 |
Finished | Jul 28 07:25:35 PM PDT 24 |
Peak memory | 381148 kb |
Host | smart-f996e63b-bf36-4963-b738-45b6c2b64315 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950999891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.3950999891 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.3795711921 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 3978664321 ps |
CPU time | 109.4 seconds |
Started | Jul 28 06:59:26 PM PDT 24 |
Finished | Jul 28 07:01:16 PM PDT 24 |
Peak memory | 353408 kb |
Host | smart-ebaa4f0a-042e-431d-ac4f-da5db3944355 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795711921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.3795711921 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.639925199 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 3692136243 ps |
CPU time | 206.35 seconds |
Started | Jul 28 06:59:25 PM PDT 24 |
Finished | Jul 28 07:02:52 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-01a4bca8-73e6-47d4-8efb-492165585d9b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639925199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.sram_ctrl_partial_access_b2b.639925199 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.3126851355 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 360053558 ps |
CPU time | 3.31 seconds |
Started | Jul 28 06:59:34 PM PDT 24 |
Finished | Jul 28 06:59:37 PM PDT 24 |
Peak memory | 203052 kb |
Host | smart-f1de1567-5a54-479b-a8f4-368b342c4bbc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126851355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3126851355 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.284791147 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 124929636065 ps |
CPU time | 458.1 seconds |
Started | Jul 28 06:59:32 PM PDT 24 |
Finished | Jul 28 07:07:11 PM PDT 24 |
Peak memory | 358552 kb |
Host | smart-2328cc53-336e-4f66-839d-e551094047c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284791147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.284791147 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.4013190932 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 642692232 ps |
CPU time | 27.23 seconds |
Started | Jul 28 06:59:25 PM PDT 24 |
Finished | Jul 28 06:59:52 PM PDT 24 |
Peak memory | 272540 kb |
Host | smart-b9016de3-3c74-4c7a-9970-f78bfe79db80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013190932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.4013190932 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.3715851428 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 238771160781 ps |
CPU time | 2555.06 seconds |
Started | Jul 28 06:59:30 PM PDT 24 |
Finished | Jul 28 07:42:06 PM PDT 24 |
Peak memory | 385176 kb |
Host | smart-0c516b13-6652-42d1-be8d-66f03baf8db9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715851428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.3715851428 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2505773372 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 3249799908 ps |
CPU time | 90.06 seconds |
Started | Jul 28 06:59:34 PM PDT 24 |
Finished | Jul 28 07:01:04 PM PDT 24 |
Peak memory | 219696 kb |
Host | smart-4b0b6553-570e-49d5-a3d7-8906dd10ab1b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2505773372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2505773372 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.4283308477 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 23972548228 ps |
CPU time | 232.87 seconds |
Started | Jul 28 06:59:23 PM PDT 24 |
Finished | Jul 28 07:03:16 PM PDT 24 |
Peak memory | 203388 kb |
Host | smart-60dfb4d4-f868-453f-b9d8-699a66fce2c0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283308477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.4283308477 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.766536445 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 3844143028 ps |
CPU time | 118.01 seconds |
Started | Jul 28 06:59:27 PM PDT 24 |
Finished | Jul 28 07:01:25 PM PDT 24 |
Peak memory | 355492 kb |
Host | smart-59fa9e43-7d14-4f2b-b889-6baccb35f9d2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766536445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.766536445 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.285050484 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 43779517427 ps |
CPU time | 465.17 seconds |
Started | Jul 28 06:59:47 PM PDT 24 |
Finished | Jul 28 07:07:32 PM PDT 24 |
Peak memory | 343340 kb |
Host | smart-3df806da-31e0-485d-af21-765bbdbd0073 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285050484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sram_ctrl_access_during_key_req.285050484 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.904144054 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 20355452 ps |
CPU time | 0.66 seconds |
Started | Jul 28 06:59:54 PM PDT 24 |
Finished | Jul 28 06:59:55 PM PDT 24 |
Peak memory | 202668 kb |
Host | smart-99565dce-91bb-4b4f-af82-dbebac694c76 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904144054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.904144054 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.1535584836 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 58703602197 ps |
CPU time | 2130.46 seconds |
Started | Jul 28 06:59:37 PM PDT 24 |
Finished | Jul 28 07:35:08 PM PDT 24 |
Peak memory | 203304 kb |
Host | smart-a6fa9488-fa7a-4839-9d13-4addb6fc2fcd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535584836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .1535584836 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.4283209777 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 10760294683 ps |
CPU time | 513.67 seconds |
Started | Jul 28 06:59:44 PM PDT 24 |
Finished | Jul 28 07:08:18 PM PDT 24 |
Peak memory | 371768 kb |
Host | smart-0cb422d5-0c30-4736-850a-f8c0318604a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283209777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.4283209777 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.768099771 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 362507978 ps |
CPU time | 3.6 seconds |
Started | Jul 28 06:59:45 PM PDT 24 |
Finished | Jul 28 06:59:49 PM PDT 24 |
Peak memory | 214732 kb |
Host | smart-94a873dc-6458-494a-b805-e8b4e43e2891 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768099771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_esc alation.768099771 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.1967280127 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 3083530015 ps |
CPU time | 67.5 seconds |
Started | Jul 28 06:59:37 PM PDT 24 |
Finished | Jul 28 07:00:44 PM PDT 24 |
Peak memory | 332072 kb |
Host | smart-b6f9a631-8786-45fe-aadf-1d22659c3cbf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967280127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.1967280127 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.1942041599 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 1412270013 ps |
CPU time | 72.2 seconds |
Started | Jul 28 06:59:45 PM PDT 24 |
Finished | Jul 28 07:00:58 PM PDT 24 |
Peak memory | 211320 kb |
Host | smart-a4f9fb35-4f56-4846-a0d6-52207756bdea |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942041599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.1942041599 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.3104021745 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 4065069459 ps |
CPU time | 252.2 seconds |
Started | Jul 28 06:59:43 PM PDT 24 |
Finished | Jul 28 07:03:56 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-7486a3a7-f7ee-4d8b-9031-2f1cecfa67ff |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104021745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.3104021745 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.883371938 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 42002042730 ps |
CPU time | 674.18 seconds |
Started | Jul 28 06:59:40 PM PDT 24 |
Finished | Jul 28 07:10:54 PM PDT 24 |
Peak memory | 372980 kb |
Host | smart-b18b59e5-01b8-4c40-914a-f2e8681f1c78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883371938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multip le_keys.883371938 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.2087404982 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 3363491400 ps |
CPU time | 70.71 seconds |
Started | Jul 28 06:59:38 PM PDT 24 |
Finished | Jul 28 07:00:49 PM PDT 24 |
Peak memory | 322016 kb |
Host | smart-91e2260e-0b9c-4e04-a115-aefa8a8da97b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087404982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.2087404982 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4132645580 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 20253904519 ps |
CPU time | 459.61 seconds |
Started | Jul 28 06:59:40 PM PDT 24 |
Finished | Jul 28 07:07:20 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-0d3ae416-2fcd-4dc5-9ed1-7df5f745e7ed |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132645580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.4132645580 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.2124796806 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 346985656 ps |
CPU time | 3.17 seconds |
Started | Jul 28 06:59:44 PM PDT 24 |
Finished | Jul 28 06:59:48 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-a3d6be67-2a3d-4cdf-810d-a750ba87d8e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124796806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2124796806 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.1448832000 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 3931444522 ps |
CPU time | 770.84 seconds |
Started | Jul 28 06:59:44 PM PDT 24 |
Finished | Jul 28 07:12:35 PM PDT 24 |
Peak memory | 379096 kb |
Host | smart-dedae2e3-6431-4ef8-8812-5c9652477a43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448832000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1448832000 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.61396157 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 804893760 ps |
CPU time | 107.5 seconds |
Started | Jul 28 06:59:31 PM PDT 24 |
Finished | Jul 28 07:01:19 PM PDT 24 |
Peak memory | 356368 kb |
Host | smart-75c0eb74-5b0e-44f0-b9dd-c5efc2e904e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61396157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.61396157 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.2665570369 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 75386392604 ps |
CPU time | 2874.24 seconds |
Started | Jul 28 06:59:53 PM PDT 24 |
Finished | Jul 28 07:47:48 PM PDT 24 |
Peak memory | 383184 kb |
Host | smart-6b486b7d-97d6-4ba7-82f8-bfaf8b4e67c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665570369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.2665570369 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.418569867 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 2884115605 ps |
CPU time | 45.06 seconds |
Started | Jul 28 06:59:53 PM PDT 24 |
Finished | Jul 28 07:00:38 PM PDT 24 |
Peak memory | 223428 kb |
Host | smart-0cb48d8e-6e15-4170-87b7-02140414532c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=418569867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.418569867 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1261863614 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 4235379496 ps |
CPU time | 225.91 seconds |
Started | Jul 28 06:59:35 PM PDT 24 |
Finished | Jul 28 07:03:21 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-c79c9e56-7104-4f62-8ec3-213db83cc183 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261863614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1261863614 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2060612810 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 811341551 ps |
CPU time | 87.22 seconds |
Started | Jul 28 06:59:38 PM PDT 24 |
Finished | Jul 28 07:01:05 PM PDT 24 |
Peak memory | 348616 kb |
Host | smart-6252e4f9-2609-436f-9698-3756c7e23ad4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060612810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.2060612810 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3956496118 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 17368947091 ps |
CPU time | 1137.61 seconds |
Started | Jul 28 06:51:48 PM PDT 24 |
Finished | Jul 28 07:10:45 PM PDT 24 |
Peak memory | 373912 kb |
Host | smart-d63c4060-f5fc-4295-950f-66ad5ff3659c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956496118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.3956496118 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.294861231 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 105659136 ps |
CPU time | 0.66 seconds |
Started | Jul 28 06:51:58 PM PDT 24 |
Finished | Jul 28 06:51:59 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-906a60d0-f8a4-4eac-8096-c58b57dc0bf2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294861231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.294861231 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.1635327865 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 91167228107 ps |
CPU time | 2057.13 seconds |
Started | Jul 28 06:51:44 PM PDT 24 |
Finished | Jul 28 07:26:02 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-6bf91a92-620b-40b9-a37d-3cbddd44affa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635327865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 1635327865 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.979655005 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 26283221670 ps |
CPU time | 1337.78 seconds |
Started | Jul 28 06:51:47 PM PDT 24 |
Finished | Jul 28 07:14:05 PM PDT 24 |
Peak memory | 381132 kb |
Host | smart-c0904b88-724e-47f0-b3d3-8795f9697818 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979655005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable .979655005 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.112878247 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 23890989835 ps |
CPU time | 36.1 seconds |
Started | Jul 28 06:51:48 PM PDT 24 |
Finished | Jul 28 06:52:24 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-747eea4f-28ea-4447-874f-4fe6e12aee84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112878247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca lation.112878247 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.990481778 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 10244353144 ps |
CPU time | 32.5 seconds |
Started | Jul 28 06:51:47 PM PDT 24 |
Finished | Jul 28 06:52:20 PM PDT 24 |
Peak memory | 291168 kb |
Host | smart-3965000f-4269-428e-b03c-1a69633cda6c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990481778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.sram_ctrl_max_throughput.990481778 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2014106267 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 10623898911 ps |
CPU time | 128.56 seconds |
Started | Jul 28 06:51:55 PM PDT 24 |
Finished | Jul 28 06:54:04 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-63c734c3-4029-465d-8a89-6a48ba0c4a58 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014106267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.2014106267 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.2202645539 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 10727700923 ps |
CPU time | 275.83 seconds |
Started | Jul 28 06:51:54 PM PDT 24 |
Finished | Jul 28 06:56:30 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-e9bb9f52-6f7d-41b1-b820-923ff430c632 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202645539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.2202645539 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.926599021 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 6603279659 ps |
CPU time | 445.69 seconds |
Started | Jul 28 06:51:43 PM PDT 24 |
Finished | Jul 28 06:59:10 PM PDT 24 |
Peak memory | 380016 kb |
Host | smart-3e3a38f9-e4c4-4640-8a97-79cb78b5a8c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926599021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl e_keys.926599021 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.4240936074 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 1455052681 ps |
CPU time | 9.52 seconds |
Started | Jul 28 06:51:44 PM PDT 24 |
Finished | Jul 28 06:51:54 PM PDT 24 |
Peak memory | 222116 kb |
Host | smart-9d18e443-de7a-47f3-960d-87e75c2a022b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240936074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.4240936074 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3063121997 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 14156999371 ps |
CPU time | 348.88 seconds |
Started | Jul 28 06:51:43 PM PDT 24 |
Finished | Jul 28 06:57:32 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-f5f5f9c7-ae26-4821-94d1-a989fd3ed563 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063121997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.3063121997 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.4052195863 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 1408767025 ps |
CPU time | 3.69 seconds |
Started | Jul 28 06:51:55 PM PDT 24 |
Finished | Jul 28 06:51:58 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-da07a0b0-b364-4938-b543-b0c4ab271e4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052195863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.4052195863 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.756344446 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 21647398906 ps |
CPU time | 708.43 seconds |
Started | Jul 28 06:51:46 PM PDT 24 |
Finished | Jul 28 07:03:35 PM PDT 24 |
Peak memory | 379016 kb |
Host | smart-39eda22b-7939-46a8-82b6-c7aeea291ec2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756344446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.756344446 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.3146671692 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 4033692492 ps |
CPU time | 107.36 seconds |
Started | Jul 28 06:51:45 PM PDT 24 |
Finished | Jul 28 06:53:32 PM PDT 24 |
Peak memory | 353836 kb |
Host | smart-5c6d954c-5dc6-46e0-b19f-2cf0e098d22a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146671692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3146671692 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3648592570 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 1052216764 ps |
CPU time | 21.71 seconds |
Started | Jul 28 06:51:55 PM PDT 24 |
Finished | Jul 28 06:52:17 PM PDT 24 |
Peak memory | 211312 kb |
Host | smart-fb4f2c92-25f4-4f3e-916e-5dc4e8bed47f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3648592570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3648592570 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2084604967 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 2940425862 ps |
CPU time | 183.41 seconds |
Started | Jul 28 06:51:44 PM PDT 24 |
Finished | Jul 28 06:54:47 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-cde13d72-f3bf-4b2a-a1f8-21ab4397a3fc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084604967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.2084604967 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.27432078 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 15652343996 ps |
CPU time | 146.71 seconds |
Started | Jul 28 06:51:49 PM PDT 24 |
Finished | Jul 28 06:54:16 PM PDT 24 |
Peak memory | 371100 kb |
Host | smart-2dab3a84-adfa-4329-af16-2b242fcd276b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27432078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.sram_ctrl_throughput_w_partial_write.27432078 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2469427574 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 37331755809 ps |
CPU time | 1163.03 seconds |
Started | Jul 28 06:59:57 PM PDT 24 |
Finished | Jul 28 07:19:20 PM PDT 24 |
Peak memory | 378028 kb |
Host | smart-ab48eb9e-b705-4fca-83ba-1e77f1856265 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469427574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.2469427574 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.534680922 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 25647916 ps |
CPU time | 0.68 seconds |
Started | Jul 28 07:00:16 PM PDT 24 |
Finished | Jul 28 07:00:16 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-813a01bd-7171-468f-987c-3300eca1a069 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534680922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.534680922 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.855158357 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 154658244615 ps |
CPU time | 812.71 seconds |
Started | Jul 28 06:59:54 PM PDT 24 |
Finished | Jul 28 07:13:27 PM PDT 24 |
Peak memory | 203860 kb |
Host | smart-04d198e6-1926-469f-8238-da2169715976 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855158357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection. 855158357 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.3524815638 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 38318472706 ps |
CPU time | 964.7 seconds |
Started | Jul 28 07:00:03 PM PDT 24 |
Finished | Jul 28 07:16:10 PM PDT 24 |
Peak memory | 375920 kb |
Host | smart-fd1da3ae-baff-4aba-88f5-79a2659a80ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524815638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.3524815638 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.3007169432 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 11586761103 ps |
CPU time | 69.02 seconds |
Started | Jul 28 06:59:58 PM PDT 24 |
Finished | Jul 28 07:01:08 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-865ea74e-39b0-4e72-93c0-7be7d537573e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007169432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.3007169432 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.663516253 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 7513034886 ps |
CPU time | 11.18 seconds |
Started | Jul 28 07:00:01 PM PDT 24 |
Finished | Jul 28 07:00:12 PM PDT 24 |
Peak memory | 224124 kb |
Host | smart-8f461201-0b6c-4402-803f-9f5835b2deda |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663516253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.sram_ctrl_max_throughput.663516253 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.4271575188 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 6024574883 ps |
CPU time | 80.88 seconds |
Started | Jul 28 07:00:14 PM PDT 24 |
Finished | Jul 28 07:01:35 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-6f7059fd-7c59-4def-b099-a58e8c49af97 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271575188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.4271575188 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.1396110846 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 17434157696 ps |
CPU time | 896.84 seconds |
Started | Jul 28 06:59:52 PM PDT 24 |
Finished | Jul 28 07:14:49 PM PDT 24 |
Peak memory | 375956 kb |
Host | smart-1741b2f4-10af-4220-97bf-ccd807a98edd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396110846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.1396110846 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.4283973565 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 894673338 ps |
CPU time | 113.31 seconds |
Started | Jul 28 06:59:57 PM PDT 24 |
Finished | Jul 28 07:01:50 PM PDT 24 |
Peak memory | 349172 kb |
Host | smart-b49f5b44-20f2-4ed3-9744-acf5427979e4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283973565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.4283973565 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.682065730 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 22159615557 ps |
CPU time | 345.12 seconds |
Started | Jul 28 06:59:59 PM PDT 24 |
Finished | Jul 28 07:05:44 PM PDT 24 |
Peak memory | 203204 kb |
Host | smart-39e8d927-5842-4d96-80b5-364c4cb0c1e5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682065730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.sram_ctrl_partial_access_b2b.682065730 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.1700595829 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 1412987720 ps |
CPU time | 3.41 seconds |
Started | Jul 28 07:00:05 PM PDT 24 |
Finished | Jul 28 07:00:09 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-0e49ac40-09ac-4b35-82b2-d0fcd597d367 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700595829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1700595829 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.2922191167 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 41733473641 ps |
CPU time | 891.03 seconds |
Started | Jul 28 07:00:06 PM PDT 24 |
Finished | Jul 28 07:14:57 PM PDT 24 |
Peak memory | 377948 kb |
Host | smart-e9aea39e-8411-4923-8b72-7eadc5121c06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922191167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2922191167 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.2208493012 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 11309961324 ps |
CPU time | 13.02 seconds |
Started | Jul 28 06:59:52 PM PDT 24 |
Finished | Jul 28 07:00:05 PM PDT 24 |
Peak memory | 226980 kb |
Host | smart-6a2b4e95-4d94-4783-bd14-c6afb76ae297 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208493012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2208493012 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.2317973583 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 106097730509 ps |
CPU time | 2272.28 seconds |
Started | Jul 28 07:00:16 PM PDT 24 |
Finished | Jul 28 07:38:08 PM PDT 24 |
Peak memory | 390300 kb |
Host | smart-c5b2d2fb-46a5-40c6-9ec5-12b7348467f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317973583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.2317973583 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.110058570 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 3751806681 ps |
CPU time | 42.77 seconds |
Started | Jul 28 07:00:13 PM PDT 24 |
Finished | Jul 28 07:00:56 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-f26bb1ae-1e08-4d79-baf9-fa877182354b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=110058570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.110058570 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3862506849 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 2311294066 ps |
CPU time | 143.57 seconds |
Started | Jul 28 06:59:52 PM PDT 24 |
Finished | Jul 28 07:02:16 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-69c41989-1f12-4bd9-ba68-a17e32a0a66e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862506849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.3862506849 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1096135006 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 696201708 ps |
CPU time | 10.53 seconds |
Started | Jul 28 06:59:58 PM PDT 24 |
Finished | Jul 28 07:00:09 PM PDT 24 |
Peak memory | 235836 kb |
Host | smart-6cf71817-2583-4e28-b771-fef28d5ed441 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096135006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1096135006 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1029412494 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 40687532393 ps |
CPU time | 547.08 seconds |
Started | Jul 28 07:00:29 PM PDT 24 |
Finished | Jul 28 07:09:37 PM PDT 24 |
Peak memory | 378032 kb |
Host | smart-eea125c6-0d8f-411b-a4f2-9e7e3d3030b2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029412494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.1029412494 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.796291360 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 71155218 ps |
CPU time | 0.65 seconds |
Started | Jul 28 07:00:25 PM PDT 24 |
Finished | Jul 28 07:00:25 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-23c51dd5-7d80-4af0-b344-319eb8cb1121 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796291360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.796291360 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.3986278340 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 135110501518 ps |
CPU time | 2218.69 seconds |
Started | Jul 28 07:00:14 PM PDT 24 |
Finished | Jul 28 07:37:13 PM PDT 24 |
Peak memory | 203936 kb |
Host | smart-1192a4f0-7528-40bb-8ef8-100516e5144e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986278340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .3986278340 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.3662276081 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 6392515858 ps |
CPU time | 646.02 seconds |
Started | Jul 28 07:00:28 PM PDT 24 |
Finished | Jul 28 07:11:14 PM PDT 24 |
Peak memory | 378984 kb |
Host | smart-438265ec-61a7-4863-a2c5-500613c0986e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662276081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.3662276081 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.3836064250 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 67068278151 ps |
CPU time | 111.31 seconds |
Started | Jul 28 07:00:20 PM PDT 24 |
Finished | Jul 28 07:02:11 PM PDT 24 |
Peak memory | 216472 kb |
Host | smart-32c5656a-53e1-4bb8-8e4c-600fff587256 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836064250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3836064250 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.2339675256 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 1489554711 ps |
CPU time | 59.92 seconds |
Started | Jul 28 07:00:20 PM PDT 24 |
Finished | Jul 28 07:01:20 PM PDT 24 |
Peak memory | 331808 kb |
Host | smart-f1c5af04-fe7d-4b15-998a-3e9d1b628223 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339675256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.2339675256 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1655720972 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 20410401867 ps |
CPU time | 166.59 seconds |
Started | Jul 28 07:00:29 PM PDT 24 |
Finished | Jul 28 07:03:15 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-ba12e801-5efb-42e0-9e2d-d5a8be2c3749 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655720972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.1655720972 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.2187696575 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 21809891435 ps |
CPU time | 356.82 seconds |
Started | Jul 28 07:00:28 PM PDT 24 |
Finished | Jul 28 07:06:25 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-90df0bda-79cb-4fe4-8e5e-1fa20cd9785d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187696575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.2187696575 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.4137452161 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 3138579837 ps |
CPU time | 432.08 seconds |
Started | Jul 28 07:00:16 PM PDT 24 |
Finished | Jul 28 07:07:28 PM PDT 24 |
Peak memory | 378872 kb |
Host | smart-5ef1e52b-e3d6-4203-ac58-3ffac7c3496d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137452161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.4137452161 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.508710334 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 1205413148 ps |
CPU time | 21.82 seconds |
Started | Jul 28 07:00:21 PM PDT 24 |
Finished | Jul 28 07:00:43 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-7e516780-1ba7-4796-90d6-405aa6406f3d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508710334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s ram_ctrl_partial_access.508710334 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.213256815 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 82530375551 ps |
CPU time | 411.29 seconds |
Started | Jul 28 07:00:20 PM PDT 24 |
Finished | Jul 28 07:07:12 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-d888dd8d-9a4c-4aa3-9cae-fc8d6a49c744 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213256815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.sram_ctrl_partial_access_b2b.213256815 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.1799057786 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 363841840 ps |
CPU time | 3.08 seconds |
Started | Jul 28 07:00:30 PM PDT 24 |
Finished | Jul 28 07:00:33 PM PDT 24 |
Peak memory | 203052 kb |
Host | smart-62eca578-4025-4ce4-8adc-0c2ae54a7f02 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799057786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1799057786 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.362448202 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 7419287407 ps |
CPU time | 968.92 seconds |
Started | Jul 28 07:00:28 PM PDT 24 |
Finished | Jul 28 07:16:37 PM PDT 24 |
Peak memory | 381916 kb |
Host | smart-fef03a8c-413d-4c2d-853c-de0385f15202 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362448202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.362448202 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.576270273 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 1089408401 ps |
CPU time | 19.77 seconds |
Started | Jul 28 07:00:13 PM PDT 24 |
Finished | Jul 28 07:00:33 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-dbe3f1f6-158c-4666-81b3-6d5f5dce828b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576270273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.576270273 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.1879943768 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 268411420847 ps |
CPU time | 2725.74 seconds |
Started | Jul 28 07:00:28 PM PDT 24 |
Finished | Jul 28 07:45:54 PM PDT 24 |
Peak memory | 383220 kb |
Host | smart-8ea1779c-9d60-41bc-a75c-6e7fde6d6b0c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879943768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.1879943768 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2041324292 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 2425240438 ps |
CPU time | 257.27 seconds |
Started | Jul 28 07:00:28 PM PDT 24 |
Finished | Jul 28 07:04:45 PM PDT 24 |
Peak memory | 374008 kb |
Host | smart-c51a7024-0657-4498-b234-ceb04f2d535c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2041324292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2041324292 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3379036658 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 19565743916 ps |
CPU time | 188.32 seconds |
Started | Jul 28 07:00:20 PM PDT 24 |
Finished | Jul 28 07:03:29 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-4206a00f-05e1-47e9-b4b5-e689c690499d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379036658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.3379036658 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1122820176 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 1618263570 ps |
CPU time | 124.35 seconds |
Started | Jul 28 07:00:20 PM PDT 24 |
Finished | Jul 28 07:02:24 PM PDT 24 |
Peak memory | 361488 kb |
Host | smart-262b816d-6389-4402-bce8-2f46cad0eb18 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122820176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1122820176 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1567958773 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 10436557514 ps |
CPU time | 655.76 seconds |
Started | Jul 28 07:00:37 PM PDT 24 |
Finished | Jul 28 07:11:33 PM PDT 24 |
Peak memory | 375980 kb |
Host | smart-dcd7aef6-63ab-4f95-9ab0-38c400aec4ce |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567958773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.1567958773 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.139597879 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 87541839 ps |
CPU time | 0.63 seconds |
Started | Jul 28 07:00:40 PM PDT 24 |
Finished | Jul 28 07:00:41 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-c0fa1a80-8445-4ca2-95d1-8592b5815d13 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139597879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.139597879 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.3521536400 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 58322561429 ps |
CPU time | 959.5 seconds |
Started | Jul 28 07:00:28 PM PDT 24 |
Finished | Jul 28 07:16:28 PM PDT 24 |
Peak memory | 203776 kb |
Host | smart-26a9669e-c35b-4de3-89f1-774daae6c3fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521536400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .3521536400 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.2565162380 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 40922582938 ps |
CPU time | 1098.14 seconds |
Started | Jul 28 07:00:35 PM PDT 24 |
Finished | Jul 28 07:18:54 PM PDT 24 |
Peak memory | 373936 kb |
Host | smart-384755a3-2b4e-484e-a2ea-423a87fcbd88 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565162380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.2565162380 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.99769454 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 3590561516 ps |
CPU time | 23.94 seconds |
Started | Jul 28 07:00:37 PM PDT 24 |
Finished | Jul 28 07:01:01 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-f4e0cedb-71d8-4a02-83cf-c4c131ffc546 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99769454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esca lation.99769454 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.921557059 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 2498860568 ps |
CPU time | 35.72 seconds |
Started | Jul 28 07:00:35 PM PDT 24 |
Finished | Jul 28 07:01:11 PM PDT 24 |
Peak memory | 296544 kb |
Host | smart-589dd515-dbd7-4cb1-810e-3f05a82034af |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921557059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.sram_ctrl_max_throughput.921557059 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4232850733 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 5411526312 ps |
CPU time | 165.67 seconds |
Started | Jul 28 07:00:42 PM PDT 24 |
Finished | Jul 28 07:03:27 PM PDT 24 |
Peak memory | 211332 kb |
Host | smart-75f892de-31d6-4935-8451-a52f60a9f625 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232850733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.4232850733 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.1075923595 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 9081915130 ps |
CPU time | 164.17 seconds |
Started | Jul 28 07:00:37 PM PDT 24 |
Finished | Jul 28 07:03:21 PM PDT 24 |
Peak memory | 211388 kb |
Host | smart-a2a7c00e-54f8-445c-9f83-4b3f8a8430b9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075923595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.1075923595 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.1432258816 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 236181495111 ps |
CPU time | 1255.74 seconds |
Started | Jul 28 07:00:29 PM PDT 24 |
Finished | Jul 28 07:21:25 PM PDT 24 |
Peak memory | 378008 kb |
Host | smart-9fe12064-5726-4f36-9494-0d7bdce92579 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432258816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.1432258816 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.733457256 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 4527472009 ps |
CPU time | 7.38 seconds |
Started | Jul 28 07:00:35 PM PDT 24 |
Finished | Jul 28 07:00:42 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-2de758d5-ceb0-477e-aad3-2502246ab7b6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733457256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s ram_ctrl_partial_access.733457256 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3025987461 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 16757831462 ps |
CPU time | 426.18 seconds |
Started | Jul 28 07:00:35 PM PDT 24 |
Finished | Jul 28 07:07:41 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-8c68b53d-b800-4f3b-a230-75116d47969f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025987461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.3025987461 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.4009946701 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1473278154 ps |
CPU time | 3.64 seconds |
Started | Jul 28 07:00:40 PM PDT 24 |
Finished | Jul 28 07:00:44 PM PDT 24 |
Peak memory | 203016 kb |
Host | smart-2298ea23-ae8d-471d-9730-df2f5ffa548f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009946701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.4009946701 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.2396278309 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 20471440462 ps |
CPU time | 735.6 seconds |
Started | Jul 28 07:00:34 PM PDT 24 |
Finished | Jul 28 07:12:50 PM PDT 24 |
Peak memory | 377892 kb |
Host | smart-948b3702-047c-44c1-bedc-a19b26a0ee52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396278309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2396278309 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.110283423 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 4286299688 ps |
CPU time | 46.46 seconds |
Started | Jul 28 07:00:27 PM PDT 24 |
Finished | Jul 28 07:01:13 PM PDT 24 |
Peak memory | 294924 kb |
Host | smart-501b44ea-2180-4980-a748-486be3472137 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110283423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.110283423 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.113380173 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 299403922686 ps |
CPU time | 7134.63 seconds |
Started | Jul 28 07:00:38 PM PDT 24 |
Finished | Jul 28 08:59:33 PM PDT 24 |
Peak memory | 376028 kb |
Host | smart-28643f58-40c2-4bdf-941d-dd7373eac657 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113380173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_stress_all.113380173 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.327173877 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 953096019 ps |
CPU time | 11.29 seconds |
Started | Jul 28 07:00:39 PM PDT 24 |
Finished | Jul 28 07:00:51 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-383927fc-41f1-4b12-88db-26d3b64eadbf |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=327173877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.327173877 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1588694748 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 30480125198 ps |
CPU time | 373.14 seconds |
Started | Jul 28 07:00:28 PM PDT 24 |
Finished | Jul 28 07:06:41 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-9147e2b8-b28a-4eaa-8e5d-a2ef5d8a04e9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588694748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.1588694748 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2865108498 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 3268875372 ps |
CPU time | 150.67 seconds |
Started | Jul 28 07:00:36 PM PDT 24 |
Finished | Jul 28 07:03:07 PM PDT 24 |
Peak memory | 372964 kb |
Host | smart-d4d6bfdf-635a-466a-ae80-a6de81e0e215 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865108498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2865108498 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3193076260 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 22160327023 ps |
CPU time | 807.5 seconds |
Started | Jul 28 07:00:55 PM PDT 24 |
Finished | Jul 28 07:14:23 PM PDT 24 |
Peak memory | 374832 kb |
Host | smart-5c1aa05b-0cc5-46dd-ac37-6e3e4bfdc658 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193076260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.3193076260 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.1147233104 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 14783330 ps |
CPU time | 0.7 seconds |
Started | Jul 28 07:01:02 PM PDT 24 |
Finished | Jul 28 07:01:02 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-70b86cb3-1210-49f7-85e5-9965742f0094 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147233104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1147233104 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.1260640659 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 47746584349 ps |
CPU time | 1049.94 seconds |
Started | Jul 28 07:00:48 PM PDT 24 |
Finished | Jul 28 07:18:18 PM PDT 24 |
Peak memory | 203724 kb |
Host | smart-6832d13a-0aea-41b9-8cad-a54011df3b9d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260640659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .1260640659 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.3606591547 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 95918686793 ps |
CPU time | 1023.26 seconds |
Started | Jul 28 07:00:56 PM PDT 24 |
Finished | Jul 28 07:17:59 PM PDT 24 |
Peak memory | 365112 kb |
Host | smart-7f3af2eb-d9d2-442a-9b65-4215a9dce9d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606591547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.3606591547 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.145366324 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 23179868642 ps |
CPU time | 71.4 seconds |
Started | Jul 28 07:00:54 PM PDT 24 |
Finished | Jul 28 07:02:06 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-10b1cdcc-d1c1-4237-8cd3-d7d82032f229 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145366324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc alation.145366324 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.2362891255 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 5447849567 ps |
CPU time | 137.68 seconds |
Started | Jul 28 07:00:47 PM PDT 24 |
Finished | Jul 28 07:03:05 PM PDT 24 |
Peak memory | 369788 kb |
Host | smart-12e02983-e982-46fa-b016-0e34d7d7e0f0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362891255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.2362891255 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.509976638 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 2442656023 ps |
CPU time | 77.29 seconds |
Started | Jul 28 07:00:56 PM PDT 24 |
Finished | Jul 28 07:02:14 PM PDT 24 |
Peak memory | 219516 kb |
Host | smart-76adde8c-1698-42d7-a334-9b2b7027fe9a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509976638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43 .sram_ctrl_mem_partial_access.509976638 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.928724159 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 10567388660 ps |
CPU time | 164.13 seconds |
Started | Jul 28 07:00:54 PM PDT 24 |
Finished | Jul 28 07:03:38 PM PDT 24 |
Peak memory | 211368 kb |
Host | smart-9410f98b-ef63-482d-9ad0-eaf83a4016bf |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928724159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _mem_walk.928724159 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.3126901585 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 60909980081 ps |
CPU time | 884.09 seconds |
Started | Jul 28 07:00:48 PM PDT 24 |
Finished | Jul 28 07:15:33 PM PDT 24 |
Peak memory | 380988 kb |
Host | smart-cb7258c3-35d2-4bde-a387-787ce6d6114d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126901585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.3126901585 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.3520290077 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 803505017 ps |
CPU time | 35.01 seconds |
Started | Jul 28 07:00:50 PM PDT 24 |
Finished | Jul 28 07:01:25 PM PDT 24 |
Peak memory | 282860 kb |
Host | smart-a4ce7620-bde1-40c1-b97b-2187c23df5fb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520290077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.3520290077 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3405456831 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 42363235834 ps |
CPU time | 387.78 seconds |
Started | Jul 28 07:00:48 PM PDT 24 |
Finished | Jul 28 07:07:16 PM PDT 24 |
Peak memory | 203192 kb |
Host | smart-249c098d-8b68-4b23-a693-3332e866b09c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405456831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3405456831 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.3065900140 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 350417282 ps |
CPU time | 3.4 seconds |
Started | Jul 28 07:00:54 PM PDT 24 |
Finished | Jul 28 07:00:58 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-fb9041d8-fa0f-46ce-9254-2d55e2e94a3d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065900140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3065900140 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.3479530039 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 76212453337 ps |
CPU time | 1201.86 seconds |
Started | Jul 28 07:00:53 PM PDT 24 |
Finished | Jul 28 07:20:55 PM PDT 24 |
Peak memory | 381056 kb |
Host | smart-51959a0a-6e0e-4e50-9326-4709ff9fe2d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479530039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3479530039 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.4145918323 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 613029531 ps |
CPU time | 19.16 seconds |
Started | Jul 28 07:00:41 PM PDT 24 |
Finished | Jul 28 07:01:00 PM PDT 24 |
Peak memory | 254980 kb |
Host | smart-5008c1bb-6f05-4376-81bf-738e6a11d6b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145918323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.4145918323 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.1591552971 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 110132136158 ps |
CPU time | 6168.51 seconds |
Started | Jul 28 07:01:03 PM PDT 24 |
Finished | Jul 28 08:43:52 PM PDT 24 |
Peak memory | 382096 kb |
Host | smart-2ab962f7-194b-4797-b0a1-561532fe90f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591552971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.1591552971 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.799711147 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 277617972 ps |
CPU time | 10.66 seconds |
Started | Jul 28 07:00:53 PM PDT 24 |
Finished | Jul 28 07:01:04 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-79d4ffde-78bd-4c1e-b77e-07b3b9a9af87 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=799711147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.799711147 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3986503145 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 11323810390 ps |
CPU time | 231.98 seconds |
Started | Jul 28 07:00:48 PM PDT 24 |
Finished | Jul 28 07:04:41 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-9e0d1a62-2b82-4f51-9812-45303ed884f0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986503145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.3986503145 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1712021086 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 780080024 ps |
CPU time | 40.8 seconds |
Started | Jul 28 07:00:49 PM PDT 24 |
Finished | Jul 28 07:01:30 PM PDT 24 |
Peak memory | 310776 kb |
Host | smart-d47557a9-371d-4e47-b936-ff11dd52fa3a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712021086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1712021086 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.645731645 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 40096427606 ps |
CPU time | 1487.9 seconds |
Started | Jul 28 07:01:07 PM PDT 24 |
Finished | Jul 28 07:25:55 PM PDT 24 |
Peak memory | 380132 kb |
Host | smart-12a2f59f-4475-442b-9aba-485ec257a548 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645731645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 44.sram_ctrl_access_during_key_req.645731645 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.606546260 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 78563537 ps |
CPU time | 0.64 seconds |
Started | Jul 28 07:01:14 PM PDT 24 |
Finished | Jul 28 07:01:15 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-6f4ac0f6-0b75-4989-af2c-65f75aad97b9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606546260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.606546260 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.2134237593 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 96663817038 ps |
CPU time | 1601.62 seconds |
Started | Jul 28 07:01:02 PM PDT 24 |
Finished | Jul 28 07:27:44 PM PDT 24 |
Peak memory | 203732 kb |
Host | smart-3d43458e-d16c-4571-8b7d-1bde816f65fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134237593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .2134237593 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.630878776 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 14422859679 ps |
CPU time | 530.24 seconds |
Started | Jul 28 07:01:09 PM PDT 24 |
Finished | Jul 28 07:09:59 PM PDT 24 |
Peak memory | 379220 kb |
Host | smart-9db057fe-1803-427b-b167-3bfbe5d6ff91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630878776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl e.630878776 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.1393800721 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 15807689060 ps |
CPU time | 75.97 seconds |
Started | Jul 28 07:01:10 PM PDT 24 |
Finished | Jul 28 07:02:26 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-b0ba1d4c-fa9b-4f04-8705-320c41ff173f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393800721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.1393800721 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.3702156368 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 779552458 ps |
CPU time | 154.05 seconds |
Started | Jul 28 07:01:09 PM PDT 24 |
Finished | Jul 28 07:03:43 PM PDT 24 |
Peak memory | 370076 kb |
Host | smart-30f7a7e1-31cc-4794-a516-575e5ebae336 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702156368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.3702156368 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.389638677 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 2780410114 ps |
CPU time | 77.13 seconds |
Started | Jul 28 07:01:17 PM PDT 24 |
Finished | Jul 28 07:02:34 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-d034aa33-7291-426c-a6cd-9220b2b6d319 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389638677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .sram_ctrl_mem_partial_access.389638677 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.2386646576 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 41393164906 ps |
CPU time | 165.93 seconds |
Started | Jul 28 07:01:15 PM PDT 24 |
Finished | Jul 28 07:04:01 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-a625fd36-7830-48e9-862a-5561ceae661b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386646576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.2386646576 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.3379549435 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 65687958654 ps |
CPU time | 1348.66 seconds |
Started | Jul 28 07:01:02 PM PDT 24 |
Finished | Jul 28 07:23:31 PM PDT 24 |
Peak memory | 378972 kb |
Host | smart-a3d11f38-3767-4411-97f6-f852905d9ce8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379549435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.3379549435 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.680794890 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 804511309 ps |
CPU time | 46.97 seconds |
Started | Jul 28 07:01:00 PM PDT 24 |
Finished | Jul 28 07:01:47 PM PDT 24 |
Peak memory | 303332 kb |
Host | smart-bb198c24-f48d-4c66-a9f7-eea22fe35bcd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680794890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s ram_ctrl_partial_access.680794890 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.1023847096 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 349228983 ps |
CPU time | 3.33 seconds |
Started | Jul 28 07:01:08 PM PDT 24 |
Finished | Jul 28 07:01:12 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-6cde370e-f7ec-4675-862f-3364a144eb67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023847096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1023847096 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.3876805565 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 71962596706 ps |
CPU time | 790.83 seconds |
Started | Jul 28 07:01:10 PM PDT 24 |
Finished | Jul 28 07:14:21 PM PDT 24 |
Peak memory | 378004 kb |
Host | smart-414d53cc-7a18-42d9-8cd4-b9a2d7b41227 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876805565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3876805565 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.3519391648 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 1502036532 ps |
CPU time | 4.09 seconds |
Started | Jul 28 07:01:02 PM PDT 24 |
Finished | Jul 28 07:01:06 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-e807a175-8d0a-4af3-834f-314f06d625d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519391648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3519391648 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.2973523286 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 55443929963 ps |
CPU time | 3459.12 seconds |
Started | Jul 28 07:01:17 PM PDT 24 |
Finished | Jul 28 07:58:57 PM PDT 24 |
Peak memory | 383184 kb |
Host | smart-a7c8505f-2a69-4a89-a658-9ea8eebcf514 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973523286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.2973523286 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1430625563 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 16408618760 ps |
CPU time | 37.67 seconds |
Started | Jul 28 07:01:15 PM PDT 24 |
Finished | Jul 28 07:01:53 PM PDT 24 |
Peak memory | 211460 kb |
Host | smart-94949d51-db32-4f70-976c-339c3b8b0d76 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1430625563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1430625563 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.4153961096 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 4948204050 ps |
CPU time | 346.34 seconds |
Started | Jul 28 07:01:02 PM PDT 24 |
Finished | Jul 28 07:06:48 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-3afd3a21-1db6-44d2-8dda-c207079500d0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153961096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.4153961096 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.620900831 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 1448752909 ps |
CPU time | 21.68 seconds |
Started | Jul 28 07:01:06 PM PDT 24 |
Finished | Jul 28 07:01:28 PM PDT 24 |
Peak memory | 262688 kb |
Host | smart-c57e31d8-bb67-4672-8aca-af532c1888ee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620900831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_throughput_w_partial_write.620900831 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3957688103 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 62589415647 ps |
CPU time | 487.65 seconds |
Started | Jul 28 07:01:24 PM PDT 24 |
Finished | Jul 28 07:09:32 PM PDT 24 |
Peak memory | 374960 kb |
Host | smart-1c903209-cfc7-410c-ae70-7c53a6efba67 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957688103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.3957688103 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.767694910 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 145753757 ps |
CPU time | 0.67 seconds |
Started | Jul 28 07:01:26 PM PDT 24 |
Finished | Jul 28 07:01:27 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-12e77a76-5bc1-4124-9d7c-e62d46cc141a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767694910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.767694910 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.1043365110 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 60585975646 ps |
CPU time | 1999.29 seconds |
Started | Jul 28 07:01:17 PM PDT 24 |
Finished | Jul 28 07:34:37 PM PDT 24 |
Peak memory | 204076 kb |
Host | smart-67419dce-5ae9-4681-8565-ba8d7ee4a3f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043365110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .1043365110 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.3486096381 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 7608047074 ps |
CPU time | 569.1 seconds |
Started | Jul 28 07:01:21 PM PDT 24 |
Finished | Jul 28 07:10:50 PM PDT 24 |
Peak memory | 379052 kb |
Host | smart-27726d6b-71d2-4454-92d7-89e8b2f4c559 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486096381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.3486096381 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.712917501 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 10283756395 ps |
CPU time | 58.49 seconds |
Started | Jul 28 07:01:22 PM PDT 24 |
Finished | Jul 28 07:02:21 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-cd46f1cc-691e-4942-a01c-cdc2af7e3c53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712917501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esc alation.712917501 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.4144600207 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 6788841514 ps |
CPU time | 69.26 seconds |
Started | Jul 28 07:01:22 PM PDT 24 |
Finished | Jul 28 07:02:31 PM PDT 24 |
Peak memory | 343368 kb |
Host | smart-e87f34df-dd81-4de1-a8e8-f0ccf14360b2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144600207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.4144600207 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2226370201 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 1417470744 ps |
CPU time | 76.27 seconds |
Started | Jul 28 07:01:29 PM PDT 24 |
Finished | Jul 28 07:02:45 PM PDT 24 |
Peak memory | 211248 kb |
Host | smart-7729110c-ab69-43b5-8db8-421b5aa39333 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226370201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.2226370201 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.2738557196 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 24742226803 ps |
CPU time | 307.19 seconds |
Started | Jul 28 07:01:29 PM PDT 24 |
Finished | Jul 28 07:06:36 PM PDT 24 |
Peak memory | 211324 kb |
Host | smart-4d16f4f3-5b7b-4754-b39a-89ca3aced0cc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738557196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.2738557196 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.731355724 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 16437316149 ps |
CPU time | 818.01 seconds |
Started | Jul 28 07:01:15 PM PDT 24 |
Finished | Jul 28 07:14:53 PM PDT 24 |
Peak memory | 379008 kb |
Host | smart-0fcaf03b-030c-44b5-b860-3e86f4d341e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731355724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip le_keys.731355724 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.3232251046 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 578621291 ps |
CPU time | 16.38 seconds |
Started | Jul 28 07:01:23 PM PDT 24 |
Finished | Jul 28 07:01:40 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-c187a5c7-fa13-4e8a-9986-63ea94a6b6d7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232251046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.3232251046 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2532428873 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 25998949739 ps |
CPU time | 350.21 seconds |
Started | Jul 28 07:01:25 PM PDT 24 |
Finished | Jul 28 07:07:15 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-cebc3e1b-38c5-428f-989f-2b2242634e45 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532428873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.2532428873 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.3062039608 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 669317750 ps |
CPU time | 3.32 seconds |
Started | Jul 28 07:01:24 PM PDT 24 |
Finished | Jul 28 07:01:28 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-18b49482-90e0-44de-b2a4-6f9d25faf14e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062039608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3062039608 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.1036085411 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 5967286311 ps |
CPU time | 268.23 seconds |
Started | Jul 28 07:01:25 PM PDT 24 |
Finished | Jul 28 07:05:54 PM PDT 24 |
Peak memory | 377492 kb |
Host | smart-0795a13d-39a7-4b02-b6f4-072c85520f89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036085411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1036085411 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.2832872176 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 1630089472 ps |
CPU time | 7.94 seconds |
Started | Jul 28 07:01:15 PM PDT 24 |
Finished | Jul 28 07:01:23 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-ed30b32f-c165-4475-8803-b434129e73dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832872176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2832872176 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.1083023451 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 38720917599 ps |
CPU time | 2730.42 seconds |
Started | Jul 28 07:01:28 PM PDT 24 |
Finished | Jul 28 07:46:59 PM PDT 24 |
Peak memory | 382540 kb |
Host | smart-e28a0fc7-cd6f-4954-b044-a41eb02511a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083023451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.1083023451 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.958618215 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 3124856915 ps |
CPU time | 34.44 seconds |
Started | Jul 28 07:01:27 PM PDT 24 |
Finished | Jul 28 07:02:02 PM PDT 24 |
Peak memory | 276036 kb |
Host | smart-4969c03d-990e-4b9b-91bd-c77b46c05bba |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=958618215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.958618215 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2518006757 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 5393549917 ps |
CPU time | 334.75 seconds |
Started | Jul 28 07:01:25 PM PDT 24 |
Finished | Jul 28 07:07:00 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-5bf0a8fa-f5a0-4b37-a399-0dd64f4d2197 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518006757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2518006757 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3452925860 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 806903344 ps |
CPU time | 139.38 seconds |
Started | Jul 28 07:01:22 PM PDT 24 |
Finished | Jul 28 07:03:41 PM PDT 24 |
Peak memory | 361640 kb |
Host | smart-008e5783-5386-47e5-b5c7-4dfd6700b237 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452925860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3452925860 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2488455624 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 14211945967 ps |
CPU time | 610.13 seconds |
Started | Jul 28 07:01:35 PM PDT 24 |
Finished | Jul 28 07:11:45 PM PDT 24 |
Peak memory | 373908 kb |
Host | smart-a5b2807f-68c4-4680-89a6-dbb2cab64c1d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488455624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.2488455624 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.760569120 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 36811198 ps |
CPU time | 0.63 seconds |
Started | Jul 28 07:01:38 PM PDT 24 |
Finished | Jul 28 07:01:39 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-c3d476b8-0295-4018-8785-54f7e12a3223 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760569120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.760569120 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.2534737751 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 93070213419 ps |
CPU time | 574.96 seconds |
Started | Jul 28 07:01:30 PM PDT 24 |
Finished | Jul 28 07:11:06 PM PDT 24 |
Peak memory | 203368 kb |
Host | smart-3dd61c51-6f33-4a84-aee5-830eb30b69c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534737751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .2534737751 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.1905596676 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 6718216062 ps |
CPU time | 583.03 seconds |
Started | Jul 28 07:01:38 PM PDT 24 |
Finished | Jul 28 07:11:21 PM PDT 24 |
Peak memory | 359596 kb |
Host | smart-16d9c146-cd19-43be-b056-accc19697672 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905596676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.1905596676 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.1341759707 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 7061054518 ps |
CPU time | 42.96 seconds |
Started | Jul 28 07:01:32 PM PDT 24 |
Finished | Jul 28 07:02:15 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-a4de0d9a-6abd-48e4-9326-a10337866337 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341759707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.1341759707 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.82768604 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 1527412672 ps |
CPU time | 146.27 seconds |
Started | Jul 28 07:01:32 PM PDT 24 |
Finished | Jul 28 07:03:58 PM PDT 24 |
Peak memory | 371832 kb |
Host | smart-4eed7201-a20c-4b4a-877b-96ff873eea29 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82768604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 46.sram_ctrl_max_throughput.82768604 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.754482176 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 4473473944 ps |
CPU time | 74.92 seconds |
Started | Jul 28 07:01:40 PM PDT 24 |
Finished | Jul 28 07:02:55 PM PDT 24 |
Peak memory | 211372 kb |
Host | smart-6b2dda0b-3e32-4bd1-8255-cf1a4669338a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754482176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sram_ctrl_mem_partial_access.754482176 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.3215864113 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 14576317576 ps |
CPU time | 324.21 seconds |
Started | Jul 28 07:01:38 PM PDT 24 |
Finished | Jul 28 07:07:02 PM PDT 24 |
Peak memory | 204072 kb |
Host | smart-f7e651cf-d051-4d62-b763-a3cf0668e5e2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215864113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.3215864113 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.1852102439 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 70397347952 ps |
CPU time | 1197.98 seconds |
Started | Jul 28 07:01:28 PM PDT 24 |
Finished | Jul 28 07:21:26 PM PDT 24 |
Peak memory | 379616 kb |
Host | smart-70a38189-ccf1-4b4a-a87b-e19709a71182 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852102439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.1852102439 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.1589763900 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 3945803863 ps |
CPU time | 24.71 seconds |
Started | Jul 28 07:01:30 PM PDT 24 |
Finished | Jul 28 07:01:55 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-a7121253-d713-4ab6-8188-50e649633e05 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589763900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.1589763900 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.720149579 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 15876608410 ps |
CPU time | 442.61 seconds |
Started | Jul 28 07:01:31 PM PDT 24 |
Finished | Jul 28 07:08:54 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-73a40bce-867b-4897-ad96-42d168c1c812 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720149579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.sram_ctrl_partial_access_b2b.720149579 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.2334983922 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 1255072467 ps |
CPU time | 3.62 seconds |
Started | Jul 28 07:01:39 PM PDT 24 |
Finished | Jul 28 07:01:43 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-d2154241-a62e-43d1-81a6-bc6e239edb07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334983922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2334983922 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.3823538211 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 30478892782 ps |
CPU time | 1014.58 seconds |
Started | Jul 28 07:01:40 PM PDT 24 |
Finished | Jul 28 07:18:34 PM PDT 24 |
Peak memory | 365680 kb |
Host | smart-92c34fa8-3864-4b97-a495-17c91a1cd165 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823538211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3823538211 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.2628909902 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 875556943 ps |
CPU time | 21.23 seconds |
Started | Jul 28 07:01:29 PM PDT 24 |
Finished | Jul 28 07:01:50 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-9869f1a9-2350-451a-abc5-530d9fe474b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628909902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2628909902 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1136508049 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 478188308 ps |
CPU time | 20.12 seconds |
Started | Jul 28 07:01:38 PM PDT 24 |
Finished | Jul 28 07:01:58 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-84bf522a-37ee-476e-b3e6-6c831fdc6ca5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1136508049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1136508049 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2905947965 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 23673295441 ps |
CPU time | 406.12 seconds |
Started | Jul 28 07:01:31 PM PDT 24 |
Finished | Jul 28 07:08:17 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-011c96fe-05e0-4da8-ae5c-bd13d86028ea |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905947965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.2905947965 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3223187414 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 2899232899 ps |
CPU time | 31.56 seconds |
Started | Jul 28 07:01:31 PM PDT 24 |
Finished | Jul 28 07:02:03 PM PDT 24 |
Peak memory | 284912 kb |
Host | smart-389ecc3e-abe8-487e-9d9f-0eb937637d0c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223187414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3223187414 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2746349870 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 31209666464 ps |
CPU time | 670.96 seconds |
Started | Jul 28 07:01:50 PM PDT 24 |
Finished | Jul 28 07:13:01 PM PDT 24 |
Peak memory | 374956 kb |
Host | smart-ceb788ed-ad4c-4f5b-96bd-4b82a1a3df0c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746349870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.2746349870 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.4049191591 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 12164825 ps |
CPU time | 0.65 seconds |
Started | Jul 28 07:01:56 PM PDT 24 |
Finished | Jul 28 07:01:57 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-c5fa9ff8-a6cd-496b-8ed7-a7da7b45855e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049191591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.4049191591 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.795511357 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 30503134754 ps |
CPU time | 2156.11 seconds |
Started | Jul 28 07:01:43 PM PDT 24 |
Finished | Jul 28 07:37:40 PM PDT 24 |
Peak memory | 203372 kb |
Host | smart-b3ca0acd-7d60-4a06-961d-c371dd2b0410 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795511357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection. 795511357 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.561073872 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 20708409686 ps |
CPU time | 1010.99 seconds |
Started | Jul 28 07:01:51 PM PDT 24 |
Finished | Jul 28 07:18:42 PM PDT 24 |
Peak memory | 380044 kb |
Host | smart-f807e76c-1788-4c16-afa1-ba653f7db167 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561073872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executabl e.561073872 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.3138955978 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 8130185177 ps |
CPU time | 31.29 seconds |
Started | Jul 28 07:01:47 PM PDT 24 |
Finished | Jul 28 07:02:19 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-85945785-b5df-4b98-b403-12c0fc3480b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138955978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.3138955978 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.2724159105 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 788979614 ps |
CPU time | 109.54 seconds |
Started | Jul 28 07:01:50 PM PDT 24 |
Finished | Jul 28 07:03:40 PM PDT 24 |
Peak memory | 349232 kb |
Host | smart-8199e7a3-795a-415c-af4e-5c85ee4d24e1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724159105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.2724159105 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.131429777 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 3590140188 ps |
CPU time | 86.21 seconds |
Started | Jul 28 07:01:56 PM PDT 24 |
Finished | Jul 28 07:03:23 PM PDT 24 |
Peak memory | 219576 kb |
Host | smart-17adcb80-61f5-414e-bec1-1d2a191faf42 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131429777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_mem_partial_access.131429777 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.3744153312 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 17984969458 ps |
CPU time | 176.37 seconds |
Started | Jul 28 07:01:49 PM PDT 24 |
Finished | Jul 28 07:04:46 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-fcc9d5d6-0b99-4bf6-bb67-6ca36bb6eaa6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744153312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.3744153312 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.1218431520 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 25766653144 ps |
CPU time | 712.31 seconds |
Started | Jul 28 07:01:40 PM PDT 24 |
Finished | Jul 28 07:13:32 PM PDT 24 |
Peak memory | 375932 kb |
Host | smart-edbe6c80-2198-42f8-bc69-09cffdce5468 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218431520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.1218431520 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.2797396279 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 846434169 ps |
CPU time | 107.39 seconds |
Started | Jul 28 07:01:43 PM PDT 24 |
Finished | Jul 28 07:03:30 PM PDT 24 |
Peak memory | 353412 kb |
Host | smart-a9339d70-5333-4de6-bf03-01100e201915 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797396279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2797396279 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1005196011 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 7001407797 ps |
CPU time | 230.64 seconds |
Started | Jul 28 07:01:47 PM PDT 24 |
Finished | Jul 28 07:05:38 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-7176915d-e3fe-4194-850d-86770f71ebb7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005196011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.1005196011 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.2249859540 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 709302499 ps |
CPU time | 3.38 seconds |
Started | Jul 28 07:01:50 PM PDT 24 |
Finished | Jul 28 07:01:53 PM PDT 24 |
Peak memory | 203124 kb |
Host | smart-c5db71ed-4b13-4e63-9d0a-0df3bdf5a94a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249859540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2249859540 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.2017289835 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 28084341894 ps |
CPU time | 1210.45 seconds |
Started | Jul 28 07:01:49 PM PDT 24 |
Finished | Jul 28 07:22:00 PM PDT 24 |
Peak memory | 377048 kb |
Host | smart-82b6463c-6b78-44f6-8c08-669e493f60a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017289835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2017289835 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.2677464356 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 2589851681 ps |
CPU time | 8.06 seconds |
Started | Jul 28 07:01:38 PM PDT 24 |
Finished | Jul 28 07:01:46 PM PDT 24 |
Peak memory | 207484 kb |
Host | smart-0d77d3d6-ba01-413e-bcba-369d839fdf7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677464356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2677464356 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.2990758800 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 860816802236 ps |
CPU time | 5392.09 seconds |
Started | Jul 28 07:01:55 PM PDT 24 |
Finished | Jul 28 08:31:48 PM PDT 24 |
Peak memory | 384172 kb |
Host | smart-ac3c65f2-0b87-4733-a8f7-d55fc2981f04 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990758800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.2990758800 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2780308864 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 1310192779 ps |
CPU time | 19.45 seconds |
Started | Jul 28 07:01:57 PM PDT 24 |
Finished | Jul 28 07:02:17 PM PDT 24 |
Peak memory | 211512 kb |
Host | smart-76cb8f31-7ff5-4351-9d04-216a4fe78ff8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2780308864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2780308864 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.774431156 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 17746319227 ps |
CPU time | 256 seconds |
Started | Jul 28 07:01:44 PM PDT 24 |
Finished | Jul 28 07:06:00 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-3cc09a9e-2e68-4db8-a726-91e983feacd1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774431156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_stress_pipeline.774431156 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.592592179 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 1713287986 ps |
CPU time | 29.26 seconds |
Started | Jul 28 07:01:51 PM PDT 24 |
Finished | Jul 28 07:02:20 PM PDT 24 |
Peak memory | 277672 kb |
Host | smart-3a297120-823b-4417-88d6-3ee79b29b181 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592592179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.592592179 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2199134049 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 5896462092 ps |
CPU time | 248.13 seconds |
Started | Jul 28 07:02:01 PM PDT 24 |
Finished | Jul 28 07:06:09 PM PDT 24 |
Peak memory | 356340 kb |
Host | smart-c3674a7b-903a-4ffb-b2d6-488c90970fdf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199134049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.2199134049 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.2029097895 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 62842103 ps |
CPU time | 0.69 seconds |
Started | Jul 28 07:02:07 PM PDT 24 |
Finished | Jul 28 07:02:07 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-f515f5f0-2130-41b2-a062-45cf160bbd33 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029097895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.2029097895 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.304560168 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 47524446193 ps |
CPU time | 879 seconds |
Started | Jul 28 07:01:56 PM PDT 24 |
Finished | Jul 28 07:16:36 PM PDT 24 |
Peak memory | 203776 kb |
Host | smart-517072f2-cc3d-4ac3-bb92-42bd214c7271 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304560168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection. 304560168 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.3681628586 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 15986030827 ps |
CPU time | 663.61 seconds |
Started | Jul 28 07:02:04 PM PDT 24 |
Finished | Jul 28 07:13:08 PM PDT 24 |
Peak memory | 372924 kb |
Host | smart-4390891f-5a17-42bd-8bc9-5c85f615daeb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681628586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.3681628586 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.1687016501 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 22393593115 ps |
CPU time | 71.15 seconds |
Started | Jul 28 07:02:01 PM PDT 24 |
Finished | Jul 28 07:03:12 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-5e5d3f27-f44f-4e52-bbe9-a7900c11b711 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687016501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.1687016501 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.4013965400 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 10901953624 ps |
CPU time | 148.56 seconds |
Started | Jul 28 07:01:59 PM PDT 24 |
Finished | Jul 28 07:04:28 PM PDT 24 |
Peak memory | 370672 kb |
Host | smart-2f8568ef-8214-496d-b4d7-e3cde6ef9d91 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013965400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.4013965400 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2894976982 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 4497033312 ps |
CPU time | 77.84 seconds |
Started | Jul 28 07:02:06 PM PDT 24 |
Finished | Jul 28 07:03:23 PM PDT 24 |
Peak memory | 219520 kb |
Host | smart-c0a38e4f-d1ed-4780-9b1a-a1b2401c4835 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894976982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.2894976982 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.3205425089 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 21002514944 ps |
CPU time | 300.64 seconds |
Started | Jul 28 07:02:06 PM PDT 24 |
Finished | Jul 28 07:07:07 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-014630a7-dc98-495e-94c5-77bd8bfaa5a5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205425089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.3205425089 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.238595917 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 3261847380 ps |
CPU time | 196.4 seconds |
Started | Jul 28 07:01:56 PM PDT 24 |
Finished | Jul 28 07:05:13 PM PDT 24 |
Peak memory | 345720 kb |
Host | smart-057de23e-763f-41f6-a217-9894205ef32a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238595917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip le_keys.238595917 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.3027804372 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 591087930 ps |
CPU time | 18.36 seconds |
Started | Jul 28 07:02:01 PM PDT 24 |
Finished | Jul 28 07:02:20 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-f4c91e0b-cafe-4dbd-8ad0-aec00f96f33e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027804372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.3027804372 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3139489314 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 118293396730 ps |
CPU time | 614.29 seconds |
Started | Jul 28 07:02:02 PM PDT 24 |
Finished | Jul 28 07:12:16 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-97dfda5e-0cb4-446c-8a02-04784c07a3e4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139489314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.3139489314 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.3949584956 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 1877279329 ps |
CPU time | 3.81 seconds |
Started | Jul 28 07:02:08 PM PDT 24 |
Finished | Jul 28 07:02:12 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-b5ddfe18-b05f-46c9-9396-9ea19b259642 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949584956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3949584956 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.1621864748 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 15264764562 ps |
CPU time | 650.33 seconds |
Started | Jul 28 07:02:06 PM PDT 24 |
Finished | Jul 28 07:12:56 PM PDT 24 |
Peak memory | 378984 kb |
Host | smart-8d2f33cf-e779-491a-96af-1bbe96450ffc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621864748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1621864748 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.4259425527 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 1505430673 ps |
CPU time | 7.73 seconds |
Started | Jul 28 07:01:57 PM PDT 24 |
Finished | Jul 28 07:02:05 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-2b4a17a8-41fb-4e6d-b23a-f1671de6e4b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259425527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.4259425527 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.3518665939 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 152185685816 ps |
CPU time | 1618.31 seconds |
Started | Jul 28 07:02:07 PM PDT 24 |
Finished | Jul 28 07:29:05 PM PDT 24 |
Peak memory | 380080 kb |
Host | smart-a1858aff-3529-4819-aa58-e472eecbd36b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518665939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.3518665939 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2299981251 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 16984363933 ps |
CPU time | 397.06 seconds |
Started | Jul 28 07:01:59 PM PDT 24 |
Finished | Jul 28 07:08:37 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-19c8d3fb-af7a-48d0-9920-57781116f218 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299981251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.2299981251 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3105098022 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 1543169666 ps |
CPU time | 29.78 seconds |
Started | Jul 28 07:02:01 PM PDT 24 |
Finished | Jul 28 07:02:30 PM PDT 24 |
Peak memory | 284780 kb |
Host | smart-6bbfba5d-85ec-44ee-964a-afb3f3c1732b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105098022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3105098022 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3550380769 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 10703682371 ps |
CPU time | 873.76 seconds |
Started | Jul 28 07:02:23 PM PDT 24 |
Finished | Jul 28 07:16:57 PM PDT 24 |
Peak memory | 376980 kb |
Host | smart-1a975ea2-e2a7-497f-a840-056d453815a4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550380769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.3550380769 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.1114384876 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 40753270 ps |
CPU time | 0.66 seconds |
Started | Jul 28 07:02:26 PM PDT 24 |
Finished | Jul 28 07:02:27 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-c4ee3e0b-8b48-4ae4-8843-0069f17fd0ae |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114384876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.1114384876 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.3772117557 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 383959889882 ps |
CPU time | 2193.99 seconds |
Started | Jul 28 07:02:10 PM PDT 24 |
Finished | Jul 28 07:38:44 PM PDT 24 |
Peak memory | 203348 kb |
Host | smart-bc7f311e-ef41-4c6f-b2a7-a8f130e3def7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772117557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .3772117557 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.2317030321 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 63081589244 ps |
CPU time | 1203.56 seconds |
Started | Jul 28 07:02:23 PM PDT 24 |
Finished | Jul 28 07:22:27 PM PDT 24 |
Peak memory | 378968 kb |
Host | smart-89c8119a-48af-4e86-8f9c-c070e48d6deb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317030321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.2317030321 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.212975659 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 10510992883 ps |
CPU time | 63.44 seconds |
Started | Jul 28 07:02:16 PM PDT 24 |
Finished | Jul 28 07:03:19 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-3e44395c-4b56-49f7-9878-160d5b46a427 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212975659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_esc alation.212975659 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.1807820560 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 779311188 ps |
CPU time | 108.4 seconds |
Started | Jul 28 07:02:17 PM PDT 24 |
Finished | Jul 28 07:04:05 PM PDT 24 |
Peak memory | 354272 kb |
Host | smart-f1cd0428-1e68-4866-b0e4-c2ec9b147688 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807820560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.1807820560 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1877184999 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 9774156835 ps |
CPU time | 150.62 seconds |
Started | Jul 28 07:02:27 PM PDT 24 |
Finished | Jul 28 07:04:57 PM PDT 24 |
Peak memory | 211352 kb |
Host | smart-e642b99e-aeb9-4d4c-bc5b-10c492e88fb5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877184999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.1877184999 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.1688145726 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 14387370198 ps |
CPU time | 310.85 seconds |
Started | Jul 28 07:02:29 PM PDT 24 |
Finished | Jul 28 07:07:40 PM PDT 24 |
Peak memory | 211348 kb |
Host | smart-06058e3f-42b3-4845-b74a-2029136e5767 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688145726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.1688145726 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.863026931 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 50027851260 ps |
CPU time | 457.39 seconds |
Started | Jul 28 07:02:11 PM PDT 24 |
Finished | Jul 28 07:09:49 PM PDT 24 |
Peak memory | 341148 kb |
Host | smart-45bcda65-7b63-4217-9cad-45de16be4f50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863026931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip le_keys.863026931 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.2007697025 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 1800924350 ps |
CPU time | 25.99 seconds |
Started | Jul 28 07:02:17 PM PDT 24 |
Finished | Jul 28 07:02:43 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-97cabefb-75ed-4c29-8d66-ede733ff77ab |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007697025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.2007697025 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2911204 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 32686968122 ps |
CPU time | 392.04 seconds |
Started | Jul 28 07:02:17 PM PDT 24 |
Finished | Jul 28 07:08:49 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-09d123e5-b4c0-4e83-97d6-2578112f64b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 49.sram_ctrl_partial_access_b2b.2911204 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.3859781277 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 1404533544 ps |
CPU time | 3 seconds |
Started | Jul 28 07:02:25 PM PDT 24 |
Finished | Jul 28 07:02:28 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-d695bab5-aeec-41ad-a0c9-632a87af0407 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859781277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3859781277 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.2349216489 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 67503528966 ps |
CPU time | 920.74 seconds |
Started | Jul 28 07:02:22 PM PDT 24 |
Finished | Jul 28 07:17:43 PM PDT 24 |
Peak memory | 369812 kb |
Host | smart-9acfdd32-1724-4f9e-bd60-eb13f3b0bbf0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349216489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2349216489 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.51778438 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 877296028 ps |
CPU time | 59.79 seconds |
Started | Jul 28 07:02:11 PM PDT 24 |
Finished | Jul 28 07:03:11 PM PDT 24 |
Peak memory | 337372 kb |
Host | smart-355643b2-c230-425f-a5d5-5cc7787012c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51778438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.51778438 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.3031847202 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 131329215716 ps |
CPU time | 2046.6 seconds |
Started | Jul 28 07:02:26 PM PDT 24 |
Finished | Jul 28 07:36:33 PM PDT 24 |
Peak memory | 219544 kb |
Host | smart-27e3539e-0418-4597-8232-01ff72bb0b30 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031847202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.3031847202 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1888497455 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 2473225991 ps |
CPU time | 42.29 seconds |
Started | Jul 28 07:02:28 PM PDT 24 |
Finished | Jul 28 07:03:10 PM PDT 24 |
Peak memory | 245076 kb |
Host | smart-d155aea4-1280-4d32-89c1-96561d33ffdb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1888497455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1888497455 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3642066276 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 19481058777 ps |
CPU time | 255 seconds |
Started | Jul 28 07:02:10 PM PDT 24 |
Finished | Jul 28 07:06:25 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-47a4edcf-1643-486c-a018-0a0ff0645f70 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642066276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.3642066276 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3267711674 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 1454507593 ps |
CPU time | 67.68 seconds |
Started | Jul 28 07:02:17 PM PDT 24 |
Finished | Jul 28 07:03:25 PM PDT 24 |
Peak memory | 306904 kb |
Host | smart-504ae381-85fa-47b4-9a2c-1e52b8f70c1f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267711674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.3267711674 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.856413112 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 15349449275 ps |
CPU time | 32.39 seconds |
Started | Jul 28 06:52:04 PM PDT 24 |
Finished | Jul 28 06:52:37 PM PDT 24 |
Peak memory | 247156 kb |
Host | smart-4a5d3487-4585-4590-8ed5-c7b297cf9a52 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856413112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_access_during_key_req.856413112 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.1446011349 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 21907304 ps |
CPU time | 0.66 seconds |
Started | Jul 28 06:52:08 PM PDT 24 |
Finished | Jul 28 06:52:09 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-7ecda093-8c49-4776-b601-c3fe15f305af |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446011349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.1446011349 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.1065533805 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 504363139343 ps |
CPU time | 2461.81 seconds |
Started | Jul 28 06:51:57 PM PDT 24 |
Finished | Jul 28 07:32:59 PM PDT 24 |
Peak memory | 203936 kb |
Host | smart-9ae10124-71c9-4215-b167-ff15348c2155 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065533805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 1065533805 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.1180429319 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 7529115356 ps |
CPU time | 536.85 seconds |
Started | Jul 28 06:52:03 PM PDT 24 |
Finished | Jul 28 07:01:00 PM PDT 24 |
Peak memory | 359696 kb |
Host | smart-43bbf683-b8fe-498d-9e9c-4b1f035e9802 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180429319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.1180429319 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.800220439 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 9095736031 ps |
CPU time | 55.12 seconds |
Started | Jul 28 06:52:02 PM PDT 24 |
Finished | Jul 28 06:52:57 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-cf5a7d20-0bd6-4873-aad0-cebafb86d29c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800220439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esca lation.800220439 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.315691976 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 1249022536 ps |
CPU time | 6.95 seconds |
Started | Jul 28 06:52:03 PM PDT 24 |
Finished | Jul 28 06:52:10 PM PDT 24 |
Peak memory | 212336 kb |
Host | smart-3950d31b-3a13-4665-af62-930c690616d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315691976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_max_throughput.315691976 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1832951298 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 2798465345 ps |
CPU time | 86.65 seconds |
Started | Jul 28 06:52:01 PM PDT 24 |
Finished | Jul 28 06:53:28 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-206e3231-82b0-4634-8503-0106cdef3879 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832951298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.1832951298 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.232269731 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 10343383205 ps |
CPU time | 165.82 seconds |
Started | Jul 28 06:52:02 PM PDT 24 |
Finished | Jul 28 06:54:48 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-24964209-f9e8-4d31-a07a-f859ad221a31 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232269731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ mem_walk.232269731 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.3908977160 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 91550809664 ps |
CPU time | 1099.46 seconds |
Started | Jul 28 06:51:58 PM PDT 24 |
Finished | Jul 28 07:10:18 PM PDT 24 |
Peak memory | 380012 kb |
Host | smart-abd6f0f3-a372-4493-aaa4-d801657dc6f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908977160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.3908977160 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.3359945979 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 1961339514 ps |
CPU time | 22.44 seconds |
Started | Jul 28 06:51:59 PM PDT 24 |
Finished | Jul 28 06:52:21 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-cb678fae-d2f0-4f91-bbd3-618c88d018a9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359945979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.3359945979 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1825054827 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 29901252558 ps |
CPU time | 366.12 seconds |
Started | Jul 28 06:51:58 PM PDT 24 |
Finished | Jul 28 06:58:04 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-5d1d9c3d-1aeb-4973-b1e5-61b25c9779f3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825054827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.1825054827 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.3545991090 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 2805089233 ps |
CPU time | 3.42 seconds |
Started | Jul 28 06:52:02 PM PDT 24 |
Finished | Jul 28 06:52:05 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-ab1406d3-a590-463d-9d5d-d800305eb86a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545991090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3545991090 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.3906495401 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 12908231181 ps |
CPU time | 593.6 seconds |
Started | Jul 28 06:52:02 PM PDT 24 |
Finished | Jul 28 07:01:56 PM PDT 24 |
Peak memory | 373004 kb |
Host | smart-f729d2df-62f6-4119-8d02-1f45e851ab20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906495401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3906495401 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.1887468647 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 705759327 ps |
CPU time | 6.84 seconds |
Started | Jul 28 06:52:03 PM PDT 24 |
Finished | Jul 28 06:52:10 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-09b3ec5e-957c-460e-be37-9a1094d66584 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887468647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1887468647 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.3268652983 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 268192482610 ps |
CPU time | 1506.05 seconds |
Started | Jul 28 06:52:08 PM PDT 24 |
Finished | Jul 28 07:17:14 PM PDT 24 |
Peak memory | 366196 kb |
Host | smart-44593d01-ec09-4ad0-b271-98b3ecd0d67c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268652983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.3268652983 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.923767670 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 571754276 ps |
CPU time | 17.41 seconds |
Started | Jul 28 06:52:08 PM PDT 24 |
Finished | Jul 28 06:52:26 PM PDT 24 |
Peak memory | 212912 kb |
Host | smart-19379f30-0f15-4e33-a553-a59c125905ea |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=923767670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.923767670 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3606356425 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 11019684017 ps |
CPU time | 209.47 seconds |
Started | Jul 28 06:51:58 PM PDT 24 |
Finished | Jul 28 06:55:28 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-f0fe355b-b6e1-4f07-846c-a2d52278e053 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606356425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.3606356425 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1930091574 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 1587226770 ps |
CPU time | 92.32 seconds |
Started | Jul 28 06:52:04 PM PDT 24 |
Finished | Jul 28 06:53:36 PM PDT 24 |
Peak memory | 342116 kb |
Host | smart-ee2e6cb2-f0f7-4b70-8431-aafd9d8e1bc1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930091574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1930091574 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2512250538 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 42455019817 ps |
CPU time | 810.42 seconds |
Started | Jul 28 06:52:13 PM PDT 24 |
Finished | Jul 28 07:05:43 PM PDT 24 |
Peak memory | 372016 kb |
Host | smart-3937d374-e152-45ed-b1f6-c349410dce3b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512250538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.2512250538 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.3744080627 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 15602336 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:52:26 PM PDT 24 |
Finished | Jul 28 06:52:27 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-344ec1cc-d387-463d-a104-bb77392d4578 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744080627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3744080627 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.2226978301 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 631133429959 ps |
CPU time | 2263.07 seconds |
Started | Jul 28 06:52:07 PM PDT 24 |
Finished | Jul 28 07:29:51 PM PDT 24 |
Peak memory | 203868 kb |
Host | smart-617e14c6-eccf-491a-895c-9f1ead81ff40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226978301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 2226978301 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.3228607997 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 58609222604 ps |
CPU time | 772.32 seconds |
Started | Jul 28 06:52:17 PM PDT 24 |
Finished | Jul 28 07:05:10 PM PDT 24 |
Peak memory | 379120 kb |
Host | smart-d2a43fc7-d5d1-4a23-8b50-fc2c13d93117 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228607997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.3228607997 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.1595602048 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 40213982490 ps |
CPU time | 61.32 seconds |
Started | Jul 28 06:52:12 PM PDT 24 |
Finished | Jul 28 06:53:13 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-75f51378-a0a8-40fc-b016-9ce59fb61bd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595602048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.1595602048 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.2652733377 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 8282991584 ps |
CPU time | 76.96 seconds |
Started | Jul 28 06:52:12 PM PDT 24 |
Finished | Jul 28 06:53:29 PM PDT 24 |
Peak memory | 343148 kb |
Host | smart-fd2c8949-d59d-44ca-94f3-352ae75d647f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652733377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.2652733377 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4038348253 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 3297730443 ps |
CPU time | 145.13 seconds |
Started | Jul 28 06:52:25 PM PDT 24 |
Finished | Jul 28 06:54:51 PM PDT 24 |
Peak memory | 211276 kb |
Host | smart-2fdea678-1e1c-418b-9bd1-71a5b0fb07b7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038348253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.4038348253 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.183626693 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 43164141721 ps |
CPU time | 189.82 seconds |
Started | Jul 28 06:52:22 PM PDT 24 |
Finished | Jul 28 06:55:32 PM PDT 24 |
Peak memory | 203852 kb |
Host | smart-afc3a809-0937-4870-91cf-36a731e885f9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183626693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ mem_walk.183626693 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.1590308507 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 6303625639 ps |
CPU time | 387.32 seconds |
Started | Jul 28 06:52:12 PM PDT 24 |
Finished | Jul 28 06:58:39 PM PDT 24 |
Peak memory | 360596 kb |
Host | smart-3938d4ea-aab3-4888-a4ff-8da48e120b64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590308507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.1590308507 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.2599451562 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 3839948685 ps |
CPU time | 42.79 seconds |
Started | Jul 28 06:52:12 PM PDT 24 |
Finished | Jul 28 06:52:55 PM PDT 24 |
Peak memory | 296160 kb |
Host | smart-5210edaf-0ed5-431a-8247-dc731fa0d9bd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599451562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.2599451562 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2348709316 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 35677209509 ps |
CPU time | 454.82 seconds |
Started | Jul 28 06:52:13 PM PDT 24 |
Finished | Jul 28 06:59:48 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-030b5557-fbd2-4cd2-9597-add4f70e54e6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348709316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.2348709316 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.514827170 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 360921390 ps |
CPU time | 3.05 seconds |
Started | Jul 28 06:52:17 PM PDT 24 |
Finished | Jul 28 06:52:20 PM PDT 24 |
Peak memory | 203092 kb |
Host | smart-a80546c7-5da6-49f4-a52a-db9a8e002684 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514827170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.514827170 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2984158399 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 3024949786 ps |
CPU time | 1119.59 seconds |
Started | Jul 28 06:52:17 PM PDT 24 |
Finished | Jul 28 07:10:57 PM PDT 24 |
Peak memory | 378008 kb |
Host | smart-1ba83081-6aec-424b-aef2-3ab8774b9dc8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984158399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2984158399 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.3688734429 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 871895834 ps |
CPU time | 17.57 seconds |
Started | Jul 28 06:52:09 PM PDT 24 |
Finished | Jul 28 06:52:27 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-90d1da4b-681c-432e-a547-febbb7930e94 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688734429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3688734429 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.507810322 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 130701771620 ps |
CPU time | 2331.5 seconds |
Started | Jul 28 06:52:21 PM PDT 24 |
Finished | Jul 28 07:31:13 PM PDT 24 |
Peak memory | 380160 kb |
Host | smart-fd289fc1-a8c2-4f81-afb0-aff29c9ca021 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507810322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_stress_all.507810322 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3359287723 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 9402738570 ps |
CPU time | 292.45 seconds |
Started | Jul 28 06:52:26 PM PDT 24 |
Finished | Jul 28 06:57:18 PM PDT 24 |
Peak memory | 376960 kb |
Host | smart-8205c644-7631-4d01-8f5b-03af1e2d7b53 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3359287723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3359287723 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.178529718 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 2389449268 ps |
CPU time | 179.96 seconds |
Started | Jul 28 06:52:09 PM PDT 24 |
Finished | Jul 28 06:55:09 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-5cf5adc2-528e-4f13-b32e-aae6ecc2a235 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178529718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_stress_pipeline.178529718 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.285194930 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 4306405189 ps |
CPU time | 40.01 seconds |
Started | Jul 28 06:52:13 PM PDT 24 |
Finished | Jul 28 06:52:53 PM PDT 24 |
Peak memory | 294100 kb |
Host | smart-7c438b66-2261-4d2c-9cc8-0432f542cc47 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285194930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.285194930 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1041489752 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 85320722371 ps |
CPU time | 1022.08 seconds |
Started | Jul 28 06:52:29 PM PDT 24 |
Finished | Jul 28 07:09:32 PM PDT 24 |
Peak memory | 379668 kb |
Host | smart-229a1dc0-7a35-4a98-a492-4f7b711e0cfe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041489752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.1041489752 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.124941886 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 79485718 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:52:38 PM PDT 24 |
Finished | Jul 28 06:52:38 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-08d175db-5c49-4375-9073-af36122c738f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124941886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.124941886 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.1862244340 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 10040892313 ps |
CPU time | 659.44 seconds |
Started | Jul 28 06:52:21 PM PDT 24 |
Finished | Jul 28 07:03:21 PM PDT 24 |
Peak memory | 204028 kb |
Host | smart-e4df3a13-562c-4058-b029-8df621c8b5fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862244340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 1862244340 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.2316723135 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 902315615 ps |
CPU time | 93.31 seconds |
Started | Jul 28 06:52:31 PM PDT 24 |
Finished | Jul 28 06:54:04 PM PDT 24 |
Peak memory | 331812 kb |
Host | smart-497b53bb-43f6-43f0-ab31-1cb1e08cf464 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316723135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.2316723135 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.1234280302 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 27452595883 ps |
CPU time | 73.85 seconds |
Started | Jul 28 06:52:33 PM PDT 24 |
Finished | Jul 28 06:53:47 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-e5f3c20c-8b02-490f-95ca-ea6d0cad1b57 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234280302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.1234280302 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.2570899243 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 1861652632 ps |
CPU time | 82.38 seconds |
Started | Jul 28 06:52:28 PM PDT 24 |
Finished | Jul 28 06:53:51 PM PDT 24 |
Peak memory | 334004 kb |
Host | smart-21bd92f8-04cf-44e0-8bfb-617be7adc811 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570899243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.2570899243 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1989782245 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 34027816218 ps |
CPU time | 90.54 seconds |
Started | Jul 28 06:52:35 PM PDT 24 |
Finished | Jul 28 06:54:06 PM PDT 24 |
Peak memory | 211912 kb |
Host | smart-8637d7b7-d9e8-4517-8735-ff269f4c380b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989782245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.1989782245 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.548398737 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 43047226796 ps |
CPU time | 351.25 seconds |
Started | Jul 28 06:52:33 PM PDT 24 |
Finished | Jul 28 06:58:25 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-d690c956-b395-4008-a877-a2f27e67f4b2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548398737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ mem_walk.548398737 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.239182311 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 13727283262 ps |
CPU time | 657.7 seconds |
Started | Jul 28 06:52:21 PM PDT 24 |
Finished | Jul 28 07:03:18 PM PDT 24 |
Peak memory | 381044 kb |
Host | smart-f686b8ab-4174-4139-846e-7d14946b86a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239182311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multipl e_keys.239182311 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.2245721093 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 628230035 ps |
CPU time | 19.69 seconds |
Started | Jul 28 06:52:28 PM PDT 24 |
Finished | Jul 28 06:52:48 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-575b4b8f-4263-48b7-b38c-b14c4f679fdc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245721093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.2245721093 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1989720921 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 9802786371 ps |
CPU time | 241.16 seconds |
Started | Jul 28 06:52:25 PM PDT 24 |
Finished | Jul 28 06:56:27 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-6830b94a-fb5e-4850-bcdd-726ccb5e430a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989720921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.1989720921 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.2376353751 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 688632195 ps |
CPU time | 3.35 seconds |
Started | Jul 28 06:52:30 PM PDT 24 |
Finished | Jul 28 06:52:34 PM PDT 24 |
Peak memory | 203056 kb |
Host | smart-ef791587-1063-41a0-90a7-f21918888954 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376353751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2376353751 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.3354393014 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 22945278739 ps |
CPU time | 1844.68 seconds |
Started | Jul 28 06:52:30 PM PDT 24 |
Finished | Jul 28 07:23:15 PM PDT 24 |
Peak memory | 375936 kb |
Host | smart-bf79502a-2deb-49cf-95b0-5ef1d0e96f47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354393014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3354393014 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.3647959137 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 934781287 ps |
CPU time | 83.64 seconds |
Started | Jul 28 06:52:22 PM PDT 24 |
Finished | Jul 28 06:53:45 PM PDT 24 |
Peak memory | 351256 kb |
Host | smart-246943bf-f5d1-4eb5-8f48-e057cb99e449 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647959137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3647959137 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.760390777 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 204135250319 ps |
CPU time | 2950.37 seconds |
Started | Jul 28 06:52:38 PM PDT 24 |
Finished | Jul 28 07:41:49 PM PDT 24 |
Peak memory | 379132 kb |
Host | smart-a116224f-186e-4767-8cf0-2b4b5a833eb1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760390777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_stress_all.760390777 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3944204293 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 2033684170 ps |
CPU time | 17.27 seconds |
Started | Jul 28 06:52:35 PM PDT 24 |
Finished | Jul 28 06:52:52 PM PDT 24 |
Peak memory | 211372 kb |
Host | smart-7d661d43-833f-4438-978f-b1f04da62ee1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3944204293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3944204293 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.18080344 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 2715002160 ps |
CPU time | 163.97 seconds |
Started | Jul 28 06:52:25 PM PDT 24 |
Finished | Jul 28 06:55:09 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-1e01b7a4-cf20-4574-8b2a-ab0f1c146a2e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18080344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_stress_pipeline.18080344 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.873934162 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 2566046688 ps |
CPU time | 6.11 seconds |
Started | Jul 28 06:52:31 PM PDT 24 |
Finished | Jul 28 06:52:38 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-cd482ec3-d3f2-4c39-9f11-99abf474d90f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873934162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_throughput_w_partial_write.873934162 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.424773164 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 17999835251 ps |
CPU time | 1106.78 seconds |
Started | Jul 28 06:52:46 PM PDT 24 |
Finished | Jul 28 07:11:13 PM PDT 24 |
Peak memory | 376960 kb |
Host | smart-cc42a4a4-7c0b-42e2-8c9c-0456cff8880c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424773164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_access_during_key_req.424773164 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.2667625096 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 13674265 ps |
CPU time | 0.68 seconds |
Started | Jul 28 06:52:52 PM PDT 24 |
Finished | Jul 28 06:52:52 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-a91da759-2511-4e08-b933-6ef5a868426f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667625096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.2667625096 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.920557382 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 43867491744 ps |
CPU time | 762.56 seconds |
Started | Jul 28 06:52:39 PM PDT 24 |
Finished | Jul 28 07:05:22 PM PDT 24 |
Peak memory | 203992 kb |
Host | smart-bdc3a979-3a4c-4ee0-bfd0-acc67c87793a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920557382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.920557382 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.3569564789 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 113020408445 ps |
CPU time | 1193.83 seconds |
Started | Jul 28 06:52:46 PM PDT 24 |
Finished | Jul 28 07:12:40 PM PDT 24 |
Peak memory | 380080 kb |
Host | smart-ee02466d-a4ac-4ae6-a3fa-f664cd931773 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569564789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.3569564789 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.2689388817 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 54420814971 ps |
CPU time | 95.24 seconds |
Started | Jul 28 06:52:46 PM PDT 24 |
Finished | Jul 28 06:54:21 PM PDT 24 |
Peak memory | 216116 kb |
Host | smart-e6cb43ad-e920-47f4-b3a9-3ad1605fb235 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689388817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.2689388817 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.1939478237 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 2884529228 ps |
CPU time | 44.14 seconds |
Started | Jul 28 06:52:39 PM PDT 24 |
Finished | Jul 28 06:53:23 PM PDT 24 |
Peak memory | 295280 kb |
Host | smart-1d2e5f2d-6653-4033-b7b8-214e32b2959c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939478237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.1939478237 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1662660898 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 17358623103 ps |
CPU time | 82.45 seconds |
Started | Jul 28 06:52:45 PM PDT 24 |
Finished | Jul 28 06:54:08 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-d63dd32c-16c8-4d54-8db5-b7038408c4a1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662660898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.1662660898 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.1855608263 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 18948263522 ps |
CPU time | 316.32 seconds |
Started | Jul 28 06:52:45 PM PDT 24 |
Finished | Jul 28 06:58:02 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-a11d211c-2e94-4e1f-bcf9-7e7cc44206a7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855608263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.1855608263 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.3507242936 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 9244831786 ps |
CPU time | 555.16 seconds |
Started | Jul 28 06:52:35 PM PDT 24 |
Finished | Jul 28 07:01:50 PM PDT 24 |
Peak memory | 380936 kb |
Host | smart-fecabde1-5b0c-44a5-b67a-fe0a508f0ab8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507242936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.3507242936 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.849617267 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 1164838509 ps |
CPU time | 17.37 seconds |
Started | Jul 28 06:52:40 PM PDT 24 |
Finished | Jul 28 06:52:58 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-599e0b78-a9cb-4ebc-b94e-cde73edfd02e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849617267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr am_ctrl_partial_access.849617267 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1278242717 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 72234816704 ps |
CPU time | 449.73 seconds |
Started | Jul 28 06:52:41 PM PDT 24 |
Finished | Jul 28 07:00:11 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-bc7b7f87-1c1e-4623-882a-d5641fafcd93 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278242717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.1278242717 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.4172196761 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1467326289 ps |
CPU time | 3.4 seconds |
Started | Jul 28 06:52:45 PM PDT 24 |
Finished | Jul 28 06:52:49 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-b01a7032-fdec-4ed6-bdb2-fef92ef0e78a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172196761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.4172196761 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.3425430177 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 13661524412 ps |
CPU time | 341.33 seconds |
Started | Jul 28 06:52:44 PM PDT 24 |
Finished | Jul 28 06:58:26 PM PDT 24 |
Peak memory | 372940 kb |
Host | smart-84d7d206-cdf2-4631-b73a-6cc366ccb75d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425430177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3425430177 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.1060197843 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 1971453651 ps |
CPU time | 8.51 seconds |
Started | Jul 28 06:52:35 PM PDT 24 |
Finished | Jul 28 06:52:44 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-f050eb2a-300f-489f-b66a-f706be38c1ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060197843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1060197843 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.106220499 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 222714481954 ps |
CPU time | 3754.85 seconds |
Started | Jul 28 06:52:48 PM PDT 24 |
Finished | Jul 28 07:55:23 PM PDT 24 |
Peak memory | 380048 kb |
Host | smart-5575f957-7caf-46d1-a5c3-438644d3c262 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106220499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_stress_all.106220499 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.646359041 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 5017317415 ps |
CPU time | 23.93 seconds |
Started | Jul 28 06:52:49 PM PDT 24 |
Finished | Jul 28 06:53:13 PM PDT 24 |
Peak memory | 211436 kb |
Host | smart-3f082ee4-2f05-4678-ac29-065af5ba192d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=646359041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.646359041 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3348236503 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 4250590145 ps |
CPU time | 301.3 seconds |
Started | Jul 28 06:52:40 PM PDT 24 |
Finished | Jul 28 06:57:42 PM PDT 24 |
Peak memory | 203188 kb |
Host | smart-5a039f66-d7bf-4290-8b68-a1847404815d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348236503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.3348236503 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.38352029 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 718820201 ps |
CPU time | 18.17 seconds |
Started | Jul 28 06:52:45 PM PDT 24 |
Finished | Jul 28 06:53:04 PM PDT 24 |
Peak memory | 261120 kb |
Host | smart-989ffc61-bd81-4daf-90a9-6c76342bbf1f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38352029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.sram_ctrl_throughput_w_partial_write.38352029 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.4208076421 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 17954742707 ps |
CPU time | 2174.77 seconds |
Started | Jul 28 06:52:58 PM PDT 24 |
Finished | Jul 28 07:29:13 PM PDT 24 |
Peak memory | 380084 kb |
Host | smart-dd2ac413-39b3-463e-ba2c-6651c0c4ab7e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208076421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.4208076421 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.2714334603 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 118753412 ps |
CPU time | 0.67 seconds |
Started | Jul 28 06:53:03 PM PDT 24 |
Finished | Jul 28 06:53:04 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-162e16b4-81c0-4574-9041-ca8b5dc85853 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714334603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2714334603 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.993696170 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 121571641471 ps |
CPU time | 2044.94 seconds |
Started | Jul 28 06:52:53 PM PDT 24 |
Finished | Jul 28 07:26:59 PM PDT 24 |
Peak memory | 203684 kb |
Host | smart-5d2c5b79-8d45-433a-8454-6dace5a15b54 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993696170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.993696170 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.2227332635 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 55575848268 ps |
CPU time | 1213.84 seconds |
Started | Jul 28 06:52:58 PM PDT 24 |
Finished | Jul 28 07:13:12 PM PDT 24 |
Peak memory | 380268 kb |
Host | smart-7ecd5dcd-5c44-4c58-af0b-39393c89ae8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227332635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.2227332635 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.1193158219 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 38549624832 ps |
CPU time | 72.01 seconds |
Started | Jul 28 06:52:58 PM PDT 24 |
Finished | Jul 28 06:54:10 PM PDT 24 |
Peak memory | 203176 kb |
Host | smart-ba144fb5-02ac-4ef8-950a-899126af3eed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193158219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.1193158219 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.4094844933 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 741482946 ps |
CPU time | 15.89 seconds |
Started | Jul 28 06:52:54 PM PDT 24 |
Finished | Jul 28 06:53:10 PM PDT 24 |
Peak memory | 253252 kb |
Host | smart-27043ffc-c7ff-45b8-8c37-4aebecc451f6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094844933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.4094844933 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1156315391 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 1632888355 ps |
CPU time | 120.54 seconds |
Started | Jul 28 06:53:01 PM PDT 24 |
Finished | Jul 28 06:55:02 PM PDT 24 |
Peak memory | 211308 kb |
Host | smart-6feaa6fd-732a-490c-9362-f6a01532182e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156315391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.1156315391 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.3342891601 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 74780189338 ps |
CPU time | 344.68 seconds |
Started | Jul 28 06:53:01 PM PDT 24 |
Finished | Jul 28 06:58:45 PM PDT 24 |
Peak memory | 204104 kb |
Host | smart-2ddbc9e0-85c1-42bc-ac28-59d7c687b5f4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342891601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3342891601 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.2502118813 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 5338139221 ps |
CPU time | 279.08 seconds |
Started | Jul 28 06:52:48 PM PDT 24 |
Finished | Jul 28 06:57:27 PM PDT 24 |
Peak memory | 327968 kb |
Host | smart-345015b5-b98a-424f-b437-a01f8beb0a42 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502118813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.2502118813 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.1188809308 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 506158880 ps |
CPU time | 13.36 seconds |
Started | Jul 28 06:52:56 PM PDT 24 |
Finished | Jul 28 06:53:09 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-15309cfa-5814-4936-9022-20420709c1f9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188809308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.1188809308 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3297199012 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 33595772245 ps |
CPU time | 355.77 seconds |
Started | Jul 28 06:52:53 PM PDT 24 |
Finished | Jul 28 06:58:49 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-d985065a-1dc7-47f6-8bd4-889b29a2de1d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297199012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.3297199012 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.2507886210 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 354299252 ps |
CPU time | 3.37 seconds |
Started | Jul 28 06:53:00 PM PDT 24 |
Finished | Jul 28 06:53:03 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-a3ac22f2-2e82-4451-a2c9-30e40a42dd25 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507886210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2507886210 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.676260912 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 23024270642 ps |
CPU time | 953.76 seconds |
Started | Jul 28 06:53:01 PM PDT 24 |
Finished | Jul 28 07:08:55 PM PDT 24 |
Peak memory | 372308 kb |
Host | smart-dae840fc-bf37-40ef-92c6-89cc2622a338 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676260912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.676260912 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.29940661 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 823888673 ps |
CPU time | 8.01 seconds |
Started | Jul 28 06:52:51 PM PDT 24 |
Finished | Jul 28 06:52:59 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-f0682e62-c0db-4d26-a501-96f195ee57d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29940661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.29940661 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.3458573163 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 73544825761 ps |
CPU time | 7274.47 seconds |
Started | Jul 28 06:53:03 PM PDT 24 |
Finished | Jul 28 08:54:18 PM PDT 24 |
Peak memory | 382568 kb |
Host | smart-349e7d29-2bde-4b01-883c-81f0d7867523 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458573163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.3458573163 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4275748744 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1919420936 ps |
CPU time | 15.1 seconds |
Started | Jul 28 06:53:04 PM PDT 24 |
Finished | Jul 28 06:53:19 PM PDT 24 |
Peak memory | 211956 kb |
Host | smart-1ad5182a-b1b1-42f7-a435-5c22992d6895 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4275748744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.4275748744 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2268530927 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 3785965410 ps |
CPU time | 246.19 seconds |
Started | Jul 28 06:52:53 PM PDT 24 |
Finished | Jul 28 06:57:00 PM PDT 24 |
Peak memory | 203092 kb |
Host | smart-d6bd91ac-6999-491c-b5c9-d30aadcc40c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268530927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.2268530927 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3362490564 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 2904510576 ps |
CPU time | 13.29 seconds |
Started | Jul 28 06:52:58 PM PDT 24 |
Finished | Jul 28 06:53:12 PM PDT 24 |
Peak memory | 240880 kb |
Host | smart-aaf8399f-b16e-4a11-9f76-958bb278d2a7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362490564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3362490564 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |