| T799 |
/workspace/coverage/default/28.sram_ctrl_smoke.2689397918 |
|
|
Aug 05 06:19:21 PM PDT 24 |
Aug 05 06:19:31 PM PDT 24 |
373394780 ps |
| T800 |
/workspace/coverage/default/2.sram_ctrl_smoke.1652276843 |
|
|
Aug 05 06:15:53 PM PDT 24 |
Aug 05 06:16:51 PM PDT 24 |
2455407515 ps |
| T801 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1251986422 |
|
|
Aug 05 06:18:49 PM PDT 24 |
Aug 05 06:20:37 PM PDT 24 |
18559765256 ps |
| T802 |
/workspace/coverage/default/29.sram_ctrl_regwen.134299361 |
|
|
Aug 05 06:19:33 PM PDT 24 |
Aug 05 06:26:18 PM PDT 24 |
8130386728 ps |
| T803 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.888453794 |
|
|
Aug 05 06:19:16 PM PDT 24 |
Aug 05 06:22:39 PM PDT 24 |
3622295730 ps |
| T804 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.410454535 |
|
|
Aug 05 06:19:23 PM PDT 24 |
Aug 05 06:22:04 PM PDT 24 |
8951313245 ps |
| T805 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.1305504114 |
|
|
Aug 05 06:15:59 PM PDT 24 |
Aug 05 06:34:45 PM PDT 24 |
80606248826 ps |
| T806 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2627188537 |
|
|
Aug 05 06:16:44 PM PDT 24 |
Aug 05 06:17:04 PM PDT 24 |
2336259553 ps |
| T807 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1829915398 |
|
|
Aug 05 06:17:35 PM PDT 24 |
Aug 05 06:18:03 PM PDT 24 |
754813079 ps |
| T808 |
/workspace/coverage/default/46.sram_ctrl_bijection.1712833150 |
|
|
Aug 05 06:22:21 PM PDT 24 |
Aug 05 07:04:24 PM PDT 24 |
205103214248 ps |
| T809 |
/workspace/coverage/default/23.sram_ctrl_smoke.2233526019 |
|
|
Aug 05 06:18:38 PM PDT 24 |
Aug 05 06:18:51 PM PDT 24 |
2100969649 ps |
| T810 |
/workspace/coverage/default/8.sram_ctrl_smoke.1399256532 |
|
|
Aug 05 06:16:23 PM PDT 24 |
Aug 05 06:17:03 PM PDT 24 |
1091663830 ps |
| T811 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.200662872 |
|
|
Aug 05 06:19:24 PM PDT 24 |
Aug 05 06:20:09 PM PDT 24 |
1574580270 ps |
| T812 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2971186158 |
|
|
Aug 05 06:16:37 PM PDT 24 |
Aug 05 06:17:21 PM PDT 24 |
2794765271 ps |
| T813 |
/workspace/coverage/default/26.sram_ctrl_regwen.736178546 |
|
|
Aug 05 06:19:18 PM PDT 24 |
Aug 05 06:40:10 PM PDT 24 |
18339627445 ps |
| T814 |
/workspace/coverage/default/20.sram_ctrl_stress_all.3084581344 |
|
|
Aug 05 06:18:14 PM PDT 24 |
Aug 05 07:28:32 PM PDT 24 |
161875344794 ps |
| T815 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3952257928 |
|
|
Aug 05 06:18:03 PM PDT 24 |
Aug 05 06:25:20 PM PDT 24 |
140919034523 ps |
| T816 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.4171999189 |
|
|
Aug 05 06:18:01 PM PDT 24 |
Aug 05 06:18:31 PM PDT 24 |
12343904224 ps |
| T817 |
/workspace/coverage/default/31.sram_ctrl_regwen.2088468453 |
|
|
Aug 05 06:19:50 PM PDT 24 |
Aug 05 06:24:32 PM PDT 24 |
24590381722 ps |
| T818 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.1899011489 |
|
|
Aug 05 06:15:58 PM PDT 24 |
Aug 05 06:21:45 PM PDT 24 |
20675857714 ps |
| T819 |
/workspace/coverage/default/35.sram_ctrl_stress_all.3587519125 |
|
|
Aug 05 06:20:39 PM PDT 24 |
Aug 05 07:34:42 PM PDT 24 |
815514720241 ps |
| T820 |
/workspace/coverage/default/32.sram_ctrl_stress_all.3463978222 |
|
|
Aug 05 06:20:01 PM PDT 24 |
Aug 05 07:43:32 PM PDT 24 |
1240954015541 ps |
| T821 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4146193599 |
|
|
Aug 05 06:16:54 PM PDT 24 |
Aug 05 06:17:28 PM PDT 24 |
762767048 ps |
| T125 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3102367782 |
|
|
Aug 05 06:20:12 PM PDT 24 |
Aug 05 06:20:21 PM PDT 24 |
3637861868 ps |
| T822 |
/workspace/coverage/default/1.sram_ctrl_bijection.3347452142 |
|
|
Aug 05 06:15:48 PM PDT 24 |
Aug 05 06:32:19 PM PDT 24 |
81792519872 ps |
| T823 |
/workspace/coverage/default/3.sram_ctrl_smoke.418649761 |
|
|
Aug 05 06:15:58 PM PDT 24 |
Aug 05 06:16:16 PM PDT 24 |
857915850 ps |
| T824 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1875311118 |
|
|
Aug 05 06:17:20 PM PDT 24 |
Aug 05 06:34:28 PM PDT 24 |
18327945376 ps |
| T825 |
/workspace/coverage/default/6.sram_ctrl_smoke.1646254969 |
|
|
Aug 05 06:16:14 PM PDT 24 |
Aug 05 06:16:20 PM PDT 24 |
2071860910 ps |
| T826 |
/workspace/coverage/default/47.sram_ctrl_regwen.1476764128 |
|
|
Aug 05 06:22:29 PM PDT 24 |
Aug 05 06:40:40 PM PDT 24 |
9871847419 ps |
| T827 |
/workspace/coverage/default/21.sram_ctrl_stress_all.3245179914 |
|
|
Aug 05 06:18:30 PM PDT 24 |
Aug 05 07:43:32 PM PDT 24 |
101336502538 ps |
| T828 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3518055365 |
|
|
Aug 05 06:17:03 PM PDT 24 |
Aug 05 06:21:32 PM PDT 24 |
19059408474 ps |
| T829 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1725762512 |
|
|
Aug 05 06:16:12 PM PDT 24 |
Aug 05 06:17:19 PM PDT 24 |
3102104701 ps |
| T830 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.486487905 |
|
|
Aug 05 06:15:48 PM PDT 24 |
Aug 05 06:17:46 PM PDT 24 |
16090581430 ps |
| T831 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2216846979 |
|
|
Aug 05 06:16:22 PM PDT 24 |
Aug 05 06:16:39 PM PDT 24 |
2925176477 ps |
| T832 |
/workspace/coverage/default/38.sram_ctrl_smoke.3466898258 |
|
|
Aug 05 06:20:54 PM PDT 24 |
Aug 05 06:21:01 PM PDT 24 |
1613476216 ps |
| T833 |
/workspace/coverage/default/45.sram_ctrl_smoke.1863808835 |
|
|
Aug 05 06:22:10 PM PDT 24 |
Aug 05 06:23:42 PM PDT 24 |
4401982757 ps |
| T834 |
/workspace/coverage/default/18.sram_ctrl_bijection.2753724097 |
|
|
Aug 05 06:18:03 PM PDT 24 |
Aug 05 06:50:43 PM PDT 24 |
110646171512 ps |
| T835 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.1861246006 |
|
|
Aug 05 06:18:32 PM PDT 24 |
Aug 05 06:18:35 PM PDT 24 |
1176505473 ps |
| T836 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.101740695 |
|
|
Aug 05 06:20:35 PM PDT 24 |
Aug 05 06:22:24 PM PDT 24 |
817540888 ps |
| T837 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.654563510 |
|
|
Aug 05 06:15:43 PM PDT 24 |
Aug 05 06:16:25 PM PDT 24 |
13114460313 ps |
| T838 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.867052706 |
|
|
Aug 05 06:19:35 PM PDT 24 |
Aug 05 06:21:42 PM PDT 24 |
1943810360 ps |
| T839 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.4007119835 |
|
|
Aug 05 06:15:41 PM PDT 24 |
Aug 05 06:21:46 PM PDT 24 |
35047255513 ps |
| T840 |
/workspace/coverage/default/1.sram_ctrl_alert_test.242210147 |
|
|
Aug 05 06:16:14 PM PDT 24 |
Aug 05 06:16:15 PM PDT 24 |
13713180 ps |
| T841 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1695711086 |
|
|
Aug 05 06:17:28 PM PDT 24 |
Aug 05 06:17:35 PM PDT 24 |
703981408 ps |
| T842 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3689137167 |
|
|
Aug 05 06:22:35 PM PDT 24 |
Aug 05 08:15:44 PM PDT 24 |
293115368485 ps |
| T843 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3083161681 |
|
|
Aug 05 06:15:58 PM PDT 24 |
Aug 05 06:18:05 PM PDT 24 |
3287400319 ps |
| T844 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.2281889314 |
|
|
Aug 05 06:19:59 PM PDT 24 |
Aug 05 06:20:12 PM PDT 24 |
5697732278 ps |
| T845 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.464025710 |
|
|
Aug 05 06:17:00 PM PDT 24 |
Aug 05 06:17:04 PM PDT 24 |
1604515771 ps |
| T846 |
/workspace/coverage/default/6.sram_ctrl_partial_access.122065617 |
|
|
Aug 05 06:16:18 PM PDT 24 |
Aug 05 06:18:33 PM PDT 24 |
5152734911 ps |
| T847 |
/workspace/coverage/default/32.sram_ctrl_smoke.3780747457 |
|
|
Aug 05 06:19:55 PM PDT 24 |
Aug 05 06:20:10 PM PDT 24 |
2129870815 ps |
| T848 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1754805074 |
|
|
Aug 05 06:20:58 PM PDT 24 |
Aug 05 06:21:04 PM PDT 24 |
982039924 ps |
| T849 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3920331238 |
|
|
Aug 05 06:21:50 PM PDT 24 |
Aug 05 06:21:54 PM PDT 24 |
356953937 ps |
| T850 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2361354424 |
|
|
Aug 05 06:16:53 PM PDT 24 |
Aug 05 06:18:29 PM PDT 24 |
11442649249 ps |
| T851 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1596499595 |
|
|
Aug 05 06:20:07 PM PDT 24 |
Aug 05 06:20:59 PM PDT 24 |
9229544229 ps |
| T852 |
/workspace/coverage/default/16.sram_ctrl_bijection.3591948645 |
|
|
Aug 05 06:17:37 PM PDT 24 |
Aug 05 06:41:00 PM PDT 24 |
221496713931 ps |
| T853 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1955174112 |
|
|
Aug 05 06:17:38 PM PDT 24 |
Aug 05 06:17:39 PM PDT 24 |
97059829 ps |
| T854 |
/workspace/coverage/default/18.sram_ctrl_partial_access.4060744129 |
|
|
Aug 05 06:17:59 PM PDT 24 |
Aug 05 06:18:16 PM PDT 24 |
2894540645 ps |
| T855 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.2310299530 |
|
|
Aug 05 06:17:32 PM PDT 24 |
Aug 05 06:18:46 PM PDT 24 |
7363218950 ps |
| T856 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2870152693 |
|
|
Aug 05 06:21:51 PM PDT 24 |
Aug 05 06:23:23 PM PDT 24 |
1549979456 ps |
| T857 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4234445527 |
|
|
Aug 05 06:16:10 PM PDT 24 |
Aug 05 06:45:20 PM PDT 24 |
104063491147 ps |
| T858 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.3116891637 |
|
|
Aug 05 06:19:20 PM PDT 24 |
Aug 05 06:22:32 PM PDT 24 |
2709543022 ps |
| T859 |
/workspace/coverage/default/13.sram_ctrl_smoke.3768404561 |
|
|
Aug 05 06:17:16 PM PDT 24 |
Aug 05 06:17:25 PM PDT 24 |
715178620 ps |
| T860 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.1724606077 |
|
|
Aug 05 06:18:01 PM PDT 24 |
Aug 05 06:19:07 PM PDT 24 |
5717558754 ps |
| T861 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1741438 |
|
|
Aug 05 06:19:15 PM PDT 24 |
Aug 05 06:19:18 PM PDT 24 |
356815624 ps |
| T862 |
/workspace/coverage/default/13.sram_ctrl_bijection.844981587 |
|
|
Aug 05 06:17:15 PM PDT 24 |
Aug 05 06:30:11 PM PDT 24 |
31199690021 ps |
| T863 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.2675208453 |
|
|
Aug 05 06:19:44 PM PDT 24 |
Aug 05 06:21:55 PM PDT 24 |
2039786059 ps |
| T34 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.669633792 |
|
|
Aug 05 06:15:48 PM PDT 24 |
Aug 05 06:15:51 PM PDT 24 |
784568713 ps |
| T864 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.129116369 |
|
|
Aug 05 06:22:09 PM PDT 24 |
Aug 05 06:44:46 PM PDT 24 |
25053859002 ps |
| T865 |
/workspace/coverage/default/28.sram_ctrl_stress_all.213574890 |
|
|
Aug 05 06:19:29 PM PDT 24 |
Aug 05 08:21:12 PM PDT 24 |
305050334224 ps |
| T866 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2215497008 |
|
|
Aug 05 06:16:22 PM PDT 24 |
Aug 05 06:16:23 PM PDT 24 |
67468070 ps |
| T867 |
/workspace/coverage/default/9.sram_ctrl_stress_all.4039358289 |
|
|
Aug 05 06:16:43 PM PDT 24 |
Aug 05 06:40:25 PM PDT 24 |
27849176123 ps |
| T868 |
/workspace/coverage/default/41.sram_ctrl_smoke.1504812515 |
|
|
Aug 05 06:21:29 PM PDT 24 |
Aug 05 06:21:45 PM PDT 24 |
1066981027 ps |
| T869 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2603583637 |
|
|
Aug 05 06:19:57 PM PDT 24 |
Aug 05 06:21:13 PM PDT 24 |
2883081161 ps |
| T870 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.630490281 |
|
|
Aug 05 06:21:40 PM PDT 24 |
Aug 05 06:22:18 PM PDT 24 |
724693623 ps |
| T871 |
/workspace/coverage/default/4.sram_ctrl_bijection.2014545563 |
|
|
Aug 05 06:16:04 PM PDT 24 |
Aug 05 06:25:28 PM PDT 24 |
17478461455 ps |
| T872 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3475439652 |
|
|
Aug 05 06:15:55 PM PDT 24 |
Aug 05 06:16:58 PM PDT 24 |
9705019237 ps |
| T873 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1142891926 |
|
|
Aug 05 06:18:10 PM PDT 24 |
Aug 05 06:18:30 PM PDT 24 |
712587624 ps |
| T874 |
/workspace/coverage/default/18.sram_ctrl_executable.1896035458 |
|
|
Aug 05 06:18:01 PM PDT 24 |
Aug 05 06:36:53 PM PDT 24 |
10253611780 ps |
| T875 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3352846406 |
|
|
Aug 05 06:17:39 PM PDT 24 |
Aug 05 06:35:48 PM PDT 24 |
27396794257 ps |
| T876 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.1032563384 |
|
|
Aug 05 06:17:43 PM PDT 24 |
Aug 05 06:18:03 PM PDT 24 |
1265661950 ps |
| T877 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3895524492 |
|
|
Aug 05 06:18:32 PM PDT 24 |
Aug 05 06:24:04 PM PDT 24 |
8994724278 ps |
| T878 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1209746126 |
|
|
Aug 05 06:21:52 PM PDT 24 |
Aug 05 06:27:11 PM PDT 24 |
5363895253 ps |
| T879 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.657162627 |
|
|
Aug 05 06:18:15 PM PDT 24 |
Aug 05 06:28:46 PM PDT 24 |
40535737648 ps |
| T880 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.3672058859 |
|
|
Aug 05 06:19:56 PM PDT 24 |
Aug 05 06:19:59 PM PDT 24 |
359810869 ps |
| T881 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2707750050 |
|
|
Aug 05 06:21:40 PM PDT 24 |
Aug 05 06:25:24 PM PDT 24 |
4276775558 ps |
| T882 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.808155641 |
|
|
Aug 05 06:18:15 PM PDT 24 |
Aug 05 06:21:47 PM PDT 24 |
43882657879 ps |
| T883 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.18325840 |
|
|
Aug 05 06:17:37 PM PDT 24 |
Aug 05 06:19:38 PM PDT 24 |
823884397 ps |
| T884 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2676206130 |
|
|
Aug 05 06:19:46 PM PDT 24 |
Aug 05 06:19:49 PM PDT 24 |
374328940 ps |
| T885 |
/workspace/coverage/default/42.sram_ctrl_bijection.4147064781 |
|
|
Aug 05 06:21:40 PM PDT 24 |
Aug 05 06:45:18 PM PDT 24 |
74925026802 ps |
| T886 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1227505917 |
|
|
Aug 05 06:16:19 PM PDT 24 |
Aug 05 06:21:15 PM PDT 24 |
9128814885 ps |
| T887 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.3003827500 |
|
|
Aug 05 06:21:41 PM PDT 24 |
Aug 05 06:25:54 PM PDT 24 |
7879168421 ps |
| T888 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2463162528 |
|
|
Aug 05 06:19:49 PM PDT 24 |
Aug 05 06:24:06 PM PDT 24 |
4388127945 ps |
| T889 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3473130226 |
|
|
Aug 05 06:20:34 PM PDT 24 |
Aug 05 06:20:56 PM PDT 24 |
742343527 ps |
| T890 |
/workspace/coverage/default/16.sram_ctrl_executable.3047269756 |
|
|
Aug 05 06:17:40 PM PDT 24 |
Aug 05 06:35:28 PM PDT 24 |
23707475375 ps |
| T891 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3407347645 |
|
|
Aug 05 06:17:32 PM PDT 24 |
Aug 05 06:18:50 PM PDT 24 |
6156725612 ps |
| T892 |
/workspace/coverage/default/26.sram_ctrl_executable.2565907996 |
|
|
Aug 05 06:19:15 PM PDT 24 |
Aug 05 06:43:34 PM PDT 24 |
44031271929 ps |
| T893 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1162490151 |
|
|
Aug 05 06:21:50 PM PDT 24 |
Aug 05 06:22:54 PM PDT 24 |
759162721 ps |
| T894 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.1865747542 |
|
|
Aug 05 06:19:53 PM PDT 24 |
Aug 05 06:20:28 PM PDT 24 |
11114947173 ps |
| T895 |
/workspace/coverage/default/0.sram_ctrl_bijection.571333264 |
|
|
Aug 05 06:15:43 PM PDT 24 |
Aug 05 06:50:28 PM PDT 24 |
37488964516 ps |
| T896 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1455142560 |
|
|
Aug 05 06:21:11 PM PDT 24 |
Aug 05 06:21:30 PM PDT 24 |
3374974735 ps |
| T897 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.2472551250 |
|
|
Aug 05 06:18:26 PM PDT 24 |
Aug 05 06:18:30 PM PDT 24 |
2255188547 ps |
| T898 |
/workspace/coverage/default/25.sram_ctrl_partial_access.1460230162 |
|
|
Aug 05 06:18:57 PM PDT 24 |
Aug 05 06:19:12 PM PDT 24 |
2382495640 ps |
| T899 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1909073608 |
|
|
Aug 05 06:19:28 PM PDT 24 |
Aug 05 06:19:33 PM PDT 24 |
370675636 ps |
| T900 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.3856868824 |
|
|
Aug 05 06:15:59 PM PDT 24 |
Aug 05 06:20:15 PM PDT 24 |
20010129753 ps |
| T901 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1816751766 |
|
|
Aug 05 06:16:51 PM PDT 24 |
Aug 05 06:16:52 PM PDT 24 |
20867694 ps |
| T902 |
/workspace/coverage/default/31.sram_ctrl_smoke.3189889530 |
|
|
Aug 05 06:19:44 PM PDT 24 |
Aug 05 06:20:14 PM PDT 24 |
419629673 ps |
| T903 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2272129499 |
|
|
Aug 05 06:21:52 PM PDT 24 |
Aug 05 06:23:09 PM PDT 24 |
7045664351 ps |
| T904 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2072738551 |
|
|
Aug 05 06:16:04 PM PDT 24 |
Aug 05 06:17:21 PM PDT 24 |
4371302734 ps |
| T905 |
/workspace/coverage/default/19.sram_ctrl_bijection.2831227221 |
|
|
Aug 05 06:18:06 PM PDT 24 |
Aug 05 06:58:21 PM PDT 24 |
405184137033 ps |
| T906 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3243209775 |
|
|
Aug 05 06:22:19 PM PDT 24 |
Aug 05 06:24:56 PM PDT 24 |
46157914052 ps |
| T907 |
/workspace/coverage/default/44.sram_ctrl_executable.1081312014 |
|
|
Aug 05 06:21:57 PM PDT 24 |
Aug 05 06:37:37 PM PDT 24 |
21803653455 ps |
| T908 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2112378324 |
|
|
Aug 05 06:19:34 PM PDT 24 |
Aug 05 06:20:01 PM PDT 24 |
4096246444 ps |
| T909 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2765768066 |
|
|
Aug 05 06:15:54 PM PDT 24 |
Aug 05 06:23:57 PM PDT 24 |
200088931245 ps |
| T910 |
/workspace/coverage/default/6.sram_ctrl_regwen.1425820482 |
|
|
Aug 05 06:16:18 PM PDT 24 |
Aug 05 06:22:18 PM PDT 24 |
114669162731 ps |
| T911 |
/workspace/coverage/default/11.sram_ctrl_bijection.2327935659 |
|
|
Aug 05 06:16:53 PM PDT 24 |
Aug 05 06:35:13 PM PDT 24 |
96237915847 ps |
| T912 |
/workspace/coverage/default/1.sram_ctrl_partial_access.282867069 |
|
|
Aug 05 06:15:46 PM PDT 24 |
Aug 05 06:15:59 PM PDT 24 |
1220822475 ps |
| T913 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1022592546 |
|
|
Aug 05 06:22:16 PM PDT 24 |
Aug 05 06:22:19 PM PDT 24 |
1608207486 ps |
| T914 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.513442465 |
|
|
Aug 05 06:18:11 PM PDT 24 |
Aug 05 06:23:50 PM PDT 24 |
12821765906 ps |
| T915 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1617722518 |
|
|
Aug 05 06:17:45 PM PDT 24 |
Aug 05 06:23:34 PM PDT 24 |
63592316094 ps |
| T916 |
/workspace/coverage/default/5.sram_ctrl_alert_test.274607813 |
|
|
Aug 05 06:16:11 PM PDT 24 |
Aug 05 06:16:12 PM PDT 24 |
19610900 ps |
| T917 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2009269385 |
|
|
Aug 05 06:16:20 PM PDT 24 |
Aug 05 06:33:24 PM PDT 24 |
53748257286 ps |
| T918 |
/workspace/coverage/default/14.sram_ctrl_smoke.2036061622 |
|
|
Aug 05 06:17:23 PM PDT 24 |
Aug 05 06:18:04 PM PDT 24 |
728467931 ps |
| T919 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1121352294 |
|
|
Aug 05 06:22:58 PM PDT 24 |
Aug 05 06:24:04 PM PDT 24 |
1011624056 ps |
| T920 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.749923498 |
|
|
Aug 05 06:19:28 PM PDT 24 |
Aug 05 06:25:01 PM PDT 24 |
10685947467 ps |
| T921 |
/workspace/coverage/default/30.sram_ctrl_executable.133871816 |
|
|
Aug 05 06:19:43 PM PDT 24 |
Aug 05 06:29:04 PM PDT 24 |
30446897155 ps |
| T922 |
/workspace/coverage/default/34.sram_ctrl_bijection.2464321296 |
|
|
Aug 05 06:20:17 PM PDT 24 |
Aug 05 06:33:15 PM PDT 24 |
32537919025 ps |
| T923 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.712532095 |
|
|
Aug 05 06:16:27 PM PDT 24 |
Aug 05 06:20:29 PM PDT 24 |
8332751772 ps |
| T924 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.638913358 |
|
|
Aug 05 06:18:48 PM PDT 24 |
Aug 05 06:25:10 PM PDT 24 |
26122612414 ps |
| T925 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1662565863 |
|
|
Aug 05 06:16:01 PM PDT 24 |
Aug 05 06:16:11 PM PDT 24 |
700998533 ps |
| T35 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.2565157581 |
|
|
Aug 05 06:16:11 PM PDT 24 |
Aug 05 06:16:14 PM PDT 24 |
171907684 ps |
| T926 |
/workspace/coverage/default/49.sram_ctrl_stress_all.4285448556 |
|
|
Aug 05 06:22:59 PM PDT 24 |
Aug 05 07:28:16 PM PDT 24 |
324426253075 ps |
| T927 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3366388911 |
|
|
Aug 05 06:22:01 PM PDT 24 |
Aug 05 06:22:02 PM PDT 24 |
42918076 ps |
| T928 |
/workspace/coverage/default/8.sram_ctrl_executable.3313378559 |
|
|
Aug 05 06:16:30 PM PDT 24 |
Aug 05 06:25:37 PM PDT 24 |
6700481459 ps |
| T929 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3101221012 |
|
|
Aug 05 06:16:12 PM PDT 24 |
Aug 05 06:24:29 PM PDT 24 |
19820402252 ps |
| T930 |
/workspace/coverage/default/32.sram_ctrl_partial_access.3640105691 |
|
|
Aug 05 06:19:57 PM PDT 24 |
Aug 05 06:20:08 PM PDT 24 |
2854393673 ps |
| T931 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.2804541292 |
|
|
Aug 05 06:15:46 PM PDT 24 |
Aug 05 06:18:37 PM PDT 24 |
21583354290 ps |
| T932 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.1292146597 |
|
|
Aug 05 06:21:19 PM PDT 24 |
Aug 05 06:22:07 PM PDT 24 |
743946501 ps |
| T933 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.3344905611 |
|
|
Aug 05 06:21:25 PM PDT 24 |
Aug 05 06:22:06 PM PDT 24 |
2353635812 ps |
| T934 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2004340791 |
|
|
Aug 05 06:19:39 PM PDT 24 |
Aug 05 06:19:47 PM PDT 24 |
4213048304 ps |
| T935 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2362709556 |
|
|
Aug 05 06:16:18 PM PDT 24 |
Aug 05 06:17:19 PM PDT 24 |
1570176193 ps |
| T936 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1496730373 |
|
|
Aug 05 06:15:52 PM PDT 24 |
Aug 05 06:15:56 PM PDT 24 |
4174074091 ps |
| T937 |
/workspace/coverage/default/47.sram_ctrl_smoke.936475891 |
|
|
Aug 05 06:22:28 PM PDT 24 |
Aug 05 06:22:35 PM PDT 24 |
386105562 ps |
| T938 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.4002257149 |
|
|
Aug 05 06:17:11 PM PDT 24 |
Aug 05 06:22:09 PM PDT 24 |
10208685474 ps |
| T939 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.2382008617 |
|
|
Aug 05 06:19:15 PM PDT 24 |
Aug 05 06:19:47 PM PDT 24 |
29995758158 ps |
| T940 |
/workspace/coverage/default/39.sram_ctrl_stress_all.615095463 |
|
|
Aug 05 06:21:17 PM PDT 24 |
Aug 05 08:35:42 PM PDT 24 |
77435712989 ps |
| T941 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.76807573 |
|
|
Aug 05 06:20:46 PM PDT 24 |
Aug 05 06:20:49 PM PDT 24 |
1401916235 ps |
| T942 |
/workspace/coverage/default/48.sram_ctrl_partial_access.4229585579 |
|
|
Aug 05 06:22:41 PM PDT 24 |
Aug 05 06:23:00 PM PDT 24 |
2362795213 ps |
| T68 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2229900258 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:22 PM PDT 24 |
36391898 ps |
| T69 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1651088931 |
|
|
Aug 05 06:10:09 PM PDT 24 |
Aug 05 06:10:11 PM PDT 24 |
94194356 ps |
| T70 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1184986973 |
|
|
Aug 05 06:10:17 PM PDT 24 |
Aug 05 06:10:17 PM PDT 24 |
21950608 ps |
| T88 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3775176019 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:22 PM PDT 24 |
16471713 ps |
| T89 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2325234111 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:22 PM PDT 24 |
11343046 ps |
| T60 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2931482898 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:24 PM PDT 24 |
111812757 ps |
| T90 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1649952349 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:46 PM PDT 24 |
3727987871 ps |
| T113 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2490069857 |
|
|
Aug 05 06:10:25 PM PDT 24 |
Aug 05 06:10:26 PM PDT 24 |
15574321 ps |
| T943 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1700431331 |
|
|
Aug 05 06:10:34 PM PDT 24 |
Aug 05 06:10:36 PM PDT 24 |
32503565 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2569465880 |
|
|
Aug 05 06:10:23 PM PDT 24 |
Aug 05 06:10:50 PM PDT 24 |
3702581615 ps |
| T61 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3927123043 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:24 PM PDT 24 |
293263829 ps |
| T92 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3533989630 |
|
|
Aug 05 06:10:14 PM PDT 24 |
Aug 05 06:10:15 PM PDT 24 |
19863886 ps |
| T62 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2403050540 |
|
|
Aug 05 06:10:23 PM PDT 24 |
Aug 05 06:10:26 PM PDT 24 |
5127742904 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.894829786 |
|
|
Aug 05 06:10:32 PM PDT 24 |
Aug 05 06:10:32 PM PDT 24 |
19385074 ps |
| T93 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2861493853 |
|
|
Aug 05 06:10:25 PM PDT 24 |
Aug 05 06:11:08 PM PDT 24 |
46065201910 ps |
| T945 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.901986332 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:27 PM PDT 24 |
79967705 ps |
| T114 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.859179460 |
|
|
Aug 05 06:10:18 PM PDT 24 |
Aug 05 06:10:19 PM PDT 24 |
23069990 ps |
| T94 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1770928861 |
|
|
Aug 05 06:10:26 PM PDT 24 |
Aug 05 06:10:54 PM PDT 24 |
3710437953 ps |
| T95 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3722132090 |
|
|
Aug 05 06:10:18 PM PDT 24 |
Aug 05 06:10:21 PM PDT 24 |
182935558 ps |
| T946 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.378788995 |
|
|
Aug 05 06:10:27 PM PDT 24 |
Aug 05 06:10:31 PM PDT 24 |
363700991 ps |
| T136 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.881158840 |
|
|
Aug 05 06:10:27 PM PDT 24 |
Aug 05 06:10:28 PM PDT 24 |
104737605 ps |
| T947 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.935660936 |
|
|
Aug 05 06:10:26 PM PDT 24 |
Aug 05 06:10:27 PM PDT 24 |
43421357 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1676996677 |
|
|
Aug 05 06:10:18 PM PDT 24 |
Aug 05 06:10:19 PM PDT 24 |
72906622 ps |
| T115 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2342745087 |
|
|
Aug 05 06:10:20 PM PDT 24 |
Aug 05 06:10:21 PM PDT 24 |
18485545 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.233195312 |
|
|
Aug 05 06:10:23 PM PDT 24 |
Aug 05 06:10:27 PM PDT 24 |
1367144392 ps |
| T949 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4239824471 |
|
|
Aug 05 06:10:18 PM PDT 24 |
Aug 05 06:10:22 PM PDT 24 |
61701878 ps |
| T98 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.250305233 |
|
|
Aug 05 06:10:43 PM PDT 24 |
Aug 05 06:11:39 PM PDT 24 |
7082214877 ps |
| T116 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2856923462 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:26 PM PDT 24 |
47793905 ps |
| T99 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1275700060 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:11:17 PM PDT 24 |
14708971870 ps |
| T950 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4251021575 |
|
|
Aug 05 06:10:28 PM PDT 24 |
Aug 05 06:10:30 PM PDT 24 |
18439857 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.279736347 |
|
|
Aug 05 06:10:19 PM PDT 24 |
Aug 05 06:10:20 PM PDT 24 |
12060594 ps |
| T105 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2519136140 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:53 PM PDT 24 |
14879867496 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3093303102 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:22 PM PDT 24 |
19627500 ps |
| T953 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3238412949 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:25 PM PDT 24 |
41567727 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.605062304 |
|
|
Aug 05 06:10:08 PM PDT 24 |
Aug 05 06:10:08 PM PDT 24 |
38285145 ps |
| T955 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2641166516 |
|
|
Aug 05 06:10:29 PM PDT 24 |
Aug 05 06:10:33 PM PDT 24 |
370896235 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3310664938 |
|
|
Aug 05 06:10:26 PM PDT 24 |
Aug 05 06:10:29 PM PDT 24 |
34301779 ps |
| T957 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4220827148 |
|
|
Aug 05 06:10:12 PM PDT 24 |
Aug 05 06:10:37 PM PDT 24 |
3900558897 ps |
| T958 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2941476925 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:23 PM PDT 24 |
21030027 ps |
| T137 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.645174940 |
|
|
Aug 05 06:10:17 PM PDT 24 |
Aug 05 06:10:19 PM PDT 24 |
316527535 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1591390293 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:27 PM PDT 24 |
87776800 ps |
| T960 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3964679748 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:22 PM PDT 24 |
44790201 ps |
| T961 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2204239543 |
|
|
Aug 05 06:10:17 PM PDT 24 |
Aug 05 06:10:18 PM PDT 24 |
19500440 ps |
| T138 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.232581429 |
|
|
Aug 05 06:10:23 PM PDT 24 |
Aug 05 06:10:25 PM PDT 24 |
273593324 ps |
| T962 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3161847031 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:22 PM PDT 24 |
14491391 ps |
| T963 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3786992514 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:25 PM PDT 24 |
710823966 ps |
| T106 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4057950249 |
|
|
Aug 05 06:10:27 PM PDT 24 |
Aug 05 06:11:17 PM PDT 24 |
7364355565 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4271443027 |
|
|
Aug 05 06:10:39 PM PDT 24 |
Aug 05 06:10:42 PM PDT 24 |
299233678 ps |
| T108 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1082562449 |
|
|
Aug 05 06:10:28 PM PDT 24 |
Aug 05 06:10:30 PM PDT 24 |
51785621 ps |
| T965 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.496711705 |
|
|
Aug 05 06:10:28 PM PDT 24 |
Aug 05 06:11:00 PM PDT 24 |
14237703246 ps |
| T966 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4169141144 |
|
|
Aug 05 06:10:25 PM PDT 24 |
Aug 05 06:10:26 PM PDT 24 |
56444700 ps |
| T967 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3087525778 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:25 PM PDT 24 |
15587581 ps |
| T968 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2500307881 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:22 PM PDT 24 |
16890254 ps |
| T969 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1365175340 |
|
|
Aug 05 06:10:33 PM PDT 24 |
Aug 05 06:10:34 PM PDT 24 |
35544240 ps |
| T970 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3987546425 |
|
|
Aug 05 06:10:20 PM PDT 24 |
Aug 05 06:10:21 PM PDT 24 |
153829027 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1489797826 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:27 PM PDT 24 |
1419460843 ps |
| T139 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3510186409 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:24 PM PDT 24 |
197900495 ps |
| T145 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1378533203 |
|
|
Aug 05 06:10:19 PM PDT 24 |
Aug 05 06:10:20 PM PDT 24 |
267901603 ps |
| T109 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2746276550 |
|
|
Aug 05 06:10:19 PM PDT 24 |
Aug 05 06:10:20 PM PDT 24 |
58698287 ps |
| T972 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1597146987 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:25 PM PDT 24 |
358672680 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3171381927 |
|
|
Aug 05 06:10:19 PM PDT 24 |
Aug 05 06:10:19 PM PDT 24 |
75766629 ps |
| T974 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3319120911 |
|
|
Aug 05 06:10:28 PM PDT 24 |
Aug 05 06:10:32 PM PDT 24 |
980108615 ps |
| T975 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2671697673 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:26 PM PDT 24 |
355479603 ps |
| T976 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1438993524 |
|
|
Aug 05 06:10:26 PM PDT 24 |
Aug 05 06:10:28 PM PDT 24 |
61886974 ps |
| T977 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1956929525 |
|
|
Aug 05 06:10:29 PM PDT 24 |
Aug 05 06:10:30 PM PDT 24 |
87697866 ps |
| T978 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.746546120 |
|
|
Aug 05 06:10:16 PM PDT 24 |
Aug 05 06:10:17 PM PDT 24 |
41710668 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3474684757 |
|
|
Aug 05 06:10:13 PM PDT 24 |
Aug 05 06:10:14 PM PDT 24 |
13404980 ps |
| T980 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1874008761 |
|
|
Aug 05 06:10:25 PM PDT 24 |
Aug 05 06:10:34 PM PDT 24 |
366212533 ps |
| T981 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1038541750 |
|
|
Aug 05 06:10:19 PM PDT 24 |
Aug 05 06:10:22 PM PDT 24 |
110640985 ps |
| T107 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1221273302 |
|
|
Aug 05 06:10:30 PM PDT 24 |
Aug 05 06:11:27 PM PDT 24 |
7064687744 ps |
| T982 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3855129427 |
|
|
Aug 05 06:10:20 PM PDT 24 |
Aug 05 06:11:23 PM PDT 24 |
70469462625 ps |
| T983 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2471428161 |
|
|
Aug 05 06:10:26 PM PDT 24 |
Aug 05 06:10:57 PM PDT 24 |
61478321182 ps |
| T984 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1200717360 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:23 PM PDT 24 |
28388954 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.992229675 |
|
|
Aug 05 06:10:17 PM PDT 24 |
Aug 05 06:10:20 PM PDT 24 |
351914710 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1263340144 |
|
|
Aug 05 06:10:18 PM PDT 24 |
Aug 05 06:10:19 PM PDT 24 |
27362555 ps |
| T146 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.832098918 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:25 PM PDT 24 |
188012049 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.505625082 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:23 PM PDT 24 |
13646008 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3936028531 |
|
|
Aug 05 06:10:20 PM PDT 24 |
Aug 05 06:10:21 PM PDT 24 |
41142727 ps |
| T989 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4112238717 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:27 PM PDT 24 |
6790199306 ps |
| T990 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.938817268 |
|
|
Aug 05 06:10:26 PM PDT 24 |
Aug 05 06:10:30 PM PDT 24 |
378798850 ps |
| T991 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2373811952 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:28 PM PDT 24 |
216075949 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2505241018 |
|
|
Aug 05 06:10:26 PM PDT 24 |
Aug 05 06:10:30 PM PDT 24 |
367927400 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3985873412 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:51 PM PDT 24 |
3741422912 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1151416384 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:25 PM PDT 24 |
921387273 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3653613849 |
|
|
Aug 05 06:10:23 PM PDT 24 |
Aug 05 06:10:24 PM PDT 24 |
21607404 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1068187737 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:25 PM PDT 24 |
1072164921 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4264060574 |
|
|
Aug 05 06:10:13 PM PDT 24 |
Aug 05 06:10:14 PM PDT 24 |
127730602 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1310854248 |
|
|
Aug 05 06:10:13 PM PDT 24 |
Aug 05 06:10:16 PM PDT 24 |
129192275 ps |
| T147 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.81938626 |
|
|
Aug 05 06:10:27 PM PDT 24 |
Aug 05 06:10:29 PM PDT 24 |
409572347 ps |
| T999 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.127301276 |
|
|
Aug 05 06:10:34 PM PDT 24 |
Aug 05 06:10:35 PM PDT 24 |
13510666 ps |
| T110 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3709835571 |
|
|
Aug 05 06:10:14 PM PDT 24 |
Aug 05 06:11:14 PM PDT 24 |
28257118650 ps |
| T142 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.51451189 |
|
|
Aug 05 06:10:44 PM PDT 24 |
Aug 05 06:10:46 PM PDT 24 |
611290115 ps |
| T1000 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2979917279 |
|
|
Aug 05 06:10:24 PM PDT 24 |
Aug 05 06:10:27 PM PDT 24 |
39071164 ps |
| T1001 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.384702860 |
|
|
Aug 05 06:10:21 PM PDT 24 |
Aug 05 06:10:25 PM PDT 24 |
127753219 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.9435912 |
|
|
Aug 05 06:10:17 PM PDT 24 |
Aug 05 06:10:45 PM PDT 24 |
3817163351 ps |
| T1003 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1804693112 |
|
|
Aug 05 06:10:20 PM PDT 24 |
Aug 05 06:10:23 PM PDT 24 |
354900051 ps |
| T1004 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.305927066 |
|
|
Aug 05 06:10:22 PM PDT 24 |
Aug 05 06:10:49 PM PDT 24 |
7703623551 ps |
| T1005 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2697771867 |
|
|
Aug 05 06:10:20 PM PDT 24 |
Aug 05 06:10:21 PM PDT 24 |
65520693 ps |
| T1006 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3555244704 |
|
|
Aug 05 06:10:19 PM PDT 24 |
Aug 05 06:11:17 PM PDT 24 |
58994971109 ps |
| T1007 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.649846020 |
|
|
Aug 05 06:10:33 PM PDT 24 |
Aug 05 06:10:36 PM PDT 24 |
124319535 ps |
| T1008 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.441924134 |
|
|
Aug 05 06:10:11 PM PDT 24 |
Aug 05 06:10:16 PM PDT 24 |
5027383252 ps |
| T1009 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2191400591 |
|
|
Aug 05 06:10:20 PM PDT 24 |
Aug 05 06:10:24 PM PDT 24 |
400478145 ps |
| T1010 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1060551821 |
|
|
Aug 05 06:10:18 PM PDT 24 |
Aug 05 06:10:19 PM PDT 24 |
31858407 ps |